wdc.c revision 1.239
1 /* $NetBSD: wdc.c,v 1.239 2006/10/25 17:33:02 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.239 2006/10/25 17:33:02 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ata/satareg.h> 102 #include <dev/ata/satavar.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "locators.h" 107 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #define WDCDELAY 100 /* 100 microseconds */ 112 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 113 #if 0 114 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 115 #define WDCNDELAY_DEBUG 50 116 #endif 117 118 /* When polling wait that much and then tsleep for 1/hz seconds */ 119 #define WDCDELAY_POLL 1 /* ms */ 120 121 /* timeout for the control commands */ 122 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 123 124 /* 125 * timeout when waiting for BSY to deassert when probing. 126 * set to 5s. From the standards this could be up to 31, but we can't 127 * wait that much at boot time, and 5s seems to be enouth. 128 */ 129 #define WDC_PROBE_WAIT 5 130 131 132 #if NWD > 0 133 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 134 #else 135 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 136 const struct ata_bustype wdc_ata_bustype = { 137 SCSIPI_BUSTYPE_ATA, 138 NULL, /* wdc_ata_bio */ 139 NULL, /* wdc_reset_drive */ 140 wdc_reset_channel, 141 wdc_exec_command, 142 NULL, /* ata_get_params */ 143 NULL, /* wdc_ata_addref */ 144 NULL, /* wdc_ata_delref */ 145 NULL /* ata_kill_pending */ 146 }; 147 #endif 148 149 /* Flags to wdcreset(). */ 150 #define RESET_POLL 1 151 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 152 153 static int wdcprobe1(struct ata_channel *, int); 154 static int wdcreset(struct ata_channel *, int); 155 static void __wdcerror(struct ata_channel *, const char *); 156 static int __wdcwait_reset(struct ata_channel *, int, int); 157 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 158 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 159 static void __wdccommand_kill_xfer(struct ata_channel *, 160 struct ata_xfer *, int); 161 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 162 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 163 static int __wdcwait(struct ata_channel *, int, int, int); 164 165 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 166 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 167 168 #define DEBUG_INTR 0x01 169 #define DEBUG_XFERS 0x02 170 #define DEBUG_STATUS 0x04 171 #define DEBUG_FUNCS 0x08 172 #define DEBUG_PROBE 0x10 173 #define DEBUG_DETACH 0x20 174 #define DEBUG_DELAY 0x40 175 #ifdef ATADEBUG 176 extern int atadebug_mask; /* init'ed in ata.c */ 177 int wdc_nxfer = 0; 178 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 179 #else 180 #define ATADEBUG_PRINT(args, level) 181 #endif 182 183 /* 184 * Initialize the "shadow register" handles for a standard wdc controller. 185 */ 186 void 187 wdc_init_shadow_regs(struct ata_channel *chp) 188 { 189 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 190 191 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 192 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 193 } 194 195 /* 196 * Allocate a wdc_regs array, based on the number of channels. 197 */ 198 void 199 wdc_allocate_regs(struct wdc_softc *wdc) 200 { 201 202 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 203 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 204 } 205 206 /* 207 * probe drives on SATA controllers with standard SATA registers: 208 * bring the PHYs online, read the drive signature and set drive flags 209 * appropriately. 210 */ 211 void 212 wdc_sataprobe(struct ata_channel *chp) 213 { 214 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 215 uint32_t scontrol, sstatus; 216 uint16_t scnt, sn, cl, ch; 217 int i, s; 218 219 /* XXX This should be done by other code. */ 220 for (i = 0; i < chp->ch_ndrive; i++) { 221 chp->ch_drive[i].chnl_softc = chp; 222 chp->ch_drive[i].drive = i; 223 } 224 225 /* bring the PHYs online. 226 * The work-around for errata #1 for the 31244 says that we must 227 * write 0 to the port first to be sure of correctly initializing 228 * the device. It doesn't hurt for other devices. 229 */ 230 bus_space_write_4(wdr->sata_iot, wdr->sata_control, 0, 0); 231 scontrol = SControl_IPM_NONE | SControl_SPD_ANY | SControl_DET_INIT; 232 bus_space_write_4 (wdr->sata_iot, wdr->sata_control, 0, scontrol); 233 234 tsleep(wdr, PRIBIO, "sataup", mstohz(50)); 235 scontrol &= ~SControl_DET_INIT; 236 bus_space_write_4(wdr->sata_iot, wdr->sata_control, 0, scontrol); 237 238 tsleep(wdr, PRIBIO, "sataup", mstohz(50)); 239 sstatus = bus_space_read_4(wdr->sata_iot, wdr->sata_status, 0); 240 241 switch (sstatus & SStatus_DET_mask) { 242 case SStatus_DET_NODEV: 243 /* No Device; be silent. */ 244 break; 245 246 case SStatus_DET_DEV_NE: 247 aprint_error("%s: port %d: device connected, but " 248 "communication not established\n", 249 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel); 250 break; 251 252 case SStatus_DET_OFFLINE: 253 aprint_error("%s: port %d: PHY offline\n", 254 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel); 255 break; 256 257 case SStatus_DET_DEV: 258 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 259 WDSD_IBM); 260 delay(10); /* 400ns delay */ 261 scnt = bus_space_read_2(wdr->cmd_iot, 262 wdr->cmd_iohs[wd_seccnt], 0); 263 sn = bus_space_read_2(wdr->cmd_iot, 264 wdr->cmd_iohs[wd_sector], 0); 265 cl = bus_space_read_2(wdr->cmd_iot, 266 wdr->cmd_iohs[wd_cyl_lo], 0); 267 ch = bus_space_read_2(wdr->cmd_iot, 268 wdr->cmd_iohs[wd_cyl_hi], 0); 269 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 270 "cl=0x%x ch=0x%x\n", 271 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 272 scnt, sn, cl, ch), DEBUG_PROBE); 273 /* 274 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 275 * cases we get wrong values here, so ignore it. 276 */ 277 s = splbio(); 278 if (cl == 0x14 && ch == 0xeb) 279 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 280 else 281 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 282 splx(s); 283 284 aprint_normal("%s: port %d: device present, speed: %s\n", 285 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 286 sata_speed(sstatus)); 287 break; 288 289 default: 290 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 291 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 292 sstatus); 293 } 294 } 295 296 297 /* Test to see controller with at last one attached drive is there. 298 * Returns a bit for each possible drive found (0x01 for drive 0, 299 * 0x02 for drive 1). 300 * Logic: 301 * - If a status register is at 0xff, assume there is no drive here 302 * (ISA has pull-up resistors). Similarly if the status register has 303 * the value we last wrote to the bus (for IDE interfaces without pullups). 304 * If no drive at all -> return. 305 * - reset the controller, wait for it to complete (may take up to 31s !). 306 * If timeout -> return. 307 * - test ATA/ATAPI signatures. If at last one drive found -> return. 308 * - try an ATA command on the master. 309 */ 310 311 void 312 wdc_drvprobe(struct ata_channel *chp) 313 { 314 struct ataparams params; 315 struct atac_softc *atac = chp->ch_atac; 316 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 317 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 318 u_int8_t st0 = 0, st1 = 0; 319 int i, j, error, s; 320 321 if (wdcprobe1(chp, 0) == 0) { 322 /* No drives, abort the attach here. */ 323 return; 324 } 325 326 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 327 for (i = 0; i < mstohz(3000); i++) { 328 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 329 if (wdc->select) 330 wdc->select(chp,0); 331 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 332 0, WDSD_IBM); 333 delay(10); /* 400ns delay */ 334 st0 = bus_space_read_1(wdr->cmd_iot, 335 wdr->cmd_iohs[wd_status], 0); 336 } 337 338 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 339 if (wdc->select) 340 wdc->select(chp,1); 341 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 342 0, WDSD_IBM | 0x10); 343 delay(10); /* 400ns delay */ 344 st1 = bus_space_read_1(wdr->cmd_iot, 345 wdr->cmd_iohs[wd_status], 0); 346 } 347 348 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 349 == 0 || 350 (st0 & WDCS_DRDY)) && 351 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 352 == 0 || 353 (st1 & WDCS_DRDY))) 354 break; 355 tsleep(¶ms, PRIBIO, "atadrdy", 1); 356 } 357 s = splbio(); 358 if ((st0 & WDCS_DRDY) == 0) 359 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 360 if ((st1 & WDCS_DRDY) == 0) 361 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 362 splx(s); 363 364 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 365 atac->atac_dev.dv_xname, 366 chp->ch_channel, st0, st1), DEBUG_PROBE); 367 368 /* Wait a bit, some devices are weird just after a reset. */ 369 delay(5000); 370 371 for (i = 0; i < chp->ch_ndrive; i++) { 372 /* XXX This should be done by other code. */ 373 chp->ch_drive[i].chnl_softc = chp; 374 chp->ch_drive[i].drive = i; 375 376 #if NATA_DMA 377 /* 378 * Init error counter so that an error withing the first xfers 379 * will trigger a downgrade 380 */ 381 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 382 #endif 383 384 /* If controller can't do 16bit flag the drives as 32bit */ 385 if ((atac->atac_cap & 386 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 387 s = splbio(); 388 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 389 splx(s); 390 } 391 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 392 continue; 393 394 /* Shortcut in case we've been shutdown */ 395 if (chp->ch_flags & ATACH_SHUTDOWN) 396 return; 397 398 /* 399 * Issue an identify, to try to detect ghosts. 400 * Note that we can't use interrupts here, because if there 401 * is no devices, we will get a command aborted without 402 * interrupts. 403 */ 404 error = ata_get_params(&chp->ch_drive[i], 405 AT_WAIT | AT_POLL, ¶ms); 406 if (error != CMD_OK) { 407 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 408 409 /* Shortcut in case we've been shutdown */ 410 if (chp->ch_flags & ATACH_SHUTDOWN) 411 return; 412 413 error = ata_get_params(&chp->ch_drive[i], 414 AT_WAIT | AT_POLL, ¶ms); 415 } 416 if (error == CMD_OK) { 417 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 418 s = splbio(); 419 for (j = 0; j < chp->ch_ndrive; j++) 420 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 421 splx(s); 422 } else { 423 s = splbio(); 424 chp->ch_drive[i].drive_flags &= 425 ~(DRIVE_ATA | DRIVE_ATAPI); 426 splx(s); 427 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 428 atac->atac_dev.dv_xname, 429 chp->ch_channel, i, error), DEBUG_PROBE); 430 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 431 continue; 432 /* 433 * Pre-ATA drive ? 434 * Test registers writability (Error register not 435 * writable, but cyllo is), then try an ATA command. 436 */ 437 if (wdc->select) 438 wdc->select(chp,i); 439 bus_space_write_1(wdr->cmd_iot, 440 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 441 delay(10); /* 400ns delay */ 442 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 443 0, 0x58); 444 bus_space_write_1(wdr->cmd_iot, 445 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 446 if (bus_space_read_1(wdr->cmd_iot, 447 wdr->cmd_iohs[wd_error], 0) == 0x58 || 448 bus_space_read_1(wdr->cmd_iot, 449 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 450 ATADEBUG_PRINT(("%s:%d:%d: register " 451 "writability failed\n", 452 atac->atac_dev.dv_xname, 453 chp->ch_channel, i), DEBUG_PROBE); 454 s = splbio(); 455 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 456 splx(s); 457 continue; 458 } 459 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 460 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 461 atac->atac_dev.dv_xname, 462 chp->ch_channel, i), DEBUG_PROBE); 463 s = splbio(); 464 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 465 splx(s); 466 continue; 467 } 468 bus_space_write_1(wdr->cmd_iot, 469 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 470 delay(10); /* 400ns delay */ 471 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 472 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 473 atac->atac_dev.dv_xname, 474 chp->ch_channel, i), DEBUG_PROBE); 475 s = splbio(); 476 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 477 splx(s); 478 } else { 479 s = splbio(); 480 for (j = 0; j < chp->ch_ndrive; j++) 481 chp->ch_drive[j].drive_flags &= 482 ~(DRIVE_ATA | DRIVE_ATAPI); 483 splx(s); 484 } 485 } 486 } 487 } 488 489 int 490 wdcprobe(struct ata_channel *chp) 491 { 492 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 493 /* default reset method */ 494 if (wdc->reset == NULL) 495 wdc->reset = wdc_do_reset; 496 497 return (wdcprobe1(chp, 1)); 498 } 499 500 static int 501 wdcprobe1(struct ata_channel *chp, int poll) 502 { 503 struct atac_softc *atac = chp->ch_atac; 504 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 505 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 506 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 507 u_int8_t ret_value = 0x03; 508 u_int8_t drive; 509 int s; 510 int wdc_probe_count = 511 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 512 513 /* 514 * Sanity check to see if the wdc channel responds at all. 515 */ 516 517 s = splbio(); 518 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 519 while (wdc_probe_count-- > 0) { 520 if (wdc->select) 521 wdc->select(chp,0); 522 523 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 524 0, WDSD_IBM); 525 delay(10); /* 400ns delay */ 526 st0 = bus_space_read_1(wdr->cmd_iot, 527 wdr->cmd_iohs[wd_status], 0); 528 529 if (wdc->select) 530 wdc->select(chp,1); 531 532 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 533 0, WDSD_IBM | 0x10); 534 delay(10); /* 400ns delay */ 535 st1 = bus_space_read_1(wdr->cmd_iot, 536 wdr->cmd_iohs[wd_status], 0); 537 if ((st0 & WDCS_BSY) == 0) 538 break; 539 } 540 541 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 542 atac->atac_dev.dv_xname, 543 chp->ch_channel, st0, st1), DEBUG_PROBE); 544 545 if (st0 == 0xff || st0 == WDSD_IBM) 546 ret_value &= ~0x01; 547 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 548 ret_value &= ~0x02; 549 /* Register writability test, drive 0. */ 550 if (ret_value & 0x01) { 551 if (wdc->select) 552 wdc->select(chp,0); 553 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 554 0, WDSD_IBM); 555 bus_space_write_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 557 cl = bus_space_read_1(wdr->cmd_iot, 558 wdr->cmd_iohs[wd_cyl_lo], 0); 559 if (cl != 0x02) { 560 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 561 "got 0x%x != 0x02\n", 562 atac->atac_dev.dv_xname, 563 chp->ch_channel, cl), 564 DEBUG_PROBE); 565 ret_value &= ~0x01; 566 } 567 bus_space_write_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 569 cl = bus_space_read_1(wdr->cmd_iot, 570 wdr->cmd_iohs[wd_cyl_lo], 0); 571 if (cl != 0x01) { 572 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 573 "got 0x%x != 0x01\n", 574 atac->atac_dev.dv_xname, 575 chp->ch_channel, cl), 576 DEBUG_PROBE); 577 ret_value &= ~0x01; 578 } 579 bus_space_write_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_sector], 0, 0x01); 581 cl = bus_space_read_1(wdr->cmd_iot, 582 wdr->cmd_iohs[wd_sector], 0); 583 if (cl != 0x01) { 584 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 585 "got 0x%x != 0x01\n", 586 atac->atac_dev.dv_xname, 587 chp->ch_channel, cl), 588 DEBUG_PROBE); 589 ret_value &= ~0x01; 590 } 591 bus_space_write_1(wdr->cmd_iot, 592 wdr->cmd_iohs[wd_sector], 0, 0x02); 593 cl = bus_space_read_1(wdr->cmd_iot, 594 wdr->cmd_iohs[wd_sector], 0); 595 if (cl != 0x02) { 596 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 597 "got 0x%x != 0x02\n", 598 atac->atac_dev.dv_xname, 599 chp->ch_channel, cl), 600 DEBUG_PROBE); 601 ret_value &= ~0x01; 602 } 603 cl = bus_space_read_1(wdr->cmd_iot, 604 wdr->cmd_iohs[wd_cyl_lo], 0); 605 if (cl != 0x01) { 606 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 607 "got 0x%x != 0x01\n", 608 atac->atac_dev.dv_xname, 609 chp->ch_channel, cl), 610 DEBUG_PROBE); 611 ret_value &= ~0x01; 612 } 613 } 614 /* Register writability test, drive 1. */ 615 if (ret_value & 0x02) { 616 if (wdc->select) 617 wdc->select(chp,1); 618 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 619 0, WDSD_IBM | 0x10); 620 bus_space_write_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 622 cl = bus_space_read_1(wdr->cmd_iot, 623 wdr->cmd_iohs[wd_cyl_lo], 0); 624 if (cl != 0x02) { 625 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 626 "got 0x%x != 0x02\n", 627 atac->atac_dev.dv_xname, 628 chp->ch_channel, cl), 629 DEBUG_PROBE); 630 ret_value &= ~0x02; 631 } 632 bus_space_write_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 634 cl = bus_space_read_1(wdr->cmd_iot, 635 wdr->cmd_iohs[wd_cyl_lo], 0); 636 if (cl != 0x01) { 637 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 638 "got 0x%x != 0x01\n", 639 atac->atac_dev.dv_xname, 640 chp->ch_channel, cl), 641 DEBUG_PROBE); 642 ret_value &= ~0x02; 643 } 644 bus_space_write_1(wdr->cmd_iot, 645 wdr->cmd_iohs[wd_sector], 0, 0x01); 646 cl = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_sector], 0); 648 if (cl != 0x01) { 649 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 650 "got 0x%x != 0x01\n", 651 atac->atac_dev.dv_xname, 652 chp->ch_channel, cl), 653 DEBUG_PROBE); 654 ret_value &= ~0x02; 655 } 656 bus_space_write_1(wdr->cmd_iot, 657 wdr->cmd_iohs[wd_sector], 0, 0x02); 658 cl = bus_space_read_1(wdr->cmd_iot, 659 wdr->cmd_iohs[wd_sector], 0); 660 if (cl != 0x02) { 661 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 662 "got 0x%x != 0x02\n", 663 atac->atac_dev.dv_xname, 664 chp->ch_channel, cl), 665 DEBUG_PROBE); 666 ret_value &= ~0x02; 667 } 668 cl = bus_space_read_1(wdr->cmd_iot, 669 wdr->cmd_iohs[wd_cyl_lo], 0); 670 if (cl != 0x01) { 671 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 672 "got 0x%x != 0x01\n", 673 atac->atac_dev.dv_xname, 674 chp->ch_channel, cl), 675 DEBUG_PROBE); 676 ret_value &= ~0x02; 677 } 678 } 679 680 if (ret_value == 0) { 681 splx(s); 682 return 0; 683 } 684 } 685 686 687 #if 0 /* XXX this break some ATA or ATAPI devices */ 688 /* 689 * reset bus. Also send an ATAPI_RESET to devices, in case there are 690 * ATAPI device out there which don't react to the bus reset 691 */ 692 if (ret_value & 0x01) { 693 if (wdc->select) 694 wdc->select(chp,0); 695 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 696 0, WDSD_IBM); 697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 698 ATAPI_SOFT_RESET); 699 } 700 if (ret_value & 0x02) { 701 if (wdc->select) 702 wdc->select(chp,0); 703 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 704 0, WDSD_IBM | 0x10); 705 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 706 ATAPI_SOFT_RESET); 707 } 708 709 delay(5000); 710 #endif 711 712 wdc->reset(chp, RESET_POLL); 713 DELAY(2000); 714 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 715 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 716 splx(s); 717 718 ret_value = __wdcwait_reset(chp, ret_value, poll); 719 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 720 atac->atac_dev.dv_xname, chp->ch_channel, 721 ret_value), DEBUG_PROBE); 722 723 /* if reset failed, there's nothing here */ 724 if (ret_value == 0) 725 return 0; 726 727 /* 728 * Test presence of drives. First test register signatures looking 729 * for ATAPI devices. If it's not an ATAPI and reset said there may 730 * be something here assume it's ATA or OLD. Ghost will be killed 731 * later in attach routine. 732 */ 733 for (drive = 0; drive < chp->ch_ndrive; drive++) { 734 if ((ret_value & (0x01 << drive)) == 0) 735 continue; 736 if (wdc->select) 737 wdc->select(chp,drive); 738 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 739 WDSD_IBM | (drive << 4)); 740 delay(10); /* 400ns delay */ 741 /* Save registers contents */ 742 sc = bus_space_read_1(wdr->cmd_iot, 743 wdr->cmd_iohs[wd_seccnt], 0); 744 sn = bus_space_read_1(wdr->cmd_iot, 745 wdr->cmd_iohs[wd_sector], 0); 746 cl = bus_space_read_1(wdr->cmd_iot, 747 wdr->cmd_iohs[wd_cyl_lo], 0); 748 ch = bus_space_read_1(wdr->cmd_iot, 749 wdr->cmd_iohs[wd_cyl_hi], 0); 750 751 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 752 "cl=0x%x ch=0x%x\n", 753 atac->atac_dev.dv_xname, 754 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 755 /* 756 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 757 * we get wrong values here, so ignore it. 758 */ 759 s = splbio(); 760 if (cl == 0x14 && ch == 0xeb) { 761 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 762 } else { 763 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 764 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 765 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 766 } 767 splx(s); 768 } 769 return (ret_value); 770 } 771 772 void 773 wdcattach(struct ata_channel *chp) 774 { 775 struct atac_softc *atac = chp->ch_atac; 776 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 777 778 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 779 780 /* default data transfer methods */ 781 if (wdc->datain_pio == NULL) 782 wdc->datain_pio = wdc_datain_pio; 783 if (wdc->dataout_pio == NULL) 784 wdc->dataout_pio = wdc_dataout_pio; 785 /* default reset method */ 786 if (wdc->reset == NULL) 787 wdc->reset = wdc_do_reset; 788 789 /* initialise global data */ 790 if (atac->atac_bustype_ata == NULL) 791 atac->atac_bustype_ata = &wdc_ata_bustype; 792 if (atac->atac_probe == NULL) 793 atac->atac_probe = wdc_drvprobe; 794 #if NATAPIBUS > 0 795 if (atac->atac_atapibus_attach == NULL) 796 atac->atac_atapibus_attach = wdc_atapibus_attach; 797 #endif 798 799 ata_channel_attach(chp); 800 } 801 802 int 803 wdcactivate(struct device *self, enum devact act) 804 { 805 struct atac_softc *atac = (struct atac_softc *) self; 806 int s, i, error = 0; 807 808 s = splbio(); 809 switch (act) { 810 case DVACT_ACTIVATE: 811 error = EOPNOTSUPP; 812 break; 813 814 case DVACT_DEACTIVATE: 815 for (i = 0; i < atac->atac_nchannels; i++) { 816 error = 817 config_deactivate(atac->atac_channels[i]->atabus); 818 if (error) 819 break; 820 } 821 break; 822 } 823 splx(s); 824 return (error); 825 } 826 827 int 828 wdcdetach(struct device *self, int flags) 829 { 830 struct atac_softc *atac = (struct atac_softc *) self; 831 struct ata_channel *chp; 832 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 833 int i, error = 0; 834 835 for (i = 0; i < atac->atac_nchannels; i++) { 836 chp = atac->atac_channels[i]; 837 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 838 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 839 DEBUG_DETACH); 840 error = config_detach(chp->atabus, flags); 841 if (error) 842 break; 843 } 844 if (adapt->adapt_refcnt != 0) { 845 #ifdef DIAGNOSTIC 846 printf("wdcdetach: refcnt should be 0 here??\n"); 847 #endif 848 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 849 } 850 return (error); 851 } 852 853 /* restart an interrupted I/O */ 854 void 855 wdcrestart(void *v) 856 { 857 struct ata_channel *chp = v; 858 int s; 859 860 s = splbio(); 861 atastart(chp); 862 splx(s); 863 } 864 865 866 /* 867 * Interrupt routine for the controller. Acknowledge the interrupt, check for 868 * errors on the current operation, mark it done if necessary, and start the 869 * next request. Also check for a partially done transfer, and continue with 870 * the next chunk if so. 871 */ 872 int 873 wdcintr(void *arg) 874 { 875 struct ata_channel *chp = arg; 876 struct atac_softc *atac = chp->ch_atac; 877 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 878 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 879 struct ata_xfer *xfer; 880 int ret; 881 882 if (!device_is_active(&atac->atac_dev)) { 883 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 884 DEBUG_INTR); 885 return (0); 886 } 887 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 888 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 889 /* try to clear the pending interrupt anyway */ 890 (void)bus_space_read_1(wdr->cmd_iot, 891 wdr->cmd_iohs[wd_status], 0); 892 return (0); 893 } 894 895 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 896 xfer = chp->ch_queue->active_xfer; 897 #ifdef DIAGNOSTIC 898 if (xfer == NULL) 899 panic("wdcintr: no xfer"); 900 if (xfer->c_chp != chp) { 901 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 902 chp->ch_channel); 903 panic("wdcintr: wrong channel"); 904 } 905 #endif 906 #if NATA_DMA || NATA_PIOBM 907 if (chp->ch_flags & ATACH_DMA_WAIT) { 908 wdc->dma_status = 909 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 910 xfer->c_drive, WDC_DMAEND_END); 911 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 912 /* IRQ not for us, not detected by DMA engine */ 913 return 0; 914 } 915 chp->ch_flags &= ~ATACH_DMA_WAIT; 916 } 917 #endif 918 chp->ch_flags &= ~ATACH_IRQ_WAIT; 919 ret = xfer->c_intr(chp, xfer, 1); 920 if (ret == 0) /* irq was not for us, still waiting for irq */ 921 chp->ch_flags |= ATACH_IRQ_WAIT; 922 return (ret); 923 } 924 925 /* Put all disk in RESET state */ 926 void 927 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 928 { 929 struct ata_channel *chp = drvp->chnl_softc; 930 struct atac_softc *atac = chp->ch_atac; 931 932 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 933 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 934 DEBUG_FUNCS); 935 936 ata_reset_channel(chp, flags); 937 } 938 939 void 940 wdc_reset_channel(struct ata_channel *chp, int flags) 941 { 942 TAILQ_HEAD(, ata_xfer) reset_xfer; 943 struct ata_xfer *xfer, *next_xfer; 944 #if NATA_DMA || NATA_PIOBM 945 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 946 #endif 947 948 TAILQ_INIT(&reset_xfer); 949 950 chp->ch_flags &= ~ATACH_IRQ_WAIT; 951 952 /* 953 * if the current command if on an ATAPI device, issue a 954 * ATAPI_SOFT_RESET 955 */ 956 xfer = chp->ch_queue->active_xfer; 957 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 958 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 959 if (flags & AT_WAIT) 960 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 961 else 962 delay(1000); 963 } 964 965 /* reset the channel */ 966 if (flags & AT_WAIT) 967 (void) wdcreset(chp, RESET_SLEEP); 968 else 969 (void) wdcreset(chp, RESET_POLL); 970 971 /* 972 * wait a bit after reset; in case the DMA engines needs some time 973 * to recover. 974 */ 975 if (flags & AT_WAIT) 976 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 977 else 978 delay(1000); 979 /* 980 * look for pending xfers. If we have a shared queue, we'll also reset 981 * the other channel if the current xfer is running on it. 982 * Then we'll dequeue only the xfers for this channel. 983 */ 984 if ((flags & AT_RST_NOCMD) == 0) { 985 /* 986 * move all xfers queued for this channel to the reset queue, 987 * and then process the current xfer and then the reset queue. 988 * We have to use a temporary queue because c_kill_xfer() 989 * may requeue commands. 990 */ 991 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 992 xfer != NULL; xfer = next_xfer) { 993 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 994 if (xfer->c_chp != chp) 995 continue; 996 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 997 xfer, c_xferchain); 998 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 999 } 1000 xfer = chp->ch_queue->active_xfer; 1001 if (xfer) { 1002 if (xfer->c_chp != chp) 1003 ata_reset_channel(xfer->c_chp, flags); 1004 else { 1005 callout_stop(&chp->ch_callout); 1006 #if NATA_DMA || NATA_PIOBM 1007 /* 1008 * If we're waiting for DMA, stop the 1009 * DMA engine 1010 */ 1011 if (chp->ch_flags & ATACH_DMA_WAIT) { 1012 (*wdc->dma_finish)( 1013 wdc->dma_arg, 1014 chp->ch_channel, 1015 xfer->c_drive, 1016 WDC_DMAEND_ABRT_QUIET); 1017 chp->ch_flags &= ~ATACH_DMA_WAIT; 1018 } 1019 #endif 1020 chp->ch_queue->active_xfer = NULL; 1021 if ((flags & AT_RST_EMERG) == 0) 1022 xfer->c_kill_xfer( 1023 chp, xfer, KILL_RESET); 1024 } 1025 } 1026 1027 for (xfer = TAILQ_FIRST(&reset_xfer); 1028 xfer != NULL; xfer = next_xfer) { 1029 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1030 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1031 if ((flags & AT_RST_EMERG) == 0) 1032 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1033 } 1034 } 1035 } 1036 1037 static int 1038 wdcreset(struct ata_channel *chp, int poll) 1039 { 1040 struct atac_softc *atac = chp->ch_atac; 1041 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1042 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1043 int drv_mask1, drv_mask2; 1044 1045 wdc->reset(chp, poll); 1046 1047 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1048 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1049 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1050 (poll == RESET_SLEEP) ? 0 : 1); 1051 if (drv_mask2 != drv_mask1) { 1052 printf("%s channel %d: reset failed for", 1053 atac->atac_dev.dv_xname, chp->ch_channel); 1054 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1055 printf(" drive 0"); 1056 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1057 printf(" drive 1"); 1058 printf("\n"); 1059 } 1060 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1061 return (drv_mask1 != drv_mask2) ? 1 : 0; 1062 } 1063 1064 void 1065 wdc_do_reset(struct ata_channel *chp, int poll) 1066 { 1067 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1068 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1069 int s = 0; 1070 1071 if (poll != RESET_SLEEP) 1072 s = splbio(); 1073 if (wdc->select) 1074 wdc->select(chp,0); 1075 /* master */ 1076 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1077 delay(10); /* 400ns delay */ 1078 /* assert SRST, wait for reset to complete */ 1079 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1080 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1081 delay(2000); 1082 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1083 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1084 WDCTL_4BIT | WDCTL_IDS); 1085 delay(10); /* 400ns delay */ 1086 if (poll != RESET_SLEEP) { 1087 /* ACK interrupt in case there is one pending left */ 1088 if (wdc->irqack) 1089 wdc->irqack(chp); 1090 splx(s); 1091 } 1092 } 1093 1094 static int 1095 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1096 { 1097 struct atac_softc *atac = chp->ch_atac; 1098 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1099 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1100 int timeout, nloop; 1101 u_int8_t st0 = 0, st1 = 0; 1102 #ifdef ATADEBUG 1103 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1104 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1105 #endif 1106 1107 if (poll) 1108 nloop = WDCNDELAY_RST; 1109 else 1110 nloop = WDC_RESET_WAIT * hz / 1000; 1111 /* wait for BSY to deassert */ 1112 for (timeout = 0; timeout < nloop; timeout++) { 1113 if ((drv_mask & 0x01) != 0) { 1114 if (wdc->select) 1115 wdc->select(chp,0); 1116 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1117 0, WDSD_IBM); /* master */ 1118 delay(10); 1119 st0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_status], 0); 1121 #ifdef ATADEBUG 1122 sc0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_seccnt], 0); 1124 sn0 = bus_space_read_1(wdr->cmd_iot, 1125 wdr->cmd_iohs[wd_sector], 0); 1126 cl0 = bus_space_read_1(wdr->cmd_iot, 1127 wdr->cmd_iohs[wd_cyl_lo], 0); 1128 ch0 = bus_space_read_1(wdr->cmd_iot, 1129 wdr->cmd_iohs[wd_cyl_hi], 0); 1130 #endif 1131 } 1132 if ((drv_mask & 0x02) != 0) { 1133 if (wdc->select) 1134 wdc->select(chp,1); 1135 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1136 0, WDSD_IBM | 0x10); /* slave */ 1137 delay(10); 1138 st1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_status], 0); 1140 #ifdef ATADEBUG 1141 sc1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_seccnt], 0); 1143 sn1 = bus_space_read_1(wdr->cmd_iot, 1144 wdr->cmd_iohs[wd_sector], 0); 1145 cl1 = bus_space_read_1(wdr->cmd_iot, 1146 wdr->cmd_iohs[wd_cyl_lo], 0); 1147 ch1 = bus_space_read_1(wdr->cmd_iot, 1148 wdr->cmd_iohs[wd_cyl_hi], 0); 1149 #endif 1150 } 1151 1152 if ((drv_mask & 0x01) == 0) { 1153 /* no master */ 1154 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1155 /* No master, slave is ready, it's done */ 1156 goto end; 1157 } 1158 if ((drv_mask & 0x02) == 0) { 1159 /* No master, no slave: it's done */ 1160 goto end; 1161 } 1162 } else if ((drv_mask & 0x02) == 0) { 1163 /* no slave */ 1164 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1165 /* No slave, master is ready, it's done */ 1166 goto end; 1167 } 1168 } else { 1169 /* Wait for both master and slave to be ready */ 1170 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1171 goto end; 1172 } 1173 } 1174 if (poll) 1175 delay(WDCDELAY); 1176 else 1177 tsleep(&nloop, PRIBIO, "atarst", 1); 1178 } 1179 /* Reset timed out. Maybe it's because drv_mask was not right */ 1180 if (st0 & WDCS_BSY) 1181 drv_mask &= ~0x01; 1182 if (st1 & WDCS_BSY) 1183 drv_mask &= ~0x02; 1184 end: 1185 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1186 "cl=0x%x ch=0x%x\n", 1187 atac->atac_dev.dv_xname, 1188 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1189 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1190 "cl=0x%x ch=0x%x\n", 1191 atac->atac_dev.dv_xname, 1192 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1193 1194 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1195 atac->atac_dev.dv_xname, chp->ch_channel, 1196 st0, st1), DEBUG_PROBE); 1197 1198 return drv_mask; 1199 } 1200 1201 /* 1202 * Wait for a drive to be !BSY, and have mask in its status register. 1203 * return -1 for a timeout after "timeout" ms. 1204 */ 1205 static int 1206 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1207 { 1208 struct atac_softc *atac = chp->ch_atac; 1209 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1210 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1211 u_char status; 1212 int xtime = 0; 1213 1214 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1215 atac->atac_dev.dv_xname, 1216 chp->ch_channel), DEBUG_STATUS); 1217 chp->ch_error = 0; 1218 1219 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1220 1221 for (;;) { 1222 chp->ch_status = status = 1223 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1224 if ((status & (WDCS_BSY | mask)) == bits) 1225 break; 1226 if (++xtime > timeout) { 1227 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1228 "status %x error %x (mask 0x%x bits 0x%x)\n", 1229 xtime, status, 1230 bus_space_read_1(wdr->cmd_iot, 1231 wdr->cmd_iohs[wd_error], 0), mask, bits), 1232 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1233 return(WDCWAIT_TOUT); 1234 } 1235 delay(WDCDELAY); 1236 } 1237 #ifdef ATADEBUG 1238 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1239 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1240 #endif 1241 if (status & WDCS_ERR) 1242 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1243 wdr->cmd_iohs[wd_error], 0); 1244 #ifdef WDCNDELAY_DEBUG 1245 /* After autoconfig, there should be no long delays. */ 1246 if (!cold && xtime > WDCNDELAY_DEBUG) { 1247 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1248 if (xfer == NULL) 1249 printf("%s channel %d: warning: busy-wait took %dus\n", 1250 atac->atac_dev.dv_xname, chp->ch_channel, 1251 WDCDELAY * xtime); 1252 else 1253 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1254 atac->atac_dev.dv_xname, chp->ch_channel, 1255 xfer->c_drive, 1256 WDCDELAY * xtime); 1257 } 1258 #endif 1259 return(WDCWAIT_OK); 1260 } 1261 1262 /* 1263 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1264 * thread if possible 1265 */ 1266 int 1267 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1268 { 1269 int error, i, timeout_hz = mstohz(timeout); 1270 1271 if (timeout_hz == 0 || 1272 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1273 error = __wdcwait(chp, mask, bits, timeout); 1274 else { 1275 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1276 if (error != 0) { 1277 if ((chp->ch_flags & ATACH_TH_RUN) || 1278 (flags & AT_WAIT)) { 1279 /* 1280 * we're running in the channel thread 1281 * or some userland thread context 1282 */ 1283 for (i = 0; i < timeout_hz; i++) { 1284 if (__wdcwait(chp, mask, bits, 1285 WDCDELAY_POLL) == 0) { 1286 error = 0; 1287 break; 1288 } 1289 tsleep(&chp, PRIBIO, "atapoll", 1); 1290 } 1291 } else { 1292 /* 1293 * we're probably in interrupt context, 1294 * ask the thread to come back here 1295 */ 1296 #ifdef DIAGNOSTIC 1297 if (chp->ch_queue->queue_freeze > 0) 1298 panic("wdcwait: queue_freeze"); 1299 #endif 1300 chp->ch_queue->queue_freeze++; 1301 wakeup(&chp->ch_thread); 1302 return(WDCWAIT_THR); 1303 } 1304 } 1305 } 1306 return (error); 1307 } 1308 1309 1310 #if NATA_DMA 1311 /* 1312 * Busy-wait for DMA to complete 1313 */ 1314 int 1315 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1316 { 1317 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1318 int xtime; 1319 1320 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1321 wdc->dma_status = 1322 (*wdc->dma_finish)(wdc->dma_arg, 1323 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1324 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1325 return 0; 1326 delay(WDCDELAY); 1327 } 1328 /* timeout, force a DMA halt */ 1329 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1330 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1331 return 1; 1332 } 1333 #endif 1334 1335 void 1336 wdctimeout(void *arg) 1337 { 1338 struct ata_channel *chp = (struct ata_channel *)arg; 1339 #if NATA_DMA || NATA_PIOBM 1340 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1341 #endif 1342 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1343 int s; 1344 1345 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1346 1347 s = splbio(); 1348 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1349 __wdcerror(chp, "lost interrupt"); 1350 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1351 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1352 xfer->c_bcount, 1353 xfer->c_skip); 1354 #if NATA_DMA || NATA_PIOBM 1355 if (chp->ch_flags & ATACH_DMA_WAIT) { 1356 wdc->dma_status = 1357 (*wdc->dma_finish)(wdc->dma_arg, 1358 chp->ch_channel, xfer->c_drive, 1359 WDC_DMAEND_ABRT); 1360 chp->ch_flags &= ~ATACH_DMA_WAIT; 1361 } 1362 #endif 1363 /* 1364 * Call the interrupt routine. If we just missed an interrupt, 1365 * it will do what's needed. Else, it will take the needed 1366 * action (reset the device). 1367 * Before that we need to reinstall the timeout callback, 1368 * in case it will miss another irq while in this transfer 1369 * We arbitray chose it to be 1s 1370 */ 1371 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1372 xfer->c_flags |= C_TIMEOU; 1373 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1374 xfer->c_intr(chp, xfer, 1); 1375 } else 1376 __wdcerror(chp, "missing untimeout"); 1377 splx(s); 1378 } 1379 1380 int 1381 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1382 { 1383 struct ata_channel *chp = drvp->chnl_softc; 1384 struct atac_softc *atac = chp->ch_atac; 1385 struct ata_xfer *xfer; 1386 int s, ret; 1387 1388 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1389 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1390 DEBUG_FUNCS); 1391 1392 /* set up an xfer and queue. Wait for completion */ 1393 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1394 ATAXF_NOSLEEP); 1395 if (xfer == NULL) { 1396 return ATACMD_TRY_AGAIN; 1397 } 1398 1399 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1400 ata_c->flags |= AT_POLL; 1401 if (ata_c->flags & AT_POLL) 1402 xfer->c_flags |= C_POLL; 1403 if (ata_c->flags & AT_WAIT) 1404 xfer->c_flags |= C_WAIT; 1405 xfer->c_drive = drvp->drive; 1406 xfer->c_databuf = ata_c->data; 1407 xfer->c_bcount = ata_c->bcount; 1408 xfer->c_cmd = ata_c; 1409 xfer->c_start = __wdccommand_start; 1410 xfer->c_intr = __wdccommand_intr; 1411 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1412 1413 s = splbio(); 1414 ata_exec_xfer(chp, xfer); 1415 #ifdef DIAGNOSTIC 1416 if ((ata_c->flags & AT_POLL) != 0 && 1417 (ata_c->flags & AT_DONE) == 0) 1418 panic("wdc_exec_command: polled command not done"); 1419 #endif 1420 if (ata_c->flags & AT_DONE) { 1421 ret = ATACMD_COMPLETE; 1422 } else { 1423 if (ata_c->flags & AT_WAIT) { 1424 while ((ata_c->flags & AT_DONE) == 0) { 1425 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1426 } 1427 ret = ATACMD_COMPLETE; 1428 } else { 1429 ret = ATACMD_QUEUED; 1430 } 1431 } 1432 splx(s); 1433 return ret; 1434 } 1435 1436 static void 1437 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1438 { 1439 struct atac_softc *atac = chp->ch_atac; 1440 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1441 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1442 int drive = xfer->c_drive; 1443 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1444 struct ata_command *ata_c = xfer->c_cmd; 1445 1446 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1447 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1448 DEBUG_FUNCS); 1449 1450 if (wdc->select) 1451 wdc->select(chp,drive); 1452 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1453 WDSD_IBM | (drive << 4)); 1454 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1455 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1456 case WDCWAIT_OK: 1457 break; 1458 case WDCWAIT_TOUT: 1459 ata_c->flags |= AT_TIMEOU; 1460 __wdccommand_done(chp, xfer); 1461 return; 1462 case WDCWAIT_THR: 1463 return; 1464 } 1465 if (ata_c->flags & AT_POLL) { 1466 /* polled command, disable interrupts */ 1467 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1468 WDCTL_4BIT | WDCTL_IDS); 1469 } 1470 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1471 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1472 1473 if ((ata_c->flags & AT_POLL) == 0) { 1474 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1475 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1476 wdctimeout, chp); 1477 return; 1478 } 1479 /* 1480 * Polled command. Wait for drive ready or drq. Done in intr(). 1481 * Wait for at last 400ns for status bit to be valid. 1482 */ 1483 delay(10); /* 400ns delay */ 1484 __wdccommand_intr(chp, xfer, 0); 1485 } 1486 1487 static int 1488 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1489 { 1490 struct atac_softc *atac = chp->ch_atac; 1491 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1492 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1493 struct ata_command *ata_c = xfer->c_cmd; 1494 int bcount = ata_c->bcount; 1495 char *data = ata_c->data; 1496 int wflags; 1497 int drive_flags; 1498 1499 if (ata_c->r_command == WDCC_IDENTIFY || 1500 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1501 /* 1502 * The IDENTIFY data has been designed as an array of 1503 * u_int16_t, so we can byteswap it on the fly. 1504 * Historically it's what we have always done so keeping it 1505 * here ensure binary backward compatibility. 1506 */ 1507 drive_flags = DRIVE_NOSTREAM | 1508 chp->ch_drive[xfer->c_drive].drive_flags; 1509 } else { 1510 /* 1511 * Other data structure are opaque and should be transfered 1512 * as is. 1513 */ 1514 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1515 } 1516 1517 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1518 /* both wait and poll, we can tsleep here */ 1519 wflags = AT_WAIT | AT_POLL; 1520 } else { 1521 wflags = AT_POLL; 1522 } 1523 1524 again: 1525 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1526 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1527 DEBUG_INTR); 1528 /* 1529 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1530 * Reselect again, it doesn't hurt for others commands, and the time 1531 * penalty for the extra regiter write is acceptable, 1532 * wdc_exec_command() isn't called often (mosly for autoconfig) 1533 */ 1534 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1535 WDSD_IBM | (xfer->c_drive << 4)); 1536 if ((ata_c->flags & AT_XFDONE) != 0) { 1537 /* 1538 * We have completed a data xfer. The drive should now be 1539 * in its initial state 1540 */ 1541 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1542 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1543 wflags) == WDCWAIT_TOUT) { 1544 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1545 return 0; /* IRQ was not for us */ 1546 ata_c->flags |= AT_TIMEOU; 1547 } 1548 goto out; 1549 } 1550 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1551 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1552 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1553 return 0; /* IRQ was not for us */ 1554 ata_c->flags |= AT_TIMEOU; 1555 goto out; 1556 } 1557 if (wdc->irqack) 1558 wdc->irqack(chp); 1559 if (ata_c->flags & AT_READ) { 1560 if ((chp->ch_status & WDCS_DRQ) == 0) { 1561 ata_c->flags |= AT_TIMEOU; 1562 goto out; 1563 } 1564 wdc->datain_pio(chp, drive_flags, data, bcount); 1565 /* at this point the drive should be in its initial state */ 1566 ata_c->flags |= AT_XFDONE; 1567 /* 1568 * XXX checking the status register again here cause some 1569 * hardware to timeout. 1570 */ 1571 } else if (ata_c->flags & AT_WRITE) { 1572 if ((chp->ch_status & WDCS_DRQ) == 0) { 1573 ata_c->flags |= AT_TIMEOU; 1574 goto out; 1575 } 1576 wdc->dataout_pio(chp, drive_flags, data, bcount); 1577 ata_c->flags |= AT_XFDONE; 1578 if ((ata_c->flags & AT_POLL) == 0) { 1579 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1580 callout_reset(&chp->ch_callout, 1581 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1582 return 1; 1583 } else { 1584 goto again; 1585 } 1586 } 1587 out: 1588 __wdccommand_done(chp, xfer); 1589 return 1; 1590 } 1591 1592 static void 1593 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1594 { 1595 struct atac_softc *atac = chp->ch_atac; 1596 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1597 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1598 struct ata_command *ata_c = xfer->c_cmd; 1599 1600 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1601 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1602 ata_c->flags), DEBUG_FUNCS); 1603 1604 1605 if (chp->ch_status & WDCS_DWF) 1606 ata_c->flags |= AT_DF; 1607 if (chp->ch_status & WDCS_ERR) { 1608 ata_c->flags |= AT_ERROR; 1609 ata_c->r_error = chp->ch_error; 1610 } 1611 if ((ata_c->flags & AT_READREG) != 0 && 1612 device_is_active(&atac->atac_dev) && 1613 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1614 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1615 wdr->cmd_iohs[wd_sdh], 0); 1616 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1617 wdr->cmd_iohs[wd_seccnt], 0); 1618 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1619 wdr->cmd_iohs[wd_sector], 0); 1620 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1621 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1622 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1623 wdr->cmd_iohs[wd_cyl_lo], 0); 1624 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1625 wdr->cmd_iohs[wd_error], 0); 1626 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1627 wdr->cmd_iohs[wd_features], 0); 1628 } 1629 callout_stop(&chp->ch_callout); 1630 chp->ch_queue->active_xfer = NULL; 1631 if (ata_c->flags & AT_POLL) { 1632 /* enable interrupts */ 1633 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1634 WDCTL_4BIT); 1635 delay(10); /* some drives need a little delay here */ 1636 } 1637 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1638 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1639 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1640 wakeup(&chp->ch_queue->active_xfer); 1641 } else 1642 __wdccommand_done_end(chp, xfer); 1643 } 1644 1645 static void 1646 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1647 { 1648 struct ata_command *ata_c = xfer->c_cmd; 1649 1650 ata_c->flags |= AT_DONE; 1651 ata_free_xfer(chp, xfer); 1652 if (ata_c->flags & AT_WAIT) 1653 wakeup(ata_c); 1654 else if (ata_c->callback) 1655 ata_c->callback(ata_c->callback_arg); 1656 atastart(chp); 1657 return; 1658 } 1659 1660 static void 1661 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1662 int reason) 1663 { 1664 struct ata_command *ata_c = xfer->c_cmd; 1665 1666 switch (reason) { 1667 case KILL_GONE: 1668 ata_c->flags |= AT_GONE; 1669 break; 1670 case KILL_RESET: 1671 ata_c->flags |= AT_RESET; 1672 break; 1673 default: 1674 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1675 reason); 1676 panic("__wdccommand_kill_xfer"); 1677 } 1678 __wdccommand_done_end(chp, xfer); 1679 } 1680 1681 /* 1682 * Send a command. The drive should be ready. 1683 * Assumes interrupts are blocked. 1684 */ 1685 void 1686 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1687 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1688 u_int8_t features) 1689 { 1690 struct atac_softc *atac = chp->ch_atac; 1691 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1692 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1693 1694 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1695 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1696 chp->ch_channel, drive, command, cylin, head, sector, count, 1697 features), DEBUG_FUNCS); 1698 1699 if (wdc->select) 1700 wdc->select(chp,drive); 1701 1702 /* Select drive, head, and addressing mode. */ 1703 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1704 WDSD_IBM | (drive << 4) | head); 1705 /* Load parameters into the wd_features register. */ 1706 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1707 features); 1708 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1709 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1710 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1711 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1712 0, cylin >> 8); 1713 1714 /* Send command. */ 1715 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1716 return; 1717 } 1718 1719 /* 1720 * Send a 48-bit addressing command. The drive should be ready. 1721 * Assumes interrupts are blocked. 1722 */ 1723 void 1724 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1725 u_int64_t blkno, u_int16_t count) 1726 { 1727 struct atac_softc *atac = chp->ch_atac; 1728 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1729 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1730 1731 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1732 "count=%d\n", atac->atac_dev.dv_xname, 1733 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1734 DEBUG_FUNCS); 1735 1736 if (wdc->select) 1737 wdc->select(chp,drive); 1738 1739 /* Select drive, head, and addressing mode. */ 1740 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1741 (drive << 4) | WDSD_LBA); 1742 1743 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1744 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1745 0); 1746 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1747 0, count); 1748 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1749 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1750 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1751 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1752 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1753 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1754 } else { 1755 /* previous */ 1756 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1757 0); 1758 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1759 0, count >> 8); 1760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1761 0, blkno >> 24); 1762 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1763 0, blkno >> 32); 1764 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1765 0, blkno >> 40); 1766 1767 /* current */ 1768 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1769 0); 1770 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1771 count); 1772 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1773 blkno); 1774 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1775 0, blkno >> 8); 1776 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1777 0, blkno >> 16); 1778 } 1779 1780 /* Send command. */ 1781 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1782 return; 1783 } 1784 1785 /* 1786 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1787 * tested by the caller. 1788 */ 1789 void 1790 wdccommandshort(struct ata_channel *chp, int drive, int command) 1791 { 1792 struct atac_softc *atac = chp->ch_atac; 1793 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1794 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1795 1796 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1797 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1798 DEBUG_FUNCS); 1799 1800 if (wdc->select) 1801 wdc->select(chp,drive); 1802 1803 /* Select drive. */ 1804 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1805 WDSD_IBM | (drive << 4)); 1806 1807 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1808 } 1809 1810 static void 1811 __wdcerror(struct ata_channel *chp, const char *msg) 1812 { 1813 struct atac_softc *atac = chp->ch_atac; 1814 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1815 1816 if (xfer == NULL) 1817 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1818 msg); 1819 else 1820 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1821 chp->ch_channel, xfer->c_drive, msg); 1822 } 1823 1824 /* 1825 * the bit bucket 1826 */ 1827 void 1828 wdcbit_bucket(struct ata_channel *chp, int size) 1829 { 1830 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1831 1832 for (; size >= 2; size -= 2) 1833 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1834 if (size) 1835 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1836 } 1837 1838 static void 1839 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1840 { 1841 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1842 1843 if (flags & DRIVE_NOSTREAM) { 1844 if (flags & DRIVE_CAP32) { 1845 bus_space_read_multi_4(wdr->data32iot, 1846 wdr->data32ioh, 0, bf, len >> 2); 1847 bf = (char *)bf + (len & ~3); 1848 len &= 3; 1849 } 1850 if (len) { 1851 bus_space_read_multi_2(wdr->cmd_iot, 1852 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1853 } 1854 } else { 1855 if (flags & DRIVE_CAP32) { 1856 bus_space_read_multi_stream_4(wdr->data32iot, 1857 wdr->data32ioh, 0, bf, len >> 2); 1858 bf = (char *)bf + (len & ~3); 1859 len &= 3; 1860 } 1861 if (len) { 1862 bus_space_read_multi_stream_2(wdr->cmd_iot, 1863 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1864 } 1865 } 1866 } 1867 1868 static void 1869 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1870 { 1871 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1872 1873 if (flags & DRIVE_NOSTREAM) { 1874 if (flags & DRIVE_CAP32) { 1875 bus_space_write_multi_4(wdr->data32iot, 1876 wdr->data32ioh, 0, bf, len >> 2); 1877 bf = (char *)bf + (len & ~3); 1878 len &= 3; 1879 } 1880 if (len) { 1881 bus_space_write_multi_2(wdr->cmd_iot, 1882 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1883 } 1884 } else { 1885 if (flags & DRIVE_CAP32) { 1886 bus_space_write_multi_stream_4(wdr->data32iot, 1887 wdr->data32ioh, 0, bf, len >> 2); 1888 bf = (char *)bf + (len & ~3); 1889 len &= 3; 1890 } 1891 if (len) { 1892 bus_space_write_multi_stream_2(wdr->cmd_iot, 1893 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1894 } 1895 } 1896 } 1897
Indexes created Thu Sep 25 16:09:42 GMT 2025