wdc.c revision 1.240
1 /* $NetBSD: wdc.c,v 1.240 2006/10/25 20:14:00 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.240 2006/10/25 20:14:00 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ata/satareg.h> 102 #include <dev/ata/satavar.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "locators.h" 107 108 #include "atapibus.h" 109 #include "wd.h" 110 #include "sata.h" 111 112 #define WDCDELAY 100 /* 100 microseconds */ 113 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 114 #if 0 115 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 116 #define WDCNDELAY_DEBUG 50 117 #endif 118 119 /* When polling wait that much and then tsleep for 1/hz seconds */ 120 #define WDCDELAY_POLL 1 /* ms */ 121 122 /* timeout for the control commands */ 123 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 124 125 /* 126 * timeout when waiting for BSY to deassert when probing. 127 * set to 5s. From the standards this could be up to 31, but we can't 128 * wait that much at boot time, and 5s seems to be enouth. 129 */ 130 #define WDC_PROBE_WAIT 5 131 132 133 #if NWD > 0 134 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 135 #else 136 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 137 const struct ata_bustype wdc_ata_bustype = { 138 SCSIPI_BUSTYPE_ATA, 139 NULL, /* wdc_ata_bio */ 140 NULL, /* wdc_reset_drive */ 141 wdc_reset_channel, 142 wdc_exec_command, 143 NULL, /* ata_get_params */ 144 NULL, /* wdc_ata_addref */ 145 NULL, /* wdc_ata_delref */ 146 NULL /* ata_kill_pending */ 147 }; 148 #endif 149 150 /* Flags to wdcreset(). */ 151 #define RESET_POLL 1 152 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 153 154 static int wdcprobe1(struct ata_channel *, int); 155 static int wdcreset(struct ata_channel *, int); 156 static void __wdcerror(struct ata_channel *, const char *); 157 static int __wdcwait_reset(struct ata_channel *, int, int); 158 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 159 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 160 static void __wdccommand_kill_xfer(struct ata_channel *, 161 struct ata_xfer *, int); 162 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 163 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 164 static int __wdcwait(struct ata_channel *, int, int, int); 165 166 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 167 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 168 169 #define DEBUG_INTR 0x01 170 #define DEBUG_XFERS 0x02 171 #define DEBUG_STATUS 0x04 172 #define DEBUG_FUNCS 0x08 173 #define DEBUG_PROBE 0x10 174 #define DEBUG_DETACH 0x20 175 #define DEBUG_DELAY 0x40 176 #ifdef ATADEBUG 177 extern int atadebug_mask; /* init'ed in ata.c */ 178 int wdc_nxfer = 0; 179 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 180 #else 181 #define ATADEBUG_PRINT(args, level) 182 #endif 183 184 /* 185 * Initialize the "shadow register" handles for a standard wdc controller. 186 */ 187 void 188 wdc_init_shadow_regs(struct ata_channel *chp) 189 { 190 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 191 192 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 193 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 194 } 195 196 /* 197 * Allocate a wdc_regs array, based on the number of channels. 198 */ 199 void 200 wdc_allocate_regs(struct wdc_softc *wdc) 201 { 202 203 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 204 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 205 } 206 207 #if NSATA > 0 208 /* 209 * probe drives on SATA controllers with standard SATA registers: 210 * bring the PHYs online, read the drive signature and set drive flags 211 * appropriately. 212 */ 213 void 214 wdc_sataprobe(struct ata_channel *chp) 215 { 216 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 217 uint32_t scontrol, sstatus; 218 uint16_t scnt, sn, cl, ch; 219 int i, s; 220 221 /* XXX This should be done by other code. */ 222 for (i = 0; i < chp->ch_ndrive; i++) { 223 chp->ch_drive[i].chnl_softc = chp; 224 chp->ch_drive[i].drive = i; 225 } 226 227 /* bring the PHYs online. 228 * The work-around for errata #1 for the 31244 says that we must 229 * write 0 to the port first to be sure of correctly initializing 230 * the device. It doesn't hurt for other devices. 231 */ 232 bus_space_write_4(wdr->sata_iot, wdr->sata_control, 0, 0); 233 scontrol = SControl_IPM_NONE | SControl_SPD_ANY | SControl_DET_INIT; 234 bus_space_write_4 (wdr->sata_iot, wdr->sata_control, 0, scontrol); 235 236 tsleep(wdr, PRIBIO, "sataup", mstohz(50)); 237 scontrol &= ~SControl_DET_INIT; 238 bus_space_write_4(wdr->sata_iot, wdr->sata_control, 0, scontrol); 239 240 tsleep(wdr, PRIBIO, "sataup", mstohz(50)); 241 sstatus = bus_space_read_4(wdr->sata_iot, wdr->sata_status, 0); 242 243 switch (sstatus & SStatus_DET_mask) { 244 case SStatus_DET_NODEV: 245 /* No Device; be silent. */ 246 break; 247 248 case SStatus_DET_DEV_NE: 249 aprint_error("%s: port %d: device connected, but " 250 "communication not established\n", 251 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel); 252 break; 253 254 case SStatus_DET_OFFLINE: 255 aprint_error("%s: port %d: PHY offline\n", 256 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel); 257 break; 258 259 case SStatus_DET_DEV: 260 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 261 WDSD_IBM); 262 delay(10); /* 400ns delay */ 263 scnt = bus_space_read_2(wdr->cmd_iot, 264 wdr->cmd_iohs[wd_seccnt], 0); 265 sn = bus_space_read_2(wdr->cmd_iot, 266 wdr->cmd_iohs[wd_sector], 0); 267 cl = bus_space_read_2(wdr->cmd_iot, 268 wdr->cmd_iohs[wd_cyl_lo], 0); 269 ch = bus_space_read_2(wdr->cmd_iot, 270 wdr->cmd_iohs[wd_cyl_hi], 0); 271 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 272 "cl=0x%x ch=0x%x\n", 273 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 274 scnt, sn, cl, ch), DEBUG_PROBE); 275 /* 276 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 277 * cases we get wrong values here, so ignore it. 278 */ 279 s = splbio(); 280 if (cl == 0x14 && ch == 0xeb) 281 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 282 else 283 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 284 splx(s); 285 286 aprint_normal("%s: port %d: device present, speed: %s\n", 287 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 288 sata_speed(sstatus)); 289 break; 290 291 default: 292 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 293 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 294 sstatus); 295 } 296 } 297 #endif /* NSATA > 0 */ 298 299 300 /* Test to see controller with at last one attached drive is there. 301 * Returns a bit for each possible drive found (0x01 for drive 0, 302 * 0x02 for drive 1). 303 * Logic: 304 * - If a status register is at 0xff, assume there is no drive here 305 * (ISA has pull-up resistors). Similarly if the status register has 306 * the value we last wrote to the bus (for IDE interfaces without pullups). 307 * If no drive at all -> return. 308 * - reset the controller, wait for it to complete (may take up to 31s !). 309 * If timeout -> return. 310 * - test ATA/ATAPI signatures. If at last one drive found -> return. 311 * - try an ATA command on the master. 312 */ 313 314 void 315 wdc_drvprobe(struct ata_channel *chp) 316 { 317 struct ataparams params; 318 struct atac_softc *atac = chp->ch_atac; 319 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 320 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 321 u_int8_t st0 = 0, st1 = 0; 322 int i, j, error, s; 323 324 if (wdcprobe1(chp, 0) == 0) { 325 /* No drives, abort the attach here. */ 326 return; 327 } 328 329 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 330 for (i = 0; i < mstohz(3000); i++) { 331 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 332 if (wdc->select) 333 wdc->select(chp,0); 334 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 335 0, WDSD_IBM); 336 delay(10); /* 400ns delay */ 337 st0 = bus_space_read_1(wdr->cmd_iot, 338 wdr->cmd_iohs[wd_status], 0); 339 } 340 341 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 342 if (wdc->select) 343 wdc->select(chp,1); 344 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 345 0, WDSD_IBM | 0x10); 346 delay(10); /* 400ns delay */ 347 st1 = bus_space_read_1(wdr->cmd_iot, 348 wdr->cmd_iohs[wd_status], 0); 349 } 350 351 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 352 == 0 || 353 (st0 & WDCS_DRDY)) && 354 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 355 == 0 || 356 (st1 & WDCS_DRDY))) 357 break; 358 tsleep(¶ms, PRIBIO, "atadrdy", 1); 359 } 360 s = splbio(); 361 if ((st0 & WDCS_DRDY) == 0) 362 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 363 if ((st1 & WDCS_DRDY) == 0) 364 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 365 splx(s); 366 367 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 368 atac->atac_dev.dv_xname, 369 chp->ch_channel, st0, st1), DEBUG_PROBE); 370 371 /* Wait a bit, some devices are weird just after a reset. */ 372 delay(5000); 373 374 for (i = 0; i < chp->ch_ndrive; i++) { 375 /* XXX This should be done by other code. */ 376 chp->ch_drive[i].chnl_softc = chp; 377 chp->ch_drive[i].drive = i; 378 379 #if NATA_DMA 380 /* 381 * Init error counter so that an error withing the first xfers 382 * will trigger a downgrade 383 */ 384 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 385 #endif 386 387 /* If controller can't do 16bit flag the drives as 32bit */ 388 if ((atac->atac_cap & 389 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 390 s = splbio(); 391 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 392 splx(s); 393 } 394 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 395 continue; 396 397 /* Shortcut in case we've been shutdown */ 398 if (chp->ch_flags & ATACH_SHUTDOWN) 399 return; 400 401 /* 402 * Issue an identify, to try to detect ghosts. 403 * Note that we can't use interrupts here, because if there 404 * is no devices, we will get a command aborted without 405 * interrupts. 406 */ 407 error = ata_get_params(&chp->ch_drive[i], 408 AT_WAIT | AT_POLL, ¶ms); 409 if (error != CMD_OK) { 410 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 411 412 /* Shortcut in case we've been shutdown */ 413 if (chp->ch_flags & ATACH_SHUTDOWN) 414 return; 415 416 error = ata_get_params(&chp->ch_drive[i], 417 AT_WAIT | AT_POLL, ¶ms); 418 } 419 if (error == CMD_OK) { 420 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 421 s = splbio(); 422 for (j = 0; j < chp->ch_ndrive; j++) 423 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 424 splx(s); 425 } else { 426 s = splbio(); 427 chp->ch_drive[i].drive_flags &= 428 ~(DRIVE_ATA | DRIVE_ATAPI); 429 splx(s); 430 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 431 atac->atac_dev.dv_xname, 432 chp->ch_channel, i, error), DEBUG_PROBE); 433 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 434 continue; 435 /* 436 * Pre-ATA drive ? 437 * Test registers writability (Error register not 438 * writable, but cyllo is), then try an ATA command. 439 */ 440 if (wdc->select) 441 wdc->select(chp,i); 442 bus_space_write_1(wdr->cmd_iot, 443 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 444 delay(10); /* 400ns delay */ 445 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 446 0, 0x58); 447 bus_space_write_1(wdr->cmd_iot, 448 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 449 if (bus_space_read_1(wdr->cmd_iot, 450 wdr->cmd_iohs[wd_error], 0) == 0x58 || 451 bus_space_read_1(wdr->cmd_iot, 452 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 453 ATADEBUG_PRINT(("%s:%d:%d: register " 454 "writability failed\n", 455 atac->atac_dev.dv_xname, 456 chp->ch_channel, i), DEBUG_PROBE); 457 s = splbio(); 458 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 459 splx(s); 460 continue; 461 } 462 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 463 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 464 atac->atac_dev.dv_xname, 465 chp->ch_channel, i), DEBUG_PROBE); 466 s = splbio(); 467 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 468 splx(s); 469 continue; 470 } 471 bus_space_write_1(wdr->cmd_iot, 472 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 473 delay(10); /* 400ns delay */ 474 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 475 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 476 atac->atac_dev.dv_xname, 477 chp->ch_channel, i), DEBUG_PROBE); 478 s = splbio(); 479 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 480 splx(s); 481 } else { 482 s = splbio(); 483 for (j = 0; j < chp->ch_ndrive; j++) 484 chp->ch_drive[j].drive_flags &= 485 ~(DRIVE_ATA | DRIVE_ATAPI); 486 splx(s); 487 } 488 } 489 } 490 } 491 492 int 493 wdcprobe(struct ata_channel *chp) 494 { 495 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 496 /* default reset method */ 497 if (wdc->reset == NULL) 498 wdc->reset = wdc_do_reset; 499 500 return (wdcprobe1(chp, 1)); 501 } 502 503 static int 504 wdcprobe1(struct ata_channel *chp, int poll) 505 { 506 struct atac_softc *atac = chp->ch_atac; 507 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 508 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 509 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 510 u_int8_t ret_value = 0x03; 511 u_int8_t drive; 512 int s; 513 int wdc_probe_count = 514 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 515 516 /* 517 * Sanity check to see if the wdc channel responds at all. 518 */ 519 520 s = splbio(); 521 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 522 while (wdc_probe_count-- > 0) { 523 if (wdc->select) 524 wdc->select(chp,0); 525 526 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 527 0, WDSD_IBM); 528 delay(10); /* 400ns delay */ 529 st0 = bus_space_read_1(wdr->cmd_iot, 530 wdr->cmd_iohs[wd_status], 0); 531 532 if (wdc->select) 533 wdc->select(chp,1); 534 535 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 536 0, WDSD_IBM | 0x10); 537 delay(10); /* 400ns delay */ 538 st1 = bus_space_read_1(wdr->cmd_iot, 539 wdr->cmd_iohs[wd_status], 0); 540 if ((st0 & WDCS_BSY) == 0) 541 break; 542 } 543 544 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 545 atac->atac_dev.dv_xname, 546 chp->ch_channel, st0, st1), DEBUG_PROBE); 547 548 if (st0 == 0xff || st0 == WDSD_IBM) 549 ret_value &= ~0x01; 550 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 551 ret_value &= ~0x02; 552 /* Register writability test, drive 0. */ 553 if (ret_value & 0x01) { 554 if (wdc->select) 555 wdc->select(chp,0); 556 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 557 0, WDSD_IBM); 558 bus_space_write_1(wdr->cmd_iot, 559 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 560 cl = bus_space_read_1(wdr->cmd_iot, 561 wdr->cmd_iohs[wd_cyl_lo], 0); 562 if (cl != 0x02) { 563 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 564 "got 0x%x != 0x02\n", 565 atac->atac_dev.dv_xname, 566 chp->ch_channel, cl), 567 DEBUG_PROBE); 568 ret_value &= ~0x01; 569 } 570 bus_space_write_1(wdr->cmd_iot, 571 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 572 cl = bus_space_read_1(wdr->cmd_iot, 573 wdr->cmd_iohs[wd_cyl_lo], 0); 574 if (cl != 0x01) { 575 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 576 "got 0x%x != 0x01\n", 577 atac->atac_dev.dv_xname, 578 chp->ch_channel, cl), 579 DEBUG_PROBE); 580 ret_value &= ~0x01; 581 } 582 bus_space_write_1(wdr->cmd_iot, 583 wdr->cmd_iohs[wd_sector], 0, 0x01); 584 cl = bus_space_read_1(wdr->cmd_iot, 585 wdr->cmd_iohs[wd_sector], 0); 586 if (cl != 0x01) { 587 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 588 "got 0x%x != 0x01\n", 589 atac->atac_dev.dv_xname, 590 chp->ch_channel, cl), 591 DEBUG_PROBE); 592 ret_value &= ~0x01; 593 } 594 bus_space_write_1(wdr->cmd_iot, 595 wdr->cmd_iohs[wd_sector], 0, 0x02); 596 cl = bus_space_read_1(wdr->cmd_iot, 597 wdr->cmd_iohs[wd_sector], 0); 598 if (cl != 0x02) { 599 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 600 "got 0x%x != 0x02\n", 601 atac->atac_dev.dv_xname, 602 chp->ch_channel, cl), 603 DEBUG_PROBE); 604 ret_value &= ~0x01; 605 } 606 cl = bus_space_read_1(wdr->cmd_iot, 607 wdr->cmd_iohs[wd_cyl_lo], 0); 608 if (cl != 0x01) { 609 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 610 "got 0x%x != 0x01\n", 611 atac->atac_dev.dv_xname, 612 chp->ch_channel, cl), 613 DEBUG_PROBE); 614 ret_value &= ~0x01; 615 } 616 } 617 /* Register writability test, drive 1. */ 618 if (ret_value & 0x02) { 619 if (wdc->select) 620 wdc->select(chp,1); 621 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 622 0, WDSD_IBM | 0x10); 623 bus_space_write_1(wdr->cmd_iot, 624 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 625 cl = bus_space_read_1(wdr->cmd_iot, 626 wdr->cmd_iohs[wd_cyl_lo], 0); 627 if (cl != 0x02) { 628 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 629 "got 0x%x != 0x02\n", 630 atac->atac_dev.dv_xname, 631 chp->ch_channel, cl), 632 DEBUG_PROBE); 633 ret_value &= ~0x02; 634 } 635 bus_space_write_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 637 cl = bus_space_read_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_cyl_lo], 0); 639 if (cl != 0x01) { 640 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 641 "got 0x%x != 0x01\n", 642 atac->atac_dev.dv_xname, 643 chp->ch_channel, cl), 644 DEBUG_PROBE); 645 ret_value &= ~0x02; 646 } 647 bus_space_write_1(wdr->cmd_iot, 648 wdr->cmd_iohs[wd_sector], 0, 0x01); 649 cl = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_sector], 0); 651 if (cl != 0x01) { 652 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 653 "got 0x%x != 0x01\n", 654 atac->atac_dev.dv_xname, 655 chp->ch_channel, cl), 656 DEBUG_PROBE); 657 ret_value &= ~0x02; 658 } 659 bus_space_write_1(wdr->cmd_iot, 660 wdr->cmd_iohs[wd_sector], 0, 0x02); 661 cl = bus_space_read_1(wdr->cmd_iot, 662 wdr->cmd_iohs[wd_sector], 0); 663 if (cl != 0x02) { 664 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 665 "got 0x%x != 0x02\n", 666 atac->atac_dev.dv_xname, 667 chp->ch_channel, cl), 668 DEBUG_PROBE); 669 ret_value &= ~0x02; 670 } 671 cl = bus_space_read_1(wdr->cmd_iot, 672 wdr->cmd_iohs[wd_cyl_lo], 0); 673 if (cl != 0x01) { 674 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 675 "got 0x%x != 0x01\n", 676 atac->atac_dev.dv_xname, 677 chp->ch_channel, cl), 678 DEBUG_PROBE); 679 ret_value &= ~0x02; 680 } 681 } 682 683 if (ret_value == 0) { 684 splx(s); 685 return 0; 686 } 687 } 688 689 690 #if 0 /* XXX this break some ATA or ATAPI devices */ 691 /* 692 * reset bus. Also send an ATAPI_RESET to devices, in case there are 693 * ATAPI device out there which don't react to the bus reset 694 */ 695 if (ret_value & 0x01) { 696 if (wdc->select) 697 wdc->select(chp,0); 698 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 699 0, WDSD_IBM); 700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 701 ATAPI_SOFT_RESET); 702 } 703 if (ret_value & 0x02) { 704 if (wdc->select) 705 wdc->select(chp,0); 706 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 707 0, WDSD_IBM | 0x10); 708 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 709 ATAPI_SOFT_RESET); 710 } 711 712 delay(5000); 713 #endif 714 715 wdc->reset(chp, RESET_POLL); 716 DELAY(2000); 717 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 718 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 719 splx(s); 720 721 ret_value = __wdcwait_reset(chp, ret_value, poll); 722 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 723 atac->atac_dev.dv_xname, chp->ch_channel, 724 ret_value), DEBUG_PROBE); 725 726 /* if reset failed, there's nothing here */ 727 if (ret_value == 0) 728 return 0; 729 730 /* 731 * Test presence of drives. First test register signatures looking 732 * for ATAPI devices. If it's not an ATAPI and reset said there may 733 * be something here assume it's ATA or OLD. Ghost will be killed 734 * later in attach routine. 735 */ 736 for (drive = 0; drive < chp->ch_ndrive; drive++) { 737 if ((ret_value & (0x01 << drive)) == 0) 738 continue; 739 if (wdc->select) 740 wdc->select(chp,drive); 741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 742 WDSD_IBM | (drive << 4)); 743 delay(10); /* 400ns delay */ 744 /* Save registers contents */ 745 sc = bus_space_read_1(wdr->cmd_iot, 746 wdr->cmd_iohs[wd_seccnt], 0); 747 sn = bus_space_read_1(wdr->cmd_iot, 748 wdr->cmd_iohs[wd_sector], 0); 749 cl = bus_space_read_1(wdr->cmd_iot, 750 wdr->cmd_iohs[wd_cyl_lo], 0); 751 ch = bus_space_read_1(wdr->cmd_iot, 752 wdr->cmd_iohs[wd_cyl_hi], 0); 753 754 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 755 "cl=0x%x ch=0x%x\n", 756 atac->atac_dev.dv_xname, 757 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 758 /* 759 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 760 * we get wrong values here, so ignore it. 761 */ 762 s = splbio(); 763 if (cl == 0x14 && ch == 0xeb) { 764 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 765 } else { 766 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 767 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 768 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 769 } 770 splx(s); 771 } 772 return (ret_value); 773 } 774 775 void 776 wdcattach(struct ata_channel *chp) 777 { 778 struct atac_softc *atac = chp->ch_atac; 779 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 780 781 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 782 783 /* default data transfer methods */ 784 if (wdc->datain_pio == NULL) 785 wdc->datain_pio = wdc_datain_pio; 786 if (wdc->dataout_pio == NULL) 787 wdc->dataout_pio = wdc_dataout_pio; 788 /* default reset method */ 789 if (wdc->reset == NULL) 790 wdc->reset = wdc_do_reset; 791 792 /* initialise global data */ 793 if (atac->atac_bustype_ata == NULL) 794 atac->atac_bustype_ata = &wdc_ata_bustype; 795 if (atac->atac_probe == NULL) 796 atac->atac_probe = wdc_drvprobe; 797 #if NATAPIBUS > 0 798 if (atac->atac_atapibus_attach == NULL) 799 atac->atac_atapibus_attach = wdc_atapibus_attach; 800 #endif 801 802 ata_channel_attach(chp); 803 } 804 805 int 806 wdcactivate(struct device *self, enum devact act) 807 { 808 struct atac_softc *atac = (struct atac_softc *) self; 809 int s, i, error = 0; 810 811 s = splbio(); 812 switch (act) { 813 case DVACT_ACTIVATE: 814 error = EOPNOTSUPP; 815 break; 816 817 case DVACT_DEACTIVATE: 818 for (i = 0; i < atac->atac_nchannels; i++) { 819 error = 820 config_deactivate(atac->atac_channels[i]->atabus); 821 if (error) 822 break; 823 } 824 break; 825 } 826 splx(s); 827 return (error); 828 } 829 830 int 831 wdcdetach(struct device *self, int flags) 832 { 833 struct atac_softc *atac = (struct atac_softc *) self; 834 struct ata_channel *chp; 835 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 836 int i, error = 0; 837 838 for (i = 0; i < atac->atac_nchannels; i++) { 839 chp = atac->atac_channels[i]; 840 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 841 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 842 DEBUG_DETACH); 843 error = config_detach(chp->atabus, flags); 844 if (error) 845 break; 846 } 847 if (adapt->adapt_refcnt != 0) { 848 #ifdef DIAGNOSTIC 849 printf("wdcdetach: refcnt should be 0 here??\n"); 850 #endif 851 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 852 } 853 return (error); 854 } 855 856 /* restart an interrupted I/O */ 857 void 858 wdcrestart(void *v) 859 { 860 struct ata_channel *chp = v; 861 int s; 862 863 s = splbio(); 864 atastart(chp); 865 splx(s); 866 } 867 868 869 /* 870 * Interrupt routine for the controller. Acknowledge the interrupt, check for 871 * errors on the current operation, mark it done if necessary, and start the 872 * next request. Also check for a partially done transfer, and continue with 873 * the next chunk if so. 874 */ 875 int 876 wdcintr(void *arg) 877 { 878 struct ata_channel *chp = arg; 879 struct atac_softc *atac = chp->ch_atac; 880 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 881 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 882 struct ata_xfer *xfer; 883 int ret; 884 885 if (!device_is_active(&atac->atac_dev)) { 886 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 887 DEBUG_INTR); 888 return (0); 889 } 890 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 891 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 892 /* try to clear the pending interrupt anyway */ 893 (void)bus_space_read_1(wdr->cmd_iot, 894 wdr->cmd_iohs[wd_status], 0); 895 return (0); 896 } 897 898 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 899 xfer = chp->ch_queue->active_xfer; 900 #ifdef DIAGNOSTIC 901 if (xfer == NULL) 902 panic("wdcintr: no xfer"); 903 if (xfer->c_chp != chp) { 904 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 905 chp->ch_channel); 906 panic("wdcintr: wrong channel"); 907 } 908 #endif 909 #if NATA_DMA || NATA_PIOBM 910 if (chp->ch_flags & ATACH_DMA_WAIT) { 911 wdc->dma_status = 912 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 913 xfer->c_drive, WDC_DMAEND_END); 914 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 915 /* IRQ not for us, not detected by DMA engine */ 916 return 0; 917 } 918 chp->ch_flags &= ~ATACH_DMA_WAIT; 919 } 920 #endif 921 chp->ch_flags &= ~ATACH_IRQ_WAIT; 922 ret = xfer->c_intr(chp, xfer, 1); 923 if (ret == 0) /* irq was not for us, still waiting for irq */ 924 chp->ch_flags |= ATACH_IRQ_WAIT; 925 return (ret); 926 } 927 928 /* Put all disk in RESET state */ 929 void 930 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 931 { 932 struct ata_channel *chp = drvp->chnl_softc; 933 struct atac_softc *atac = chp->ch_atac; 934 935 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 936 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 937 DEBUG_FUNCS); 938 939 ata_reset_channel(chp, flags); 940 } 941 942 void 943 wdc_reset_channel(struct ata_channel *chp, int flags) 944 { 945 TAILQ_HEAD(, ata_xfer) reset_xfer; 946 struct ata_xfer *xfer, *next_xfer; 947 #if NATA_DMA || NATA_PIOBM 948 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 949 #endif 950 951 TAILQ_INIT(&reset_xfer); 952 953 chp->ch_flags &= ~ATACH_IRQ_WAIT; 954 955 /* 956 * if the current command if on an ATAPI device, issue a 957 * ATAPI_SOFT_RESET 958 */ 959 xfer = chp->ch_queue->active_xfer; 960 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 961 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 962 if (flags & AT_WAIT) 963 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 964 else 965 delay(1000); 966 } 967 968 /* reset the channel */ 969 if (flags & AT_WAIT) 970 (void) wdcreset(chp, RESET_SLEEP); 971 else 972 (void) wdcreset(chp, RESET_POLL); 973 974 /* 975 * wait a bit after reset; in case the DMA engines needs some time 976 * to recover. 977 */ 978 if (flags & AT_WAIT) 979 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 980 else 981 delay(1000); 982 /* 983 * look for pending xfers. If we have a shared queue, we'll also reset 984 * the other channel if the current xfer is running on it. 985 * Then we'll dequeue only the xfers for this channel. 986 */ 987 if ((flags & AT_RST_NOCMD) == 0) { 988 /* 989 * move all xfers queued for this channel to the reset queue, 990 * and then process the current xfer and then the reset queue. 991 * We have to use a temporary queue because c_kill_xfer() 992 * may requeue commands. 993 */ 994 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 995 xfer != NULL; xfer = next_xfer) { 996 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 997 if (xfer->c_chp != chp) 998 continue; 999 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 1000 xfer, c_xferchain); 1001 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 1002 } 1003 xfer = chp->ch_queue->active_xfer; 1004 if (xfer) { 1005 if (xfer->c_chp != chp) 1006 ata_reset_channel(xfer->c_chp, flags); 1007 else { 1008 callout_stop(&chp->ch_callout); 1009 #if NATA_DMA || NATA_PIOBM 1010 /* 1011 * If we're waiting for DMA, stop the 1012 * DMA engine 1013 */ 1014 if (chp->ch_flags & ATACH_DMA_WAIT) { 1015 (*wdc->dma_finish)( 1016 wdc->dma_arg, 1017 chp->ch_channel, 1018 xfer->c_drive, 1019 WDC_DMAEND_ABRT_QUIET); 1020 chp->ch_flags &= ~ATACH_DMA_WAIT; 1021 } 1022 #endif 1023 chp->ch_queue->active_xfer = NULL; 1024 if ((flags & AT_RST_EMERG) == 0) 1025 xfer->c_kill_xfer( 1026 chp, xfer, KILL_RESET); 1027 } 1028 } 1029 1030 for (xfer = TAILQ_FIRST(&reset_xfer); 1031 xfer != NULL; xfer = next_xfer) { 1032 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1033 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1034 if ((flags & AT_RST_EMERG) == 0) 1035 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1036 } 1037 } 1038 } 1039 1040 static int 1041 wdcreset(struct ata_channel *chp, int poll) 1042 { 1043 struct atac_softc *atac = chp->ch_atac; 1044 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1045 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1046 int drv_mask1, drv_mask2; 1047 1048 wdc->reset(chp, poll); 1049 1050 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1051 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1052 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1053 (poll == RESET_SLEEP) ? 0 : 1); 1054 if (drv_mask2 != drv_mask1) { 1055 printf("%s channel %d: reset failed for", 1056 atac->atac_dev.dv_xname, chp->ch_channel); 1057 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1058 printf(" drive 0"); 1059 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1060 printf(" drive 1"); 1061 printf("\n"); 1062 } 1063 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1064 return (drv_mask1 != drv_mask2) ? 1 : 0; 1065 } 1066 1067 void 1068 wdc_do_reset(struct ata_channel *chp, int poll) 1069 { 1070 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1071 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1072 int s = 0; 1073 1074 if (poll != RESET_SLEEP) 1075 s = splbio(); 1076 if (wdc->select) 1077 wdc->select(chp,0); 1078 /* master */ 1079 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1080 delay(10); /* 400ns delay */ 1081 /* assert SRST, wait for reset to complete */ 1082 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1083 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1084 delay(2000); 1085 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1086 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1087 WDCTL_4BIT | WDCTL_IDS); 1088 delay(10); /* 400ns delay */ 1089 if (poll != RESET_SLEEP) { 1090 /* ACK interrupt in case there is one pending left */ 1091 if (wdc->irqack) 1092 wdc->irqack(chp); 1093 splx(s); 1094 } 1095 } 1096 1097 static int 1098 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1099 { 1100 struct atac_softc *atac = chp->ch_atac; 1101 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1102 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1103 int timeout, nloop; 1104 u_int8_t st0 = 0, st1 = 0; 1105 #ifdef ATADEBUG 1106 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1107 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1108 #endif 1109 1110 if (poll) 1111 nloop = WDCNDELAY_RST; 1112 else 1113 nloop = WDC_RESET_WAIT * hz / 1000; 1114 /* wait for BSY to deassert */ 1115 for (timeout = 0; timeout < nloop; timeout++) { 1116 if ((drv_mask & 0x01) != 0) { 1117 if (wdc->select) 1118 wdc->select(chp,0); 1119 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1120 0, WDSD_IBM); /* master */ 1121 delay(10); 1122 st0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_status], 0); 1124 #ifdef ATADEBUG 1125 sc0 = bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_seccnt], 0); 1127 sn0 = bus_space_read_1(wdr->cmd_iot, 1128 wdr->cmd_iohs[wd_sector], 0); 1129 cl0 = bus_space_read_1(wdr->cmd_iot, 1130 wdr->cmd_iohs[wd_cyl_lo], 0); 1131 ch0 = bus_space_read_1(wdr->cmd_iot, 1132 wdr->cmd_iohs[wd_cyl_hi], 0); 1133 #endif 1134 } 1135 if ((drv_mask & 0x02) != 0) { 1136 if (wdc->select) 1137 wdc->select(chp,1); 1138 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1139 0, WDSD_IBM | 0x10); /* slave */ 1140 delay(10); 1141 st1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_status], 0); 1143 #ifdef ATADEBUG 1144 sc1 = bus_space_read_1(wdr->cmd_iot, 1145 wdr->cmd_iohs[wd_seccnt], 0); 1146 sn1 = bus_space_read_1(wdr->cmd_iot, 1147 wdr->cmd_iohs[wd_sector], 0); 1148 cl1 = bus_space_read_1(wdr->cmd_iot, 1149 wdr->cmd_iohs[wd_cyl_lo], 0); 1150 ch1 = bus_space_read_1(wdr->cmd_iot, 1151 wdr->cmd_iohs[wd_cyl_hi], 0); 1152 #endif 1153 } 1154 1155 if ((drv_mask & 0x01) == 0) { 1156 /* no master */ 1157 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1158 /* No master, slave is ready, it's done */ 1159 goto end; 1160 } 1161 if ((drv_mask & 0x02) == 0) { 1162 /* No master, no slave: it's done */ 1163 goto end; 1164 } 1165 } else if ((drv_mask & 0x02) == 0) { 1166 /* no slave */ 1167 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1168 /* No slave, master is ready, it's done */ 1169 goto end; 1170 } 1171 } else { 1172 /* Wait for both master and slave to be ready */ 1173 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1174 goto end; 1175 } 1176 } 1177 if (poll) 1178 delay(WDCDELAY); 1179 else 1180 tsleep(&nloop, PRIBIO, "atarst", 1); 1181 } 1182 /* Reset timed out. Maybe it's because drv_mask was not right */ 1183 if (st0 & WDCS_BSY) 1184 drv_mask &= ~0x01; 1185 if (st1 & WDCS_BSY) 1186 drv_mask &= ~0x02; 1187 end: 1188 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1189 "cl=0x%x ch=0x%x\n", 1190 atac->atac_dev.dv_xname, 1191 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1192 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1193 "cl=0x%x ch=0x%x\n", 1194 atac->atac_dev.dv_xname, 1195 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1196 1197 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1198 atac->atac_dev.dv_xname, chp->ch_channel, 1199 st0, st1), DEBUG_PROBE); 1200 1201 return drv_mask; 1202 } 1203 1204 /* 1205 * Wait for a drive to be !BSY, and have mask in its status register. 1206 * return -1 for a timeout after "timeout" ms. 1207 */ 1208 static int 1209 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1210 { 1211 struct atac_softc *atac = chp->ch_atac; 1212 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1213 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1214 u_char status; 1215 int xtime = 0; 1216 1217 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1218 atac->atac_dev.dv_xname, 1219 chp->ch_channel), DEBUG_STATUS); 1220 chp->ch_error = 0; 1221 1222 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1223 1224 for (;;) { 1225 chp->ch_status = status = 1226 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1227 if ((status & (WDCS_BSY | mask)) == bits) 1228 break; 1229 if (++xtime > timeout) { 1230 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1231 "status %x error %x (mask 0x%x bits 0x%x)\n", 1232 xtime, status, 1233 bus_space_read_1(wdr->cmd_iot, 1234 wdr->cmd_iohs[wd_error], 0), mask, bits), 1235 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1236 return(WDCWAIT_TOUT); 1237 } 1238 delay(WDCDELAY); 1239 } 1240 #ifdef ATADEBUG 1241 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1242 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1243 #endif 1244 if (status & WDCS_ERR) 1245 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1246 wdr->cmd_iohs[wd_error], 0); 1247 #ifdef WDCNDELAY_DEBUG 1248 /* After autoconfig, there should be no long delays. */ 1249 if (!cold && xtime > WDCNDELAY_DEBUG) { 1250 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1251 if (xfer == NULL) 1252 printf("%s channel %d: warning: busy-wait took %dus\n", 1253 atac->atac_dev.dv_xname, chp->ch_channel, 1254 WDCDELAY * xtime); 1255 else 1256 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1257 atac->atac_dev.dv_xname, chp->ch_channel, 1258 xfer->c_drive, 1259 WDCDELAY * xtime); 1260 } 1261 #endif 1262 return(WDCWAIT_OK); 1263 } 1264 1265 /* 1266 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1267 * thread if possible 1268 */ 1269 int 1270 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1271 { 1272 int error, i, timeout_hz = mstohz(timeout); 1273 1274 if (timeout_hz == 0 || 1275 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1276 error = __wdcwait(chp, mask, bits, timeout); 1277 else { 1278 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1279 if (error != 0) { 1280 if ((chp->ch_flags & ATACH_TH_RUN) || 1281 (flags & AT_WAIT)) { 1282 /* 1283 * we're running in the channel thread 1284 * or some userland thread context 1285 */ 1286 for (i = 0; i < timeout_hz; i++) { 1287 if (__wdcwait(chp, mask, bits, 1288 WDCDELAY_POLL) == 0) { 1289 error = 0; 1290 break; 1291 } 1292 tsleep(&chp, PRIBIO, "atapoll", 1); 1293 } 1294 } else { 1295 /* 1296 * we're probably in interrupt context, 1297 * ask the thread to come back here 1298 */ 1299 #ifdef DIAGNOSTIC 1300 if (chp->ch_queue->queue_freeze > 0) 1301 panic("wdcwait: queue_freeze"); 1302 #endif 1303 chp->ch_queue->queue_freeze++; 1304 wakeup(&chp->ch_thread); 1305 return(WDCWAIT_THR); 1306 } 1307 } 1308 } 1309 return (error); 1310 } 1311 1312 1313 #if NATA_DMA 1314 /* 1315 * Busy-wait for DMA to complete 1316 */ 1317 int 1318 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1319 { 1320 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1321 int xtime; 1322 1323 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1324 wdc->dma_status = 1325 (*wdc->dma_finish)(wdc->dma_arg, 1326 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1327 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1328 return 0; 1329 delay(WDCDELAY); 1330 } 1331 /* timeout, force a DMA halt */ 1332 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1333 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1334 return 1; 1335 } 1336 #endif 1337 1338 void 1339 wdctimeout(void *arg) 1340 { 1341 struct ata_channel *chp = (struct ata_channel *)arg; 1342 #if NATA_DMA || NATA_PIOBM 1343 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1344 #endif 1345 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1346 int s; 1347 1348 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1349 1350 s = splbio(); 1351 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1352 __wdcerror(chp, "lost interrupt"); 1353 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1354 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1355 xfer->c_bcount, 1356 xfer->c_skip); 1357 #if NATA_DMA || NATA_PIOBM 1358 if (chp->ch_flags & ATACH_DMA_WAIT) { 1359 wdc->dma_status = 1360 (*wdc->dma_finish)(wdc->dma_arg, 1361 chp->ch_channel, xfer->c_drive, 1362 WDC_DMAEND_ABRT); 1363 chp->ch_flags &= ~ATACH_DMA_WAIT; 1364 } 1365 #endif 1366 /* 1367 * Call the interrupt routine. If we just missed an interrupt, 1368 * it will do what's needed. Else, it will take the needed 1369 * action (reset the device). 1370 * Before that we need to reinstall the timeout callback, 1371 * in case it will miss another irq while in this transfer 1372 * We arbitray chose it to be 1s 1373 */ 1374 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1375 xfer->c_flags |= C_TIMEOU; 1376 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1377 xfer->c_intr(chp, xfer, 1); 1378 } else 1379 __wdcerror(chp, "missing untimeout"); 1380 splx(s); 1381 } 1382 1383 int 1384 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1385 { 1386 struct ata_channel *chp = drvp->chnl_softc; 1387 struct atac_softc *atac = chp->ch_atac; 1388 struct ata_xfer *xfer; 1389 int s, ret; 1390 1391 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1392 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1393 DEBUG_FUNCS); 1394 1395 /* set up an xfer and queue. Wait for completion */ 1396 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1397 ATAXF_NOSLEEP); 1398 if (xfer == NULL) { 1399 return ATACMD_TRY_AGAIN; 1400 } 1401 1402 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1403 ata_c->flags |= AT_POLL; 1404 if (ata_c->flags & AT_POLL) 1405 xfer->c_flags |= C_POLL; 1406 if (ata_c->flags & AT_WAIT) 1407 xfer->c_flags |= C_WAIT; 1408 xfer->c_drive = drvp->drive; 1409 xfer->c_databuf = ata_c->data; 1410 xfer->c_bcount = ata_c->bcount; 1411 xfer->c_cmd = ata_c; 1412 xfer->c_start = __wdccommand_start; 1413 xfer->c_intr = __wdccommand_intr; 1414 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1415 1416 s = splbio(); 1417 ata_exec_xfer(chp, xfer); 1418 #ifdef DIAGNOSTIC 1419 if ((ata_c->flags & AT_POLL) != 0 && 1420 (ata_c->flags & AT_DONE) == 0) 1421 panic("wdc_exec_command: polled command not done"); 1422 #endif 1423 if (ata_c->flags & AT_DONE) { 1424 ret = ATACMD_COMPLETE; 1425 } else { 1426 if (ata_c->flags & AT_WAIT) { 1427 while ((ata_c->flags & AT_DONE) == 0) { 1428 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1429 } 1430 ret = ATACMD_COMPLETE; 1431 } else { 1432 ret = ATACMD_QUEUED; 1433 } 1434 } 1435 splx(s); 1436 return ret; 1437 } 1438 1439 static void 1440 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1441 { 1442 struct atac_softc *atac = chp->ch_atac; 1443 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1444 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1445 int drive = xfer->c_drive; 1446 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1447 struct ata_command *ata_c = xfer->c_cmd; 1448 1449 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1450 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1451 DEBUG_FUNCS); 1452 1453 if (wdc->select) 1454 wdc->select(chp,drive); 1455 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1456 WDSD_IBM | (drive << 4)); 1457 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1458 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1459 case WDCWAIT_OK: 1460 break; 1461 case WDCWAIT_TOUT: 1462 ata_c->flags |= AT_TIMEOU; 1463 __wdccommand_done(chp, xfer); 1464 return; 1465 case WDCWAIT_THR: 1466 return; 1467 } 1468 if (ata_c->flags & AT_POLL) { 1469 /* polled command, disable interrupts */ 1470 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1471 WDCTL_4BIT | WDCTL_IDS); 1472 } 1473 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1474 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1475 1476 if ((ata_c->flags & AT_POLL) == 0) { 1477 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1478 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1479 wdctimeout, chp); 1480 return; 1481 } 1482 /* 1483 * Polled command. Wait for drive ready or drq. Done in intr(). 1484 * Wait for at last 400ns for status bit to be valid. 1485 */ 1486 delay(10); /* 400ns delay */ 1487 __wdccommand_intr(chp, xfer, 0); 1488 } 1489 1490 static int 1491 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1492 { 1493 struct atac_softc *atac = chp->ch_atac; 1494 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1495 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1496 struct ata_command *ata_c = xfer->c_cmd; 1497 int bcount = ata_c->bcount; 1498 char *data = ata_c->data; 1499 int wflags; 1500 int drive_flags; 1501 1502 if (ata_c->r_command == WDCC_IDENTIFY || 1503 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1504 /* 1505 * The IDENTIFY data has been designed as an array of 1506 * u_int16_t, so we can byteswap it on the fly. 1507 * Historically it's what we have always done so keeping it 1508 * here ensure binary backward compatibility. 1509 */ 1510 drive_flags = DRIVE_NOSTREAM | 1511 chp->ch_drive[xfer->c_drive].drive_flags; 1512 } else { 1513 /* 1514 * Other data structure are opaque and should be transfered 1515 * as is. 1516 */ 1517 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1518 } 1519 1520 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1521 /* both wait and poll, we can tsleep here */ 1522 wflags = AT_WAIT | AT_POLL; 1523 } else { 1524 wflags = AT_POLL; 1525 } 1526 1527 again: 1528 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1529 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1530 DEBUG_INTR); 1531 /* 1532 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1533 * Reselect again, it doesn't hurt for others commands, and the time 1534 * penalty for the extra regiter write is acceptable, 1535 * wdc_exec_command() isn't called often (mosly for autoconfig) 1536 */ 1537 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1538 WDSD_IBM | (xfer->c_drive << 4)); 1539 if ((ata_c->flags & AT_XFDONE) != 0) { 1540 /* 1541 * We have completed a data xfer. The drive should now be 1542 * in its initial state 1543 */ 1544 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1545 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1546 wflags) == WDCWAIT_TOUT) { 1547 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1548 return 0; /* IRQ was not for us */ 1549 ata_c->flags |= AT_TIMEOU; 1550 } 1551 goto out; 1552 } 1553 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1554 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1555 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1556 return 0; /* IRQ was not for us */ 1557 ata_c->flags |= AT_TIMEOU; 1558 goto out; 1559 } 1560 if (wdc->irqack) 1561 wdc->irqack(chp); 1562 if (ata_c->flags & AT_READ) { 1563 if ((chp->ch_status & WDCS_DRQ) == 0) { 1564 ata_c->flags |= AT_TIMEOU; 1565 goto out; 1566 } 1567 wdc->datain_pio(chp, drive_flags, data, bcount); 1568 /* at this point the drive should be in its initial state */ 1569 ata_c->flags |= AT_XFDONE; 1570 /* 1571 * XXX checking the status register again here cause some 1572 * hardware to timeout. 1573 */ 1574 } else if (ata_c->flags & AT_WRITE) { 1575 if ((chp->ch_status & WDCS_DRQ) == 0) { 1576 ata_c->flags |= AT_TIMEOU; 1577 goto out; 1578 } 1579 wdc->dataout_pio(chp, drive_flags, data, bcount); 1580 ata_c->flags |= AT_XFDONE; 1581 if ((ata_c->flags & AT_POLL) == 0) { 1582 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1583 callout_reset(&chp->ch_callout, 1584 ata_c->timeout / 1000 * hz, wdctimeout, chp); 1585 return 1; 1586 } else { 1587 goto again; 1588 } 1589 } 1590 out: 1591 __wdccommand_done(chp, xfer); 1592 return 1; 1593 } 1594 1595 static void 1596 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1597 { 1598 struct atac_softc *atac = chp->ch_atac; 1599 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1600 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1601 struct ata_command *ata_c = xfer->c_cmd; 1602 1603 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1604 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1605 ata_c->flags), DEBUG_FUNCS); 1606 1607 1608 if (chp->ch_status & WDCS_DWF) 1609 ata_c->flags |= AT_DF; 1610 if (chp->ch_status & WDCS_ERR) { 1611 ata_c->flags |= AT_ERROR; 1612 ata_c->r_error = chp->ch_error; 1613 } 1614 if ((ata_c->flags & AT_READREG) != 0 && 1615 device_is_active(&atac->atac_dev) && 1616 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1617 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1618 wdr->cmd_iohs[wd_sdh], 0); 1619 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1620 wdr->cmd_iohs[wd_seccnt], 0); 1621 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1622 wdr->cmd_iohs[wd_sector], 0); 1623 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1624 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1625 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1626 wdr->cmd_iohs[wd_cyl_lo], 0); 1627 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1628 wdr->cmd_iohs[wd_error], 0); 1629 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1630 wdr->cmd_iohs[wd_features], 0); 1631 } 1632 callout_stop(&chp->ch_callout); 1633 chp->ch_queue->active_xfer = NULL; 1634 if (ata_c->flags & AT_POLL) { 1635 /* enable interrupts */ 1636 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1637 WDCTL_4BIT); 1638 delay(10); /* some drives need a little delay here */ 1639 } 1640 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1641 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1642 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1643 wakeup(&chp->ch_queue->active_xfer); 1644 } else 1645 __wdccommand_done_end(chp, xfer); 1646 } 1647 1648 static void 1649 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1650 { 1651 struct ata_command *ata_c = xfer->c_cmd; 1652 1653 ata_c->flags |= AT_DONE; 1654 ata_free_xfer(chp, xfer); 1655 if (ata_c->flags & AT_WAIT) 1656 wakeup(ata_c); 1657 else if (ata_c->callback) 1658 ata_c->callback(ata_c->callback_arg); 1659 atastart(chp); 1660 return; 1661 } 1662 1663 static void 1664 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1665 int reason) 1666 { 1667 struct ata_command *ata_c = xfer->c_cmd; 1668 1669 switch (reason) { 1670 case KILL_GONE: 1671 ata_c->flags |= AT_GONE; 1672 break; 1673 case KILL_RESET: 1674 ata_c->flags |= AT_RESET; 1675 break; 1676 default: 1677 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1678 reason); 1679 panic("__wdccommand_kill_xfer"); 1680 } 1681 __wdccommand_done_end(chp, xfer); 1682 } 1683 1684 /* 1685 * Send a command. The drive should be ready. 1686 * Assumes interrupts are blocked. 1687 */ 1688 void 1689 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1690 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1691 u_int8_t features) 1692 { 1693 struct atac_softc *atac = chp->ch_atac; 1694 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1695 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1696 1697 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1698 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1699 chp->ch_channel, drive, command, cylin, head, sector, count, 1700 features), DEBUG_FUNCS); 1701 1702 if (wdc->select) 1703 wdc->select(chp,drive); 1704 1705 /* Select drive, head, and addressing mode. */ 1706 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1707 WDSD_IBM | (drive << 4) | head); 1708 /* Load parameters into the wd_features register. */ 1709 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1710 features); 1711 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1712 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1713 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1714 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1715 0, cylin >> 8); 1716 1717 /* Send command. */ 1718 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1719 return; 1720 } 1721 1722 /* 1723 * Send a 48-bit addressing command. The drive should be ready. 1724 * Assumes interrupts are blocked. 1725 */ 1726 void 1727 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1728 u_int64_t blkno, u_int16_t count) 1729 { 1730 struct atac_softc *atac = chp->ch_atac; 1731 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1732 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1733 1734 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1735 "count=%d\n", atac->atac_dev.dv_xname, 1736 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1737 DEBUG_FUNCS); 1738 1739 if (wdc->select) 1740 wdc->select(chp,drive); 1741 1742 /* Select drive, head, and addressing mode. */ 1743 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1744 (drive << 4) | WDSD_LBA); 1745 1746 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1747 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1748 0); 1749 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1750 0, count); 1751 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1752 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1753 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1754 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1755 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1756 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1757 } else { 1758 /* previous */ 1759 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1760 0); 1761 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1762 0, count >> 8); 1763 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1764 0, blkno >> 24); 1765 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1766 0, blkno >> 32); 1767 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1768 0, blkno >> 40); 1769 1770 /* current */ 1771 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1772 0); 1773 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1774 count); 1775 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1776 blkno); 1777 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1778 0, blkno >> 8); 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1780 0, blkno >> 16); 1781 } 1782 1783 /* Send command. */ 1784 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1785 return; 1786 } 1787 1788 /* 1789 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1790 * tested by the caller. 1791 */ 1792 void 1793 wdccommandshort(struct ata_channel *chp, int drive, int command) 1794 { 1795 struct atac_softc *atac = chp->ch_atac; 1796 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1797 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1798 1799 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1800 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1801 DEBUG_FUNCS); 1802 1803 if (wdc->select) 1804 wdc->select(chp,drive); 1805 1806 /* Select drive. */ 1807 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1808 WDSD_IBM | (drive << 4)); 1809 1810 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1811 } 1812 1813 static void 1814 __wdcerror(struct ata_channel *chp, const char *msg) 1815 { 1816 struct atac_softc *atac = chp->ch_atac; 1817 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1818 1819 if (xfer == NULL) 1820 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1821 msg); 1822 else 1823 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1824 chp->ch_channel, xfer->c_drive, msg); 1825 } 1826 1827 /* 1828 * the bit bucket 1829 */ 1830 void 1831 wdcbit_bucket(struct ata_channel *chp, int size) 1832 { 1833 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1834 1835 for (; size >= 2; size -= 2) 1836 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1837 if (size) 1838 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1839 } 1840 1841 static void 1842 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1843 { 1844 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1845 1846 if (flags & DRIVE_NOSTREAM) { 1847 if (flags & DRIVE_CAP32) { 1848 bus_space_read_multi_4(wdr->data32iot, 1849 wdr->data32ioh, 0, bf, len >> 2); 1850 bf = (char *)bf + (len & ~3); 1851 len &= 3; 1852 } 1853 if (len) { 1854 bus_space_read_multi_2(wdr->cmd_iot, 1855 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1856 } 1857 } else { 1858 if (flags & DRIVE_CAP32) { 1859 bus_space_read_multi_stream_4(wdr->data32iot, 1860 wdr->data32ioh, 0, bf, len >> 2); 1861 bf = (char *)bf + (len & ~3); 1862 len &= 3; 1863 } 1864 if (len) { 1865 bus_space_read_multi_stream_2(wdr->cmd_iot, 1866 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1867 } 1868 } 1869 } 1870 1871 static void 1872 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1873 { 1874 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1875 1876 if (flags & DRIVE_NOSTREAM) { 1877 if (flags & DRIVE_CAP32) { 1878 bus_space_write_multi_4(wdr->data32iot, 1879 wdr->data32ioh, 0, bf, len >> 2); 1880 bf = (char *)bf + (len & ~3); 1881 len &= 3; 1882 } 1883 if (len) { 1884 bus_space_write_multi_2(wdr->cmd_iot, 1885 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1886 } 1887 } else { 1888 if (flags & DRIVE_CAP32) { 1889 bus_space_write_multi_stream_4(wdr->data32iot, 1890 wdr->data32ioh, 0, bf, len >> 2); 1891 bf = (char *)bf + (len & ~3); 1892 len &= 3; 1893 } 1894 if (len) { 1895 bus_space_write_multi_stream_2(wdr->cmd_iot, 1896 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1897 } 1898 } 1899 } 1900
Indexes created Wed Sep 24 05:09:52 GMT 2025