wdc.c revision 1.245
1 /* $NetBSD: wdc.c,v 1.245 2007/01/18 21:42:57 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.245 2007/01/18 21:42:57 bouyer Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ata/satareg.h> 102 #include <dev/ata/satavar.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "locators.h" 107 108 #include "atapibus.h" 109 #include "wd.h" 110 #include "sata.h" 111 112 #define WDCDELAY 100 /* 100 microseconds */ 113 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 114 #if 0 115 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 116 #define WDCNDELAY_DEBUG 50 117 #endif 118 119 /* When polling wait that much and then tsleep for 1/hz seconds */ 120 #define WDCDELAY_POLL 1 /* ms */ 121 122 /* timeout for the control commands */ 123 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 124 125 /* 126 * timeout when waiting for BSY to deassert when probing. 127 * set to 5s. From the standards this could be up to 31, but we can't 128 * wait that much at boot time, and 5s seems to be enouth. 129 */ 130 #define WDC_PROBE_WAIT 5 131 132 133 #if NWD > 0 134 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 135 #else 136 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 137 const struct ata_bustype wdc_ata_bustype = { 138 SCSIPI_BUSTYPE_ATA, 139 NULL, /* wdc_ata_bio */ 140 NULL, /* wdc_reset_drive */ 141 wdc_reset_channel, 142 wdc_exec_command, 143 NULL, /* ata_get_params */ 144 NULL, /* wdc_ata_addref */ 145 NULL, /* wdc_ata_delref */ 146 NULL /* ata_kill_pending */ 147 }; 148 #endif 149 150 /* Flags to wdcreset(). */ 151 #define RESET_POLL 1 152 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 153 154 static int wdcprobe1(struct ata_channel *, int); 155 static int wdcreset(struct ata_channel *, int); 156 static void __wdcerror(struct ata_channel *, const char *); 157 static int __wdcwait_reset(struct ata_channel *, int, int); 158 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 159 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 160 static void __wdccommand_kill_xfer(struct ata_channel *, 161 struct ata_xfer *, int); 162 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 163 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 164 static int __wdcwait(struct ata_channel *, int, int, int); 165 166 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 167 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 168 169 #define DEBUG_INTR 0x01 170 #define DEBUG_XFERS 0x02 171 #define DEBUG_STATUS 0x04 172 #define DEBUG_FUNCS 0x08 173 #define DEBUG_PROBE 0x10 174 #define DEBUG_DETACH 0x20 175 #define DEBUG_DELAY 0x40 176 #ifdef ATADEBUG 177 extern int atadebug_mask; /* init'ed in ata.c */ 178 int wdc_nxfer = 0; 179 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 180 #else 181 #define ATADEBUG_PRINT(args, level) 182 #endif 183 184 /* 185 * Initialize the "shadow register" handles for a standard wdc controller. 186 */ 187 void 188 wdc_init_shadow_regs(struct ata_channel *chp) 189 { 190 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 191 192 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 193 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 194 } 195 196 /* 197 * Allocate a wdc_regs array, based on the number of channels. 198 */ 199 void 200 wdc_allocate_regs(struct wdc_softc *wdc) 201 { 202 203 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 204 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 205 } 206 207 #if NSATA > 0 208 /* 209 * probe drives on SATA controllers with standard SATA registers: 210 * bring the PHYs online, read the drive signature and set drive flags 211 * appropriately. 212 */ 213 void 214 wdc_sataprobe(struct ata_channel *chp) 215 { 216 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 217 uint16_t scnt, sn, cl, ch; 218 int i, s; 219 220 /* XXX This should be done by other code. */ 221 for (i = 0; i < chp->ch_ndrive; i++) { 222 chp->ch_drive[i].chnl_softc = chp; 223 chp->ch_drive[i].drive = i; 224 } 225 226 /* reset the PHY and bring online */ 227 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 228 wdr->sata_status)) { 229 case SStatus_DET_DEV: 230 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 231 WDSD_IBM); 232 delay(10); /* 400ns delay */ 233 scnt = bus_space_read_2(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_seccnt], 0); 235 sn = bus_space_read_2(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_sector], 0); 237 cl = bus_space_read_2(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_cyl_lo], 0); 239 ch = bus_space_read_2(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_hi], 0); 241 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 242 "cl=0x%x ch=0x%x\n", 243 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 244 scnt, sn, cl, ch), DEBUG_PROBE); 245 /* 246 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 247 * cases we get wrong values here, so ignore it. 248 */ 249 s = splbio(); 250 if (cl == 0x14 && ch == 0xeb) 251 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 252 else 253 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 254 splx(s); 255 256 /* 257 * issue a reset in case only the interface part of the drive 258 * is up 259 */ 260 if (wdcreset(chp, RESET_SLEEP) != 0) 261 chp->ch_drive[0].drive_flags = 0; 262 break; 263 264 default: 265 break; 266 } 267 } 268 #endif /* NSATA > 0 */ 269 270 271 /* Test to see controller with at last one attached drive is there. 272 * Returns a bit for each possible drive found (0x01 for drive 0, 273 * 0x02 for drive 1). 274 * Logic: 275 * - If a status register is at 0xff, assume there is no drive here 276 * (ISA has pull-up resistors). Similarly if the status register has 277 * the value we last wrote to the bus (for IDE interfaces without pullups). 278 * If no drive at all -> return. 279 * - reset the controller, wait for it to complete (may take up to 31s !). 280 * If timeout -> return. 281 * - test ATA/ATAPI signatures. If at last one drive found -> return. 282 * - try an ATA command on the master. 283 */ 284 285 void 286 wdc_drvprobe(struct ata_channel *chp) 287 { 288 struct ataparams params; 289 struct atac_softc *atac = chp->ch_atac; 290 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 291 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 292 u_int8_t st0 = 0, st1 = 0; 293 int i, j, error, s; 294 295 if (wdcprobe1(chp, 0) == 0) { 296 /* No drives, abort the attach here. */ 297 return; 298 } 299 300 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 301 for (i = 0; i < mstohz(3000); i++) { 302 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 303 if (wdc->select) 304 wdc->select(chp,0); 305 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 306 0, WDSD_IBM); 307 delay(10); /* 400ns delay */ 308 st0 = bus_space_read_1(wdr->cmd_iot, 309 wdr->cmd_iohs[wd_status], 0); 310 } 311 312 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 313 if (wdc->select) 314 wdc->select(chp,1); 315 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 316 0, WDSD_IBM | 0x10); 317 delay(10); /* 400ns delay */ 318 st1 = bus_space_read_1(wdr->cmd_iot, 319 wdr->cmd_iohs[wd_status], 0); 320 } 321 322 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 323 == 0 || 324 (st0 & WDCS_DRDY)) && 325 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 326 == 0 || 327 (st1 & WDCS_DRDY))) 328 break; 329 tsleep(¶ms, PRIBIO, "atadrdy", 1); 330 } 331 s = splbio(); 332 if ((st0 & WDCS_DRDY) == 0) 333 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 334 if ((st1 & WDCS_DRDY) == 0) 335 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 336 splx(s); 337 338 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 339 atac->atac_dev.dv_xname, 340 chp->ch_channel, st0, st1), DEBUG_PROBE); 341 342 /* Wait a bit, some devices are weird just after a reset. */ 343 delay(5000); 344 345 for (i = 0; i < chp->ch_ndrive; i++) { 346 /* XXX This should be done by other code. */ 347 chp->ch_drive[i].chnl_softc = chp; 348 chp->ch_drive[i].drive = i; 349 350 #if NATA_DMA 351 /* 352 * Init error counter so that an error withing the first xfers 353 * will trigger a downgrade 354 */ 355 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 356 #endif 357 358 /* If controller can't do 16bit flag the drives as 32bit */ 359 if ((atac->atac_cap & 360 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 361 s = splbio(); 362 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 363 splx(s); 364 } 365 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 366 continue; 367 368 /* Shortcut in case we've been shutdown */ 369 if (chp->ch_flags & ATACH_SHUTDOWN) 370 return; 371 372 /* 373 * Issue an identify, to try to detect ghosts. 374 * Note that we can't use interrupts here, because if there 375 * is no devices, we will get a command aborted without 376 * interrupts. 377 */ 378 error = ata_get_params(&chp->ch_drive[i], 379 AT_WAIT | AT_POLL, ¶ms); 380 if (error != CMD_OK) { 381 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 382 383 /* Shortcut in case we've been shutdown */ 384 if (chp->ch_flags & ATACH_SHUTDOWN) 385 return; 386 387 error = ata_get_params(&chp->ch_drive[i], 388 AT_WAIT | AT_POLL, ¶ms); 389 } 390 if (error == CMD_OK) { 391 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 392 s = splbio(); 393 for (j = 0; j < chp->ch_ndrive; j++) 394 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 395 splx(s); 396 } else { 397 s = splbio(); 398 chp->ch_drive[i].drive_flags &= 399 ~(DRIVE_ATA | DRIVE_ATAPI); 400 splx(s); 401 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 402 atac->atac_dev.dv_xname, 403 chp->ch_channel, i, error), DEBUG_PROBE); 404 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 405 continue; 406 /* 407 * Pre-ATA drive ? 408 * Test registers writability (Error register not 409 * writable, but cyllo is), then try an ATA command. 410 */ 411 if (wdc->select) 412 wdc->select(chp,i); 413 bus_space_write_1(wdr->cmd_iot, 414 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 415 delay(10); /* 400ns delay */ 416 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 417 0, 0x58); 418 bus_space_write_1(wdr->cmd_iot, 419 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 420 if (bus_space_read_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_error], 0) == 0x58 || 422 bus_space_read_1(wdr->cmd_iot, 423 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 424 ATADEBUG_PRINT(("%s:%d:%d: register " 425 "writability failed\n", 426 atac->atac_dev.dv_xname, 427 chp->ch_channel, i), DEBUG_PROBE); 428 s = splbio(); 429 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 430 splx(s); 431 continue; 432 } 433 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 434 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 435 atac->atac_dev.dv_xname, 436 chp->ch_channel, i), DEBUG_PROBE); 437 s = splbio(); 438 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 439 splx(s); 440 continue; 441 } 442 bus_space_write_1(wdr->cmd_iot, 443 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 444 delay(10); /* 400ns delay */ 445 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 446 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 447 atac->atac_dev.dv_xname, 448 chp->ch_channel, i), DEBUG_PROBE); 449 s = splbio(); 450 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 451 splx(s); 452 } else { 453 s = splbio(); 454 for (j = 0; j < chp->ch_ndrive; j++) 455 chp->ch_drive[j].drive_flags &= 456 ~(DRIVE_ATA | DRIVE_ATAPI); 457 splx(s); 458 } 459 } 460 } 461 } 462 463 int 464 wdcprobe(struct ata_channel *chp) 465 { 466 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 467 /* default reset method */ 468 if (wdc->reset == NULL) 469 wdc->reset = wdc_do_reset; 470 471 return (wdcprobe1(chp, 1)); 472 } 473 474 static int 475 wdcprobe1(struct ata_channel *chp, int poll) 476 { 477 struct atac_softc *atac = chp->ch_atac; 478 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 479 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 480 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 481 u_int8_t ret_value = 0x03; 482 u_int8_t drive; 483 int s; 484 int wdc_probe_count = 485 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 486 487 /* 488 * Sanity check to see if the wdc channel responds at all. 489 */ 490 491 s = splbio(); 492 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 493 while (wdc_probe_count-- > 0) { 494 if (wdc->select) 495 wdc->select(chp,0); 496 497 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 498 0, WDSD_IBM); 499 delay(10); /* 400ns delay */ 500 st0 = bus_space_read_1(wdr->cmd_iot, 501 wdr->cmd_iohs[wd_status], 0); 502 503 if (wdc->select) 504 wdc->select(chp,1); 505 506 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 507 0, WDSD_IBM | 0x10); 508 delay(10); /* 400ns delay */ 509 st1 = bus_space_read_1(wdr->cmd_iot, 510 wdr->cmd_iohs[wd_status], 0); 511 if ((st0 & WDCS_BSY) == 0) 512 break; 513 } 514 515 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 516 atac->atac_dev.dv_xname, 517 chp->ch_channel, st0, st1), DEBUG_PROBE); 518 519 if (st0 == 0xff || st0 == WDSD_IBM) 520 ret_value &= ~0x01; 521 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 522 ret_value &= ~0x02; 523 /* Register writability test, drive 0. */ 524 if (ret_value & 0x01) { 525 if (wdc->select) 526 wdc->select(chp,0); 527 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 528 0, WDSD_IBM); 529 bus_space_write_1(wdr->cmd_iot, 530 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 531 cl = bus_space_read_1(wdr->cmd_iot, 532 wdr->cmd_iohs[wd_cyl_lo], 0); 533 if (cl != 0x02) { 534 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 535 "got 0x%x != 0x02\n", 536 atac->atac_dev.dv_xname, 537 chp->ch_channel, cl), 538 DEBUG_PROBE); 539 ret_value &= ~0x01; 540 } 541 bus_space_write_1(wdr->cmd_iot, 542 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 543 cl = bus_space_read_1(wdr->cmd_iot, 544 wdr->cmd_iohs[wd_cyl_lo], 0); 545 if (cl != 0x01) { 546 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 547 "got 0x%x != 0x01\n", 548 atac->atac_dev.dv_xname, 549 chp->ch_channel, cl), 550 DEBUG_PROBE); 551 ret_value &= ~0x01; 552 } 553 bus_space_write_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_sector], 0, 0x01); 555 cl = bus_space_read_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_sector], 0); 557 if (cl != 0x01) { 558 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 559 "got 0x%x != 0x01\n", 560 atac->atac_dev.dv_xname, 561 chp->ch_channel, cl), 562 DEBUG_PROBE); 563 ret_value &= ~0x01; 564 } 565 bus_space_write_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_sector], 0, 0x02); 567 cl = bus_space_read_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_sector], 0); 569 if (cl != 0x02) { 570 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 571 "got 0x%x != 0x02\n", 572 atac->atac_dev.dv_xname, 573 chp->ch_channel, cl), 574 DEBUG_PROBE); 575 ret_value &= ~0x01; 576 } 577 cl = bus_space_read_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_cyl_lo], 0); 579 if (cl != 0x01) { 580 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 581 "got 0x%x != 0x01\n", 582 atac->atac_dev.dv_xname, 583 chp->ch_channel, cl), 584 DEBUG_PROBE); 585 ret_value &= ~0x01; 586 } 587 } 588 /* Register writability test, drive 1. */ 589 if (ret_value & 0x02) { 590 if (wdc->select) 591 wdc->select(chp,1); 592 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 593 0, WDSD_IBM | 0x10); 594 bus_space_write_1(wdr->cmd_iot, 595 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 596 cl = bus_space_read_1(wdr->cmd_iot, 597 wdr->cmd_iohs[wd_cyl_lo], 0); 598 if (cl != 0x02) { 599 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 600 "got 0x%x != 0x02\n", 601 atac->atac_dev.dv_xname, 602 chp->ch_channel, cl), 603 DEBUG_PROBE); 604 ret_value &= ~0x02; 605 } 606 bus_space_write_1(wdr->cmd_iot, 607 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 608 cl = bus_space_read_1(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_lo], 0); 610 if (cl != 0x01) { 611 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 612 "got 0x%x != 0x01\n", 613 atac->atac_dev.dv_xname, 614 chp->ch_channel, cl), 615 DEBUG_PROBE); 616 ret_value &= ~0x02; 617 } 618 bus_space_write_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_sector], 0, 0x01); 620 cl = bus_space_read_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_sector], 0); 622 if (cl != 0x01) { 623 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 624 "got 0x%x != 0x01\n", 625 atac->atac_dev.dv_xname, 626 chp->ch_channel, cl), 627 DEBUG_PROBE); 628 ret_value &= ~0x02; 629 } 630 bus_space_write_1(wdr->cmd_iot, 631 wdr->cmd_iohs[wd_sector], 0, 0x02); 632 cl = bus_space_read_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_sector], 0); 634 if (cl != 0x02) { 635 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 636 "got 0x%x != 0x02\n", 637 atac->atac_dev.dv_xname, 638 chp->ch_channel, cl), 639 DEBUG_PROBE); 640 ret_value &= ~0x02; 641 } 642 cl = bus_space_read_1(wdr->cmd_iot, 643 wdr->cmd_iohs[wd_cyl_lo], 0); 644 if (cl != 0x01) { 645 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 646 "got 0x%x != 0x01\n", 647 atac->atac_dev.dv_xname, 648 chp->ch_channel, cl), 649 DEBUG_PROBE); 650 ret_value &= ~0x02; 651 } 652 } 653 654 if (ret_value == 0) { 655 splx(s); 656 return 0; 657 } 658 } 659 660 661 #if 0 /* XXX this break some ATA or ATAPI devices */ 662 /* 663 * reset bus. Also send an ATAPI_RESET to devices, in case there are 664 * ATAPI device out there which don't react to the bus reset 665 */ 666 if (ret_value & 0x01) { 667 if (wdc->select) 668 wdc->select(chp,0); 669 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 670 0, WDSD_IBM); 671 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 672 ATAPI_SOFT_RESET); 673 } 674 if (ret_value & 0x02) { 675 if (wdc->select) 676 wdc->select(chp,0); 677 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 678 0, WDSD_IBM | 0x10); 679 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 680 ATAPI_SOFT_RESET); 681 } 682 683 delay(5000); 684 #endif 685 686 wdc->reset(chp, RESET_POLL); 687 DELAY(2000); 688 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 689 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 690 splx(s); 691 692 ret_value = __wdcwait_reset(chp, ret_value, poll); 693 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 694 atac->atac_dev.dv_xname, chp->ch_channel, 695 ret_value), DEBUG_PROBE); 696 697 /* if reset failed, there's nothing here */ 698 if (ret_value == 0) 699 return 0; 700 701 /* 702 * Test presence of drives. First test register signatures looking 703 * for ATAPI devices. If it's not an ATAPI and reset said there may 704 * be something here assume it's ATA or OLD. Ghost will be killed 705 * later in attach routine. 706 */ 707 for (drive = 0; drive < chp->ch_ndrive; drive++) { 708 if ((ret_value & (0x01 << drive)) == 0) 709 continue; 710 if (wdc->select) 711 wdc->select(chp,drive); 712 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 713 WDSD_IBM | (drive << 4)); 714 delay(10); /* 400ns delay */ 715 /* Save registers contents */ 716 sc = bus_space_read_1(wdr->cmd_iot, 717 wdr->cmd_iohs[wd_seccnt], 0); 718 sn = bus_space_read_1(wdr->cmd_iot, 719 wdr->cmd_iohs[wd_sector], 0); 720 cl = bus_space_read_1(wdr->cmd_iot, 721 wdr->cmd_iohs[wd_cyl_lo], 0); 722 ch = bus_space_read_1(wdr->cmd_iot, 723 wdr->cmd_iohs[wd_cyl_hi], 0); 724 725 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 726 "cl=0x%x ch=0x%x\n", 727 atac->atac_dev.dv_xname, 728 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 729 /* 730 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 731 * we get wrong values here, so ignore it. 732 */ 733 s = splbio(); 734 if (cl == 0x14 && ch == 0xeb) { 735 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 736 } else { 737 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 738 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 739 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 740 } 741 splx(s); 742 } 743 return (ret_value); 744 } 745 746 void 747 wdcattach(struct ata_channel *chp) 748 { 749 struct atac_softc *atac = chp->ch_atac; 750 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 751 752 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 753 754 /* default data transfer methods */ 755 if (wdc->datain_pio == NULL) 756 wdc->datain_pio = wdc_datain_pio; 757 if (wdc->dataout_pio == NULL) 758 wdc->dataout_pio = wdc_dataout_pio; 759 /* default reset method */ 760 if (wdc->reset == NULL) 761 wdc->reset = wdc_do_reset; 762 763 /* initialise global data */ 764 if (atac->atac_bustype_ata == NULL) 765 atac->atac_bustype_ata = &wdc_ata_bustype; 766 if (atac->atac_probe == NULL) 767 atac->atac_probe = wdc_drvprobe; 768 #if NATAPIBUS > 0 769 if (atac->atac_atapibus_attach == NULL) 770 atac->atac_atapibus_attach = wdc_atapibus_attach; 771 #endif 772 773 ata_channel_attach(chp); 774 } 775 776 int 777 wdcactivate(struct device *self, enum devact act) 778 { 779 struct atac_softc *atac = (struct atac_softc *) self; 780 int s, i, error = 0; 781 782 s = splbio(); 783 switch (act) { 784 case DVACT_ACTIVATE: 785 error = EOPNOTSUPP; 786 break; 787 788 case DVACT_DEACTIVATE: 789 for (i = 0; i < atac->atac_nchannels; i++) { 790 error = 791 config_deactivate(atac->atac_channels[i]->atabus); 792 if (error) 793 break; 794 } 795 break; 796 } 797 splx(s); 798 return (error); 799 } 800 801 int 802 wdcdetach(struct device *self, int flags) 803 { 804 struct atac_softc *atac = (struct atac_softc *) self; 805 struct ata_channel *chp; 806 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 807 int i, error = 0; 808 809 for (i = 0; i < atac->atac_nchannels; i++) { 810 chp = atac->atac_channels[i]; 811 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 812 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 813 DEBUG_DETACH); 814 error = config_detach(chp->atabus, flags); 815 if (error) 816 break; 817 } 818 if (adapt->adapt_refcnt != 0) { 819 #ifdef DIAGNOSTIC 820 printf("wdcdetach: refcnt should be 0 here??\n"); 821 #endif 822 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 823 } 824 return (error); 825 } 826 827 /* restart an interrupted I/O */ 828 void 829 wdcrestart(void *v) 830 { 831 struct ata_channel *chp = v; 832 int s; 833 834 s = splbio(); 835 atastart(chp); 836 splx(s); 837 } 838 839 840 /* 841 * Interrupt routine for the controller. Acknowledge the interrupt, check for 842 * errors on the current operation, mark it done if necessary, and start the 843 * next request. Also check for a partially done transfer, and continue with 844 * the next chunk if so. 845 */ 846 int 847 wdcintr(void *arg) 848 { 849 struct ata_channel *chp = arg; 850 struct atac_softc *atac = chp->ch_atac; 851 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 852 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 853 struct ata_xfer *xfer; 854 int ret; 855 856 if (!device_is_active(&atac->atac_dev)) { 857 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 858 DEBUG_INTR); 859 return (0); 860 } 861 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 862 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 863 /* try to clear the pending interrupt anyway */ 864 (void)bus_space_read_1(wdr->cmd_iot, 865 wdr->cmd_iohs[wd_status], 0); 866 return (0); 867 } 868 869 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 870 xfer = chp->ch_queue->active_xfer; 871 #ifdef DIAGNOSTIC 872 if (xfer == NULL) 873 panic("wdcintr: no xfer"); 874 if (xfer->c_chp != chp) { 875 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 876 chp->ch_channel); 877 panic("wdcintr: wrong channel"); 878 } 879 #endif 880 #if NATA_DMA || NATA_PIOBM 881 if (chp->ch_flags & ATACH_DMA_WAIT) { 882 wdc->dma_status = 883 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 884 xfer->c_drive, WDC_DMAEND_END); 885 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 886 /* IRQ not for us, not detected by DMA engine */ 887 return 0; 888 } 889 chp->ch_flags &= ~ATACH_DMA_WAIT; 890 } 891 #endif 892 chp->ch_flags &= ~ATACH_IRQ_WAIT; 893 ret = xfer->c_intr(chp, xfer, 1); 894 if (ret == 0) /* irq was not for us, still waiting for irq */ 895 chp->ch_flags |= ATACH_IRQ_WAIT; 896 return (ret); 897 } 898 899 /* Put all disk in RESET state */ 900 void 901 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 902 { 903 struct ata_channel *chp = drvp->chnl_softc; 904 struct atac_softc *atac = chp->ch_atac; 905 906 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 907 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 908 DEBUG_FUNCS); 909 910 ata_reset_channel(chp, flags); 911 } 912 913 void 914 wdc_reset_channel(struct ata_channel *chp, int flags) 915 { 916 TAILQ_HEAD(, ata_xfer) reset_xfer; 917 struct ata_xfer *xfer, *next_xfer; 918 #if NATA_DMA || NATA_PIOBM 919 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 920 #endif 921 922 TAILQ_INIT(&reset_xfer); 923 924 chp->ch_flags &= ~ATACH_IRQ_WAIT; 925 926 /* 927 * if the current command if on an ATAPI device, issue a 928 * ATAPI_SOFT_RESET 929 */ 930 xfer = chp->ch_queue->active_xfer; 931 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 932 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 933 if (flags & AT_WAIT) 934 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 935 else 936 delay(1000); 937 } 938 939 /* reset the channel */ 940 if (flags & AT_WAIT) 941 (void) wdcreset(chp, RESET_SLEEP); 942 else 943 (void) wdcreset(chp, RESET_POLL); 944 945 /* 946 * wait a bit after reset; in case the DMA engines needs some time 947 * to recover. 948 */ 949 if (flags & AT_WAIT) 950 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 951 else 952 delay(1000); 953 /* 954 * look for pending xfers. If we have a shared queue, we'll also reset 955 * the other channel if the current xfer is running on it. 956 * Then we'll dequeue only the xfers for this channel. 957 */ 958 if ((flags & AT_RST_NOCMD) == 0) { 959 /* 960 * move all xfers queued for this channel to the reset queue, 961 * and then process the current xfer and then the reset queue. 962 * We have to use a temporary queue because c_kill_xfer() 963 * may requeue commands. 964 */ 965 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 966 xfer != NULL; xfer = next_xfer) { 967 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 968 if (xfer->c_chp != chp) 969 continue; 970 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 971 xfer, c_xferchain); 972 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 973 } 974 xfer = chp->ch_queue->active_xfer; 975 if (xfer) { 976 if (xfer->c_chp != chp) 977 ata_reset_channel(xfer->c_chp, flags); 978 else { 979 callout_stop(&chp->ch_callout); 980 #if NATA_DMA || NATA_PIOBM 981 /* 982 * If we're waiting for DMA, stop the 983 * DMA engine 984 */ 985 if (chp->ch_flags & ATACH_DMA_WAIT) { 986 (*wdc->dma_finish)( 987 wdc->dma_arg, 988 chp->ch_channel, 989 xfer->c_drive, 990 WDC_DMAEND_ABRT_QUIET); 991 chp->ch_flags &= ~ATACH_DMA_WAIT; 992 } 993 #endif 994 chp->ch_queue->active_xfer = NULL; 995 if ((flags & AT_RST_EMERG) == 0) 996 xfer->c_kill_xfer( 997 chp, xfer, KILL_RESET); 998 } 999 } 1000 1001 for (xfer = TAILQ_FIRST(&reset_xfer); 1002 xfer != NULL; xfer = next_xfer) { 1003 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1004 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1005 if ((flags & AT_RST_EMERG) == 0) 1006 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1007 } 1008 } 1009 } 1010 1011 static int 1012 wdcreset(struct ata_channel *chp, int poll) 1013 { 1014 struct atac_softc *atac = chp->ch_atac; 1015 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1016 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1017 int drv_mask1, drv_mask2; 1018 1019 wdc->reset(chp, poll); 1020 1021 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1022 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1023 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1024 (poll == RESET_SLEEP) ? 0 : 1); 1025 if (drv_mask2 != drv_mask1) { 1026 printf("%s channel %d: reset failed for", 1027 atac->atac_dev.dv_xname, chp->ch_channel); 1028 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1029 printf(" drive 0"); 1030 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1031 printf(" drive 1"); 1032 printf("\n"); 1033 } 1034 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1035 return (drv_mask1 != drv_mask2) ? 1 : 0; 1036 } 1037 1038 void 1039 wdc_do_reset(struct ata_channel *chp, int poll) 1040 { 1041 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1042 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1043 int s = 0; 1044 1045 if (poll != RESET_SLEEP) 1046 s = splbio(); 1047 if (wdc->select) 1048 wdc->select(chp,0); 1049 /* master */ 1050 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1051 delay(10); /* 400ns delay */ 1052 /* assert SRST, wait for reset to complete */ 1053 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1054 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1055 delay(2000); 1056 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1057 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1058 WDCTL_4BIT | WDCTL_IDS); 1059 delay(10); /* 400ns delay */ 1060 if (poll != RESET_SLEEP) { 1061 /* ACK interrupt in case there is one pending left */ 1062 if (wdc->irqack) 1063 wdc->irqack(chp); 1064 splx(s); 1065 } 1066 } 1067 1068 static int 1069 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1070 { 1071 struct atac_softc *atac = chp->ch_atac; 1072 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1073 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1074 int timeout, nloop; 1075 u_int8_t st0 = 0, st1 = 0; 1076 #ifdef ATADEBUG 1077 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1078 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1079 #endif 1080 1081 if (poll) 1082 nloop = WDCNDELAY_RST; 1083 else 1084 nloop = WDC_RESET_WAIT * hz / 1000; 1085 /* wait for BSY to deassert */ 1086 for (timeout = 0; timeout < nloop; timeout++) { 1087 if ((drv_mask & 0x01) != 0) { 1088 if (wdc->select) 1089 wdc->select(chp,0); 1090 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1091 0, WDSD_IBM); /* master */ 1092 delay(10); 1093 st0 = bus_space_read_1(wdr->cmd_iot, 1094 wdr->cmd_iohs[wd_status], 0); 1095 #ifdef ATADEBUG 1096 sc0 = bus_space_read_1(wdr->cmd_iot, 1097 wdr->cmd_iohs[wd_seccnt], 0); 1098 sn0 = bus_space_read_1(wdr->cmd_iot, 1099 wdr->cmd_iohs[wd_sector], 0); 1100 cl0 = bus_space_read_1(wdr->cmd_iot, 1101 wdr->cmd_iohs[wd_cyl_lo], 0); 1102 ch0 = bus_space_read_1(wdr->cmd_iot, 1103 wdr->cmd_iohs[wd_cyl_hi], 0); 1104 #endif 1105 } 1106 if ((drv_mask & 0x02) != 0) { 1107 if (wdc->select) 1108 wdc->select(chp,1); 1109 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1110 0, WDSD_IBM | 0x10); /* slave */ 1111 delay(10); 1112 st1 = bus_space_read_1(wdr->cmd_iot, 1113 wdr->cmd_iohs[wd_status], 0); 1114 #ifdef ATADEBUG 1115 sc1 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_seccnt], 0); 1117 sn1 = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_sector], 0); 1119 cl1 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_cyl_lo], 0); 1121 ch1 = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_cyl_hi], 0); 1123 #endif 1124 } 1125 1126 if ((drv_mask & 0x01) == 0) { 1127 /* no master */ 1128 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1129 /* No master, slave is ready, it's done */ 1130 goto end; 1131 } 1132 if ((drv_mask & 0x02) == 0) { 1133 /* No master, no slave: it's done */ 1134 goto end; 1135 } 1136 } else if ((drv_mask & 0x02) == 0) { 1137 /* no slave */ 1138 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1139 /* No slave, master is ready, it's done */ 1140 goto end; 1141 } 1142 } else { 1143 /* Wait for both master and slave to be ready */ 1144 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1145 goto end; 1146 } 1147 } 1148 if (poll) 1149 delay(WDCDELAY); 1150 else 1151 tsleep(&nloop, PRIBIO, "atarst", 1); 1152 } 1153 /* Reset timed out. Maybe it's because drv_mask was not right */ 1154 if (st0 & WDCS_BSY) 1155 drv_mask &= ~0x01; 1156 if (st1 & WDCS_BSY) 1157 drv_mask &= ~0x02; 1158 end: 1159 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1160 "cl=0x%x ch=0x%x\n", 1161 atac->atac_dev.dv_xname, 1162 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1163 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1164 "cl=0x%x ch=0x%x\n", 1165 atac->atac_dev.dv_xname, 1166 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1167 1168 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1169 atac->atac_dev.dv_xname, chp->ch_channel, 1170 st0, st1), DEBUG_PROBE); 1171 1172 return drv_mask; 1173 } 1174 1175 /* 1176 * Wait for a drive to be !BSY, and have mask in its status register. 1177 * return -1 for a timeout after "timeout" ms. 1178 */ 1179 static int 1180 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1181 { 1182 struct atac_softc *atac = chp->ch_atac; 1183 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1184 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1185 u_char status; 1186 int xtime = 0; 1187 1188 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1189 atac->atac_dev.dv_xname, 1190 chp->ch_channel), DEBUG_STATUS); 1191 chp->ch_error = 0; 1192 1193 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1194 1195 for (;;) { 1196 chp->ch_status = status = 1197 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1198 if ((status & (WDCS_BSY | mask)) == bits) 1199 break; 1200 if (++xtime > timeout) { 1201 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1202 "status %x error %x (mask 0x%x bits 0x%x)\n", 1203 xtime, status, 1204 bus_space_read_1(wdr->cmd_iot, 1205 wdr->cmd_iohs[wd_error], 0), mask, bits), 1206 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1207 return(WDCWAIT_TOUT); 1208 } 1209 delay(WDCDELAY); 1210 } 1211 #ifdef ATADEBUG 1212 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1213 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1214 #endif 1215 if (status & WDCS_ERR) 1216 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1217 wdr->cmd_iohs[wd_error], 0); 1218 #ifdef WDCNDELAY_DEBUG 1219 /* After autoconfig, there should be no long delays. */ 1220 if (!cold && xtime > WDCNDELAY_DEBUG) { 1221 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1222 if (xfer == NULL) 1223 printf("%s channel %d: warning: busy-wait took %dus\n", 1224 atac->atac_dev.dv_xname, chp->ch_channel, 1225 WDCDELAY * xtime); 1226 else 1227 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1228 atac->atac_dev.dv_xname, chp->ch_channel, 1229 xfer->c_drive, 1230 WDCDELAY * xtime); 1231 } 1232 #endif 1233 return(WDCWAIT_OK); 1234 } 1235 1236 /* 1237 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1238 * thread if possible 1239 */ 1240 int 1241 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1242 { 1243 int error, i, timeout_hz = mstohz(timeout); 1244 1245 if (timeout_hz == 0 || 1246 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1247 error = __wdcwait(chp, mask, bits, timeout); 1248 else { 1249 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1250 if (error != 0) { 1251 if ((chp->ch_flags & ATACH_TH_RUN) || 1252 (flags & AT_WAIT)) { 1253 /* 1254 * we're running in the channel thread 1255 * or some userland thread context 1256 */ 1257 for (i = 0; i < timeout_hz; i++) { 1258 if (__wdcwait(chp, mask, bits, 1259 WDCDELAY_POLL) == 0) { 1260 error = 0; 1261 break; 1262 } 1263 tsleep(&chp, PRIBIO, "atapoll", 1); 1264 } 1265 } else { 1266 /* 1267 * we're probably in interrupt context, 1268 * ask the thread to come back here 1269 */ 1270 #ifdef DIAGNOSTIC 1271 if (chp->ch_queue->queue_freeze > 0) 1272 panic("wdcwait: queue_freeze"); 1273 #endif 1274 chp->ch_queue->queue_freeze++; 1275 wakeup(&chp->ch_thread); 1276 return(WDCWAIT_THR); 1277 } 1278 } 1279 } 1280 return (error); 1281 } 1282 1283 1284 #if NATA_DMA 1285 /* 1286 * Busy-wait for DMA to complete 1287 */ 1288 int 1289 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1290 { 1291 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1292 int xtime; 1293 1294 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1295 wdc->dma_status = 1296 (*wdc->dma_finish)(wdc->dma_arg, 1297 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1298 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1299 return 0; 1300 delay(WDCDELAY); 1301 } 1302 /* timeout, force a DMA halt */ 1303 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1304 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1305 return 1; 1306 } 1307 #endif 1308 1309 void 1310 wdctimeout(void *arg) 1311 { 1312 struct ata_channel *chp = (struct ata_channel *)arg; 1313 #if NATA_DMA || NATA_PIOBM 1314 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1315 #endif 1316 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1317 int s; 1318 1319 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1320 1321 s = splbio(); 1322 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1323 __wdcerror(chp, "lost interrupt"); 1324 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1325 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1326 xfer->c_bcount, 1327 xfer->c_skip); 1328 #if NATA_DMA || NATA_PIOBM 1329 if (chp->ch_flags & ATACH_DMA_WAIT) { 1330 wdc->dma_status = 1331 (*wdc->dma_finish)(wdc->dma_arg, 1332 chp->ch_channel, xfer->c_drive, 1333 WDC_DMAEND_ABRT); 1334 chp->ch_flags &= ~ATACH_DMA_WAIT; 1335 } 1336 #endif 1337 /* 1338 * Call the interrupt routine. If we just missed an interrupt, 1339 * it will do what's needed. Else, it will take the needed 1340 * action (reset the device). 1341 * Before that we need to reinstall the timeout callback, 1342 * in case it will miss another irq while in this transfer 1343 * We arbitray chose it to be 1s 1344 */ 1345 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1346 xfer->c_flags |= C_TIMEOU; 1347 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1348 xfer->c_intr(chp, xfer, 1); 1349 } else 1350 __wdcerror(chp, "missing untimeout"); 1351 splx(s); 1352 } 1353 1354 int 1355 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1356 { 1357 struct ata_channel *chp = drvp->chnl_softc; 1358 struct atac_softc *atac = chp->ch_atac; 1359 struct ata_xfer *xfer; 1360 int s, ret; 1361 1362 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1363 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1364 DEBUG_FUNCS); 1365 1366 /* set up an xfer and queue. Wait for completion */ 1367 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1368 ATAXF_NOSLEEP); 1369 if (xfer == NULL) { 1370 return ATACMD_TRY_AGAIN; 1371 } 1372 1373 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1374 ata_c->flags |= AT_POLL; 1375 if (ata_c->flags & AT_POLL) 1376 xfer->c_flags |= C_POLL; 1377 if (ata_c->flags & AT_WAIT) 1378 xfer->c_flags |= C_WAIT; 1379 xfer->c_drive = drvp->drive; 1380 xfer->c_databuf = ata_c->data; 1381 xfer->c_bcount = ata_c->bcount; 1382 xfer->c_cmd = ata_c; 1383 xfer->c_start = __wdccommand_start; 1384 xfer->c_intr = __wdccommand_intr; 1385 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1386 1387 s = splbio(); 1388 ata_exec_xfer(chp, xfer); 1389 #ifdef DIAGNOSTIC 1390 if ((ata_c->flags & AT_POLL) != 0 && 1391 (ata_c->flags & AT_DONE) == 0) 1392 panic("wdc_exec_command: polled command not done"); 1393 #endif 1394 if (ata_c->flags & AT_DONE) { 1395 ret = ATACMD_COMPLETE; 1396 } else { 1397 if (ata_c->flags & AT_WAIT) { 1398 while ((ata_c->flags & AT_DONE) == 0) { 1399 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1400 } 1401 ret = ATACMD_COMPLETE; 1402 } else { 1403 ret = ATACMD_QUEUED; 1404 } 1405 } 1406 splx(s); 1407 return ret; 1408 } 1409 1410 static void 1411 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1412 { 1413 struct atac_softc *atac = chp->ch_atac; 1414 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1415 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1416 int drive = xfer->c_drive; 1417 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1418 struct ata_command *ata_c = xfer->c_cmd; 1419 1420 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1421 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1422 DEBUG_FUNCS); 1423 1424 if (wdc->select) 1425 wdc->select(chp,drive); 1426 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1427 WDSD_IBM | (drive << 4)); 1428 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1429 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1430 case WDCWAIT_OK: 1431 break; 1432 case WDCWAIT_TOUT: 1433 ata_c->flags |= AT_TIMEOU; 1434 __wdccommand_done(chp, xfer); 1435 return; 1436 case WDCWAIT_THR: 1437 return; 1438 } 1439 if (ata_c->flags & AT_POLL) { 1440 /* polled command, disable interrupts */ 1441 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1442 WDCTL_4BIT | WDCTL_IDS); 1443 } 1444 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1445 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1446 1447 if ((ata_c->flags & AT_POLL) == 0) { 1448 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1449 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1450 wdctimeout, chp); 1451 return; 1452 } 1453 /* 1454 * Polled command. Wait for drive ready or drq. Done in intr(). 1455 * Wait for at last 400ns for status bit to be valid. 1456 */ 1457 delay(10); /* 400ns delay */ 1458 __wdccommand_intr(chp, xfer, 0); 1459 } 1460 1461 static int 1462 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1463 { 1464 struct atac_softc *atac = chp->ch_atac; 1465 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1466 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1467 struct ata_command *ata_c = xfer->c_cmd; 1468 int bcount = ata_c->bcount; 1469 char *data = ata_c->data; 1470 int wflags; 1471 int drive_flags; 1472 1473 if (ata_c->r_command == WDCC_IDENTIFY || 1474 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1475 /* 1476 * The IDENTIFY data has been designed as an array of 1477 * u_int16_t, so we can byteswap it on the fly. 1478 * Historically it's what we have always done so keeping it 1479 * here ensure binary backward compatibility. 1480 */ 1481 drive_flags = DRIVE_NOSTREAM | 1482 chp->ch_drive[xfer->c_drive].drive_flags; 1483 } else { 1484 /* 1485 * Other data structure are opaque and should be transfered 1486 * as is. 1487 */ 1488 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1489 } 1490 1491 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1492 /* both wait and poll, we can tsleep here */ 1493 wflags = AT_WAIT | AT_POLL; 1494 } else { 1495 wflags = AT_POLL; 1496 } 1497 1498 again: 1499 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1500 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1501 DEBUG_INTR); 1502 /* 1503 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1504 * Reselect again, it doesn't hurt for others commands, and the time 1505 * penalty for the extra regiter write is acceptable, 1506 * wdc_exec_command() isn't called often (mosly for autoconfig) 1507 */ 1508 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1509 WDSD_IBM | (xfer->c_drive << 4)); 1510 if ((ata_c->flags & AT_XFDONE) != 0) { 1511 /* 1512 * We have completed a data xfer. The drive should now be 1513 * in its initial state 1514 */ 1515 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1516 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1517 wflags) == WDCWAIT_TOUT) { 1518 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1519 return 0; /* IRQ was not for us */ 1520 ata_c->flags |= AT_TIMEOU; 1521 } 1522 goto out; 1523 } 1524 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1525 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1526 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1527 return 0; /* IRQ was not for us */ 1528 ata_c->flags |= AT_TIMEOU; 1529 goto out; 1530 } 1531 if (wdc->irqack) 1532 wdc->irqack(chp); 1533 if (ata_c->flags & AT_READ) { 1534 if ((chp->ch_status & WDCS_DRQ) == 0) { 1535 ata_c->flags |= AT_TIMEOU; 1536 goto out; 1537 } 1538 wdc->datain_pio(chp, drive_flags, data, bcount); 1539 /* at this point the drive should be in its initial state */ 1540 ata_c->flags |= AT_XFDONE; 1541 /* 1542 * XXX checking the status register again here cause some 1543 * hardware to timeout. 1544 */ 1545 } else if (ata_c->flags & AT_WRITE) { 1546 if ((chp->ch_status & WDCS_DRQ) == 0) { 1547 ata_c->flags |= AT_TIMEOU; 1548 goto out; 1549 } 1550 wdc->dataout_pio(chp, drive_flags, data, bcount); 1551 ata_c->flags |= AT_XFDONE; 1552 if ((ata_c->flags & AT_POLL) == 0) { 1553 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1554 callout_reset(&chp->ch_callout, 1555 mstohz(ata_c->timeout), wdctimeout, chp); 1556 return 1; 1557 } else { 1558 goto again; 1559 } 1560 } 1561 out: 1562 __wdccommand_done(chp, xfer); 1563 return 1; 1564 } 1565 1566 static void 1567 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1568 { 1569 struct atac_softc *atac = chp->ch_atac; 1570 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1571 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1572 struct ata_command *ata_c = xfer->c_cmd; 1573 1574 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1575 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1576 ata_c->flags), DEBUG_FUNCS); 1577 1578 1579 if (chp->ch_status & WDCS_DWF) 1580 ata_c->flags |= AT_DF; 1581 if (chp->ch_status & WDCS_ERR) { 1582 ata_c->flags |= AT_ERROR; 1583 ata_c->r_error = chp->ch_error; 1584 } 1585 if ((ata_c->flags & AT_READREG) != 0 && 1586 device_is_active(&atac->atac_dev) && 1587 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1588 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1589 wdr->cmd_iohs[wd_sdh], 0); 1590 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1591 wdr->cmd_iohs[wd_seccnt], 0); 1592 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1593 wdr->cmd_iohs[wd_sector], 0); 1594 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1595 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1596 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1597 wdr->cmd_iohs[wd_cyl_lo], 0); 1598 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1599 wdr->cmd_iohs[wd_error], 0); 1600 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1601 wdr->cmd_iohs[wd_features], 0); 1602 } 1603 callout_stop(&chp->ch_callout); 1604 chp->ch_queue->active_xfer = NULL; 1605 if (ata_c->flags & AT_POLL) { 1606 /* enable interrupts */ 1607 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1608 WDCTL_4BIT); 1609 delay(10); /* some drives need a little delay here */ 1610 } 1611 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1612 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1613 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1614 wakeup(&chp->ch_queue->active_xfer); 1615 } else 1616 __wdccommand_done_end(chp, xfer); 1617 } 1618 1619 static void 1620 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1621 { 1622 struct ata_command *ata_c = xfer->c_cmd; 1623 1624 ata_c->flags |= AT_DONE; 1625 ata_free_xfer(chp, xfer); 1626 if (ata_c->flags & AT_WAIT) 1627 wakeup(ata_c); 1628 else if (ata_c->callback) 1629 ata_c->callback(ata_c->callback_arg); 1630 atastart(chp); 1631 return; 1632 } 1633 1634 static void 1635 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1636 int reason) 1637 { 1638 struct ata_command *ata_c = xfer->c_cmd; 1639 1640 switch (reason) { 1641 case KILL_GONE: 1642 ata_c->flags |= AT_GONE; 1643 break; 1644 case KILL_RESET: 1645 ata_c->flags |= AT_RESET; 1646 break; 1647 default: 1648 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1649 reason); 1650 panic("__wdccommand_kill_xfer"); 1651 } 1652 __wdccommand_done_end(chp, xfer); 1653 } 1654 1655 /* 1656 * Send a command. The drive should be ready. 1657 * Assumes interrupts are blocked. 1658 */ 1659 void 1660 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1661 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1662 u_int8_t features) 1663 { 1664 struct atac_softc *atac = chp->ch_atac; 1665 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1666 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1667 1668 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1669 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1670 chp->ch_channel, drive, command, cylin, head, sector, count, 1671 features), DEBUG_FUNCS); 1672 1673 if (wdc->select) 1674 wdc->select(chp,drive); 1675 1676 /* Select drive, head, and addressing mode. */ 1677 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1678 WDSD_IBM | (drive << 4) | head); 1679 /* Load parameters into the wd_features register. */ 1680 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1681 features); 1682 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1684 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1685 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1686 0, cylin >> 8); 1687 1688 /* Send command. */ 1689 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1690 return; 1691 } 1692 1693 /* 1694 * Send a 48-bit addressing command. The drive should be ready. 1695 * Assumes interrupts are blocked. 1696 */ 1697 void 1698 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1699 u_int64_t blkno, u_int16_t count) 1700 { 1701 struct atac_softc *atac = chp->ch_atac; 1702 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1703 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1704 1705 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1706 "count=%d\n", atac->atac_dev.dv_xname, 1707 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1708 DEBUG_FUNCS); 1709 1710 if (wdc->select) 1711 wdc->select(chp,drive); 1712 1713 /* Select drive, head, and addressing mode. */ 1714 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1715 (drive << 4) | WDSD_LBA); 1716 1717 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1718 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1719 0); 1720 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1721 0, count); 1722 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1723 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1724 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1725 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1726 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1727 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1728 } else { 1729 /* previous */ 1730 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1731 0); 1732 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1733 0, count >> 8); 1734 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1735 0, blkno >> 24); 1736 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1737 0, blkno >> 32); 1738 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1739 0, blkno >> 40); 1740 1741 /* current */ 1742 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1743 0); 1744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1745 count); 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1747 blkno); 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1749 0, blkno >> 8); 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1751 0, blkno >> 16); 1752 } 1753 1754 /* Send command. */ 1755 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1756 return; 1757 } 1758 1759 /* 1760 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1761 * tested by the caller. 1762 */ 1763 void 1764 wdccommandshort(struct ata_channel *chp, int drive, int command) 1765 { 1766 struct atac_softc *atac = chp->ch_atac; 1767 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1768 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1769 1770 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1771 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1772 DEBUG_FUNCS); 1773 1774 if (wdc->select) 1775 wdc->select(chp,drive); 1776 1777 /* Select drive. */ 1778 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1779 WDSD_IBM | (drive << 4)); 1780 1781 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1782 } 1783 1784 static void 1785 __wdcerror(struct ata_channel *chp, const char *msg) 1786 { 1787 struct atac_softc *atac = chp->ch_atac; 1788 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1789 1790 if (xfer == NULL) 1791 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1792 msg); 1793 else 1794 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1795 chp->ch_channel, xfer->c_drive, msg); 1796 } 1797 1798 /* 1799 * the bit bucket 1800 */ 1801 void 1802 wdcbit_bucket(struct ata_channel *chp, int size) 1803 { 1804 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1805 1806 for (; size >= 2; size -= 2) 1807 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1808 if (size) 1809 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1810 } 1811 1812 static void 1813 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1814 { 1815 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1816 1817 #ifndef __NO_STRICT_ALIGNMENT 1818 if ((uintptr_t)bf & 1) 1819 goto unaligned; 1820 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1821 goto unaligned; 1822 #endif 1823 1824 if (flags & DRIVE_NOSTREAM) { 1825 if (flags & DRIVE_CAP32) { 1826 bus_space_read_multi_4(wdr->data32iot, 1827 wdr->data32ioh, 0, bf, len >> 2); 1828 bf = (char *)bf + (len & ~3); 1829 len &= 3; 1830 } 1831 if (len) { 1832 bus_space_read_multi_2(wdr->cmd_iot, 1833 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1834 } 1835 } else { 1836 if (flags & DRIVE_CAP32) { 1837 bus_space_read_multi_stream_4(wdr->data32iot, 1838 wdr->data32ioh, 0, bf, len >> 2); 1839 bf = (char *)bf + (len & ~3); 1840 len &= 3; 1841 } 1842 if (len) { 1843 bus_space_read_multi_stream_2(wdr->cmd_iot, 1844 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1845 } 1846 } 1847 return; 1848 1849 #ifndef __NO_STRICT_ALIGNMENT 1850 unaligned: 1851 if (flags & DRIVE_NOSTREAM) { 1852 if (flags & DRIVE_CAP32) { 1853 while (len > 3) { 1854 uint32_t val; 1855 1856 val = bus_space_read_4(wdr->data32iot, 1857 wdr->data32ioh, 0); 1858 memcpy(bf, &val, 4); 1859 bf = (char *)bf + 4; 1860 len -= 4; 1861 } 1862 } 1863 while (len > 1) { 1864 uint16_t val; 1865 1866 val = bus_space_read_2(wdr->cmd_iot, 1867 wdr->cmd_iohs[wd_data], 0); 1868 memcpy(bf, &val, 2); 1869 bf = (char *)bf + 2; 1870 len -= 2; 1871 } 1872 } else { 1873 if (flags & DRIVE_CAP32) { 1874 while (len > 3) { 1875 uint32_t val; 1876 1877 val = bus_space_read_stream_4(wdr->data32iot, 1878 wdr->data32ioh, 0); 1879 memcpy(bf, &val, 4); 1880 bf = (char *)bf + 4; 1881 len -= 4; 1882 } 1883 } 1884 while (len > 1) { 1885 uint16_t val; 1886 1887 val = bus_space_read_stream_2(wdr->cmd_iot, 1888 wdr->cmd_iohs[wd_data], 0); 1889 memcpy(bf, &val, 2); 1890 bf = (char *)bf + 2; 1891 len -= 2; 1892 } 1893 } 1894 #endif 1895 } 1896 1897 static void 1898 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1899 { 1900 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1901 1902 #ifndef __NO_STRICT_ALIGNMENT 1903 if ((uintptr_t)bf & 1) 1904 goto unaligned; 1905 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1906 goto unaligned; 1907 #endif 1908 1909 if (flags & DRIVE_NOSTREAM) { 1910 if (flags & DRIVE_CAP32) { 1911 bus_space_write_multi_4(wdr->data32iot, 1912 wdr->data32ioh, 0, bf, len >> 2); 1913 bf = (char *)bf + (len & ~3); 1914 len &= 3; 1915 } 1916 if (len) { 1917 bus_space_write_multi_2(wdr->cmd_iot, 1918 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1919 } 1920 } else { 1921 if (flags & DRIVE_CAP32) { 1922 bus_space_write_multi_stream_4(wdr->data32iot, 1923 wdr->data32ioh, 0, bf, len >> 2); 1924 bf = (char *)bf + (len & ~3); 1925 len &= 3; 1926 } 1927 if (len) { 1928 bus_space_write_multi_stream_2(wdr->cmd_iot, 1929 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1930 } 1931 } 1932 return; 1933 1934 #ifndef __NO_STRICT_ALIGNMENT 1935 unaligned: 1936 if (flags & DRIVE_NOSTREAM) { 1937 if (flags & DRIVE_CAP32) { 1938 while (len > 3) { 1939 uint32_t val; 1940 1941 memcpy(&val, bf, 4); 1942 bus_space_write_4(wdr->data32iot, 1943 wdr->data32ioh, 0, val); 1944 bf = (char *)bf + 4; 1945 len -= 4; 1946 } 1947 } 1948 while (len > 1) { 1949 uint16_t val; 1950 1951 memcpy(&val, bf, 2); 1952 bus_space_write_2(wdr->cmd_iot, 1953 wdr->cmd_iohs[wd_data], 0, val); 1954 bf = (char *)bf + 2; 1955 len -= 2; 1956 } 1957 } else { 1958 if (flags & DRIVE_CAP32) { 1959 while (len > 3) { 1960 uint32_t val; 1961 1962 memcpy(&val, bf, 4); 1963 bus_space_write_stream_4(wdr->data32iot, 1964 wdr->data32ioh, 0, val); 1965 bf = (char *)bf + 4; 1966 len -= 4; 1967 } 1968 } 1969 while (len > 1) { 1970 uint16_t val; 1971 1972 memcpy(&val, bf, 2); 1973 bus_space_write_stream_2(wdr->cmd_iot, 1974 wdr->cmd_iohs[wd_data], 0, val); 1975 bf = (char *)bf + 2; 1976 len -= 2; 1977 } 1978 } 1979 #endif 1980 } 1981
Indexes created Tue Sep 23 14:10:03 GMT 2025