wdc.c revision 1.246
1 /* $NetBSD: wdc.c,v 1.246 2007/01/26 16:28:18 sborrill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.246 2007/01/26 16:28:18 sborrill Exp $"); 74 75 #ifndef ATADEBUG 76 #define ATADEBUG 77 #endif /* ATADEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #define bus_space_read_stream_2 bus_space_read_2 98 #define bus_space_read_stream_4 bus_space_read_4 99 #define bus_space_write_stream_2 bus_space_write_2 100 #define bus_space_write_stream_4 bus_space_write_4 101 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 102 103 #include <dev/ata/atavar.h> 104 #include <dev/ata/atareg.h> 105 #include <dev/ata/satareg.h> 106 #include <dev/ata/satavar.h> 107 #include <dev/ic/wdcreg.h> 108 #include <dev/ic/wdcvar.h> 109 110 #include "locators.h" 111 112 #include "atapibus.h" 113 #include "wd.h" 114 #include "sata.h" 115 116 #define WDCDELAY 100 /* 100 microseconds */ 117 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 118 #if 0 119 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 120 #define WDCNDELAY_DEBUG 50 121 #endif 122 123 /* When polling wait that much and then tsleep for 1/hz seconds */ 124 #define WDCDELAY_POLL 1 /* ms */ 125 126 /* timeout for the control commands */ 127 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 128 129 /* 130 * timeout when waiting for BSY to deassert when probing. 131 * set to 5s. From the standards this could be up to 31, but we can't 132 * wait that much at boot time, and 5s seems to be enouth. 133 */ 134 #define WDC_PROBE_WAIT 5 135 136 137 #if NWD > 0 138 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 139 #else 140 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 141 const struct ata_bustype wdc_ata_bustype = { 142 SCSIPI_BUSTYPE_ATA, 143 NULL, /* wdc_ata_bio */ 144 NULL, /* wdc_reset_drive */ 145 wdc_reset_channel, 146 wdc_exec_command, 147 NULL, /* ata_get_params */ 148 NULL, /* wdc_ata_addref */ 149 NULL, /* wdc_ata_delref */ 150 NULL /* ata_kill_pending */ 151 }; 152 #endif 153 154 /* Flags to wdcreset(). */ 155 #define RESET_POLL 1 156 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 157 158 static int wdcprobe1(struct ata_channel *, int); 159 static int wdcreset(struct ata_channel *, int); 160 static void __wdcerror(struct ata_channel *, const char *); 161 static int __wdcwait_reset(struct ata_channel *, int, int); 162 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 163 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 164 static void __wdccommand_kill_xfer(struct ata_channel *, 165 struct ata_xfer *, int); 166 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 167 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 168 static int __wdcwait(struct ata_channel *, int, int, int); 169 170 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 171 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 172 173 #define DEBUG_INTR 0x01 174 #define DEBUG_XFERS 0x02 175 #define DEBUG_STATUS 0x04 176 #define DEBUG_FUNCS 0x08 177 #define DEBUG_PROBE 0x10 178 #define DEBUG_DETACH 0x20 179 #define DEBUG_DELAY 0x40 180 #ifdef ATADEBUG 181 extern int atadebug_mask; /* init'ed in ata.c */ 182 int wdc_nxfer = 0; 183 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 184 #else 185 #define ATADEBUG_PRINT(args, level) 186 #endif 187 188 /* 189 * Initialize the "shadow register" handles for a standard wdc controller. 190 */ 191 void 192 wdc_init_shadow_regs(struct ata_channel *chp) 193 { 194 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 195 196 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 197 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 198 } 199 200 /* 201 * Allocate a wdc_regs array, based on the number of channels. 202 */ 203 void 204 wdc_allocate_regs(struct wdc_softc *wdc) 205 { 206 207 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 208 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 209 } 210 211 #if NSATA > 0 212 /* 213 * probe drives on SATA controllers with standard SATA registers: 214 * bring the PHYs online, read the drive signature and set drive flags 215 * appropriately. 216 */ 217 void 218 wdc_sataprobe(struct ata_channel *chp) 219 { 220 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 221 uint16_t scnt, sn, cl, ch; 222 int i, s; 223 224 /* XXX This should be done by other code. */ 225 for (i = 0; i < chp->ch_ndrive; i++) { 226 chp->ch_drive[i].chnl_softc = chp; 227 chp->ch_drive[i].drive = i; 228 } 229 230 /* reset the PHY and bring online */ 231 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 232 wdr->sata_status)) { 233 case SStatus_DET_DEV: 234 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 235 WDSD_IBM); 236 delay(10); /* 400ns delay */ 237 scnt = bus_space_read_2(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_seccnt], 0); 239 sn = bus_space_read_2(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_sector], 0); 241 cl = bus_space_read_2(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_lo], 0); 243 ch = bus_space_read_2(wdr->cmd_iot, 244 wdr->cmd_iohs[wd_cyl_hi], 0); 245 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 248 scnt, sn, cl, ch), DEBUG_PROBE); 249 /* 250 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 251 * cases we get wrong values here, so ignore it. 252 */ 253 s = splbio(); 254 if (cl == 0x14 && ch == 0xeb) 255 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 256 else 257 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 258 splx(s); 259 260 /* 261 * issue a reset in case only the interface part of the drive 262 * is up 263 */ 264 if (wdcreset(chp, RESET_SLEEP) != 0) 265 chp->ch_drive[0].drive_flags = 0; 266 break; 267 268 default: 269 break; 270 } 271 } 272 #endif /* NSATA > 0 */ 273 274 275 /* Test to see controller with at last one attached drive is there. 276 * Returns a bit for each possible drive found (0x01 for drive 0, 277 * 0x02 for drive 1). 278 * Logic: 279 * - If a status register is at 0xff, assume there is no drive here 280 * (ISA has pull-up resistors). Similarly if the status register has 281 * the value we last wrote to the bus (for IDE interfaces without pullups). 282 * If no drive at all -> return. 283 * - reset the controller, wait for it to complete (may take up to 31s !). 284 * If timeout -> return. 285 * - test ATA/ATAPI signatures. If at last one drive found -> return. 286 * - try an ATA command on the master. 287 */ 288 289 void 290 wdc_drvprobe(struct ata_channel *chp) 291 { 292 struct ataparams params; 293 struct atac_softc *atac = chp->ch_atac; 294 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 295 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 296 u_int8_t st0 = 0, st1 = 0; 297 int i, j, error, s; 298 299 if (wdcprobe1(chp, 0) == 0) { 300 /* No drives, abort the attach here. */ 301 return; 302 } 303 304 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 305 for (i = 0; i < mstohz(3000); i++) { 306 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 307 if (wdc->select) 308 wdc->select(chp,0); 309 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 310 0, WDSD_IBM); 311 delay(10); /* 400ns delay */ 312 st0 = bus_space_read_1(wdr->cmd_iot, 313 wdr->cmd_iohs[wd_status], 0); 314 } 315 316 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 317 if (wdc->select) 318 wdc->select(chp,1); 319 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 320 0, WDSD_IBM | 0x10); 321 delay(10); /* 400ns delay */ 322 st1 = bus_space_read_1(wdr->cmd_iot, 323 wdr->cmd_iohs[wd_status], 0); 324 } 325 326 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 327 == 0 || 328 (st0 & WDCS_DRDY)) && 329 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 330 == 0 || 331 (st1 & WDCS_DRDY))) 332 break; 333 tsleep(¶ms, PRIBIO, "atadrdy", 1); 334 } 335 s = splbio(); 336 if ((st0 & WDCS_DRDY) == 0) 337 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 338 if ((st1 & WDCS_DRDY) == 0) 339 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 340 splx(s); 341 342 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 343 atac->atac_dev.dv_xname, 344 chp->ch_channel, st0, st1), DEBUG_PROBE); 345 346 /* Wait a bit, some devices are weird just after a reset. */ 347 delay(5000); 348 349 for (i = 0; i < chp->ch_ndrive; i++) { 350 /* XXX This should be done by other code. */ 351 chp->ch_drive[i].chnl_softc = chp; 352 chp->ch_drive[i].drive = i; 353 354 #if NATA_DMA 355 /* 356 * Init error counter so that an error withing the first xfers 357 * will trigger a downgrade 358 */ 359 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 360 #endif 361 362 /* If controller can't do 16bit flag the drives as 32bit */ 363 if ((atac->atac_cap & 364 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 365 s = splbio(); 366 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 367 splx(s); 368 } 369 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 370 continue; 371 372 /* Shortcut in case we've been shutdown */ 373 if (chp->ch_flags & ATACH_SHUTDOWN) 374 return; 375 376 /* 377 * Issue an identify, to try to detect ghosts. 378 * Note that we can't use interrupts here, because if there 379 * is no devices, we will get a command aborted without 380 * interrupts. 381 */ 382 error = ata_get_params(&chp->ch_drive[i], 383 AT_WAIT | AT_POLL, ¶ms); 384 if (error != CMD_OK) { 385 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 386 387 /* Shortcut in case we've been shutdown */ 388 if (chp->ch_flags & ATACH_SHUTDOWN) 389 return; 390 391 error = ata_get_params(&chp->ch_drive[i], 392 AT_WAIT | AT_POLL, ¶ms); 393 } 394 if (error == CMD_OK) { 395 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 396 s = splbio(); 397 for (j = 0; j < chp->ch_ndrive; j++) 398 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 399 splx(s); 400 } else { 401 s = splbio(); 402 chp->ch_drive[i].drive_flags &= 403 ~(DRIVE_ATA | DRIVE_ATAPI); 404 splx(s); 405 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 406 atac->atac_dev.dv_xname, 407 chp->ch_channel, i, error), DEBUG_PROBE); 408 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 409 continue; 410 /* 411 * Pre-ATA drive ? 412 * Test registers writability (Error register not 413 * writable, but cyllo is), then try an ATA command. 414 */ 415 if (wdc->select) 416 wdc->select(chp,i); 417 bus_space_write_1(wdr->cmd_iot, 418 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 419 delay(10); /* 400ns delay */ 420 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 421 0, 0x58); 422 bus_space_write_1(wdr->cmd_iot, 423 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 424 if (bus_space_read_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_error], 0) == 0x58 || 426 bus_space_read_1(wdr->cmd_iot, 427 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 428 ATADEBUG_PRINT(("%s:%d:%d: register " 429 "writability failed\n", 430 atac->atac_dev.dv_xname, 431 chp->ch_channel, i), DEBUG_PROBE); 432 s = splbio(); 433 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 434 splx(s); 435 continue; 436 } 437 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 438 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 439 atac->atac_dev.dv_xname, 440 chp->ch_channel, i), DEBUG_PROBE); 441 s = splbio(); 442 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 443 splx(s); 444 continue; 445 } 446 bus_space_write_1(wdr->cmd_iot, 447 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 448 delay(10); /* 400ns delay */ 449 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 450 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 451 atac->atac_dev.dv_xname, 452 chp->ch_channel, i), DEBUG_PROBE); 453 s = splbio(); 454 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 455 splx(s); 456 } else { 457 s = splbio(); 458 for (j = 0; j < chp->ch_ndrive; j++) 459 chp->ch_drive[j].drive_flags &= 460 ~(DRIVE_ATA | DRIVE_ATAPI); 461 splx(s); 462 } 463 } 464 } 465 } 466 467 int 468 wdcprobe(struct ata_channel *chp) 469 { 470 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 471 /* default reset method */ 472 if (wdc->reset == NULL) 473 wdc->reset = wdc_do_reset; 474 475 return (wdcprobe1(chp, 1)); 476 } 477 478 static int 479 wdcprobe1(struct ata_channel *chp, int poll) 480 { 481 struct atac_softc *atac = chp->ch_atac; 482 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 483 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 484 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 485 u_int8_t ret_value = 0x03; 486 u_int8_t drive; 487 int s; 488 int wdc_probe_count = 489 poll ? (WDC_PROBE_WAIT / WDCDELAY) : (WDC_PROBE_WAIT * hz); 490 491 /* 492 * Sanity check to see if the wdc channel responds at all. 493 */ 494 495 s = splbio(); 496 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 497 while (wdc_probe_count-- > 0) { 498 if (wdc->select) 499 wdc->select(chp,0); 500 501 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 502 0, WDSD_IBM); 503 delay(10); /* 400ns delay */ 504 st0 = bus_space_read_1(wdr->cmd_iot, 505 wdr->cmd_iohs[wd_status], 0); 506 507 if (wdc->select) 508 wdc->select(chp,1); 509 510 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 511 0, WDSD_IBM | 0x10); 512 delay(10); /* 400ns delay */ 513 st1 = bus_space_read_1(wdr->cmd_iot, 514 wdr->cmd_iohs[wd_status], 0); 515 if ((st0 & WDCS_BSY) == 0) 516 break; 517 } 518 519 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 520 atac->atac_dev.dv_xname, 521 chp->ch_channel, st0, st1), DEBUG_PROBE); 522 523 if (st0 == 0xff || st0 == WDSD_IBM) 524 ret_value &= ~0x01; 525 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 526 ret_value &= ~0x02; 527 /* Register writability test, drive 0. */ 528 if (ret_value & 0x01) { 529 if (wdc->select) 530 wdc->select(chp,0); 531 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 532 0, WDSD_IBM); 533 bus_space_write_1(wdr->cmd_iot, 534 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 535 cl = bus_space_read_1(wdr->cmd_iot, 536 wdr->cmd_iohs[wd_cyl_lo], 0); 537 if (cl != 0x02) { 538 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 539 "got 0x%x != 0x02\n", 540 atac->atac_dev.dv_xname, 541 chp->ch_channel, cl), 542 DEBUG_PROBE); 543 ret_value &= ~0x01; 544 } 545 bus_space_write_1(wdr->cmd_iot, 546 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 547 cl = bus_space_read_1(wdr->cmd_iot, 548 wdr->cmd_iohs[wd_cyl_lo], 0); 549 if (cl != 0x01) { 550 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 551 "got 0x%x != 0x01\n", 552 atac->atac_dev.dv_xname, 553 chp->ch_channel, cl), 554 DEBUG_PROBE); 555 ret_value &= ~0x01; 556 } 557 bus_space_write_1(wdr->cmd_iot, 558 wdr->cmd_iohs[wd_sector], 0, 0x01); 559 cl = bus_space_read_1(wdr->cmd_iot, 560 wdr->cmd_iohs[wd_sector], 0); 561 if (cl != 0x01) { 562 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 563 "got 0x%x != 0x01\n", 564 atac->atac_dev.dv_xname, 565 chp->ch_channel, cl), 566 DEBUG_PROBE); 567 ret_value &= ~0x01; 568 } 569 bus_space_write_1(wdr->cmd_iot, 570 wdr->cmd_iohs[wd_sector], 0, 0x02); 571 cl = bus_space_read_1(wdr->cmd_iot, 572 wdr->cmd_iohs[wd_sector], 0); 573 if (cl != 0x02) { 574 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 575 "got 0x%x != 0x02\n", 576 atac->atac_dev.dv_xname, 577 chp->ch_channel, cl), 578 DEBUG_PROBE); 579 ret_value &= ~0x01; 580 } 581 cl = bus_space_read_1(wdr->cmd_iot, 582 wdr->cmd_iohs[wd_cyl_lo], 0); 583 if (cl != 0x01) { 584 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 585 "got 0x%x != 0x01\n", 586 atac->atac_dev.dv_xname, 587 chp->ch_channel, cl), 588 DEBUG_PROBE); 589 ret_value &= ~0x01; 590 } 591 } 592 /* Register writability test, drive 1. */ 593 if (ret_value & 0x02) { 594 if (wdc->select) 595 wdc->select(chp,1); 596 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 597 0, WDSD_IBM | 0x10); 598 bus_space_write_1(wdr->cmd_iot, 599 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 600 cl = bus_space_read_1(wdr->cmd_iot, 601 wdr->cmd_iohs[wd_cyl_lo], 0); 602 if (cl != 0x02) { 603 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 604 "got 0x%x != 0x02\n", 605 atac->atac_dev.dv_xname, 606 chp->ch_channel, cl), 607 DEBUG_PROBE); 608 ret_value &= ~0x02; 609 } 610 bus_space_write_1(wdr->cmd_iot, 611 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 612 cl = bus_space_read_1(wdr->cmd_iot, 613 wdr->cmd_iohs[wd_cyl_lo], 0); 614 if (cl != 0x01) { 615 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 616 "got 0x%x != 0x01\n", 617 atac->atac_dev.dv_xname, 618 chp->ch_channel, cl), 619 DEBUG_PROBE); 620 ret_value &= ~0x02; 621 } 622 bus_space_write_1(wdr->cmd_iot, 623 wdr->cmd_iohs[wd_sector], 0, 0x01); 624 cl = bus_space_read_1(wdr->cmd_iot, 625 wdr->cmd_iohs[wd_sector], 0); 626 if (cl != 0x01) { 627 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 628 "got 0x%x != 0x01\n", 629 atac->atac_dev.dv_xname, 630 chp->ch_channel, cl), 631 DEBUG_PROBE); 632 ret_value &= ~0x02; 633 } 634 bus_space_write_1(wdr->cmd_iot, 635 wdr->cmd_iohs[wd_sector], 0, 0x02); 636 cl = bus_space_read_1(wdr->cmd_iot, 637 wdr->cmd_iohs[wd_sector], 0); 638 if (cl != 0x02) { 639 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 640 "got 0x%x != 0x02\n", 641 atac->atac_dev.dv_xname, 642 chp->ch_channel, cl), 643 DEBUG_PROBE); 644 ret_value &= ~0x02; 645 } 646 cl = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_cyl_lo], 0); 648 if (cl != 0x01) { 649 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 650 "got 0x%x != 0x01\n", 651 atac->atac_dev.dv_xname, 652 chp->ch_channel, cl), 653 DEBUG_PROBE); 654 ret_value &= ~0x02; 655 } 656 } 657 658 if (ret_value == 0) { 659 splx(s); 660 return 0; 661 } 662 } 663 664 665 #if 0 /* XXX this break some ATA or ATAPI devices */ 666 /* 667 * reset bus. Also send an ATAPI_RESET to devices, in case there are 668 * ATAPI device out there which don't react to the bus reset 669 */ 670 if (ret_value & 0x01) { 671 if (wdc->select) 672 wdc->select(chp,0); 673 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 674 0, WDSD_IBM); 675 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 676 ATAPI_SOFT_RESET); 677 } 678 if (ret_value & 0x02) { 679 if (wdc->select) 680 wdc->select(chp,0); 681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 682 0, WDSD_IBM | 0x10); 683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 684 ATAPI_SOFT_RESET); 685 } 686 687 delay(5000); 688 #endif 689 690 wdc->reset(chp, RESET_POLL); 691 DELAY(2000); 692 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 693 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 694 splx(s); 695 696 ret_value = __wdcwait_reset(chp, ret_value, poll); 697 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 698 atac->atac_dev.dv_xname, chp->ch_channel, 699 ret_value), DEBUG_PROBE); 700 701 /* if reset failed, there's nothing here */ 702 if (ret_value == 0) 703 return 0; 704 705 /* 706 * Test presence of drives. First test register signatures looking 707 * for ATAPI devices. If it's not an ATAPI and reset said there may 708 * be something here assume it's ATA or OLD. Ghost will be killed 709 * later in attach routine. 710 */ 711 for (drive = 0; drive < chp->ch_ndrive; drive++) { 712 if ((ret_value & (0x01 << drive)) == 0) 713 continue; 714 if (wdc->select) 715 wdc->select(chp,drive); 716 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 717 WDSD_IBM | (drive << 4)); 718 delay(10); /* 400ns delay */ 719 /* Save registers contents */ 720 sc = bus_space_read_1(wdr->cmd_iot, 721 wdr->cmd_iohs[wd_seccnt], 0); 722 sn = bus_space_read_1(wdr->cmd_iot, 723 wdr->cmd_iohs[wd_sector], 0); 724 cl = bus_space_read_1(wdr->cmd_iot, 725 wdr->cmd_iohs[wd_cyl_lo], 0); 726 ch = bus_space_read_1(wdr->cmd_iot, 727 wdr->cmd_iohs[wd_cyl_hi], 0); 728 729 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 730 "cl=0x%x ch=0x%x\n", 731 atac->atac_dev.dv_xname, 732 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 733 /* 734 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 735 * we get wrong values here, so ignore it. 736 */ 737 s = splbio(); 738 if (cl == 0x14 && ch == 0xeb) { 739 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 740 } else { 741 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 742 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 743 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 744 } 745 splx(s); 746 } 747 return (ret_value); 748 } 749 750 void 751 wdcattach(struct ata_channel *chp) 752 { 753 struct atac_softc *atac = chp->ch_atac; 754 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 755 756 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 757 758 /* default data transfer methods */ 759 if (wdc->datain_pio == NULL) 760 wdc->datain_pio = wdc_datain_pio; 761 if (wdc->dataout_pio == NULL) 762 wdc->dataout_pio = wdc_dataout_pio; 763 /* default reset method */ 764 if (wdc->reset == NULL) 765 wdc->reset = wdc_do_reset; 766 767 /* initialise global data */ 768 if (atac->atac_bustype_ata == NULL) 769 atac->atac_bustype_ata = &wdc_ata_bustype; 770 if (atac->atac_probe == NULL) 771 atac->atac_probe = wdc_drvprobe; 772 #if NATAPIBUS > 0 773 if (atac->atac_atapibus_attach == NULL) 774 atac->atac_atapibus_attach = wdc_atapibus_attach; 775 #endif 776 777 ata_channel_attach(chp); 778 } 779 780 int 781 wdcactivate(struct device *self, enum devact act) 782 { 783 struct atac_softc *atac = (struct atac_softc *) self; 784 int s, i, error = 0; 785 786 s = splbio(); 787 switch (act) { 788 case DVACT_ACTIVATE: 789 error = EOPNOTSUPP; 790 break; 791 792 case DVACT_DEACTIVATE: 793 for (i = 0; i < atac->atac_nchannels; i++) { 794 error = 795 config_deactivate(atac->atac_channels[i]->atabus); 796 if (error) 797 break; 798 } 799 break; 800 } 801 splx(s); 802 return (error); 803 } 804 805 int 806 wdcdetach(struct device *self, int flags) 807 { 808 struct atac_softc *atac = (struct atac_softc *) self; 809 struct ata_channel *chp; 810 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 811 int i, error = 0; 812 813 for (i = 0; i < atac->atac_nchannels; i++) { 814 chp = atac->atac_channels[i]; 815 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 816 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 817 DEBUG_DETACH); 818 error = config_detach(chp->atabus, flags); 819 if (error) 820 break; 821 } 822 if (adapt->adapt_refcnt != 0) { 823 #ifdef DIAGNOSTIC 824 printf("wdcdetach: refcnt should be 0 here??\n"); 825 #endif 826 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 827 } 828 return (error); 829 } 830 831 /* restart an interrupted I/O */ 832 void 833 wdcrestart(void *v) 834 { 835 struct ata_channel *chp = v; 836 int s; 837 838 s = splbio(); 839 atastart(chp); 840 splx(s); 841 } 842 843 844 /* 845 * Interrupt routine for the controller. Acknowledge the interrupt, check for 846 * errors on the current operation, mark it done if necessary, and start the 847 * next request. Also check for a partially done transfer, and continue with 848 * the next chunk if so. 849 */ 850 int 851 wdcintr(void *arg) 852 { 853 struct ata_channel *chp = arg; 854 struct atac_softc *atac = chp->ch_atac; 855 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 856 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 857 struct ata_xfer *xfer; 858 int ret; 859 860 if (!device_is_active(&atac->atac_dev)) { 861 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 862 DEBUG_INTR); 863 return (0); 864 } 865 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 866 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 867 /* try to clear the pending interrupt anyway */ 868 (void)bus_space_read_1(wdr->cmd_iot, 869 wdr->cmd_iohs[wd_status], 0); 870 return (0); 871 } 872 873 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 874 xfer = chp->ch_queue->active_xfer; 875 #ifdef DIAGNOSTIC 876 if (xfer == NULL) 877 panic("wdcintr: no xfer"); 878 if (xfer->c_chp != chp) { 879 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 880 chp->ch_channel); 881 panic("wdcintr: wrong channel"); 882 } 883 #endif 884 #if NATA_DMA || NATA_PIOBM 885 if (chp->ch_flags & ATACH_DMA_WAIT) { 886 wdc->dma_status = 887 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 888 xfer->c_drive, WDC_DMAEND_END); 889 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 890 /* IRQ not for us, not detected by DMA engine */ 891 return 0; 892 } 893 chp->ch_flags &= ~ATACH_DMA_WAIT; 894 } 895 #endif 896 chp->ch_flags &= ~ATACH_IRQ_WAIT; 897 ret = xfer->c_intr(chp, xfer, 1); 898 if (ret == 0) /* irq was not for us, still waiting for irq */ 899 chp->ch_flags |= ATACH_IRQ_WAIT; 900 return (ret); 901 } 902 903 /* Put all disk in RESET state */ 904 void 905 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 906 { 907 struct ata_channel *chp = drvp->chnl_softc; 908 struct atac_softc *atac = chp->ch_atac; 909 910 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 911 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 912 DEBUG_FUNCS); 913 914 ata_reset_channel(chp, flags); 915 } 916 917 void 918 wdc_reset_channel(struct ata_channel *chp, int flags) 919 { 920 TAILQ_HEAD(, ata_xfer) reset_xfer; 921 struct ata_xfer *xfer, *next_xfer; 922 #if NATA_DMA || NATA_PIOBM 923 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 924 #endif 925 926 TAILQ_INIT(&reset_xfer); 927 928 chp->ch_flags &= ~ATACH_IRQ_WAIT; 929 930 /* 931 * if the current command if on an ATAPI device, issue a 932 * ATAPI_SOFT_RESET 933 */ 934 xfer = chp->ch_queue->active_xfer; 935 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 936 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 937 if (flags & AT_WAIT) 938 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 939 else 940 delay(1000); 941 } 942 943 /* reset the channel */ 944 if (flags & AT_WAIT) 945 (void) wdcreset(chp, RESET_SLEEP); 946 else 947 (void) wdcreset(chp, RESET_POLL); 948 949 /* 950 * wait a bit after reset; in case the DMA engines needs some time 951 * to recover. 952 */ 953 if (flags & AT_WAIT) 954 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 955 else 956 delay(1000); 957 /* 958 * look for pending xfers. If we have a shared queue, we'll also reset 959 * the other channel if the current xfer is running on it. 960 * Then we'll dequeue only the xfers for this channel. 961 */ 962 if ((flags & AT_RST_NOCMD) == 0) { 963 /* 964 * move all xfers queued for this channel to the reset queue, 965 * and then process the current xfer and then the reset queue. 966 * We have to use a temporary queue because c_kill_xfer() 967 * may requeue commands. 968 */ 969 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 970 xfer != NULL; xfer = next_xfer) { 971 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 972 if (xfer->c_chp != chp) 973 continue; 974 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 975 xfer, c_xferchain); 976 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 977 } 978 xfer = chp->ch_queue->active_xfer; 979 if (xfer) { 980 if (xfer->c_chp != chp) 981 ata_reset_channel(xfer->c_chp, flags); 982 else { 983 callout_stop(&chp->ch_callout); 984 #if NATA_DMA || NATA_PIOBM 985 /* 986 * If we're waiting for DMA, stop the 987 * DMA engine 988 */ 989 if (chp->ch_flags & ATACH_DMA_WAIT) { 990 (*wdc->dma_finish)( 991 wdc->dma_arg, 992 chp->ch_channel, 993 xfer->c_drive, 994 WDC_DMAEND_ABRT_QUIET); 995 chp->ch_flags &= ~ATACH_DMA_WAIT; 996 } 997 #endif 998 chp->ch_queue->active_xfer = NULL; 999 if ((flags & AT_RST_EMERG) == 0) 1000 xfer->c_kill_xfer( 1001 chp, xfer, KILL_RESET); 1002 } 1003 } 1004 1005 for (xfer = TAILQ_FIRST(&reset_xfer); 1006 xfer != NULL; xfer = next_xfer) { 1007 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1008 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1009 if ((flags & AT_RST_EMERG) == 0) 1010 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1011 } 1012 } 1013 } 1014 1015 static int 1016 wdcreset(struct ata_channel *chp, int poll) 1017 { 1018 struct atac_softc *atac = chp->ch_atac; 1019 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1020 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1021 int drv_mask1, drv_mask2; 1022 1023 wdc->reset(chp, poll); 1024 1025 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1026 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1027 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1028 (poll == RESET_SLEEP) ? 0 : 1); 1029 if (drv_mask2 != drv_mask1) { 1030 printf("%s channel %d: reset failed for", 1031 atac->atac_dev.dv_xname, chp->ch_channel); 1032 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1033 printf(" drive 0"); 1034 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1035 printf(" drive 1"); 1036 printf("\n"); 1037 } 1038 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1039 return (drv_mask1 != drv_mask2) ? 1 : 0; 1040 } 1041 1042 void 1043 wdc_do_reset(struct ata_channel *chp, int poll) 1044 { 1045 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1046 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1047 int s = 0; 1048 1049 if (poll != RESET_SLEEP) 1050 s = splbio(); 1051 if (wdc->select) 1052 wdc->select(chp,0); 1053 /* master */ 1054 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1055 delay(10); /* 400ns delay */ 1056 /* assert SRST, wait for reset to complete */ 1057 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1058 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1059 delay(2000); 1060 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1061 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1062 WDCTL_4BIT | WDCTL_IDS); 1063 delay(10); /* 400ns delay */ 1064 if (poll != RESET_SLEEP) { 1065 /* ACK interrupt in case there is one pending left */ 1066 if (wdc->irqack) 1067 wdc->irqack(chp); 1068 splx(s); 1069 } 1070 } 1071 1072 static int 1073 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1074 { 1075 struct atac_softc *atac = chp->ch_atac; 1076 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1077 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1078 int timeout, nloop; 1079 u_int8_t st0 = 0, st1 = 0; 1080 #ifdef ATADEBUG 1081 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1082 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1083 #endif 1084 1085 if (poll) 1086 nloop = WDCNDELAY_RST; 1087 else 1088 nloop = WDC_RESET_WAIT * hz / 1000; 1089 /* wait for BSY to deassert */ 1090 for (timeout = 0; timeout < nloop; timeout++) { 1091 if ((drv_mask & 0x01) != 0) { 1092 if (wdc->select) 1093 wdc->select(chp,0); 1094 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1095 0, WDSD_IBM); /* master */ 1096 delay(10); 1097 st0 = bus_space_read_1(wdr->cmd_iot, 1098 wdr->cmd_iohs[wd_status], 0); 1099 #ifdef ATADEBUG 1100 sc0 = bus_space_read_1(wdr->cmd_iot, 1101 wdr->cmd_iohs[wd_seccnt], 0); 1102 sn0 = bus_space_read_1(wdr->cmd_iot, 1103 wdr->cmd_iohs[wd_sector], 0); 1104 cl0 = bus_space_read_1(wdr->cmd_iot, 1105 wdr->cmd_iohs[wd_cyl_lo], 0); 1106 ch0 = bus_space_read_1(wdr->cmd_iot, 1107 wdr->cmd_iohs[wd_cyl_hi], 0); 1108 #endif 1109 } 1110 if ((drv_mask & 0x02) != 0) { 1111 if (wdc->select) 1112 wdc->select(chp,1); 1113 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1114 0, WDSD_IBM | 0x10); /* slave */ 1115 delay(10); 1116 st1 = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_status], 0); 1118 #ifdef ATADEBUG 1119 sc1 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_seccnt], 0); 1121 sn1 = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_sector], 0); 1123 cl1 = bus_space_read_1(wdr->cmd_iot, 1124 wdr->cmd_iohs[wd_cyl_lo], 0); 1125 ch1 = bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_cyl_hi], 0); 1127 #endif 1128 } 1129 1130 if ((drv_mask & 0x01) == 0) { 1131 /* no master */ 1132 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1133 /* No master, slave is ready, it's done */ 1134 goto end; 1135 } 1136 if ((drv_mask & 0x02) == 0) { 1137 /* No master, no slave: it's done */ 1138 goto end; 1139 } 1140 } else if ((drv_mask & 0x02) == 0) { 1141 /* no slave */ 1142 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1143 /* No slave, master is ready, it's done */ 1144 goto end; 1145 } 1146 } else { 1147 /* Wait for both master and slave to be ready */ 1148 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1149 goto end; 1150 } 1151 } 1152 if (poll) 1153 delay(WDCDELAY); 1154 else 1155 tsleep(&nloop, PRIBIO, "atarst", 1); 1156 } 1157 /* Reset timed out. Maybe it's because drv_mask was not right */ 1158 if (st0 & WDCS_BSY) 1159 drv_mask &= ~0x01; 1160 if (st1 & WDCS_BSY) 1161 drv_mask &= ~0x02; 1162 end: 1163 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1164 "cl=0x%x ch=0x%x\n", 1165 atac->atac_dev.dv_xname, 1166 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1167 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1168 "cl=0x%x ch=0x%x\n", 1169 atac->atac_dev.dv_xname, 1170 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1171 1172 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1173 atac->atac_dev.dv_xname, chp->ch_channel, 1174 st0, st1), DEBUG_PROBE); 1175 1176 return drv_mask; 1177 } 1178 1179 /* 1180 * Wait for a drive to be !BSY, and have mask in its status register. 1181 * return -1 for a timeout after "timeout" ms. 1182 */ 1183 static int 1184 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1185 { 1186 struct atac_softc *atac = chp->ch_atac; 1187 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1188 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1189 u_char status; 1190 int xtime = 0; 1191 1192 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1193 atac->atac_dev.dv_xname, 1194 chp->ch_channel), DEBUG_STATUS); 1195 chp->ch_error = 0; 1196 1197 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1198 1199 for (;;) { 1200 chp->ch_status = status = 1201 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1202 if ((status & (WDCS_BSY | mask)) == bits) 1203 break; 1204 if (++xtime > timeout) { 1205 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1206 "status %x error %x (mask 0x%x bits 0x%x)\n", 1207 xtime, status, 1208 bus_space_read_1(wdr->cmd_iot, 1209 wdr->cmd_iohs[wd_error], 0), mask, bits), 1210 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1211 return(WDCWAIT_TOUT); 1212 } 1213 delay(WDCDELAY); 1214 } 1215 #ifdef ATADEBUG 1216 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1217 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1218 #endif 1219 if (status & WDCS_ERR) 1220 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1221 wdr->cmd_iohs[wd_error], 0); 1222 #ifdef WDCNDELAY_DEBUG 1223 /* After autoconfig, there should be no long delays. */ 1224 if (!cold && xtime > WDCNDELAY_DEBUG) { 1225 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1226 if (xfer == NULL) 1227 printf("%s channel %d: warning: busy-wait took %dus\n", 1228 atac->atac_dev.dv_xname, chp->ch_channel, 1229 WDCDELAY * xtime); 1230 else 1231 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1232 atac->atac_dev.dv_xname, chp->ch_channel, 1233 xfer->c_drive, 1234 WDCDELAY * xtime); 1235 } 1236 #endif 1237 return(WDCWAIT_OK); 1238 } 1239 1240 /* 1241 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1242 * thread if possible 1243 */ 1244 int 1245 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1246 { 1247 int error, i, timeout_hz = mstohz(timeout); 1248 1249 if (timeout_hz == 0 || 1250 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1251 error = __wdcwait(chp, mask, bits, timeout); 1252 else { 1253 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1254 if (error != 0) { 1255 if ((chp->ch_flags & ATACH_TH_RUN) || 1256 (flags & AT_WAIT)) { 1257 /* 1258 * we're running in the channel thread 1259 * or some userland thread context 1260 */ 1261 for (i = 0; i < timeout_hz; i++) { 1262 if (__wdcwait(chp, mask, bits, 1263 WDCDELAY_POLL) == 0) { 1264 error = 0; 1265 break; 1266 } 1267 tsleep(&chp, PRIBIO, "atapoll", 1); 1268 } 1269 } else { 1270 /* 1271 * we're probably in interrupt context, 1272 * ask the thread to come back here 1273 */ 1274 #ifdef DIAGNOSTIC 1275 if (chp->ch_queue->queue_freeze > 0) 1276 panic("wdcwait: queue_freeze"); 1277 #endif 1278 chp->ch_queue->queue_freeze++; 1279 wakeup(&chp->ch_thread); 1280 return(WDCWAIT_THR); 1281 } 1282 } 1283 } 1284 return (error); 1285 } 1286 1287 1288 #if NATA_DMA 1289 /* 1290 * Busy-wait for DMA to complete 1291 */ 1292 int 1293 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1294 { 1295 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1296 int xtime; 1297 1298 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1299 wdc->dma_status = 1300 (*wdc->dma_finish)(wdc->dma_arg, 1301 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1302 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1303 return 0; 1304 delay(WDCDELAY); 1305 } 1306 /* timeout, force a DMA halt */ 1307 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1308 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1309 return 1; 1310 } 1311 #endif 1312 1313 void 1314 wdctimeout(void *arg) 1315 { 1316 struct ata_channel *chp = (struct ata_channel *)arg; 1317 #if NATA_DMA || NATA_PIOBM 1318 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1319 #endif 1320 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1321 int s; 1322 1323 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1324 1325 s = splbio(); 1326 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1327 __wdcerror(chp, "lost interrupt"); 1328 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1329 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1330 xfer->c_bcount, 1331 xfer->c_skip); 1332 #if NATA_DMA || NATA_PIOBM 1333 if (chp->ch_flags & ATACH_DMA_WAIT) { 1334 wdc->dma_status = 1335 (*wdc->dma_finish)(wdc->dma_arg, 1336 chp->ch_channel, xfer->c_drive, 1337 WDC_DMAEND_ABRT); 1338 chp->ch_flags &= ~ATACH_DMA_WAIT; 1339 } 1340 #endif 1341 /* 1342 * Call the interrupt routine. If we just missed an interrupt, 1343 * it will do what's needed. Else, it will take the needed 1344 * action (reset the device). 1345 * Before that we need to reinstall the timeout callback, 1346 * in case it will miss another irq while in this transfer 1347 * We arbitray chose it to be 1s 1348 */ 1349 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1350 xfer->c_flags |= C_TIMEOU; 1351 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1352 xfer->c_intr(chp, xfer, 1); 1353 } else 1354 __wdcerror(chp, "missing untimeout"); 1355 splx(s); 1356 } 1357 1358 int 1359 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1360 { 1361 struct ata_channel *chp = drvp->chnl_softc; 1362 struct atac_softc *atac = chp->ch_atac; 1363 struct ata_xfer *xfer; 1364 int s, ret; 1365 1366 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1367 atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1368 DEBUG_FUNCS); 1369 1370 /* set up an xfer and queue. Wait for completion */ 1371 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1372 ATAXF_NOSLEEP); 1373 if (xfer == NULL) { 1374 return ATACMD_TRY_AGAIN; 1375 } 1376 1377 if (atac->atac_cap & ATAC_CAP_NOIRQ) 1378 ata_c->flags |= AT_POLL; 1379 if (ata_c->flags & AT_POLL) 1380 xfer->c_flags |= C_POLL; 1381 if (ata_c->flags & AT_WAIT) 1382 xfer->c_flags |= C_WAIT; 1383 xfer->c_drive = drvp->drive; 1384 xfer->c_databuf = ata_c->data; 1385 xfer->c_bcount = ata_c->bcount; 1386 xfer->c_cmd = ata_c; 1387 xfer->c_start = __wdccommand_start; 1388 xfer->c_intr = __wdccommand_intr; 1389 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1390 1391 s = splbio(); 1392 ata_exec_xfer(chp, xfer); 1393 #ifdef DIAGNOSTIC 1394 if ((ata_c->flags & AT_POLL) != 0 && 1395 (ata_c->flags & AT_DONE) == 0) 1396 panic("wdc_exec_command: polled command not done"); 1397 #endif 1398 if (ata_c->flags & AT_DONE) { 1399 ret = ATACMD_COMPLETE; 1400 } else { 1401 if (ata_c->flags & AT_WAIT) { 1402 while ((ata_c->flags & AT_DONE) == 0) { 1403 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1404 } 1405 ret = ATACMD_COMPLETE; 1406 } else { 1407 ret = ATACMD_QUEUED; 1408 } 1409 } 1410 splx(s); 1411 return ret; 1412 } 1413 1414 static void 1415 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1416 { 1417 struct atac_softc *atac = chp->ch_atac; 1418 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1419 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1420 int drive = xfer->c_drive; 1421 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1422 struct ata_command *ata_c = xfer->c_cmd; 1423 1424 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1425 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1426 DEBUG_FUNCS); 1427 1428 if (wdc->select) 1429 wdc->select(chp,drive); 1430 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1431 WDSD_IBM | (drive << 4)); 1432 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1433 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1434 case WDCWAIT_OK: 1435 break; 1436 case WDCWAIT_TOUT: 1437 ata_c->flags |= AT_TIMEOU; 1438 __wdccommand_done(chp, xfer); 1439 return; 1440 case WDCWAIT_THR: 1441 return; 1442 } 1443 if (ata_c->flags & AT_POLL) { 1444 /* polled command, disable interrupts */ 1445 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1446 WDCTL_4BIT | WDCTL_IDS); 1447 } 1448 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1449 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1450 1451 if ((ata_c->flags & AT_POLL) == 0) { 1452 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1453 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1454 wdctimeout, chp); 1455 return; 1456 } 1457 /* 1458 * Polled command. Wait for drive ready or drq. Done in intr(). 1459 * Wait for at last 400ns for status bit to be valid. 1460 */ 1461 delay(10); /* 400ns delay */ 1462 __wdccommand_intr(chp, xfer, 0); 1463 } 1464 1465 static int 1466 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1467 { 1468 struct atac_softc *atac = chp->ch_atac; 1469 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1470 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1471 struct ata_command *ata_c = xfer->c_cmd; 1472 int bcount = ata_c->bcount; 1473 char *data = ata_c->data; 1474 int wflags; 1475 int drive_flags; 1476 1477 if (ata_c->r_command == WDCC_IDENTIFY || 1478 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1479 /* 1480 * The IDENTIFY data has been designed as an array of 1481 * u_int16_t, so we can byteswap it on the fly. 1482 * Historically it's what we have always done so keeping it 1483 * here ensure binary backward compatibility. 1484 */ 1485 drive_flags = DRIVE_NOSTREAM | 1486 chp->ch_drive[xfer->c_drive].drive_flags; 1487 } else { 1488 /* 1489 * Other data structure are opaque and should be transfered 1490 * as is. 1491 */ 1492 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1493 } 1494 1495 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1496 /* both wait and poll, we can tsleep here */ 1497 wflags = AT_WAIT | AT_POLL; 1498 } else { 1499 wflags = AT_POLL; 1500 } 1501 1502 again: 1503 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1504 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1505 DEBUG_INTR); 1506 /* 1507 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1508 * Reselect again, it doesn't hurt for others commands, and the time 1509 * penalty for the extra regiter write is acceptable, 1510 * wdc_exec_command() isn't called often (mosly for autoconfig) 1511 */ 1512 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1513 WDSD_IBM | (xfer->c_drive << 4)); 1514 if ((ata_c->flags & AT_XFDONE) != 0) { 1515 /* 1516 * We have completed a data xfer. The drive should now be 1517 * in its initial state 1518 */ 1519 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1520 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1521 wflags) == WDCWAIT_TOUT) { 1522 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1523 return 0; /* IRQ was not for us */ 1524 ata_c->flags |= AT_TIMEOU; 1525 } 1526 goto out; 1527 } 1528 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1529 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1530 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1531 return 0; /* IRQ was not for us */ 1532 ata_c->flags |= AT_TIMEOU; 1533 goto out; 1534 } 1535 if (wdc->irqack) 1536 wdc->irqack(chp); 1537 if (ata_c->flags & AT_READ) { 1538 if ((chp->ch_status & WDCS_DRQ) == 0) { 1539 ata_c->flags |= AT_TIMEOU; 1540 goto out; 1541 } 1542 wdc->datain_pio(chp, drive_flags, data, bcount); 1543 /* at this point the drive should be in its initial state */ 1544 ata_c->flags |= AT_XFDONE; 1545 /* 1546 * XXX checking the status register again here cause some 1547 * hardware to timeout. 1548 */ 1549 } else if (ata_c->flags & AT_WRITE) { 1550 if ((chp->ch_status & WDCS_DRQ) == 0) { 1551 ata_c->flags |= AT_TIMEOU; 1552 goto out; 1553 } 1554 wdc->dataout_pio(chp, drive_flags, data, bcount); 1555 ata_c->flags |= AT_XFDONE; 1556 if ((ata_c->flags & AT_POLL) == 0) { 1557 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1558 callout_reset(&chp->ch_callout, 1559 mstohz(ata_c->timeout), wdctimeout, chp); 1560 return 1; 1561 } else { 1562 goto again; 1563 } 1564 } 1565 out: 1566 __wdccommand_done(chp, xfer); 1567 return 1; 1568 } 1569 1570 static void 1571 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1572 { 1573 struct atac_softc *atac = chp->ch_atac; 1574 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1575 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1576 struct ata_command *ata_c = xfer->c_cmd; 1577 1578 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1579 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1580 ata_c->flags), DEBUG_FUNCS); 1581 1582 1583 if (chp->ch_status & WDCS_DWF) 1584 ata_c->flags |= AT_DF; 1585 if (chp->ch_status & WDCS_ERR) { 1586 ata_c->flags |= AT_ERROR; 1587 ata_c->r_error = chp->ch_error; 1588 } 1589 if ((ata_c->flags & AT_READREG) != 0 && 1590 device_is_active(&atac->atac_dev) && 1591 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1592 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1593 wdr->cmd_iohs[wd_sdh], 0); 1594 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1595 wdr->cmd_iohs[wd_seccnt], 0); 1596 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1597 wdr->cmd_iohs[wd_sector], 0); 1598 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1599 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1600 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1601 wdr->cmd_iohs[wd_cyl_lo], 0); 1602 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1603 wdr->cmd_iohs[wd_error], 0); 1604 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1605 wdr->cmd_iohs[wd_features], 0); 1606 } 1607 callout_stop(&chp->ch_callout); 1608 chp->ch_queue->active_xfer = NULL; 1609 if (ata_c->flags & AT_POLL) { 1610 /* enable interrupts */ 1611 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1612 WDCTL_4BIT); 1613 delay(10); /* some drives need a little delay here */ 1614 } 1615 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1616 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1617 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1618 wakeup(&chp->ch_queue->active_xfer); 1619 } else 1620 __wdccommand_done_end(chp, xfer); 1621 } 1622 1623 static void 1624 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1625 { 1626 struct ata_command *ata_c = xfer->c_cmd; 1627 1628 ata_c->flags |= AT_DONE; 1629 ata_free_xfer(chp, xfer); 1630 if (ata_c->flags & AT_WAIT) 1631 wakeup(ata_c); 1632 else if (ata_c->callback) 1633 ata_c->callback(ata_c->callback_arg); 1634 atastart(chp); 1635 return; 1636 } 1637 1638 static void 1639 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1640 int reason) 1641 { 1642 struct ata_command *ata_c = xfer->c_cmd; 1643 1644 switch (reason) { 1645 case KILL_GONE: 1646 ata_c->flags |= AT_GONE; 1647 break; 1648 case KILL_RESET: 1649 ata_c->flags |= AT_RESET; 1650 break; 1651 default: 1652 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1653 reason); 1654 panic("__wdccommand_kill_xfer"); 1655 } 1656 __wdccommand_done_end(chp, xfer); 1657 } 1658 1659 /* 1660 * Send a command. The drive should be ready. 1661 * Assumes interrupts are blocked. 1662 */ 1663 void 1664 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1665 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1666 u_int8_t features) 1667 { 1668 struct atac_softc *atac = chp->ch_atac; 1669 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1670 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1671 1672 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1673 "sector=%d count=%d features=%d\n", atac->atac_dev.dv_xname, 1674 chp->ch_channel, drive, command, cylin, head, sector, count, 1675 features), DEBUG_FUNCS); 1676 1677 if (wdc->select) 1678 wdc->select(chp,drive); 1679 1680 /* Select drive, head, and addressing mode. */ 1681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1682 WDSD_IBM | (drive << 4) | head); 1683 /* Load parameters into the wd_features register. */ 1684 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1685 features); 1686 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1687 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1688 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1689 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1690 0, cylin >> 8); 1691 1692 /* Send command. */ 1693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1694 return; 1695 } 1696 1697 /* 1698 * Send a 48-bit addressing command. The drive should be ready. 1699 * Assumes interrupts are blocked. 1700 */ 1701 void 1702 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1703 u_int64_t blkno, u_int16_t count) 1704 { 1705 struct atac_softc *atac = chp->ch_atac; 1706 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1707 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1708 1709 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1710 "count=%d\n", atac->atac_dev.dv_xname, 1711 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1712 DEBUG_FUNCS); 1713 1714 if (wdc->select) 1715 wdc->select(chp,drive); 1716 1717 /* Select drive, head, and addressing mode. */ 1718 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1719 (drive << 4) | WDSD_LBA); 1720 1721 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1722 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1723 0); 1724 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1725 0, count); 1726 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1727 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1728 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1729 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1730 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1731 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1732 } else { 1733 /* previous */ 1734 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1735 0); 1736 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1737 0, count >> 8); 1738 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1739 0, blkno >> 24); 1740 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1741 0, blkno >> 32); 1742 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1743 0, blkno >> 40); 1744 1745 /* current */ 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1747 0); 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1749 count); 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1751 blkno); 1752 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1753 0, blkno >> 8); 1754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1755 0, blkno >> 16); 1756 } 1757 1758 /* Send command. */ 1759 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1760 return; 1761 } 1762 1763 /* 1764 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1765 * tested by the caller. 1766 */ 1767 void 1768 wdccommandshort(struct ata_channel *chp, int drive, int command) 1769 { 1770 struct atac_softc *atac = chp->ch_atac; 1771 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1772 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1773 1774 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1775 atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1776 DEBUG_FUNCS); 1777 1778 if (wdc->select) 1779 wdc->select(chp,drive); 1780 1781 /* Select drive. */ 1782 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1783 WDSD_IBM | (drive << 4)); 1784 1785 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1786 } 1787 1788 static void 1789 __wdcerror(struct ata_channel *chp, const char *msg) 1790 { 1791 struct atac_softc *atac = chp->ch_atac; 1792 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1793 1794 if (xfer == NULL) 1795 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1796 msg); 1797 else 1798 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1799 chp->ch_channel, xfer->c_drive, msg); 1800 } 1801 1802 /* 1803 * the bit bucket 1804 */ 1805 void 1806 wdcbit_bucket(struct ata_channel *chp, int size) 1807 { 1808 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1809 1810 for (; size >= 2; size -= 2) 1811 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1812 if (size) 1813 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1814 } 1815 1816 static void 1817 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1818 { 1819 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1820 1821 #ifndef __NO_STRICT_ALIGNMENT 1822 if ((uintptr_t)bf & 1) 1823 goto unaligned; 1824 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1825 goto unaligned; 1826 #endif 1827 1828 if (flags & DRIVE_NOSTREAM) { 1829 if (flags & DRIVE_CAP32) { 1830 bus_space_read_multi_4(wdr->data32iot, 1831 wdr->data32ioh, 0, bf, len >> 2); 1832 bf = (char *)bf + (len & ~3); 1833 len &= 3; 1834 } 1835 if (len) { 1836 bus_space_read_multi_2(wdr->cmd_iot, 1837 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1838 } 1839 } else { 1840 if (flags & DRIVE_CAP32) { 1841 bus_space_read_multi_stream_4(wdr->data32iot, 1842 wdr->data32ioh, 0, bf, len >> 2); 1843 bf = (char *)bf + (len & ~3); 1844 len &= 3; 1845 } 1846 if (len) { 1847 bus_space_read_multi_stream_2(wdr->cmd_iot, 1848 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1849 } 1850 } 1851 return; 1852 1853 #ifndef __NO_STRICT_ALIGNMENT 1854 unaligned: 1855 if (flags & DRIVE_NOSTREAM) { 1856 if (flags & DRIVE_CAP32) { 1857 while (len > 3) { 1858 uint32_t val; 1859 1860 val = bus_space_read_4(wdr->data32iot, 1861 wdr->data32ioh, 0); 1862 memcpy(bf, &val, 4); 1863 bf = (char *)bf + 4; 1864 len -= 4; 1865 } 1866 } 1867 while (len > 1) { 1868 uint16_t val; 1869 1870 val = bus_space_read_2(wdr->cmd_iot, 1871 wdr->cmd_iohs[wd_data], 0); 1872 memcpy(bf, &val, 2); 1873 bf = (char *)bf + 2; 1874 len -= 2; 1875 } 1876 } else { 1877 if (flags & DRIVE_CAP32) { 1878 while (len > 3) { 1879 uint32_t val; 1880 1881 val = bus_space_read_stream_4(wdr->data32iot, 1882 wdr->data32ioh, 0); 1883 memcpy(bf, &val, 4); 1884 bf = (char *)bf + 4; 1885 len -= 4; 1886 } 1887 } 1888 while (len > 1) { 1889 uint16_t val; 1890 1891 val = bus_space_read_stream_2(wdr->cmd_iot, 1892 wdr->cmd_iohs[wd_data], 0); 1893 memcpy(bf, &val, 2); 1894 bf = (char *)bf + 2; 1895 len -= 2; 1896 } 1897 } 1898 #endif 1899 } 1900 1901 static void 1902 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1903 { 1904 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1905 1906 #ifndef __NO_STRICT_ALIGNMENT 1907 if ((uintptr_t)bf & 1) 1908 goto unaligned; 1909 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1910 goto unaligned; 1911 #endif 1912 1913 if (flags & DRIVE_NOSTREAM) { 1914 if (flags & DRIVE_CAP32) { 1915 bus_space_write_multi_4(wdr->data32iot, 1916 wdr->data32ioh, 0, bf, len >> 2); 1917 bf = (char *)bf + (len & ~3); 1918 len &= 3; 1919 } 1920 if (len) { 1921 bus_space_write_multi_2(wdr->cmd_iot, 1922 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1923 } 1924 } else { 1925 if (flags & DRIVE_CAP32) { 1926 bus_space_write_multi_stream_4(wdr->data32iot, 1927 wdr->data32ioh, 0, bf, len >> 2); 1928 bf = (char *)bf + (len & ~3); 1929 len &= 3; 1930 } 1931 if (len) { 1932 bus_space_write_multi_stream_2(wdr->cmd_iot, 1933 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1934 } 1935 } 1936 return; 1937 1938 #ifndef __NO_STRICT_ALIGNMENT 1939 unaligned: 1940 if (flags & DRIVE_NOSTREAM) { 1941 if (flags & DRIVE_CAP32) { 1942 while (len > 3) { 1943 uint32_t val; 1944 1945 memcpy(&val, bf, 4); 1946 bus_space_write_4(wdr->data32iot, 1947 wdr->data32ioh, 0, val); 1948 bf = (char *)bf + 4; 1949 len -= 4; 1950 } 1951 } 1952 while (len > 1) { 1953 uint16_t val; 1954 1955 memcpy(&val, bf, 2); 1956 bus_space_write_2(wdr->cmd_iot, 1957 wdr->cmd_iohs[wd_data], 0, val); 1958 bf = (char *)bf + 2; 1959 len -= 2; 1960 } 1961 } else { 1962 if (flags & DRIVE_CAP32) { 1963 while (len > 3) { 1964 uint32_t val; 1965 1966 memcpy(&val, bf, 4); 1967 bus_space_write_stream_4(wdr->data32iot, 1968 wdr->data32ioh, 0, val); 1969 bf = (char *)bf + 4; 1970 len -= 4; 1971 } 1972 } 1973 while (len > 1) { 1974 uint16_t val; 1975 1976 memcpy(&val, bf, 2); 1977 bus_space_write_stream_2(wdr->cmd_iot, 1978 wdr->cmd_iohs[wd_data], 0, val); 1979 bf = (char *)bf + 2; 1980 len -= 2; 1981 } 1982 } 1983 #endif 1984 } 1985
Indexes created Tue Sep 23 07:09:52 GMT 2025