wdc.c revision 1.249
1 /* $NetBSD: wdc.c,v 1.249 2007/10/19 12:00:04 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.249 2007/10/19 12:00:04 ad Exp $"); 74 75 #include "opt_ata.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/conf.h> 81 #include <sys/buf.h> 82 #include <sys/device.h> 83 #include <sys/malloc.h> 84 #include <sys/syslog.h> 85 #include <sys/proc.h> 86 87 #include <sys/intr.h> 88 #include <sys/bus.h> 89 90 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 91 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 92 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 93 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 94 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 95 #define bus_space_read_stream_2 bus_space_read_2 96 #define bus_space_read_stream_4 bus_space_read_4 97 #define bus_space_write_stream_2 bus_space_write_2 98 #define bus_space_write_stream_4 bus_space_write_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ata/satareg.h> 104 #include <dev/ata/satavar.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "locators.h" 109 110 #include "atapibus.h" 111 #include "wd.h" 112 #include "sata.h" 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 /* 128 * timeout when waiting for BSY to deassert when probing. 129 * set to 5s. From the standards this could be up to 31, but we can't 130 * wait that much at boot time, and 5s seems to be enouth. 131 */ 132 #define WDC_PROBE_WAIT 5 133 134 135 #if NWD > 0 136 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 137 #else 138 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 139 const struct ata_bustype wdc_ata_bustype = { 140 SCSIPI_BUSTYPE_ATA, 141 NULL, /* wdc_ata_bio */ 142 NULL, /* wdc_reset_drive */ 143 wdc_reset_channel, 144 wdc_exec_command, 145 NULL, /* ata_get_params */ 146 NULL, /* wdc_ata_addref */ 147 NULL, /* wdc_ata_delref */ 148 NULL /* ata_kill_pending */ 149 }; 150 #endif 151 152 /* Flags to wdcreset(). */ 153 #define RESET_POLL 1 154 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 155 156 static int wdcprobe1(struct ata_channel *, int); 157 static int wdcreset(struct ata_channel *, int); 158 static void __wdcerror(struct ata_channel *, const char *); 159 static int __wdcwait_reset(struct ata_channel *, int, int); 160 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 161 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 162 static void __wdccommand_kill_xfer(struct ata_channel *, 163 struct ata_xfer *, int); 164 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 165 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 166 static int __wdcwait(struct ata_channel *, int, int, int); 167 168 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 169 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 170 171 #define DEBUG_INTR 0x01 172 #define DEBUG_XFERS 0x02 173 #define DEBUG_STATUS 0x04 174 #define DEBUG_FUNCS 0x08 175 #define DEBUG_PROBE 0x10 176 #define DEBUG_DETACH 0x20 177 #define DEBUG_DELAY 0x40 178 #ifdef ATADEBUG 179 extern int atadebug_mask; /* init'ed in ata.c */ 180 int wdc_nxfer = 0; 181 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 182 #else 183 #define ATADEBUG_PRINT(args, level) 184 #endif 185 186 /* 187 * Initialize the "shadow register" handles for a standard wdc controller. 188 */ 189 void 190 wdc_init_shadow_regs(struct ata_channel *chp) 191 { 192 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 193 194 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 195 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 196 } 197 198 /* 199 * Allocate a wdc_regs array, based on the number of channels. 200 */ 201 void 202 wdc_allocate_regs(struct wdc_softc *wdc) 203 { 204 205 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 206 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 207 } 208 209 #if NSATA > 0 210 /* 211 * probe drives on SATA controllers with standard SATA registers: 212 * bring the PHYs online, read the drive signature and set drive flags 213 * appropriately. 214 */ 215 void 216 wdc_sataprobe(struct ata_channel *chp) 217 { 218 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 219 uint16_t scnt, sn, cl, ch; 220 int i, s; 221 222 /* XXX This should be done by other code. */ 223 for (i = 0; i < chp->ch_ndrive; i++) { 224 chp->ch_drive[i].chnl_softc = chp; 225 chp->ch_drive[i].drive = i; 226 } 227 228 /* reset the PHY and bring online */ 229 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 230 wdr->sata_status)) { 231 case SStatus_DET_DEV: 232 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 233 WDSD_IBM); 234 delay(10); /* 400ns delay */ 235 scnt = bus_space_read_2(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_seccnt], 0); 237 sn = bus_space_read_2(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_sector], 0); 239 cl = bus_space_read_2(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_lo], 0); 241 ch = bus_space_read_2(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_hi], 0); 243 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 244 "cl=0x%x ch=0x%x\n", 245 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 246 scnt, sn, cl, ch), DEBUG_PROBE); 247 /* 248 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 s = splbio(); 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 254 else 255 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 256 splx(s); 257 258 /* 259 * issue a reset in case only the interface part of the drive 260 * is up 261 */ 262 if (wdcreset(chp, RESET_SLEEP) != 0) 263 chp->ch_drive[0].drive_flags = 0; 264 break; 265 266 default: 267 break; 268 } 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, s; 296 297 if (wdcprobe1(chp, 0) == 0) { 298 /* No drives, abort the attach here. */ 299 return; 300 } 301 302 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 303 for (i = 0; i < mstohz(3000); i++) { 304 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 305 if (wdc->select) 306 wdc->select(chp,0); 307 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 308 0, WDSD_IBM); 309 delay(10); /* 400ns delay */ 310 st0 = bus_space_read_1(wdr->cmd_iot, 311 wdr->cmd_iohs[wd_status], 0); 312 } 313 314 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 315 if (wdc->select) 316 wdc->select(chp,1); 317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 318 0, WDSD_IBM | 0x10); 319 delay(10); /* 400ns delay */ 320 st1 = bus_space_read_1(wdr->cmd_iot, 321 wdr->cmd_iohs[wd_status], 0); 322 } 323 324 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 325 == 0 || 326 (st0 & WDCS_DRDY)) && 327 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 328 == 0 || 329 (st1 & WDCS_DRDY))) 330 break; 331 tsleep(¶ms, PRIBIO, "atadrdy", 1); 332 } 333 s = splbio(); 334 if ((st0 & WDCS_DRDY) == 0) 335 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 336 if ((st1 & WDCS_DRDY) == 0) 337 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 338 splx(s); 339 340 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 341 atac->atac_dev.dv_xname, 342 chp->ch_channel, st0, st1), DEBUG_PROBE); 343 344 /* Wait a bit, some devices are weird just after a reset. */ 345 delay(5000); 346 347 for (i = 0; i < chp->ch_ndrive; i++) { 348 /* XXX This should be done by other code. */ 349 chp->ch_drive[i].chnl_softc = chp; 350 chp->ch_drive[i].drive = i; 351 352 #if NATA_DMA 353 /* 354 * Init error counter so that an error withing the first xfers 355 * will trigger a downgrade 356 */ 357 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 358 #endif 359 360 /* If controller can't do 16bit flag the drives as 32bit */ 361 if ((atac->atac_cap & 362 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 363 s = splbio(); 364 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 365 splx(s); 366 } 367 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 368 continue; 369 370 /* Shortcut in case we've been shutdown */ 371 if (chp->ch_flags & ATACH_SHUTDOWN) 372 return; 373 374 /* 375 * Issue an identify, to try to detect ghosts. 376 * Note that we can't use interrupts here, because if there 377 * is no devices, we will get a command aborted without 378 * interrupts. 379 */ 380 error = ata_get_params(&chp->ch_drive[i], 381 AT_WAIT | AT_POLL, ¶ms); 382 if (error != CMD_OK) { 383 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 384 385 /* Shortcut in case we've been shutdown */ 386 if (chp->ch_flags & ATACH_SHUTDOWN) 387 return; 388 389 error = ata_get_params(&chp->ch_drive[i], 390 AT_WAIT | AT_POLL, ¶ms); 391 } 392 if (error == CMD_OK) { 393 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 394 s = splbio(); 395 for (j = 0; j < chp->ch_ndrive; j++) 396 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 397 splx(s); 398 } else { 399 s = splbio(); 400 chp->ch_drive[i].drive_flags &= 401 ~(DRIVE_ATA | DRIVE_ATAPI); 402 splx(s); 403 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 404 atac->atac_dev.dv_xname, 405 chp->ch_channel, i, error), DEBUG_PROBE); 406 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 407 continue; 408 /* 409 * Pre-ATA drive ? 410 * Test registers writability (Error register not 411 * writable, but cyllo is), then try an ATA command. 412 */ 413 if (wdc->select) 414 wdc->select(chp,i); 415 bus_space_write_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 417 delay(10); /* 400ns delay */ 418 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 419 0, 0x58); 420 bus_space_write_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 422 if (bus_space_read_1(wdr->cmd_iot, 423 wdr->cmd_iohs[wd_error], 0) == 0x58 || 424 bus_space_read_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 426 ATADEBUG_PRINT(("%s:%d:%d: register " 427 "writability failed\n", 428 atac->atac_dev.dv_xname, 429 chp->ch_channel, i), DEBUG_PROBE); 430 s = splbio(); 431 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 432 splx(s); 433 continue; 434 } 435 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 436 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 437 atac->atac_dev.dv_xname, 438 chp->ch_channel, i), DEBUG_PROBE); 439 s = splbio(); 440 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 441 splx(s); 442 continue; 443 } 444 bus_space_write_1(wdr->cmd_iot, 445 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 446 delay(10); /* 400ns delay */ 447 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 448 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 449 atac->atac_dev.dv_xname, 450 chp->ch_channel, i), DEBUG_PROBE); 451 s = splbio(); 452 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 453 splx(s); 454 } else { 455 s = splbio(); 456 for (j = 0; j < chp->ch_ndrive; j++) 457 chp->ch_drive[j].drive_flags &= 458 ~(DRIVE_ATA | DRIVE_ATAPI); 459 splx(s); 460 } 461 } 462 } 463 } 464 465 int 466 wdcprobe(struct ata_channel *chp) 467 { 468 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 469 /* default reset method */ 470 if (wdc->reset == NULL) 471 wdc->reset = wdc_do_reset; 472 473 return (wdcprobe1(chp, 1)); 474 } 475 476 static int 477 wdcprobe1(struct ata_channel *chp, int poll) 478 { 479 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 480 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 481 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 482 u_int8_t ret_value = 0x03; 483 u_int8_t drive; 484 int s; 485 /* XXX if poll, wdc_probe_count is 0. */ 486 int wdc_probe_count = 487 poll ? (WDC_PROBE_WAIT / WDCDELAY) 488 : (WDC_PROBE_WAIT * hz); 489 490 /* 491 * Sanity check to see if the wdc channel responds at all. 492 */ 493 494 s = splbio(); 495 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 496 while (wdc_probe_count-- > 0) { 497 if (wdc->select) 498 wdc->select(chp,0); 499 500 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 501 0, WDSD_IBM); 502 delay(10); /* 400ns delay */ 503 st0 = bus_space_read_1(wdr->cmd_iot, 504 wdr->cmd_iohs[wd_status], 0); 505 506 if (wdc->select) 507 wdc->select(chp,1); 508 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM | 0x10); 511 delay(10); /* 400ns delay */ 512 st1 = bus_space_read_1(wdr->cmd_iot, 513 wdr->cmd_iohs[wd_status], 0); 514 if ((st0 & WDCS_BSY) == 0) 515 break; 516 } 517 518 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 519 chp->ch_atac->atac_dev.dv_xname, 520 chp->ch_channel, st0, st1), DEBUG_PROBE); 521 522 if (st0 == 0xff || st0 == WDSD_IBM) 523 ret_value &= ~0x01; 524 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 525 ret_value &= ~0x02; 526 /* Register writability test, drive 0. */ 527 if (ret_value & 0x01) { 528 if (wdc->select) 529 wdc->select(chp,0); 530 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 531 0, WDSD_IBM); 532 bus_space_write_1(wdr->cmd_iot, 533 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 534 cl = bus_space_read_1(wdr->cmd_iot, 535 wdr->cmd_iohs[wd_cyl_lo], 0); 536 if (cl != 0x02) { 537 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 538 "got 0x%x != 0x02\n", 539 chp->ch_atac->atac_dev.dv_xname, 540 chp->ch_channel, cl), 541 DEBUG_PROBE); 542 ret_value &= ~0x01; 543 } 544 bus_space_write_1(wdr->cmd_iot, 545 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 546 cl = bus_space_read_1(wdr->cmd_iot, 547 wdr->cmd_iohs[wd_cyl_lo], 0); 548 if (cl != 0x01) { 549 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 550 "got 0x%x != 0x01\n", 551 chp->ch_atac->atac_dev.dv_xname, 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(wdr->cmd_iot, 557 wdr->cmd_iohs[wd_sector], 0, 0x01); 558 cl = bus_space_read_1(wdr->cmd_iot, 559 wdr->cmd_iohs[wd_sector], 0); 560 if (cl != 0x01) { 561 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 562 "got 0x%x != 0x01\n", 563 chp->ch_atac->atac_dev.dv_xname, 564 chp->ch_channel, cl), 565 DEBUG_PROBE); 566 ret_value &= ~0x01; 567 } 568 bus_space_write_1(wdr->cmd_iot, 569 wdr->cmd_iohs[wd_sector], 0, 0x02); 570 cl = bus_space_read_1(wdr->cmd_iot, 571 wdr->cmd_iohs[wd_sector], 0); 572 if (cl != 0x02) { 573 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 574 "got 0x%x != 0x02\n", 575 chp->ch_atac->atac_dev.dv_xname, 576 chp->ch_channel, cl), 577 DEBUG_PROBE); 578 ret_value &= ~0x01; 579 } 580 cl = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_cyl_lo], 0); 582 if (cl != 0x01) { 583 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 584 "got 0x%x != 0x01\n", 585 chp->ch_atac->atac_dev.dv_xname, 586 chp->ch_channel, cl), 587 DEBUG_PROBE); 588 ret_value &= ~0x01; 589 } 590 } 591 /* Register writability test, drive 1. */ 592 if (ret_value & 0x02) { 593 if (wdc->select) 594 wdc->select(chp,1); 595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 596 0, WDSD_IBM | 0x10); 597 bus_space_write_1(wdr->cmd_iot, 598 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_lo], 0); 601 if (cl != 0x02) { 602 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 603 "got 0x%x != 0x02\n", 604 chp->ch_atac->atac_dev.dv_xname, 605 chp->ch_channel, cl), 606 DEBUG_PROBE); 607 ret_value &= ~0x02; 608 } 609 bus_space_write_1(wdr->cmd_iot, 610 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 611 cl = bus_space_read_1(wdr->cmd_iot, 612 wdr->cmd_iohs[wd_cyl_lo], 0); 613 if (cl != 0x01) { 614 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 615 "got 0x%x != 0x01\n", 616 chp->ch_atac->atac_dev.dv_xname, 617 chp->ch_channel, cl), 618 DEBUG_PROBE); 619 ret_value &= ~0x02; 620 } 621 bus_space_write_1(wdr->cmd_iot, 622 wdr->cmd_iohs[wd_sector], 0, 0x01); 623 cl = bus_space_read_1(wdr->cmd_iot, 624 wdr->cmd_iohs[wd_sector], 0); 625 if (cl != 0x01) { 626 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 627 "got 0x%x != 0x01\n", 628 chp->ch_atac->atac_dev.dv_xname, 629 chp->ch_channel, cl), 630 DEBUG_PROBE); 631 ret_value &= ~0x02; 632 } 633 bus_space_write_1(wdr->cmd_iot, 634 wdr->cmd_iohs[wd_sector], 0, 0x02); 635 cl = bus_space_read_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_sector], 0); 637 if (cl != 0x02) { 638 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 639 "got 0x%x != 0x02\n", 640 chp->ch_atac->atac_dev.dv_xname, 641 chp->ch_channel, cl), 642 DEBUG_PROBE); 643 ret_value &= ~0x02; 644 } 645 cl = bus_space_read_1(wdr->cmd_iot, 646 wdr->cmd_iohs[wd_cyl_lo], 0); 647 if (cl != 0x01) { 648 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 649 "got 0x%x != 0x01\n", 650 chp->ch_atac->atac_dev.dv_xname, 651 chp->ch_channel, cl), 652 DEBUG_PROBE); 653 ret_value &= ~0x02; 654 } 655 } 656 657 if (ret_value == 0) { 658 splx(s); 659 return 0; 660 } 661 } 662 663 664 #if 0 /* XXX this break some ATA or ATAPI devices */ 665 /* 666 * reset bus. Also send an ATAPI_RESET to devices, in case there are 667 * ATAPI device out there which don't react to the bus reset 668 */ 669 if (ret_value & 0x01) { 670 if (wdc->select) 671 wdc->select(chp,0); 672 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 673 0, WDSD_IBM); 674 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 675 ATAPI_SOFT_RESET); 676 } 677 if (ret_value & 0x02) { 678 if (wdc->select) 679 wdc->select(chp,0); 680 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 681 0, WDSD_IBM | 0x10); 682 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 683 ATAPI_SOFT_RESET); 684 } 685 686 delay(5000); 687 #endif 688 689 wdc->reset(chp, RESET_POLL); 690 DELAY(2000); 691 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 692 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 693 splx(s); 694 695 ret_value = __wdcwait_reset(chp, ret_value, poll); 696 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 697 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 698 ret_value), DEBUG_PROBE); 699 700 /* if reset failed, there's nothing here */ 701 if (ret_value == 0) 702 return 0; 703 704 /* 705 * Test presence of drives. First test register signatures looking 706 * for ATAPI devices. If it's not an ATAPI and reset said there may 707 * be something here assume it's ATA or OLD. Ghost will be killed 708 * later in attach routine. 709 */ 710 for (drive = 0; drive < chp->ch_ndrive; drive++) { 711 if ((ret_value & (0x01 << drive)) == 0) 712 continue; 713 if (wdc->select) 714 wdc->select(chp,drive); 715 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 716 WDSD_IBM | (drive << 4)); 717 delay(10); /* 400ns delay */ 718 /* Save registers contents */ 719 sc = bus_space_read_1(wdr->cmd_iot, 720 wdr->cmd_iohs[wd_seccnt], 0); 721 sn = bus_space_read_1(wdr->cmd_iot, 722 wdr->cmd_iohs[wd_sector], 0); 723 cl = bus_space_read_1(wdr->cmd_iot, 724 wdr->cmd_iohs[wd_cyl_lo], 0); 725 ch = bus_space_read_1(wdr->cmd_iot, 726 wdr->cmd_iohs[wd_cyl_hi], 0); 727 728 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 729 "cl=0x%x ch=0x%x\n", 730 chp->ch_atac->atac_dev.dv_xname, 731 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 732 /* 733 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 734 * we get wrong values here, so ignore it. 735 */ 736 s = splbio(); 737 if (cl == 0x14 && ch == 0xeb) { 738 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 739 } else { 740 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 741 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 742 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 743 } 744 splx(s); 745 } 746 return (ret_value); 747 } 748 749 void 750 wdcattach(struct ata_channel *chp) 751 { 752 struct atac_softc *atac = chp->ch_atac; 753 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 754 755 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 756 757 /* default data transfer methods */ 758 if (wdc->datain_pio == NULL) 759 wdc->datain_pio = wdc_datain_pio; 760 if (wdc->dataout_pio == NULL) 761 wdc->dataout_pio = wdc_dataout_pio; 762 /* default reset method */ 763 if (wdc->reset == NULL) 764 wdc->reset = wdc_do_reset; 765 766 /* initialise global data */ 767 if (atac->atac_bustype_ata == NULL) 768 atac->atac_bustype_ata = &wdc_ata_bustype; 769 if (atac->atac_probe == NULL) 770 atac->atac_probe = wdc_drvprobe; 771 #if NATAPIBUS > 0 772 if (atac->atac_atapibus_attach == NULL) 773 atac->atac_atapibus_attach = wdc_atapibus_attach; 774 #endif 775 776 ata_channel_attach(chp); 777 } 778 779 int 780 wdcactivate(struct device *self, enum devact act) 781 { 782 struct atac_softc *atac = (struct atac_softc *) self; 783 int s, i, error = 0; 784 785 s = splbio(); 786 switch (act) { 787 case DVACT_ACTIVATE: 788 error = EOPNOTSUPP; 789 break; 790 791 case DVACT_DEACTIVATE: 792 for (i = 0; i < atac->atac_nchannels; i++) { 793 error = 794 config_deactivate(atac->atac_channels[i]->atabus); 795 if (error) 796 break; 797 } 798 break; 799 } 800 splx(s); 801 return (error); 802 } 803 804 int 805 wdcdetach(struct device *self, int flags) 806 { 807 struct atac_softc *atac = (struct atac_softc *) self; 808 struct ata_channel *chp; 809 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 810 int i, error = 0; 811 812 for (i = 0; i < atac->atac_nchannels; i++) { 813 chp = atac->atac_channels[i]; 814 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 815 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 816 DEBUG_DETACH); 817 error = config_detach(chp->atabus, flags); 818 if (error) 819 break; 820 } 821 if (adapt->adapt_refcnt != 0) { 822 #ifdef DIAGNOSTIC 823 printf("wdcdetach: refcnt should be 0 here??\n"); 824 #endif 825 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 826 } 827 return (error); 828 } 829 830 /* restart an interrupted I/O */ 831 void 832 wdcrestart(void *v) 833 { 834 struct ata_channel *chp = v; 835 int s; 836 837 s = splbio(); 838 atastart(chp); 839 splx(s); 840 } 841 842 843 /* 844 * Interrupt routine for the controller. Acknowledge the interrupt, check for 845 * errors on the current operation, mark it done if necessary, and start the 846 * next request. Also check for a partially done transfer, and continue with 847 * the next chunk if so. 848 */ 849 int 850 wdcintr(void *arg) 851 { 852 struct ata_channel *chp = arg; 853 struct atac_softc *atac = chp->ch_atac; 854 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 855 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 856 struct ata_xfer *xfer; 857 int ret; 858 859 if (!device_is_active(&atac->atac_dev)) { 860 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 861 DEBUG_INTR); 862 return (0); 863 } 864 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 865 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 866 /* try to clear the pending interrupt anyway */ 867 (void)bus_space_read_1(wdr->cmd_iot, 868 wdr->cmd_iohs[wd_status], 0); 869 return (0); 870 } 871 872 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 873 xfer = chp->ch_queue->active_xfer; 874 #ifdef DIAGNOSTIC 875 if (xfer == NULL) 876 panic("wdcintr: no xfer"); 877 if (xfer->c_chp != chp) { 878 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 879 chp->ch_channel); 880 panic("wdcintr: wrong channel"); 881 } 882 #endif 883 #if NATA_DMA || NATA_PIOBM 884 if (chp->ch_flags & ATACH_DMA_WAIT) { 885 wdc->dma_status = 886 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 887 xfer->c_drive, WDC_DMAEND_END); 888 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 889 /* IRQ not for us, not detected by DMA engine */ 890 return 0; 891 } 892 chp->ch_flags &= ~ATACH_DMA_WAIT; 893 } 894 #endif 895 chp->ch_flags &= ~ATACH_IRQ_WAIT; 896 ret = xfer->c_intr(chp, xfer, 1); 897 if (ret == 0) /* irq was not for us, still waiting for irq */ 898 chp->ch_flags |= ATACH_IRQ_WAIT; 899 return (ret); 900 } 901 902 /* Put all disk in RESET state */ 903 void 904 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 905 { 906 struct ata_channel *chp = drvp->chnl_softc; 907 908 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 909 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 910 DEBUG_FUNCS); 911 912 ata_reset_channel(chp, flags); 913 } 914 915 void 916 wdc_reset_channel(struct ata_channel *chp, int flags) 917 { 918 TAILQ_HEAD(, ata_xfer) reset_xfer; 919 struct ata_xfer *xfer, *next_xfer; 920 #if NATA_DMA || NATA_PIOBM 921 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 922 #endif 923 924 TAILQ_INIT(&reset_xfer); 925 926 chp->ch_flags &= ~ATACH_IRQ_WAIT; 927 928 /* 929 * if the current command if on an ATAPI device, issue a 930 * ATAPI_SOFT_RESET 931 */ 932 xfer = chp->ch_queue->active_xfer; 933 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 934 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 935 if (flags & AT_WAIT) 936 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 937 else 938 delay(1000); 939 } 940 941 /* reset the channel */ 942 if (flags & AT_WAIT) 943 (void) wdcreset(chp, RESET_SLEEP); 944 else 945 (void) wdcreset(chp, RESET_POLL); 946 947 /* 948 * wait a bit after reset; in case the DMA engines needs some time 949 * to recover. 950 */ 951 if (flags & AT_WAIT) 952 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 953 else 954 delay(1000); 955 /* 956 * look for pending xfers. If we have a shared queue, we'll also reset 957 * the other channel if the current xfer is running on it. 958 * Then we'll dequeue only the xfers for this channel. 959 */ 960 if ((flags & AT_RST_NOCMD) == 0) { 961 /* 962 * move all xfers queued for this channel to the reset queue, 963 * and then process the current xfer and then the reset queue. 964 * We have to use a temporary queue because c_kill_xfer() 965 * may requeue commands. 966 */ 967 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 968 xfer != NULL; xfer = next_xfer) { 969 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 970 if (xfer->c_chp != chp) 971 continue; 972 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 973 xfer, c_xferchain); 974 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 975 } 976 xfer = chp->ch_queue->active_xfer; 977 if (xfer) { 978 if (xfer->c_chp != chp) 979 ata_reset_channel(xfer->c_chp, flags); 980 else { 981 callout_stop(&chp->ch_callout); 982 #if NATA_DMA || NATA_PIOBM 983 /* 984 * If we're waiting for DMA, stop the 985 * DMA engine 986 */ 987 if (chp->ch_flags & ATACH_DMA_WAIT) { 988 (*wdc->dma_finish)( 989 wdc->dma_arg, 990 chp->ch_channel, 991 xfer->c_drive, 992 WDC_DMAEND_ABRT_QUIET); 993 chp->ch_flags &= ~ATACH_DMA_WAIT; 994 } 995 #endif 996 chp->ch_queue->active_xfer = NULL; 997 if ((flags & AT_RST_EMERG) == 0) 998 xfer->c_kill_xfer( 999 chp, xfer, KILL_RESET); 1000 } 1001 } 1002 1003 for (xfer = TAILQ_FIRST(&reset_xfer); 1004 xfer != NULL; xfer = next_xfer) { 1005 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1006 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1007 if ((flags & AT_RST_EMERG) == 0) 1008 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1009 } 1010 } 1011 } 1012 1013 static int 1014 wdcreset(struct ata_channel *chp, int poll) 1015 { 1016 struct atac_softc *atac = chp->ch_atac; 1017 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1018 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1019 int drv_mask1, drv_mask2; 1020 1021 wdc->reset(chp, poll); 1022 1023 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1024 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1025 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1026 (poll == RESET_SLEEP) ? 0 : 1); 1027 if (drv_mask2 != drv_mask1) { 1028 printf("%s channel %d: reset failed for", 1029 atac->atac_dev.dv_xname, chp->ch_channel); 1030 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1031 printf(" drive 0"); 1032 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1033 printf(" drive 1"); 1034 printf("\n"); 1035 } 1036 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1037 return (drv_mask1 != drv_mask2) ? 1 : 0; 1038 } 1039 1040 void 1041 wdc_do_reset(struct ata_channel *chp, int poll) 1042 { 1043 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1044 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1045 int s = 0; 1046 1047 if (poll != RESET_SLEEP) 1048 s = splbio(); 1049 if (wdc->select) 1050 wdc->select(chp,0); 1051 /* master */ 1052 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1053 delay(10); /* 400ns delay */ 1054 /* assert SRST, wait for reset to complete */ 1055 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1056 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1057 delay(2000); 1058 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1059 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1060 WDCTL_4BIT | WDCTL_IDS); 1061 delay(10); /* 400ns delay */ 1062 if (poll != RESET_SLEEP) { 1063 /* ACK interrupt in case there is one pending left */ 1064 if (wdc->irqack) 1065 wdc->irqack(chp); 1066 splx(s); 1067 } 1068 } 1069 1070 static int 1071 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1072 { 1073 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1074 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1075 int timeout, nloop; 1076 u_int8_t st0 = 0, st1 = 0; 1077 #ifdef ATADEBUG 1078 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1079 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1080 #endif 1081 1082 if (poll) 1083 nloop = WDCNDELAY_RST; 1084 else 1085 nloop = WDC_RESET_WAIT * hz / 1000; 1086 /* wait for BSY to deassert */ 1087 for (timeout = 0; timeout < nloop; timeout++) { 1088 if ((drv_mask & 0x01) != 0) { 1089 if (wdc->select) 1090 wdc->select(chp,0); 1091 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1092 0, WDSD_IBM); /* master */ 1093 delay(10); 1094 st0 = bus_space_read_1(wdr->cmd_iot, 1095 wdr->cmd_iohs[wd_status], 0); 1096 #ifdef ATADEBUG 1097 sc0 = bus_space_read_1(wdr->cmd_iot, 1098 wdr->cmd_iohs[wd_seccnt], 0); 1099 sn0 = bus_space_read_1(wdr->cmd_iot, 1100 wdr->cmd_iohs[wd_sector], 0); 1101 cl0 = bus_space_read_1(wdr->cmd_iot, 1102 wdr->cmd_iohs[wd_cyl_lo], 0); 1103 ch0 = bus_space_read_1(wdr->cmd_iot, 1104 wdr->cmd_iohs[wd_cyl_hi], 0); 1105 #endif 1106 } 1107 if ((drv_mask & 0x02) != 0) { 1108 if (wdc->select) 1109 wdc->select(chp,1); 1110 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1111 0, WDSD_IBM | 0x10); /* slave */ 1112 delay(10); 1113 st1 = bus_space_read_1(wdr->cmd_iot, 1114 wdr->cmd_iohs[wd_status], 0); 1115 #ifdef ATADEBUG 1116 sc1 = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_seccnt], 0); 1118 sn1 = bus_space_read_1(wdr->cmd_iot, 1119 wdr->cmd_iohs[wd_sector], 0); 1120 cl1 = bus_space_read_1(wdr->cmd_iot, 1121 wdr->cmd_iohs[wd_cyl_lo], 0); 1122 ch1 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_cyl_hi], 0); 1124 #endif 1125 } 1126 1127 if ((drv_mask & 0x01) == 0) { 1128 /* no master */ 1129 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1130 /* No master, slave is ready, it's done */ 1131 goto end; 1132 } 1133 if ((drv_mask & 0x02) == 0) { 1134 /* No master, no slave: it's done */ 1135 goto end; 1136 } 1137 } else if ((drv_mask & 0x02) == 0) { 1138 /* no slave */ 1139 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1140 /* No slave, master is ready, it's done */ 1141 goto end; 1142 } 1143 } else { 1144 /* Wait for both master and slave to be ready */ 1145 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1146 goto end; 1147 } 1148 } 1149 if (poll) 1150 delay(WDCDELAY); 1151 else 1152 tsleep(&nloop, PRIBIO, "atarst", 1); 1153 } 1154 /* Reset timed out. Maybe it's because drv_mask was not right */ 1155 if (st0 & WDCS_BSY) 1156 drv_mask &= ~0x01; 1157 if (st1 & WDCS_BSY) 1158 drv_mask &= ~0x02; 1159 end: 1160 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1161 "cl=0x%x ch=0x%x\n", 1162 chp->ch_atac->atac_dev.dv_xname, 1163 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1164 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1165 "cl=0x%x ch=0x%x\n", 1166 chp->ch_atac->atac_dev.dv_xname, 1167 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1168 1169 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1170 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1171 st0, st1), DEBUG_PROBE); 1172 1173 return drv_mask; 1174 } 1175 1176 /* 1177 * Wait for a drive to be !BSY, and have mask in its status register. 1178 * return -1 for a timeout after "timeout" ms. 1179 */ 1180 static int 1181 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1182 { 1183 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1184 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1185 u_char status; 1186 int xtime = 0; 1187 1188 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1189 chp->ch_atac->atac_dev.dv_xname, 1190 chp->ch_channel), DEBUG_STATUS); 1191 chp->ch_error = 0; 1192 1193 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1194 1195 for (;;) { 1196 chp->ch_status = status = 1197 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1198 if ((status & (WDCS_BSY | mask)) == bits) 1199 break; 1200 if (++xtime > timeout) { 1201 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1202 "status %x error %x (mask 0x%x bits 0x%x)\n", 1203 xtime, status, 1204 bus_space_read_1(wdr->cmd_iot, 1205 wdr->cmd_iohs[wd_error], 0), mask, bits), 1206 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1207 return(WDCWAIT_TOUT); 1208 } 1209 delay(WDCDELAY); 1210 } 1211 #ifdef ATADEBUG 1212 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1213 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1214 #endif 1215 if (status & WDCS_ERR) 1216 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1217 wdr->cmd_iohs[wd_error], 0); 1218 #ifdef WDCNDELAY_DEBUG 1219 /* After autoconfig, there should be no long delays. */ 1220 if (!cold && xtime > WDCNDELAY_DEBUG) { 1221 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1222 if (xfer == NULL) 1223 printf("%s channel %d: warning: busy-wait took %dus\n", 1224 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1225 WDCDELAY * xtime); 1226 else 1227 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1228 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1229 xfer->c_drive, 1230 WDCDELAY * xtime); 1231 } 1232 #endif 1233 return(WDCWAIT_OK); 1234 } 1235 1236 /* 1237 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1238 * thread if possible 1239 */ 1240 int 1241 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1242 { 1243 int error, i, timeout_hz = mstohz(timeout); 1244 1245 if (timeout_hz == 0 || 1246 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1247 error = __wdcwait(chp, mask, bits, timeout); 1248 else { 1249 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1250 if (error != 0) { 1251 if ((chp->ch_flags & ATACH_TH_RUN) || 1252 (flags & AT_WAIT)) { 1253 /* 1254 * we're running in the channel thread 1255 * or some userland thread context 1256 */ 1257 for (i = 0; i < timeout_hz; i++) { 1258 if (__wdcwait(chp, mask, bits, 1259 WDCDELAY_POLL) == 0) { 1260 error = 0; 1261 break; 1262 } 1263 tsleep(&chp, PRIBIO, "atapoll", 1); 1264 } 1265 } else { 1266 /* 1267 * we're probably in interrupt context, 1268 * ask the thread to come back here 1269 */ 1270 #ifdef DIAGNOSTIC 1271 if (chp->ch_queue->queue_freeze > 0) 1272 panic("wdcwait: queue_freeze"); 1273 #endif 1274 chp->ch_queue->queue_freeze++; 1275 wakeup(&chp->ch_thread); 1276 return(WDCWAIT_THR); 1277 } 1278 } 1279 } 1280 return (error); 1281 } 1282 1283 1284 #if NATA_DMA 1285 /* 1286 * Busy-wait for DMA to complete 1287 */ 1288 int 1289 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1290 { 1291 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1292 int xtime; 1293 1294 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1295 wdc->dma_status = 1296 (*wdc->dma_finish)(wdc->dma_arg, 1297 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1298 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1299 return 0; 1300 delay(WDCDELAY); 1301 } 1302 /* timeout, force a DMA halt */ 1303 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1304 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1305 return 1; 1306 } 1307 #endif 1308 1309 void 1310 wdctimeout(void *arg) 1311 { 1312 struct ata_channel *chp = (struct ata_channel *)arg; 1313 #if NATA_DMA || NATA_PIOBM 1314 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1315 #endif 1316 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1317 int s; 1318 1319 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1320 1321 s = splbio(); 1322 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1323 __wdcerror(chp, "lost interrupt"); 1324 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1325 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1326 xfer->c_bcount, 1327 xfer->c_skip); 1328 #if NATA_DMA || NATA_PIOBM 1329 if (chp->ch_flags & ATACH_DMA_WAIT) { 1330 wdc->dma_status = 1331 (*wdc->dma_finish)(wdc->dma_arg, 1332 chp->ch_channel, xfer->c_drive, 1333 WDC_DMAEND_ABRT); 1334 chp->ch_flags &= ~ATACH_DMA_WAIT; 1335 } 1336 #endif 1337 /* 1338 * Call the interrupt routine. If we just missed an interrupt, 1339 * it will do what's needed. Else, it will take the needed 1340 * action (reset the device). 1341 * Before that we need to reinstall the timeout callback, 1342 * in case it will miss another irq while in this transfer 1343 * We arbitray chose it to be 1s 1344 */ 1345 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1346 xfer->c_flags |= C_TIMEOU; 1347 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1348 xfer->c_intr(chp, xfer, 1); 1349 } else 1350 __wdcerror(chp, "missing untimeout"); 1351 splx(s); 1352 } 1353 1354 int 1355 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1356 { 1357 struct ata_channel *chp = drvp->chnl_softc; 1358 struct ata_xfer *xfer; 1359 int s, ret; 1360 1361 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1362 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1363 DEBUG_FUNCS); 1364 1365 /* set up an xfer and queue. Wait for completion */ 1366 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1367 ATAXF_NOSLEEP); 1368 if (xfer == NULL) { 1369 return ATACMD_TRY_AGAIN; 1370 } 1371 1372 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1373 ata_c->flags |= AT_POLL; 1374 if (ata_c->flags & AT_POLL) 1375 xfer->c_flags |= C_POLL; 1376 if (ata_c->flags & AT_WAIT) 1377 xfer->c_flags |= C_WAIT; 1378 xfer->c_drive = drvp->drive; 1379 xfer->c_databuf = ata_c->data; 1380 xfer->c_bcount = ata_c->bcount; 1381 xfer->c_cmd = ata_c; 1382 xfer->c_start = __wdccommand_start; 1383 xfer->c_intr = __wdccommand_intr; 1384 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1385 1386 s = splbio(); 1387 ata_exec_xfer(chp, xfer); 1388 #ifdef DIAGNOSTIC 1389 if ((ata_c->flags & AT_POLL) != 0 && 1390 (ata_c->flags & AT_DONE) == 0) 1391 panic("wdc_exec_command: polled command not done"); 1392 #endif 1393 if (ata_c->flags & AT_DONE) { 1394 ret = ATACMD_COMPLETE; 1395 } else { 1396 if (ata_c->flags & AT_WAIT) { 1397 while ((ata_c->flags & AT_DONE) == 0) { 1398 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1399 } 1400 ret = ATACMD_COMPLETE; 1401 } else { 1402 ret = ATACMD_QUEUED; 1403 } 1404 } 1405 splx(s); 1406 return ret; 1407 } 1408 1409 static void 1410 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1411 { 1412 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1413 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1414 int drive = xfer->c_drive; 1415 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1416 struct ata_command *ata_c = xfer->c_cmd; 1417 1418 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1419 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1420 DEBUG_FUNCS); 1421 1422 if (wdc->select) 1423 wdc->select(chp,drive); 1424 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1425 WDSD_IBM | (drive << 4)); 1426 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1427 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1428 case WDCWAIT_OK: 1429 break; 1430 case WDCWAIT_TOUT: 1431 ata_c->flags |= AT_TIMEOU; 1432 __wdccommand_done(chp, xfer); 1433 return; 1434 case WDCWAIT_THR: 1435 return; 1436 } 1437 if (ata_c->flags & AT_POLL) { 1438 /* polled command, disable interrupts */ 1439 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1440 WDCTL_4BIT | WDCTL_IDS); 1441 } 1442 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1443 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1444 1445 if ((ata_c->flags & AT_POLL) == 0) { 1446 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1447 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1448 wdctimeout, chp); 1449 return; 1450 } 1451 /* 1452 * Polled command. Wait for drive ready or drq. Done in intr(). 1453 * Wait for at last 400ns for status bit to be valid. 1454 */ 1455 delay(10); /* 400ns delay */ 1456 __wdccommand_intr(chp, xfer, 0); 1457 } 1458 1459 static int 1460 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1461 { 1462 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1463 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1464 struct ata_command *ata_c = xfer->c_cmd; 1465 int bcount = ata_c->bcount; 1466 char *data = ata_c->data; 1467 int wflags; 1468 int drive_flags; 1469 1470 if (ata_c->r_command == WDCC_IDENTIFY || 1471 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1472 /* 1473 * The IDENTIFY data has been designed as an array of 1474 * u_int16_t, so we can byteswap it on the fly. 1475 * Historically it's what we have always done so keeping it 1476 * here ensure binary backward compatibility. 1477 */ 1478 drive_flags = DRIVE_NOSTREAM | 1479 chp->ch_drive[xfer->c_drive].drive_flags; 1480 } else { 1481 /* 1482 * Other data structure are opaque and should be transfered 1483 * as is. 1484 */ 1485 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1486 } 1487 1488 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1489 /* both wait and poll, we can tsleep here */ 1490 wflags = AT_WAIT | AT_POLL; 1491 } else { 1492 wflags = AT_POLL; 1493 } 1494 1495 again: 1496 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1497 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1498 DEBUG_INTR); 1499 /* 1500 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1501 * Reselect again, it doesn't hurt for others commands, and the time 1502 * penalty for the extra regiter write is acceptable, 1503 * wdc_exec_command() isn't called often (mosly for autoconfig) 1504 */ 1505 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1506 WDSD_IBM | (xfer->c_drive << 4)); 1507 if ((ata_c->flags & AT_XFDONE) != 0) { 1508 /* 1509 * We have completed a data xfer. The drive should now be 1510 * in its initial state 1511 */ 1512 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1513 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1514 wflags) == WDCWAIT_TOUT) { 1515 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1516 return 0; /* IRQ was not for us */ 1517 ata_c->flags |= AT_TIMEOU; 1518 } 1519 goto out; 1520 } 1521 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1522 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1523 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1524 return 0; /* IRQ was not for us */ 1525 ata_c->flags |= AT_TIMEOU; 1526 goto out; 1527 } 1528 if (wdc->irqack) 1529 wdc->irqack(chp); 1530 if (ata_c->flags & AT_READ) { 1531 if ((chp->ch_status & WDCS_DRQ) == 0) { 1532 ata_c->flags |= AT_TIMEOU; 1533 goto out; 1534 } 1535 wdc->datain_pio(chp, drive_flags, data, bcount); 1536 /* at this point the drive should be in its initial state */ 1537 ata_c->flags |= AT_XFDONE; 1538 /* 1539 * XXX checking the status register again here cause some 1540 * hardware to timeout. 1541 */ 1542 } else if (ata_c->flags & AT_WRITE) { 1543 if ((chp->ch_status & WDCS_DRQ) == 0) { 1544 ata_c->flags |= AT_TIMEOU; 1545 goto out; 1546 } 1547 wdc->dataout_pio(chp, drive_flags, data, bcount); 1548 ata_c->flags |= AT_XFDONE; 1549 if ((ata_c->flags & AT_POLL) == 0) { 1550 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1551 callout_reset(&chp->ch_callout, 1552 mstohz(ata_c->timeout), wdctimeout, chp); 1553 return 1; 1554 } else { 1555 goto again; 1556 } 1557 } 1558 out: 1559 __wdccommand_done(chp, xfer); 1560 return 1; 1561 } 1562 1563 static void 1564 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1565 { 1566 struct atac_softc *atac = chp->ch_atac; 1567 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1568 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1569 struct ata_command *ata_c = xfer->c_cmd; 1570 1571 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1572 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1573 ata_c->flags), DEBUG_FUNCS); 1574 1575 1576 if (chp->ch_status & WDCS_DWF) 1577 ata_c->flags |= AT_DF; 1578 if (chp->ch_status & WDCS_ERR) { 1579 ata_c->flags |= AT_ERROR; 1580 ata_c->r_error = chp->ch_error; 1581 } 1582 if ((ata_c->flags & AT_READREG) != 0 && 1583 device_is_active(&atac->atac_dev) && 1584 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1585 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1586 wdr->cmd_iohs[wd_sdh], 0); 1587 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1588 wdr->cmd_iohs[wd_seccnt], 0); 1589 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1590 wdr->cmd_iohs[wd_sector], 0); 1591 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1592 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1593 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1594 wdr->cmd_iohs[wd_cyl_lo], 0); 1595 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1596 wdr->cmd_iohs[wd_error], 0); 1597 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1598 wdr->cmd_iohs[wd_features], 0); 1599 } 1600 callout_stop(&chp->ch_callout); 1601 chp->ch_queue->active_xfer = NULL; 1602 if (ata_c->flags & AT_POLL) { 1603 /* enable interrupts */ 1604 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1605 WDCTL_4BIT); 1606 delay(10); /* some drives need a little delay here */ 1607 } 1608 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1609 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1610 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1611 wakeup(&chp->ch_queue->active_xfer); 1612 } else 1613 __wdccommand_done_end(chp, xfer); 1614 } 1615 1616 static void 1617 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1618 { 1619 struct ata_command *ata_c = xfer->c_cmd; 1620 1621 ata_c->flags |= AT_DONE; 1622 ata_free_xfer(chp, xfer); 1623 if (ata_c->flags & AT_WAIT) 1624 wakeup(ata_c); 1625 else if (ata_c->callback) 1626 ata_c->callback(ata_c->callback_arg); 1627 atastart(chp); 1628 return; 1629 } 1630 1631 static void 1632 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1633 int reason) 1634 { 1635 struct ata_command *ata_c = xfer->c_cmd; 1636 1637 switch (reason) { 1638 case KILL_GONE: 1639 ata_c->flags |= AT_GONE; 1640 break; 1641 case KILL_RESET: 1642 ata_c->flags |= AT_RESET; 1643 break; 1644 default: 1645 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1646 reason); 1647 panic("__wdccommand_kill_xfer"); 1648 } 1649 __wdccommand_done_end(chp, xfer); 1650 } 1651 1652 /* 1653 * Send a command. The drive should be ready. 1654 * Assumes interrupts are blocked. 1655 */ 1656 void 1657 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1658 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1659 u_int8_t features) 1660 { 1661 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1662 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1663 1664 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1665 "sector=%d count=%d features=%d\n", chp->ch_atac->atac_dev.dv_xname, 1666 chp->ch_channel, drive, command, cylin, head, sector, count, 1667 features), DEBUG_FUNCS); 1668 1669 if (wdc->select) 1670 wdc->select(chp,drive); 1671 1672 /* Select drive, head, and addressing mode. */ 1673 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1674 WDSD_IBM | (drive << 4) | head); 1675 /* Load parameters into the wd_features register. */ 1676 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1677 features); 1678 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1679 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1680 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1682 0, cylin >> 8); 1683 1684 /* Send command. */ 1685 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1686 return; 1687 } 1688 1689 /* 1690 * Send a 48-bit addressing command. The drive should be ready. 1691 * Assumes interrupts are blocked. 1692 */ 1693 void 1694 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1695 u_int64_t blkno, u_int16_t count) 1696 { 1697 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1698 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1699 1700 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1701 "count=%d\n", chp->ch_atac->atac_dev.dv_xname, 1702 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1703 DEBUG_FUNCS); 1704 1705 if (wdc->select) 1706 wdc->select(chp,drive); 1707 1708 /* Select drive, head, and addressing mode. */ 1709 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1710 (drive << 4) | WDSD_LBA); 1711 1712 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1713 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1714 0); 1715 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1716 0, count); 1717 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1718 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1719 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1720 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1721 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1722 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1723 } else { 1724 /* previous */ 1725 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1726 0); 1727 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1728 0, count >> 8); 1729 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1730 0, blkno >> 24); 1731 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1732 0, blkno >> 32); 1733 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1734 0, blkno >> 40); 1735 1736 /* current */ 1737 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1738 0); 1739 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1740 count); 1741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1742 blkno); 1743 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1744 0, blkno >> 8); 1745 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1746 0, blkno >> 16); 1747 } 1748 1749 /* Send command. */ 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1751 return; 1752 } 1753 1754 /* 1755 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1756 * tested by the caller. 1757 */ 1758 void 1759 wdccommandshort(struct ata_channel *chp, int drive, int command) 1760 { 1761 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1762 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1763 1764 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1765 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1766 DEBUG_FUNCS); 1767 1768 if (wdc->select) 1769 wdc->select(chp,drive); 1770 1771 /* Select drive. */ 1772 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1773 WDSD_IBM | (drive << 4)); 1774 1775 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1776 } 1777 1778 static void 1779 __wdcerror(struct ata_channel *chp, const char *msg) 1780 { 1781 struct atac_softc *atac = chp->ch_atac; 1782 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1783 1784 if (xfer == NULL) 1785 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1786 msg); 1787 else 1788 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1789 chp->ch_channel, xfer->c_drive, msg); 1790 } 1791 1792 /* 1793 * the bit bucket 1794 */ 1795 void 1796 wdcbit_bucket(struct ata_channel *chp, int size) 1797 { 1798 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1799 1800 for (; size >= 2; size -= 2) 1801 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1802 if (size) 1803 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1804 } 1805 1806 static void 1807 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1808 { 1809 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1810 1811 #ifndef __NO_STRICT_ALIGNMENT 1812 if ((uintptr_t)bf & 1) 1813 goto unaligned; 1814 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1815 goto unaligned; 1816 #endif 1817 1818 if (flags & DRIVE_NOSTREAM) { 1819 if (flags & DRIVE_CAP32) { 1820 bus_space_read_multi_4(wdr->data32iot, 1821 wdr->data32ioh, 0, bf, len >> 2); 1822 bf = (char *)bf + (len & ~3); 1823 len &= 3; 1824 } 1825 if (len) { 1826 bus_space_read_multi_2(wdr->cmd_iot, 1827 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1828 } 1829 } else { 1830 if (flags & DRIVE_CAP32) { 1831 bus_space_read_multi_stream_4(wdr->data32iot, 1832 wdr->data32ioh, 0, bf, len >> 2); 1833 bf = (char *)bf + (len & ~3); 1834 len &= 3; 1835 } 1836 if (len) { 1837 bus_space_read_multi_stream_2(wdr->cmd_iot, 1838 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1839 } 1840 } 1841 return; 1842 1843 #ifndef __NO_STRICT_ALIGNMENT 1844 unaligned: 1845 if (flags & DRIVE_NOSTREAM) { 1846 if (flags & DRIVE_CAP32) { 1847 while (len > 3) { 1848 uint32_t val; 1849 1850 val = bus_space_read_4(wdr->data32iot, 1851 wdr->data32ioh, 0); 1852 memcpy(bf, &val, 4); 1853 bf = (char *)bf + 4; 1854 len -= 4; 1855 } 1856 } 1857 while (len > 1) { 1858 uint16_t val; 1859 1860 val = bus_space_read_2(wdr->cmd_iot, 1861 wdr->cmd_iohs[wd_data], 0); 1862 memcpy(bf, &val, 2); 1863 bf = (char *)bf + 2; 1864 len -= 2; 1865 } 1866 } else { 1867 if (flags & DRIVE_CAP32) { 1868 while (len > 3) { 1869 uint32_t val; 1870 1871 val = bus_space_read_stream_4(wdr->data32iot, 1872 wdr->data32ioh, 0); 1873 memcpy(bf, &val, 4); 1874 bf = (char *)bf + 4; 1875 len -= 4; 1876 } 1877 } 1878 while (len > 1) { 1879 uint16_t val; 1880 1881 val = bus_space_read_stream_2(wdr->cmd_iot, 1882 wdr->cmd_iohs[wd_data], 0); 1883 memcpy(bf, &val, 2); 1884 bf = (char *)bf + 2; 1885 len -= 2; 1886 } 1887 } 1888 #endif 1889 } 1890 1891 static void 1892 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1893 { 1894 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1895 1896 #ifndef __NO_STRICT_ALIGNMENT 1897 if ((uintptr_t)bf & 1) 1898 goto unaligned; 1899 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1900 goto unaligned; 1901 #endif 1902 1903 if (flags & DRIVE_NOSTREAM) { 1904 if (flags & DRIVE_CAP32) { 1905 bus_space_write_multi_4(wdr->data32iot, 1906 wdr->data32ioh, 0, bf, len >> 2); 1907 bf = (char *)bf + (len & ~3); 1908 len &= 3; 1909 } 1910 if (len) { 1911 bus_space_write_multi_2(wdr->cmd_iot, 1912 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1913 } 1914 } else { 1915 if (flags & DRIVE_CAP32) { 1916 bus_space_write_multi_stream_4(wdr->data32iot, 1917 wdr->data32ioh, 0, bf, len >> 2); 1918 bf = (char *)bf + (len & ~3); 1919 len &= 3; 1920 } 1921 if (len) { 1922 bus_space_write_multi_stream_2(wdr->cmd_iot, 1923 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1924 } 1925 } 1926 return; 1927 1928 #ifndef __NO_STRICT_ALIGNMENT 1929 unaligned: 1930 if (flags & DRIVE_NOSTREAM) { 1931 if (flags & DRIVE_CAP32) { 1932 while (len > 3) { 1933 uint32_t val; 1934 1935 memcpy(&val, bf, 4); 1936 bus_space_write_4(wdr->data32iot, 1937 wdr->data32ioh, 0, val); 1938 bf = (char *)bf + 4; 1939 len -= 4; 1940 } 1941 } 1942 while (len > 1) { 1943 uint16_t val; 1944 1945 memcpy(&val, bf, 2); 1946 bus_space_write_2(wdr->cmd_iot, 1947 wdr->cmd_iohs[wd_data], 0, val); 1948 bf = (char *)bf + 2; 1949 len -= 2; 1950 } 1951 } else { 1952 if (flags & DRIVE_CAP32) { 1953 while (len > 3) { 1954 uint32_t val; 1955 1956 memcpy(&val, bf, 4); 1957 bus_space_write_stream_4(wdr->data32iot, 1958 wdr->data32ioh, 0, val); 1959 bf = (char *)bf + 4; 1960 len -= 4; 1961 } 1962 } 1963 while (len > 1) { 1964 uint16_t val; 1965 1966 memcpy(&val, bf, 2); 1967 bus_space_write_stream_2(wdr->cmd_iot, 1968 wdr->cmd_iohs[wd_data], 0, val); 1969 bf = (char *)bf + 2; 1970 len -= 2; 1971 } 1972 } 1973 #endif 1974 } 1975
Indexes created Thu Sep 25 08:09:54 GMT 2025