wdc.c revision 1.250
1 /* $NetBSD: wdc.c,v 1.250 2008/01/10 07:44:07 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.250 2008/01/10 07:44:07 dyoung Exp $"); 74 75 #include "opt_ata.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/conf.h> 81 #include <sys/buf.h> 82 #include <sys/device.h> 83 #include <sys/malloc.h> 84 #include <sys/syslog.h> 85 #include <sys/proc.h> 86 87 #include <sys/intr.h> 88 #include <sys/bus.h> 89 90 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 91 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 92 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 93 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 94 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 95 #define bus_space_read_stream_2 bus_space_read_2 96 #define bus_space_read_stream_4 bus_space_read_4 97 #define bus_space_write_stream_2 bus_space_write_2 98 #define bus_space_write_stream_4 bus_space_write_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ata/satareg.h> 104 #include <dev/ata/satavar.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "locators.h" 109 110 #include "atapibus.h" 111 #include "wd.h" 112 #include "sata.h" 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 /* 128 * timeout when waiting for BSY to deassert when probing. 129 * set to 5s. From the standards this could be up to 31, but we can't 130 * wait that much at boot time, and 5s seems to be enouth. 131 */ 132 #define WDC_PROBE_WAIT 5 133 134 135 #if NWD > 0 136 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 137 #else 138 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 139 const struct ata_bustype wdc_ata_bustype = { 140 SCSIPI_BUSTYPE_ATA, 141 NULL, /* wdc_ata_bio */ 142 NULL, /* wdc_reset_drive */ 143 wdc_reset_channel, 144 wdc_exec_command, 145 NULL, /* ata_get_params */ 146 NULL, /* wdc_ata_addref */ 147 NULL, /* wdc_ata_delref */ 148 NULL /* ata_kill_pending */ 149 }; 150 #endif 151 152 /* Flags to wdcreset(). */ 153 #define RESET_POLL 1 154 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 155 156 static int wdcprobe1(struct ata_channel *, int); 157 static int wdcreset(struct ata_channel *, int); 158 static void __wdcerror(struct ata_channel *, const char *); 159 static int __wdcwait_reset(struct ata_channel *, int, int); 160 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 161 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 162 static void __wdccommand_kill_xfer(struct ata_channel *, 163 struct ata_xfer *, int); 164 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 165 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 166 static int __wdcwait(struct ata_channel *, int, int, int); 167 168 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 169 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 170 171 #define DEBUG_INTR 0x01 172 #define DEBUG_XFERS 0x02 173 #define DEBUG_STATUS 0x04 174 #define DEBUG_FUNCS 0x08 175 #define DEBUG_PROBE 0x10 176 #define DEBUG_DETACH 0x20 177 #define DEBUG_DELAY 0x40 178 #ifdef ATADEBUG 179 extern int atadebug_mask; /* init'ed in ata.c */ 180 int wdc_nxfer = 0; 181 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 182 #else 183 #define ATADEBUG_PRINT(args, level) 184 #endif 185 186 /* 187 * Initialize the "shadow register" handles for a standard wdc controller. 188 */ 189 void 190 wdc_init_shadow_regs(struct ata_channel *chp) 191 { 192 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 193 194 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 195 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 196 } 197 198 /* 199 * Allocate a wdc_regs array, based on the number of channels. 200 */ 201 void 202 wdc_allocate_regs(struct wdc_softc *wdc) 203 { 204 205 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 206 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 207 } 208 209 #if NSATA > 0 210 /* 211 * probe drives on SATA controllers with standard SATA registers: 212 * bring the PHYs online, read the drive signature and set drive flags 213 * appropriately. 214 */ 215 void 216 wdc_sataprobe(struct ata_channel *chp) 217 { 218 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 219 uint16_t scnt, sn, cl, ch; 220 int i, s; 221 222 /* XXX This should be done by other code. */ 223 for (i = 0; i < chp->ch_ndrive; i++) { 224 chp->ch_drive[i].chnl_softc = chp; 225 chp->ch_drive[i].drive = i; 226 } 227 228 /* reset the PHY and bring online */ 229 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 230 wdr->sata_status)) { 231 case SStatus_DET_DEV: 232 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 233 WDSD_IBM); 234 delay(10); /* 400ns delay */ 235 scnt = bus_space_read_2(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_seccnt], 0); 237 sn = bus_space_read_2(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_sector], 0); 239 cl = bus_space_read_2(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_lo], 0); 241 ch = bus_space_read_2(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_hi], 0); 243 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 244 "cl=0x%x ch=0x%x\n", 245 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 246 scnt, sn, cl, ch), DEBUG_PROBE); 247 /* 248 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 s = splbio(); 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 254 else 255 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 256 splx(s); 257 258 /* 259 * issue a reset in case only the interface part of the drive 260 * is up 261 */ 262 if (wdcreset(chp, RESET_SLEEP) != 0) 263 chp->ch_drive[0].drive_flags = 0; 264 break; 265 266 default: 267 break; 268 } 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, s; 296 297 if (wdcprobe1(chp, 0) == 0) { 298 /* No drives, abort the attach here. */ 299 return; 300 } 301 302 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 303 for (i = 0; i < mstohz(3000); i++) { 304 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 305 if (wdc->select) 306 wdc->select(chp,0); 307 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 308 0, WDSD_IBM); 309 delay(10); /* 400ns delay */ 310 st0 = bus_space_read_1(wdr->cmd_iot, 311 wdr->cmd_iohs[wd_status], 0); 312 } 313 314 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 315 if (wdc->select) 316 wdc->select(chp,1); 317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 318 0, WDSD_IBM | 0x10); 319 delay(10); /* 400ns delay */ 320 st1 = bus_space_read_1(wdr->cmd_iot, 321 wdr->cmd_iohs[wd_status], 0); 322 } 323 324 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 325 == 0 || 326 (st0 & WDCS_DRDY)) && 327 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 328 == 0 || 329 (st1 & WDCS_DRDY))) 330 break; 331 tsleep(¶ms, PRIBIO, "atadrdy", 1); 332 } 333 s = splbio(); 334 if ((st0 & WDCS_DRDY) == 0) 335 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 336 if ((st1 & WDCS_DRDY) == 0) 337 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 338 splx(s); 339 340 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 341 atac->atac_dev.dv_xname, 342 chp->ch_channel, st0, st1), DEBUG_PROBE); 343 344 /* Wait a bit, some devices are weird just after a reset. */ 345 delay(5000); 346 347 for (i = 0; i < chp->ch_ndrive; i++) { 348 /* XXX This should be done by other code. */ 349 chp->ch_drive[i].chnl_softc = chp; 350 chp->ch_drive[i].drive = i; 351 352 #if NATA_DMA 353 /* 354 * Init error counter so that an error withing the first xfers 355 * will trigger a downgrade 356 */ 357 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 358 #endif 359 360 /* If controller can't do 16bit flag the drives as 32bit */ 361 if ((atac->atac_cap & 362 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 363 s = splbio(); 364 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 365 splx(s); 366 } 367 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 368 continue; 369 370 /* Shortcut in case we've been shutdown */ 371 if (chp->ch_flags & ATACH_SHUTDOWN) 372 return; 373 374 /* 375 * Issue an identify, to try to detect ghosts. 376 * Note that we can't use interrupts here, because if there 377 * is no devices, we will get a command aborted without 378 * interrupts. 379 */ 380 error = ata_get_params(&chp->ch_drive[i], 381 AT_WAIT | AT_POLL, ¶ms); 382 if (error != CMD_OK) { 383 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 384 385 /* Shortcut in case we've been shutdown */ 386 if (chp->ch_flags & ATACH_SHUTDOWN) 387 return; 388 389 error = ata_get_params(&chp->ch_drive[i], 390 AT_WAIT | AT_POLL, ¶ms); 391 } 392 if (error == CMD_OK) { 393 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 394 s = splbio(); 395 for (j = 0; j < chp->ch_ndrive; j++) 396 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 397 splx(s); 398 } else { 399 s = splbio(); 400 chp->ch_drive[i].drive_flags &= 401 ~(DRIVE_ATA | DRIVE_ATAPI); 402 splx(s); 403 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 404 atac->atac_dev.dv_xname, 405 chp->ch_channel, i, error), DEBUG_PROBE); 406 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 407 continue; 408 /* 409 * Pre-ATA drive ? 410 * Test registers writability (Error register not 411 * writable, but cyllo is), then try an ATA command. 412 */ 413 if (wdc->select) 414 wdc->select(chp,i); 415 bus_space_write_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 417 delay(10); /* 400ns delay */ 418 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 419 0, 0x58); 420 bus_space_write_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 422 if (bus_space_read_1(wdr->cmd_iot, 423 wdr->cmd_iohs[wd_error], 0) == 0x58 || 424 bus_space_read_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 426 ATADEBUG_PRINT(("%s:%d:%d: register " 427 "writability failed\n", 428 atac->atac_dev.dv_xname, 429 chp->ch_channel, i), DEBUG_PROBE); 430 s = splbio(); 431 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 432 splx(s); 433 continue; 434 } 435 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 436 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 437 atac->atac_dev.dv_xname, 438 chp->ch_channel, i), DEBUG_PROBE); 439 s = splbio(); 440 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 441 splx(s); 442 continue; 443 } 444 bus_space_write_1(wdr->cmd_iot, 445 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 446 delay(10); /* 400ns delay */ 447 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 448 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 449 atac->atac_dev.dv_xname, 450 chp->ch_channel, i), DEBUG_PROBE); 451 s = splbio(); 452 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 453 splx(s); 454 } else { 455 s = splbio(); 456 for (j = 0; j < chp->ch_ndrive; j++) 457 chp->ch_drive[j].drive_flags &= 458 ~(DRIVE_ATA | DRIVE_ATAPI); 459 splx(s); 460 } 461 } 462 } 463 } 464 465 int 466 wdcprobe(struct ata_channel *chp) 467 { 468 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 469 /* default reset method */ 470 if (wdc->reset == NULL) 471 wdc->reset = wdc_do_reset; 472 473 return (wdcprobe1(chp, 1)); 474 } 475 476 static int 477 wdcprobe1(struct ata_channel *chp, int poll) 478 { 479 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 480 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 481 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 482 u_int8_t ret_value = 0x03; 483 u_int8_t drive; 484 int s; 485 /* XXX if poll, wdc_probe_count is 0. */ 486 int wdc_probe_count = 487 poll ? (WDC_PROBE_WAIT / WDCDELAY) 488 : (WDC_PROBE_WAIT * hz); 489 490 /* 491 * Sanity check to see if the wdc channel responds at all. 492 */ 493 494 s = splbio(); 495 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 496 while (wdc_probe_count-- > 0) { 497 if (wdc->select) 498 wdc->select(chp,0); 499 500 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 501 0, WDSD_IBM); 502 delay(10); /* 400ns delay */ 503 st0 = bus_space_read_1(wdr->cmd_iot, 504 wdr->cmd_iohs[wd_status], 0); 505 506 if (wdc->select) 507 wdc->select(chp,1); 508 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM | 0x10); 511 delay(10); /* 400ns delay */ 512 st1 = bus_space_read_1(wdr->cmd_iot, 513 wdr->cmd_iohs[wd_status], 0); 514 if ((st0 & WDCS_BSY) == 0) 515 break; 516 } 517 518 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 519 chp->ch_atac->atac_dev.dv_xname, 520 chp->ch_channel, st0, st1), DEBUG_PROBE); 521 522 if (st0 == 0xff || st0 == WDSD_IBM) 523 ret_value &= ~0x01; 524 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 525 ret_value &= ~0x02; 526 /* Register writability test, drive 0. */ 527 if (ret_value & 0x01) { 528 if (wdc->select) 529 wdc->select(chp,0); 530 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 531 0, WDSD_IBM); 532 bus_space_write_1(wdr->cmd_iot, 533 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 534 cl = bus_space_read_1(wdr->cmd_iot, 535 wdr->cmd_iohs[wd_cyl_lo], 0); 536 if (cl != 0x02) { 537 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 538 "got 0x%x != 0x02\n", 539 chp->ch_atac->atac_dev.dv_xname, 540 chp->ch_channel, cl), 541 DEBUG_PROBE); 542 ret_value &= ~0x01; 543 } 544 bus_space_write_1(wdr->cmd_iot, 545 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 546 cl = bus_space_read_1(wdr->cmd_iot, 547 wdr->cmd_iohs[wd_cyl_lo], 0); 548 if (cl != 0x01) { 549 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 550 "got 0x%x != 0x01\n", 551 chp->ch_atac->atac_dev.dv_xname, 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(wdr->cmd_iot, 557 wdr->cmd_iohs[wd_sector], 0, 0x01); 558 cl = bus_space_read_1(wdr->cmd_iot, 559 wdr->cmd_iohs[wd_sector], 0); 560 if (cl != 0x01) { 561 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 562 "got 0x%x != 0x01\n", 563 chp->ch_atac->atac_dev.dv_xname, 564 chp->ch_channel, cl), 565 DEBUG_PROBE); 566 ret_value &= ~0x01; 567 } 568 bus_space_write_1(wdr->cmd_iot, 569 wdr->cmd_iohs[wd_sector], 0, 0x02); 570 cl = bus_space_read_1(wdr->cmd_iot, 571 wdr->cmd_iohs[wd_sector], 0); 572 if (cl != 0x02) { 573 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 574 "got 0x%x != 0x02\n", 575 chp->ch_atac->atac_dev.dv_xname, 576 chp->ch_channel, cl), 577 DEBUG_PROBE); 578 ret_value &= ~0x01; 579 } 580 cl = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_cyl_lo], 0); 582 if (cl != 0x01) { 583 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 584 "got 0x%x != 0x01\n", 585 chp->ch_atac->atac_dev.dv_xname, 586 chp->ch_channel, cl), 587 DEBUG_PROBE); 588 ret_value &= ~0x01; 589 } 590 } 591 /* Register writability test, drive 1. */ 592 if (ret_value & 0x02) { 593 if (wdc->select) 594 wdc->select(chp,1); 595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 596 0, WDSD_IBM | 0x10); 597 bus_space_write_1(wdr->cmd_iot, 598 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_lo], 0); 601 if (cl != 0x02) { 602 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 603 "got 0x%x != 0x02\n", 604 chp->ch_atac->atac_dev.dv_xname, 605 chp->ch_channel, cl), 606 DEBUG_PROBE); 607 ret_value &= ~0x02; 608 } 609 bus_space_write_1(wdr->cmd_iot, 610 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 611 cl = bus_space_read_1(wdr->cmd_iot, 612 wdr->cmd_iohs[wd_cyl_lo], 0); 613 if (cl != 0x01) { 614 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 615 "got 0x%x != 0x01\n", 616 chp->ch_atac->atac_dev.dv_xname, 617 chp->ch_channel, cl), 618 DEBUG_PROBE); 619 ret_value &= ~0x02; 620 } 621 bus_space_write_1(wdr->cmd_iot, 622 wdr->cmd_iohs[wd_sector], 0, 0x01); 623 cl = bus_space_read_1(wdr->cmd_iot, 624 wdr->cmd_iohs[wd_sector], 0); 625 if (cl != 0x01) { 626 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 627 "got 0x%x != 0x01\n", 628 chp->ch_atac->atac_dev.dv_xname, 629 chp->ch_channel, cl), 630 DEBUG_PROBE); 631 ret_value &= ~0x02; 632 } 633 bus_space_write_1(wdr->cmd_iot, 634 wdr->cmd_iohs[wd_sector], 0, 0x02); 635 cl = bus_space_read_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_sector], 0); 637 if (cl != 0x02) { 638 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 639 "got 0x%x != 0x02\n", 640 chp->ch_atac->atac_dev.dv_xname, 641 chp->ch_channel, cl), 642 DEBUG_PROBE); 643 ret_value &= ~0x02; 644 } 645 cl = bus_space_read_1(wdr->cmd_iot, 646 wdr->cmd_iohs[wd_cyl_lo], 0); 647 if (cl != 0x01) { 648 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 649 "got 0x%x != 0x01\n", 650 chp->ch_atac->atac_dev.dv_xname, 651 chp->ch_channel, cl), 652 DEBUG_PROBE); 653 ret_value &= ~0x02; 654 } 655 } 656 657 if (ret_value == 0) { 658 splx(s); 659 return 0; 660 } 661 } 662 663 664 #if 0 /* XXX this break some ATA or ATAPI devices */ 665 /* 666 * reset bus. Also send an ATAPI_RESET to devices, in case there are 667 * ATAPI device out there which don't react to the bus reset 668 */ 669 if (ret_value & 0x01) { 670 if (wdc->select) 671 wdc->select(chp,0); 672 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 673 0, WDSD_IBM); 674 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 675 ATAPI_SOFT_RESET); 676 } 677 if (ret_value & 0x02) { 678 if (wdc->select) 679 wdc->select(chp,0); 680 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 681 0, WDSD_IBM | 0x10); 682 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 683 ATAPI_SOFT_RESET); 684 } 685 686 delay(5000); 687 #endif 688 689 wdc->reset(chp, RESET_POLL); 690 DELAY(2000); 691 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 692 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 693 splx(s); 694 695 ret_value = __wdcwait_reset(chp, ret_value, poll); 696 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 697 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 698 ret_value), DEBUG_PROBE); 699 700 /* if reset failed, there's nothing here */ 701 if (ret_value == 0) 702 return 0; 703 704 /* 705 * Test presence of drives. First test register signatures looking 706 * for ATAPI devices. If it's not an ATAPI and reset said there may 707 * be something here assume it's ATA or OLD. Ghost will be killed 708 * later in attach routine. 709 */ 710 for (drive = 0; drive < chp->ch_ndrive; drive++) { 711 if ((ret_value & (0x01 << drive)) == 0) 712 continue; 713 if (wdc->select) 714 wdc->select(chp,drive); 715 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 716 WDSD_IBM | (drive << 4)); 717 delay(10); /* 400ns delay */ 718 /* Save registers contents */ 719 sc = bus_space_read_1(wdr->cmd_iot, 720 wdr->cmd_iohs[wd_seccnt], 0); 721 sn = bus_space_read_1(wdr->cmd_iot, 722 wdr->cmd_iohs[wd_sector], 0); 723 cl = bus_space_read_1(wdr->cmd_iot, 724 wdr->cmd_iohs[wd_cyl_lo], 0); 725 ch = bus_space_read_1(wdr->cmd_iot, 726 wdr->cmd_iohs[wd_cyl_hi], 0); 727 728 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 729 "cl=0x%x ch=0x%x\n", 730 chp->ch_atac->atac_dev.dv_xname, 731 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 732 /* 733 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 734 * we get wrong values here, so ignore it. 735 */ 736 s = splbio(); 737 if (cl == 0x14 && ch == 0xeb) { 738 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 739 } else { 740 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 741 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 742 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 743 } 744 splx(s); 745 } 746 return (ret_value); 747 } 748 749 void 750 wdcattach(struct ata_channel *chp) 751 { 752 struct atac_softc *atac = chp->ch_atac; 753 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 754 755 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 756 757 /* default data transfer methods */ 758 if (wdc->datain_pio == NULL) 759 wdc->datain_pio = wdc_datain_pio; 760 if (wdc->dataout_pio == NULL) 761 wdc->dataout_pio = wdc_dataout_pio; 762 /* default reset method */ 763 if (wdc->reset == NULL) 764 wdc->reset = wdc_do_reset; 765 766 /* initialise global data */ 767 if (atac->atac_bustype_ata == NULL) 768 atac->atac_bustype_ata = &wdc_ata_bustype; 769 if (atac->atac_probe == NULL) 770 atac->atac_probe = wdc_drvprobe; 771 #if NATAPIBUS > 0 772 if (atac->atac_atapibus_attach == NULL) 773 atac->atac_atapibus_attach = wdc_atapibus_attach; 774 #endif 775 776 ata_channel_attach(chp); 777 } 778 779 int 780 wdcactivate(device_t self, enum devact act) 781 { 782 struct atac_softc *atac = device_private(self); 783 struct ata_channel *chp; 784 int s, i, error = 0; 785 786 s = splbio(); 787 switch (act) { 788 case DVACT_ACTIVATE: 789 error = EOPNOTSUPP; 790 break; 791 792 case DVACT_DEACTIVATE: 793 for (i = 0; i < atac->atac_nchannels; i++) { 794 chp = atac->atac_channels[i]; 795 if (chp->atabus == NULL) 796 continue; 797 error = config_deactivate(chp->atabus); 798 if (error) 799 break; 800 } 801 break; 802 } 803 splx(s); 804 return (error); 805 } 806 807 void 808 wdc_childdetached(device_t self, device_t child) 809 { 810 struct atac_softc *atac = device_private(self); 811 struct ata_channel *chp; 812 int i; 813 814 for (i = 0; i < atac->atac_nchannels; i++) { 815 chp = atac->atac_channels[i]; 816 if (child == chp->atabus) { 817 chp->atabus = NULL; 818 return; 819 } 820 } 821 } 822 823 int 824 wdcdetach(device_t self, int flags) 825 { 826 struct atac_softc *atac = device_private(self); 827 struct ata_channel *chp; 828 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 829 int i, error = 0; 830 831 for (i = 0; i < atac->atac_nchannels; i++) { 832 chp = atac->atac_channels[i]; 833 if (chp->atabus == NULL) 834 continue; 835 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 836 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 837 DEBUG_DETACH); 838 error = config_detach(chp->atabus, flags); 839 if (error) 840 break; 841 } 842 if (adapt->adapt_refcnt != 0) { 843 #ifdef DIAGNOSTIC 844 printf("wdcdetach: refcnt should be 0 here??\n"); 845 #endif 846 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 847 } 848 return (error); 849 } 850 851 /* restart an interrupted I/O */ 852 void 853 wdcrestart(void *v) 854 { 855 struct ata_channel *chp = v; 856 int s; 857 858 s = splbio(); 859 atastart(chp); 860 splx(s); 861 } 862 863 864 /* 865 * Interrupt routine for the controller. Acknowledge the interrupt, check for 866 * errors on the current operation, mark it done if necessary, and start the 867 * next request. Also check for a partially done transfer, and continue with 868 * the next chunk if so. 869 */ 870 int 871 wdcintr(void *arg) 872 { 873 struct ata_channel *chp = arg; 874 struct atac_softc *atac = chp->ch_atac; 875 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 876 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 877 struct ata_xfer *xfer; 878 int ret; 879 880 if (!device_is_active(&atac->atac_dev)) { 881 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 882 DEBUG_INTR); 883 return (0); 884 } 885 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 886 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 887 /* try to clear the pending interrupt anyway */ 888 (void)bus_space_read_1(wdr->cmd_iot, 889 wdr->cmd_iohs[wd_status], 0); 890 return (0); 891 } 892 893 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 894 xfer = chp->ch_queue->active_xfer; 895 #ifdef DIAGNOSTIC 896 if (xfer == NULL) 897 panic("wdcintr: no xfer"); 898 if (xfer->c_chp != chp) { 899 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 900 chp->ch_channel); 901 panic("wdcintr: wrong channel"); 902 } 903 #endif 904 #if NATA_DMA || NATA_PIOBM 905 if (chp->ch_flags & ATACH_DMA_WAIT) { 906 wdc->dma_status = 907 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 908 xfer->c_drive, WDC_DMAEND_END); 909 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 910 /* IRQ not for us, not detected by DMA engine */ 911 return 0; 912 } 913 chp->ch_flags &= ~ATACH_DMA_WAIT; 914 } 915 #endif 916 chp->ch_flags &= ~ATACH_IRQ_WAIT; 917 ret = xfer->c_intr(chp, xfer, 1); 918 if (ret == 0) /* irq was not for us, still waiting for irq */ 919 chp->ch_flags |= ATACH_IRQ_WAIT; 920 return (ret); 921 } 922 923 /* Put all disk in RESET state */ 924 void 925 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 926 { 927 struct ata_channel *chp = drvp->chnl_softc; 928 929 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 930 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 931 DEBUG_FUNCS); 932 933 ata_reset_channel(chp, flags); 934 } 935 936 void 937 wdc_reset_channel(struct ata_channel *chp, int flags) 938 { 939 TAILQ_HEAD(, ata_xfer) reset_xfer; 940 struct ata_xfer *xfer, *next_xfer; 941 #if NATA_DMA || NATA_PIOBM 942 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 943 #endif 944 945 TAILQ_INIT(&reset_xfer); 946 947 chp->ch_flags &= ~ATACH_IRQ_WAIT; 948 949 /* 950 * if the current command if on an ATAPI device, issue a 951 * ATAPI_SOFT_RESET 952 */ 953 xfer = chp->ch_queue->active_xfer; 954 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 955 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 956 if (flags & AT_WAIT) 957 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 958 else 959 delay(1000); 960 } 961 962 /* reset the channel */ 963 if (flags & AT_WAIT) 964 (void) wdcreset(chp, RESET_SLEEP); 965 else 966 (void) wdcreset(chp, RESET_POLL); 967 968 /* 969 * wait a bit after reset; in case the DMA engines needs some time 970 * to recover. 971 */ 972 if (flags & AT_WAIT) 973 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 974 else 975 delay(1000); 976 /* 977 * look for pending xfers. If we have a shared queue, we'll also reset 978 * the other channel if the current xfer is running on it. 979 * Then we'll dequeue only the xfers for this channel. 980 */ 981 if ((flags & AT_RST_NOCMD) == 0) { 982 /* 983 * move all xfers queued for this channel to the reset queue, 984 * and then process the current xfer and then the reset queue. 985 * We have to use a temporary queue because c_kill_xfer() 986 * may requeue commands. 987 */ 988 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 989 xfer != NULL; xfer = next_xfer) { 990 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 991 if (xfer->c_chp != chp) 992 continue; 993 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 994 xfer, c_xferchain); 995 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 996 } 997 xfer = chp->ch_queue->active_xfer; 998 if (xfer) { 999 if (xfer->c_chp != chp) 1000 ata_reset_channel(xfer->c_chp, flags); 1001 else { 1002 callout_stop(&chp->ch_callout); 1003 #if NATA_DMA || NATA_PIOBM 1004 /* 1005 * If we're waiting for DMA, stop the 1006 * DMA engine 1007 */ 1008 if (chp->ch_flags & ATACH_DMA_WAIT) { 1009 (*wdc->dma_finish)( 1010 wdc->dma_arg, 1011 chp->ch_channel, 1012 xfer->c_drive, 1013 WDC_DMAEND_ABRT_QUIET); 1014 chp->ch_flags &= ~ATACH_DMA_WAIT; 1015 } 1016 #endif 1017 chp->ch_queue->active_xfer = NULL; 1018 if ((flags & AT_RST_EMERG) == 0) 1019 xfer->c_kill_xfer( 1020 chp, xfer, KILL_RESET); 1021 } 1022 } 1023 1024 for (xfer = TAILQ_FIRST(&reset_xfer); 1025 xfer != NULL; xfer = next_xfer) { 1026 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1027 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1028 if ((flags & AT_RST_EMERG) == 0) 1029 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1030 } 1031 } 1032 } 1033 1034 static int 1035 wdcreset(struct ata_channel *chp, int poll) 1036 { 1037 struct atac_softc *atac = chp->ch_atac; 1038 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1039 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1040 int drv_mask1, drv_mask2; 1041 1042 wdc->reset(chp, poll); 1043 1044 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1045 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1046 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1047 (poll == RESET_SLEEP) ? 0 : 1); 1048 if (drv_mask2 != drv_mask1) { 1049 printf("%s channel %d: reset failed for", 1050 atac->atac_dev.dv_xname, chp->ch_channel); 1051 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1052 printf(" drive 0"); 1053 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1054 printf(" drive 1"); 1055 printf("\n"); 1056 } 1057 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1058 return (drv_mask1 != drv_mask2) ? 1 : 0; 1059 } 1060 1061 void 1062 wdc_do_reset(struct ata_channel *chp, int poll) 1063 { 1064 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1065 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1066 int s = 0; 1067 1068 if (poll != RESET_SLEEP) 1069 s = splbio(); 1070 if (wdc->select) 1071 wdc->select(chp,0); 1072 /* master */ 1073 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1074 delay(10); /* 400ns delay */ 1075 /* assert SRST, wait for reset to complete */ 1076 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1077 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1078 delay(2000); 1079 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1080 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1081 WDCTL_4BIT | WDCTL_IDS); 1082 delay(10); /* 400ns delay */ 1083 if (poll != RESET_SLEEP) { 1084 /* ACK interrupt in case there is one pending left */ 1085 if (wdc->irqack) 1086 wdc->irqack(chp); 1087 splx(s); 1088 } 1089 } 1090 1091 static int 1092 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1093 { 1094 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1095 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1096 int timeout, nloop; 1097 u_int8_t st0 = 0, st1 = 0; 1098 #ifdef ATADEBUG 1099 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1100 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1101 #endif 1102 1103 if (poll) 1104 nloop = WDCNDELAY_RST; 1105 else 1106 nloop = WDC_RESET_WAIT * hz / 1000; 1107 /* wait for BSY to deassert */ 1108 for (timeout = 0; timeout < nloop; timeout++) { 1109 if ((drv_mask & 0x01) != 0) { 1110 if (wdc->select) 1111 wdc->select(chp,0); 1112 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1113 0, WDSD_IBM); /* master */ 1114 delay(10); 1115 st0 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_status], 0); 1117 #ifdef ATADEBUG 1118 sc0 = bus_space_read_1(wdr->cmd_iot, 1119 wdr->cmd_iohs[wd_seccnt], 0); 1120 sn0 = bus_space_read_1(wdr->cmd_iot, 1121 wdr->cmd_iohs[wd_sector], 0); 1122 cl0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_cyl_lo], 0); 1124 ch0 = bus_space_read_1(wdr->cmd_iot, 1125 wdr->cmd_iohs[wd_cyl_hi], 0); 1126 #endif 1127 } 1128 if ((drv_mask & 0x02) != 0) { 1129 if (wdc->select) 1130 wdc->select(chp,1); 1131 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1132 0, WDSD_IBM | 0x10); /* slave */ 1133 delay(10); 1134 st1 = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_status], 0); 1136 #ifdef ATADEBUG 1137 sc1 = bus_space_read_1(wdr->cmd_iot, 1138 wdr->cmd_iohs[wd_seccnt], 0); 1139 sn1 = bus_space_read_1(wdr->cmd_iot, 1140 wdr->cmd_iohs[wd_sector], 0); 1141 cl1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_cyl_lo], 0); 1143 ch1 = bus_space_read_1(wdr->cmd_iot, 1144 wdr->cmd_iohs[wd_cyl_hi], 0); 1145 #endif 1146 } 1147 1148 if ((drv_mask & 0x01) == 0) { 1149 /* no master */ 1150 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1151 /* No master, slave is ready, it's done */ 1152 goto end; 1153 } 1154 if ((drv_mask & 0x02) == 0) { 1155 /* No master, no slave: it's done */ 1156 goto end; 1157 } 1158 } else if ((drv_mask & 0x02) == 0) { 1159 /* no slave */ 1160 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1161 /* No slave, master is ready, it's done */ 1162 goto end; 1163 } 1164 } else { 1165 /* Wait for both master and slave to be ready */ 1166 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1167 goto end; 1168 } 1169 } 1170 if (poll) 1171 delay(WDCDELAY); 1172 else 1173 tsleep(&nloop, PRIBIO, "atarst", 1); 1174 } 1175 /* Reset timed out. Maybe it's because drv_mask was not right */ 1176 if (st0 & WDCS_BSY) 1177 drv_mask &= ~0x01; 1178 if (st1 & WDCS_BSY) 1179 drv_mask &= ~0x02; 1180 end: 1181 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1182 "cl=0x%x ch=0x%x\n", 1183 chp->ch_atac->atac_dev.dv_xname, 1184 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1185 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1186 "cl=0x%x ch=0x%x\n", 1187 chp->ch_atac->atac_dev.dv_xname, 1188 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1189 1190 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1191 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1192 st0, st1), DEBUG_PROBE); 1193 1194 return drv_mask; 1195 } 1196 1197 /* 1198 * Wait for a drive to be !BSY, and have mask in its status register. 1199 * return -1 for a timeout after "timeout" ms. 1200 */ 1201 static int 1202 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1203 { 1204 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1205 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1206 u_char status; 1207 int xtime = 0; 1208 1209 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1210 chp->ch_atac->atac_dev.dv_xname, 1211 chp->ch_channel), DEBUG_STATUS); 1212 chp->ch_error = 0; 1213 1214 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1215 1216 for (;;) { 1217 chp->ch_status = status = 1218 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1219 if ((status & (WDCS_BSY | mask)) == bits) 1220 break; 1221 if (++xtime > timeout) { 1222 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1223 "status %x error %x (mask 0x%x bits 0x%x)\n", 1224 xtime, status, 1225 bus_space_read_1(wdr->cmd_iot, 1226 wdr->cmd_iohs[wd_error], 0), mask, bits), 1227 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1228 return(WDCWAIT_TOUT); 1229 } 1230 delay(WDCDELAY); 1231 } 1232 #ifdef ATADEBUG 1233 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1234 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1235 #endif 1236 if (status & WDCS_ERR) 1237 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1238 wdr->cmd_iohs[wd_error], 0); 1239 #ifdef WDCNDELAY_DEBUG 1240 /* After autoconfig, there should be no long delays. */ 1241 if (!cold && xtime > WDCNDELAY_DEBUG) { 1242 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1243 if (xfer == NULL) 1244 printf("%s channel %d: warning: busy-wait took %dus\n", 1245 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1246 WDCDELAY * xtime); 1247 else 1248 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1249 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1250 xfer->c_drive, 1251 WDCDELAY * xtime); 1252 } 1253 #endif 1254 return(WDCWAIT_OK); 1255 } 1256 1257 /* 1258 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1259 * thread if possible 1260 */ 1261 int 1262 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1263 { 1264 int error, i, timeout_hz = mstohz(timeout); 1265 1266 if (timeout_hz == 0 || 1267 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1268 error = __wdcwait(chp, mask, bits, timeout); 1269 else { 1270 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1271 if (error != 0) { 1272 if ((chp->ch_flags & ATACH_TH_RUN) || 1273 (flags & AT_WAIT)) { 1274 /* 1275 * we're running in the channel thread 1276 * or some userland thread context 1277 */ 1278 for (i = 0; i < timeout_hz; i++) { 1279 if (__wdcwait(chp, mask, bits, 1280 WDCDELAY_POLL) == 0) { 1281 error = 0; 1282 break; 1283 } 1284 tsleep(&chp, PRIBIO, "atapoll", 1); 1285 } 1286 } else { 1287 /* 1288 * we're probably in interrupt context, 1289 * ask the thread to come back here 1290 */ 1291 #ifdef DIAGNOSTIC 1292 if (chp->ch_queue->queue_freeze > 0) 1293 panic("wdcwait: queue_freeze"); 1294 #endif 1295 chp->ch_queue->queue_freeze++; 1296 wakeup(&chp->ch_thread); 1297 return(WDCWAIT_THR); 1298 } 1299 } 1300 } 1301 return (error); 1302 } 1303 1304 1305 #if NATA_DMA 1306 /* 1307 * Busy-wait for DMA to complete 1308 */ 1309 int 1310 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1311 { 1312 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1313 int xtime; 1314 1315 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1316 wdc->dma_status = 1317 (*wdc->dma_finish)(wdc->dma_arg, 1318 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1319 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1320 return 0; 1321 delay(WDCDELAY); 1322 } 1323 /* timeout, force a DMA halt */ 1324 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1325 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1326 return 1; 1327 } 1328 #endif 1329 1330 void 1331 wdctimeout(void *arg) 1332 { 1333 struct ata_channel *chp = (struct ata_channel *)arg; 1334 #if NATA_DMA || NATA_PIOBM 1335 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1336 #endif 1337 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1338 int s; 1339 1340 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1341 1342 s = splbio(); 1343 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1344 __wdcerror(chp, "lost interrupt"); 1345 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1346 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1347 xfer->c_bcount, 1348 xfer->c_skip); 1349 #if NATA_DMA || NATA_PIOBM 1350 if (chp->ch_flags & ATACH_DMA_WAIT) { 1351 wdc->dma_status = 1352 (*wdc->dma_finish)(wdc->dma_arg, 1353 chp->ch_channel, xfer->c_drive, 1354 WDC_DMAEND_ABRT); 1355 chp->ch_flags &= ~ATACH_DMA_WAIT; 1356 } 1357 #endif 1358 /* 1359 * Call the interrupt routine. If we just missed an interrupt, 1360 * it will do what's needed. Else, it will take the needed 1361 * action (reset the device). 1362 * Before that we need to reinstall the timeout callback, 1363 * in case it will miss another irq while in this transfer 1364 * We arbitray chose it to be 1s 1365 */ 1366 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1367 xfer->c_flags |= C_TIMEOU; 1368 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1369 xfer->c_intr(chp, xfer, 1); 1370 } else 1371 __wdcerror(chp, "missing untimeout"); 1372 splx(s); 1373 } 1374 1375 int 1376 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1377 { 1378 struct ata_channel *chp = drvp->chnl_softc; 1379 struct ata_xfer *xfer; 1380 int s, ret; 1381 1382 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1383 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1384 DEBUG_FUNCS); 1385 1386 /* set up an xfer and queue. Wait for completion */ 1387 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1388 ATAXF_NOSLEEP); 1389 if (xfer == NULL) { 1390 return ATACMD_TRY_AGAIN; 1391 } 1392 1393 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1394 ata_c->flags |= AT_POLL; 1395 if (ata_c->flags & AT_POLL) 1396 xfer->c_flags |= C_POLL; 1397 if (ata_c->flags & AT_WAIT) 1398 xfer->c_flags |= C_WAIT; 1399 xfer->c_drive = drvp->drive; 1400 xfer->c_databuf = ata_c->data; 1401 xfer->c_bcount = ata_c->bcount; 1402 xfer->c_cmd = ata_c; 1403 xfer->c_start = __wdccommand_start; 1404 xfer->c_intr = __wdccommand_intr; 1405 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1406 1407 s = splbio(); 1408 ata_exec_xfer(chp, xfer); 1409 #ifdef DIAGNOSTIC 1410 if ((ata_c->flags & AT_POLL) != 0 && 1411 (ata_c->flags & AT_DONE) == 0) 1412 panic("wdc_exec_command: polled command not done"); 1413 #endif 1414 if (ata_c->flags & AT_DONE) { 1415 ret = ATACMD_COMPLETE; 1416 } else { 1417 if (ata_c->flags & AT_WAIT) { 1418 while ((ata_c->flags & AT_DONE) == 0) { 1419 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1420 } 1421 ret = ATACMD_COMPLETE; 1422 } else { 1423 ret = ATACMD_QUEUED; 1424 } 1425 } 1426 splx(s); 1427 return ret; 1428 } 1429 1430 static void 1431 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1432 { 1433 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1434 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1435 int drive = xfer->c_drive; 1436 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1437 struct ata_command *ata_c = xfer->c_cmd; 1438 1439 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1440 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1441 DEBUG_FUNCS); 1442 1443 if (wdc->select) 1444 wdc->select(chp,drive); 1445 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1446 WDSD_IBM | (drive << 4)); 1447 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1448 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1449 case WDCWAIT_OK: 1450 break; 1451 case WDCWAIT_TOUT: 1452 ata_c->flags |= AT_TIMEOU; 1453 __wdccommand_done(chp, xfer); 1454 return; 1455 case WDCWAIT_THR: 1456 return; 1457 } 1458 if (ata_c->flags & AT_POLL) { 1459 /* polled command, disable interrupts */ 1460 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1461 WDCTL_4BIT | WDCTL_IDS); 1462 } 1463 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1464 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1465 1466 if ((ata_c->flags & AT_POLL) == 0) { 1467 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1468 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1469 wdctimeout, chp); 1470 return; 1471 } 1472 /* 1473 * Polled command. Wait for drive ready or drq. Done in intr(). 1474 * Wait for at last 400ns for status bit to be valid. 1475 */ 1476 delay(10); /* 400ns delay */ 1477 __wdccommand_intr(chp, xfer, 0); 1478 } 1479 1480 static int 1481 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1482 { 1483 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1484 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1485 struct ata_command *ata_c = xfer->c_cmd; 1486 int bcount = ata_c->bcount; 1487 char *data = ata_c->data; 1488 int wflags; 1489 int drive_flags; 1490 1491 if (ata_c->r_command == WDCC_IDENTIFY || 1492 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1493 /* 1494 * The IDENTIFY data has been designed as an array of 1495 * u_int16_t, so we can byteswap it on the fly. 1496 * Historically it's what we have always done so keeping it 1497 * here ensure binary backward compatibility. 1498 */ 1499 drive_flags = DRIVE_NOSTREAM | 1500 chp->ch_drive[xfer->c_drive].drive_flags; 1501 } else { 1502 /* 1503 * Other data structure are opaque and should be transfered 1504 * as is. 1505 */ 1506 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1507 } 1508 1509 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1510 /* both wait and poll, we can tsleep here */ 1511 wflags = AT_WAIT | AT_POLL; 1512 } else { 1513 wflags = AT_POLL; 1514 } 1515 1516 again: 1517 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1518 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1519 DEBUG_INTR); 1520 /* 1521 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1522 * Reselect again, it doesn't hurt for others commands, and the time 1523 * penalty for the extra regiter write is acceptable, 1524 * wdc_exec_command() isn't called often (mosly for autoconfig) 1525 */ 1526 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1527 WDSD_IBM | (xfer->c_drive << 4)); 1528 if ((ata_c->flags & AT_XFDONE) != 0) { 1529 /* 1530 * We have completed a data xfer. The drive should now be 1531 * in its initial state 1532 */ 1533 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1534 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1535 wflags) == WDCWAIT_TOUT) { 1536 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1537 return 0; /* IRQ was not for us */ 1538 ata_c->flags |= AT_TIMEOU; 1539 } 1540 goto out; 1541 } 1542 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1543 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1544 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1545 return 0; /* IRQ was not for us */ 1546 ata_c->flags |= AT_TIMEOU; 1547 goto out; 1548 } 1549 if (wdc->irqack) 1550 wdc->irqack(chp); 1551 if (ata_c->flags & AT_READ) { 1552 if ((chp->ch_status & WDCS_DRQ) == 0) { 1553 ata_c->flags |= AT_TIMEOU; 1554 goto out; 1555 } 1556 wdc->datain_pio(chp, drive_flags, data, bcount); 1557 /* at this point the drive should be in its initial state */ 1558 ata_c->flags |= AT_XFDONE; 1559 /* 1560 * XXX checking the status register again here cause some 1561 * hardware to timeout. 1562 */ 1563 } else if (ata_c->flags & AT_WRITE) { 1564 if ((chp->ch_status & WDCS_DRQ) == 0) { 1565 ata_c->flags |= AT_TIMEOU; 1566 goto out; 1567 } 1568 wdc->dataout_pio(chp, drive_flags, data, bcount); 1569 ata_c->flags |= AT_XFDONE; 1570 if ((ata_c->flags & AT_POLL) == 0) { 1571 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1572 callout_reset(&chp->ch_callout, 1573 mstohz(ata_c->timeout), wdctimeout, chp); 1574 return 1; 1575 } else { 1576 goto again; 1577 } 1578 } 1579 out: 1580 __wdccommand_done(chp, xfer); 1581 return 1; 1582 } 1583 1584 static void 1585 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1586 { 1587 struct atac_softc *atac = chp->ch_atac; 1588 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1589 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1590 struct ata_command *ata_c = xfer->c_cmd; 1591 1592 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1593 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1594 ata_c->flags), DEBUG_FUNCS); 1595 1596 1597 if (chp->ch_status & WDCS_DWF) 1598 ata_c->flags |= AT_DF; 1599 if (chp->ch_status & WDCS_ERR) { 1600 ata_c->flags |= AT_ERROR; 1601 ata_c->r_error = chp->ch_error; 1602 } 1603 if ((ata_c->flags & AT_READREG) != 0 && 1604 device_is_active(&atac->atac_dev) && 1605 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1606 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1607 wdr->cmd_iohs[wd_sdh], 0); 1608 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1609 wdr->cmd_iohs[wd_seccnt], 0); 1610 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1611 wdr->cmd_iohs[wd_sector], 0); 1612 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1613 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1614 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1615 wdr->cmd_iohs[wd_cyl_lo], 0); 1616 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1617 wdr->cmd_iohs[wd_error], 0); 1618 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1619 wdr->cmd_iohs[wd_features], 0); 1620 } 1621 callout_stop(&chp->ch_callout); 1622 chp->ch_queue->active_xfer = NULL; 1623 if (ata_c->flags & AT_POLL) { 1624 /* enable interrupts */ 1625 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1626 WDCTL_4BIT); 1627 delay(10); /* some drives need a little delay here */ 1628 } 1629 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1630 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1631 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1632 wakeup(&chp->ch_queue->active_xfer); 1633 } else 1634 __wdccommand_done_end(chp, xfer); 1635 } 1636 1637 static void 1638 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1639 { 1640 struct ata_command *ata_c = xfer->c_cmd; 1641 1642 ata_c->flags |= AT_DONE; 1643 ata_free_xfer(chp, xfer); 1644 if (ata_c->flags & AT_WAIT) 1645 wakeup(ata_c); 1646 else if (ata_c->callback) 1647 ata_c->callback(ata_c->callback_arg); 1648 atastart(chp); 1649 return; 1650 } 1651 1652 static void 1653 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1654 int reason) 1655 { 1656 struct ata_command *ata_c = xfer->c_cmd; 1657 1658 switch (reason) { 1659 case KILL_GONE: 1660 ata_c->flags |= AT_GONE; 1661 break; 1662 case KILL_RESET: 1663 ata_c->flags |= AT_RESET; 1664 break; 1665 default: 1666 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1667 reason); 1668 panic("__wdccommand_kill_xfer"); 1669 } 1670 __wdccommand_done_end(chp, xfer); 1671 } 1672 1673 /* 1674 * Send a command. The drive should be ready. 1675 * Assumes interrupts are blocked. 1676 */ 1677 void 1678 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1679 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1680 u_int8_t features) 1681 { 1682 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1683 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1684 1685 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1686 "sector=%d count=%d features=%d\n", chp->ch_atac->atac_dev.dv_xname, 1687 chp->ch_channel, drive, command, cylin, head, sector, count, 1688 features), DEBUG_FUNCS); 1689 1690 if (wdc->select) 1691 wdc->select(chp,drive); 1692 1693 /* Select drive, head, and addressing mode. */ 1694 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1695 WDSD_IBM | (drive << 4) | head); 1696 /* Load parameters into the wd_features register. */ 1697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1698 features); 1699 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1701 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1703 0, cylin >> 8); 1704 1705 /* Send command. */ 1706 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1707 return; 1708 } 1709 1710 /* 1711 * Send a 48-bit addressing command. The drive should be ready. 1712 * Assumes interrupts are blocked. 1713 */ 1714 void 1715 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1716 u_int64_t blkno, u_int16_t count) 1717 { 1718 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1719 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1720 1721 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1722 "count=%d\n", chp->ch_atac->atac_dev.dv_xname, 1723 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1724 DEBUG_FUNCS); 1725 1726 if (wdc->select) 1727 wdc->select(chp,drive); 1728 1729 /* Select drive, head, and addressing mode. */ 1730 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1731 (drive << 4) | WDSD_LBA); 1732 1733 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1734 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1735 0); 1736 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1737 0, count); 1738 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1739 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1740 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1741 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1742 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1743 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1744 } else { 1745 /* previous */ 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1747 0); 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1749 0, count >> 8); 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1751 0, blkno >> 24); 1752 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1753 0, blkno >> 32); 1754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1755 0, blkno >> 40); 1756 1757 /* current */ 1758 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1759 0); 1760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1761 count); 1762 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1763 blkno); 1764 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1765 0, blkno >> 8); 1766 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1767 0, blkno >> 16); 1768 } 1769 1770 /* Send command. */ 1771 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1772 return; 1773 } 1774 1775 /* 1776 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1777 * tested by the caller. 1778 */ 1779 void 1780 wdccommandshort(struct ata_channel *chp, int drive, int command) 1781 { 1782 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1783 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1784 1785 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1786 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1787 DEBUG_FUNCS); 1788 1789 if (wdc->select) 1790 wdc->select(chp,drive); 1791 1792 /* Select drive. */ 1793 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1794 WDSD_IBM | (drive << 4)); 1795 1796 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1797 } 1798 1799 static void 1800 __wdcerror(struct ata_channel *chp, const char *msg) 1801 { 1802 struct atac_softc *atac = chp->ch_atac; 1803 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1804 1805 if (xfer == NULL) 1806 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1807 msg); 1808 else 1809 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1810 chp->ch_channel, xfer->c_drive, msg); 1811 } 1812 1813 /* 1814 * the bit bucket 1815 */ 1816 void 1817 wdcbit_bucket(struct ata_channel *chp, int size) 1818 { 1819 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1820 1821 for (; size >= 2; size -= 2) 1822 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1823 if (size) 1824 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1825 } 1826 1827 static void 1828 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1829 { 1830 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1831 1832 #ifndef __NO_STRICT_ALIGNMENT 1833 if ((uintptr_t)bf & 1) 1834 goto unaligned; 1835 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1836 goto unaligned; 1837 #endif 1838 1839 if (flags & DRIVE_NOSTREAM) { 1840 if (flags & DRIVE_CAP32) { 1841 bus_space_read_multi_4(wdr->data32iot, 1842 wdr->data32ioh, 0, bf, len >> 2); 1843 bf = (char *)bf + (len & ~3); 1844 len &= 3; 1845 } 1846 if (len) { 1847 bus_space_read_multi_2(wdr->cmd_iot, 1848 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1849 } 1850 } else { 1851 if (flags & DRIVE_CAP32) { 1852 bus_space_read_multi_stream_4(wdr->data32iot, 1853 wdr->data32ioh, 0, bf, len >> 2); 1854 bf = (char *)bf + (len & ~3); 1855 len &= 3; 1856 } 1857 if (len) { 1858 bus_space_read_multi_stream_2(wdr->cmd_iot, 1859 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1860 } 1861 } 1862 return; 1863 1864 #ifndef __NO_STRICT_ALIGNMENT 1865 unaligned: 1866 if (flags & DRIVE_NOSTREAM) { 1867 if (flags & DRIVE_CAP32) { 1868 while (len > 3) { 1869 uint32_t val; 1870 1871 val = bus_space_read_4(wdr->data32iot, 1872 wdr->data32ioh, 0); 1873 memcpy(bf, &val, 4); 1874 bf = (char *)bf + 4; 1875 len -= 4; 1876 } 1877 } 1878 while (len > 1) { 1879 uint16_t val; 1880 1881 val = bus_space_read_2(wdr->cmd_iot, 1882 wdr->cmd_iohs[wd_data], 0); 1883 memcpy(bf, &val, 2); 1884 bf = (char *)bf + 2; 1885 len -= 2; 1886 } 1887 } else { 1888 if (flags & DRIVE_CAP32) { 1889 while (len > 3) { 1890 uint32_t val; 1891 1892 val = bus_space_read_stream_4(wdr->data32iot, 1893 wdr->data32ioh, 0); 1894 memcpy(bf, &val, 4); 1895 bf = (char *)bf + 4; 1896 len -= 4; 1897 } 1898 } 1899 while (len > 1) { 1900 uint16_t val; 1901 1902 val = bus_space_read_stream_2(wdr->cmd_iot, 1903 wdr->cmd_iohs[wd_data], 0); 1904 memcpy(bf, &val, 2); 1905 bf = (char *)bf + 2; 1906 len -= 2; 1907 } 1908 } 1909 #endif 1910 } 1911 1912 static void 1913 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1914 { 1915 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1916 1917 #ifndef __NO_STRICT_ALIGNMENT 1918 if ((uintptr_t)bf & 1) 1919 goto unaligned; 1920 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1921 goto unaligned; 1922 #endif 1923 1924 if (flags & DRIVE_NOSTREAM) { 1925 if (flags & DRIVE_CAP32) { 1926 bus_space_write_multi_4(wdr->data32iot, 1927 wdr->data32ioh, 0, bf, len >> 2); 1928 bf = (char *)bf + (len & ~3); 1929 len &= 3; 1930 } 1931 if (len) { 1932 bus_space_write_multi_2(wdr->cmd_iot, 1933 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1934 } 1935 } else { 1936 if (flags & DRIVE_CAP32) { 1937 bus_space_write_multi_stream_4(wdr->data32iot, 1938 wdr->data32ioh, 0, bf, len >> 2); 1939 bf = (char *)bf + (len & ~3); 1940 len &= 3; 1941 } 1942 if (len) { 1943 bus_space_write_multi_stream_2(wdr->cmd_iot, 1944 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1945 } 1946 } 1947 return; 1948 1949 #ifndef __NO_STRICT_ALIGNMENT 1950 unaligned: 1951 if (flags & DRIVE_NOSTREAM) { 1952 if (flags & DRIVE_CAP32) { 1953 while (len > 3) { 1954 uint32_t val; 1955 1956 memcpy(&val, bf, 4); 1957 bus_space_write_4(wdr->data32iot, 1958 wdr->data32ioh, 0, val); 1959 bf = (char *)bf + 4; 1960 len -= 4; 1961 } 1962 } 1963 while (len > 1) { 1964 uint16_t val; 1965 1966 memcpy(&val, bf, 2); 1967 bus_space_write_2(wdr->cmd_iot, 1968 wdr->cmd_iohs[wd_data], 0, val); 1969 bf = (char *)bf + 2; 1970 len -= 2; 1971 } 1972 } else { 1973 if (flags & DRIVE_CAP32) { 1974 while (len > 3) { 1975 uint32_t val; 1976 1977 memcpy(&val, bf, 4); 1978 bus_space_write_stream_4(wdr->data32iot, 1979 wdr->data32ioh, 0, val); 1980 bf = (char *)bf + 4; 1981 len -= 4; 1982 } 1983 } 1984 while (len > 1) { 1985 uint16_t val; 1986 1987 memcpy(&val, bf, 2); 1988 bus_space_write_stream_2(wdr->cmd_iot, 1989 wdr->cmd_iohs[wd_data], 0, val); 1990 bf = (char *)bf + 2; 1991 len -= 2; 1992 } 1993 } 1994 #endif 1995 } 1996
Indexes created Tue Sep 23 01:09:51 GMT 2025