wdc.c revision 1.251
1 /* $NetBSD: wdc.c,v 1.251 2008/01/19 22:22:14 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.251 2008/01/19 22:22:14 dyoung Exp $"); 74 75 #include "opt_ata.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/conf.h> 81 #include <sys/buf.h> 82 #include <sys/device.h> 83 #include <sys/malloc.h> 84 #include <sys/syslog.h> 85 #include <sys/proc.h> 86 87 #include <sys/intr.h> 88 #include <sys/bus.h> 89 90 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 91 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 92 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 93 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 94 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 95 #define bus_space_read_stream_2 bus_space_read_2 96 #define bus_space_read_stream_4 bus_space_read_4 97 #define bus_space_write_stream_2 bus_space_write_2 98 #define bus_space_write_stream_4 bus_space_write_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ata/satareg.h> 104 #include <dev/ata/satavar.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "locators.h" 109 110 #include "atapibus.h" 111 #include "wd.h" 112 #include "sata.h" 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 /* 128 * timeout when waiting for BSY to deassert when probing. 129 * set to 5s. From the standards this could be up to 31, but we can't 130 * wait that much at boot time, and 5s seems to be enouth. 131 */ 132 #define WDC_PROBE_WAIT 5 133 134 135 #if NWD > 0 136 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 137 #else 138 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 139 const struct ata_bustype wdc_ata_bustype = { 140 SCSIPI_BUSTYPE_ATA, 141 NULL, /* wdc_ata_bio */ 142 NULL, /* wdc_reset_drive */ 143 wdc_reset_channel, 144 wdc_exec_command, 145 NULL, /* ata_get_params */ 146 NULL, /* wdc_ata_addref */ 147 NULL, /* wdc_ata_delref */ 148 NULL /* ata_kill_pending */ 149 }; 150 #endif 151 152 /* Flags to wdcreset(). */ 153 #define RESET_POLL 1 154 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 155 156 static int wdcprobe1(struct ata_channel *, int); 157 static int wdcreset(struct ata_channel *, int); 158 static void __wdcerror(struct ata_channel *, const char *); 159 static int __wdcwait_reset(struct ata_channel *, int, int); 160 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 161 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 162 static void __wdccommand_kill_xfer(struct ata_channel *, 163 struct ata_xfer *, int); 164 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 165 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 166 static int __wdcwait(struct ata_channel *, int, int, int); 167 168 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 169 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 170 171 #define DEBUG_INTR 0x01 172 #define DEBUG_XFERS 0x02 173 #define DEBUG_STATUS 0x04 174 #define DEBUG_FUNCS 0x08 175 #define DEBUG_PROBE 0x10 176 #define DEBUG_DETACH 0x20 177 #define DEBUG_DELAY 0x40 178 #ifdef ATADEBUG 179 extern int atadebug_mask; /* init'ed in ata.c */ 180 int wdc_nxfer = 0; 181 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 182 #else 183 #define ATADEBUG_PRINT(args, level) 184 #endif 185 186 /* 187 * Initialize the "shadow register" handles for a standard wdc controller. 188 */ 189 void 190 wdc_init_shadow_regs(struct ata_channel *chp) 191 { 192 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 193 194 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 195 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 196 } 197 198 /* 199 * Allocate a wdc_regs array, based on the number of channels. 200 */ 201 void 202 wdc_allocate_regs(struct wdc_softc *wdc) 203 { 204 205 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 206 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 207 } 208 209 #if NSATA > 0 210 /* 211 * probe drives on SATA controllers with standard SATA registers: 212 * bring the PHYs online, read the drive signature and set drive flags 213 * appropriately. 214 */ 215 void 216 wdc_sataprobe(struct ata_channel *chp) 217 { 218 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 219 uint16_t scnt, sn, cl, ch; 220 int i, s; 221 222 /* XXX This should be done by other code. */ 223 for (i = 0; i < chp->ch_ndrive; i++) { 224 chp->ch_drive[i].chnl_softc = chp; 225 chp->ch_drive[i].drive = i; 226 } 227 228 /* reset the PHY and bring online */ 229 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 230 wdr->sata_status)) { 231 case SStatus_DET_DEV: 232 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 233 WDSD_IBM); 234 delay(10); /* 400ns delay */ 235 scnt = bus_space_read_2(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_seccnt], 0); 237 sn = bus_space_read_2(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_sector], 0); 239 cl = bus_space_read_2(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_lo], 0); 241 ch = bus_space_read_2(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_hi], 0); 243 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 244 "cl=0x%x ch=0x%x\n", 245 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 246 scnt, sn, cl, ch), DEBUG_PROBE); 247 /* 248 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 s = splbio(); 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 254 else 255 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 256 splx(s); 257 258 /* 259 * issue a reset in case only the interface part of the drive 260 * is up 261 */ 262 if (wdcreset(chp, RESET_SLEEP) != 0) 263 chp->ch_drive[0].drive_flags = 0; 264 break; 265 266 default: 267 break; 268 } 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, s; 296 297 if (wdcprobe1(chp, 0) == 0) { 298 /* No drives, abort the attach here. */ 299 return; 300 } 301 302 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 303 for (i = 0; i < mstohz(3000); i++) { 304 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 305 if (wdc->select) 306 wdc->select(chp,0); 307 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 308 0, WDSD_IBM); 309 delay(10); /* 400ns delay */ 310 st0 = bus_space_read_1(wdr->cmd_iot, 311 wdr->cmd_iohs[wd_status], 0); 312 } 313 314 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 315 if (wdc->select) 316 wdc->select(chp,1); 317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 318 0, WDSD_IBM | 0x10); 319 delay(10); /* 400ns delay */ 320 st1 = bus_space_read_1(wdr->cmd_iot, 321 wdr->cmd_iohs[wd_status], 0); 322 } 323 324 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 325 == 0 || 326 (st0 & WDCS_DRDY)) && 327 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 328 == 0 || 329 (st1 & WDCS_DRDY))) 330 break; 331 tsleep(¶ms, PRIBIO, "atadrdy", 1); 332 } 333 s = splbio(); 334 if ((st0 & WDCS_DRDY) == 0) 335 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 336 if ((st1 & WDCS_DRDY) == 0) 337 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 338 splx(s); 339 340 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 341 atac->atac_dev.dv_xname, 342 chp->ch_channel, st0, st1), DEBUG_PROBE); 343 344 /* Wait a bit, some devices are weird just after a reset. */ 345 delay(5000); 346 347 for (i = 0; i < chp->ch_ndrive; i++) { 348 /* XXX This should be done by other code. */ 349 chp->ch_drive[i].chnl_softc = chp; 350 chp->ch_drive[i].drive = i; 351 352 #if NATA_DMA 353 /* 354 * Init error counter so that an error withing the first xfers 355 * will trigger a downgrade 356 */ 357 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 358 #endif 359 360 /* If controller can't do 16bit flag the drives as 32bit */ 361 if ((atac->atac_cap & 362 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 363 s = splbio(); 364 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 365 splx(s); 366 } 367 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 368 continue; 369 370 /* Shortcut in case we've been shutdown */ 371 if (chp->ch_flags & ATACH_SHUTDOWN) 372 return; 373 374 /* 375 * Issue an identify, to try to detect ghosts. 376 * Note that we can't use interrupts here, because if there 377 * is no devices, we will get a command aborted without 378 * interrupts. 379 */ 380 error = ata_get_params(&chp->ch_drive[i], 381 AT_WAIT | AT_POLL, ¶ms); 382 if (error != CMD_OK) { 383 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 384 385 /* Shortcut in case we've been shutdown */ 386 if (chp->ch_flags & ATACH_SHUTDOWN) 387 return; 388 389 error = ata_get_params(&chp->ch_drive[i], 390 AT_WAIT | AT_POLL, ¶ms); 391 } 392 if (error == CMD_OK) { 393 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 394 s = splbio(); 395 for (j = 0; j < chp->ch_ndrive; j++) 396 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 397 splx(s); 398 } else { 399 s = splbio(); 400 chp->ch_drive[i].drive_flags &= 401 ~(DRIVE_ATA | DRIVE_ATAPI); 402 splx(s); 403 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 404 atac->atac_dev.dv_xname, 405 chp->ch_channel, i, error), DEBUG_PROBE); 406 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 407 continue; 408 /* 409 * Pre-ATA drive ? 410 * Test registers writability (Error register not 411 * writable, but cyllo is), then try an ATA command. 412 */ 413 if (wdc->select) 414 wdc->select(chp,i); 415 bus_space_write_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 417 delay(10); /* 400ns delay */ 418 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 419 0, 0x58); 420 bus_space_write_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 422 if (bus_space_read_1(wdr->cmd_iot, 423 wdr->cmd_iohs[wd_error], 0) == 0x58 || 424 bus_space_read_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 426 ATADEBUG_PRINT(("%s:%d:%d: register " 427 "writability failed\n", 428 atac->atac_dev.dv_xname, 429 chp->ch_channel, i), DEBUG_PROBE); 430 s = splbio(); 431 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 432 splx(s); 433 continue; 434 } 435 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 436 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 437 atac->atac_dev.dv_xname, 438 chp->ch_channel, i), DEBUG_PROBE); 439 s = splbio(); 440 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 441 splx(s); 442 continue; 443 } 444 bus_space_write_1(wdr->cmd_iot, 445 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 446 delay(10); /* 400ns delay */ 447 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 448 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 449 atac->atac_dev.dv_xname, 450 chp->ch_channel, i), DEBUG_PROBE); 451 s = splbio(); 452 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 453 splx(s); 454 } else { 455 s = splbio(); 456 for (j = 0; j < chp->ch_ndrive; j++) 457 chp->ch_drive[j].drive_flags &= 458 ~(DRIVE_ATA | DRIVE_ATAPI); 459 splx(s); 460 } 461 } 462 } 463 } 464 465 int 466 wdcprobe(struct ata_channel *chp) 467 { 468 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 469 /* default reset method */ 470 if (wdc->reset == NULL) 471 wdc->reset = wdc_do_reset; 472 473 return (wdcprobe1(chp, 1)); 474 } 475 476 static int 477 wdcprobe1(struct ata_channel *chp, int poll) 478 { 479 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 480 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 481 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 482 u_int8_t ret_value = 0x03; 483 u_int8_t drive; 484 int s; 485 /* XXX if poll, wdc_probe_count is 0. */ 486 int wdc_probe_count = 487 poll ? (WDC_PROBE_WAIT / WDCDELAY) 488 : (WDC_PROBE_WAIT * hz); 489 490 /* 491 * Sanity check to see if the wdc channel responds at all. 492 */ 493 494 s = splbio(); 495 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 496 while (wdc_probe_count-- > 0) { 497 if (wdc->select) 498 wdc->select(chp,0); 499 500 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 501 0, WDSD_IBM); 502 delay(10); /* 400ns delay */ 503 st0 = bus_space_read_1(wdr->cmd_iot, 504 wdr->cmd_iohs[wd_status], 0); 505 506 if (wdc->select) 507 wdc->select(chp,1); 508 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM | 0x10); 511 delay(10); /* 400ns delay */ 512 st1 = bus_space_read_1(wdr->cmd_iot, 513 wdr->cmd_iohs[wd_status], 0); 514 if ((st0 & WDCS_BSY) == 0) 515 break; 516 } 517 518 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 519 chp->ch_atac->atac_dev.dv_xname, 520 chp->ch_channel, st0, st1), DEBUG_PROBE); 521 522 if (st0 == 0xff || st0 == WDSD_IBM) 523 ret_value &= ~0x01; 524 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 525 ret_value &= ~0x02; 526 /* Register writability test, drive 0. */ 527 if (ret_value & 0x01) { 528 if (wdc->select) 529 wdc->select(chp,0); 530 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 531 0, WDSD_IBM); 532 bus_space_write_1(wdr->cmd_iot, 533 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 534 cl = bus_space_read_1(wdr->cmd_iot, 535 wdr->cmd_iohs[wd_cyl_lo], 0); 536 if (cl != 0x02) { 537 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 538 "got 0x%x != 0x02\n", 539 chp->ch_atac->atac_dev.dv_xname, 540 chp->ch_channel, cl), 541 DEBUG_PROBE); 542 ret_value &= ~0x01; 543 } 544 bus_space_write_1(wdr->cmd_iot, 545 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 546 cl = bus_space_read_1(wdr->cmd_iot, 547 wdr->cmd_iohs[wd_cyl_lo], 0); 548 if (cl != 0x01) { 549 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 550 "got 0x%x != 0x01\n", 551 chp->ch_atac->atac_dev.dv_xname, 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(wdr->cmd_iot, 557 wdr->cmd_iohs[wd_sector], 0, 0x01); 558 cl = bus_space_read_1(wdr->cmd_iot, 559 wdr->cmd_iohs[wd_sector], 0); 560 if (cl != 0x01) { 561 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 562 "got 0x%x != 0x01\n", 563 chp->ch_atac->atac_dev.dv_xname, 564 chp->ch_channel, cl), 565 DEBUG_PROBE); 566 ret_value &= ~0x01; 567 } 568 bus_space_write_1(wdr->cmd_iot, 569 wdr->cmd_iohs[wd_sector], 0, 0x02); 570 cl = bus_space_read_1(wdr->cmd_iot, 571 wdr->cmd_iohs[wd_sector], 0); 572 if (cl != 0x02) { 573 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 574 "got 0x%x != 0x02\n", 575 chp->ch_atac->atac_dev.dv_xname, 576 chp->ch_channel, cl), 577 DEBUG_PROBE); 578 ret_value &= ~0x01; 579 } 580 cl = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_cyl_lo], 0); 582 if (cl != 0x01) { 583 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 584 "got 0x%x != 0x01\n", 585 chp->ch_atac->atac_dev.dv_xname, 586 chp->ch_channel, cl), 587 DEBUG_PROBE); 588 ret_value &= ~0x01; 589 } 590 } 591 /* Register writability test, drive 1. */ 592 if (ret_value & 0x02) { 593 if (wdc->select) 594 wdc->select(chp,1); 595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 596 0, WDSD_IBM | 0x10); 597 bus_space_write_1(wdr->cmd_iot, 598 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_lo], 0); 601 if (cl != 0x02) { 602 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 603 "got 0x%x != 0x02\n", 604 chp->ch_atac->atac_dev.dv_xname, 605 chp->ch_channel, cl), 606 DEBUG_PROBE); 607 ret_value &= ~0x02; 608 } 609 bus_space_write_1(wdr->cmd_iot, 610 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 611 cl = bus_space_read_1(wdr->cmd_iot, 612 wdr->cmd_iohs[wd_cyl_lo], 0); 613 if (cl != 0x01) { 614 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 615 "got 0x%x != 0x01\n", 616 chp->ch_atac->atac_dev.dv_xname, 617 chp->ch_channel, cl), 618 DEBUG_PROBE); 619 ret_value &= ~0x02; 620 } 621 bus_space_write_1(wdr->cmd_iot, 622 wdr->cmd_iohs[wd_sector], 0, 0x01); 623 cl = bus_space_read_1(wdr->cmd_iot, 624 wdr->cmd_iohs[wd_sector], 0); 625 if (cl != 0x01) { 626 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 627 "got 0x%x != 0x01\n", 628 chp->ch_atac->atac_dev.dv_xname, 629 chp->ch_channel, cl), 630 DEBUG_PROBE); 631 ret_value &= ~0x02; 632 } 633 bus_space_write_1(wdr->cmd_iot, 634 wdr->cmd_iohs[wd_sector], 0, 0x02); 635 cl = bus_space_read_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_sector], 0); 637 if (cl != 0x02) { 638 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 639 "got 0x%x != 0x02\n", 640 chp->ch_atac->atac_dev.dv_xname, 641 chp->ch_channel, cl), 642 DEBUG_PROBE); 643 ret_value &= ~0x02; 644 } 645 cl = bus_space_read_1(wdr->cmd_iot, 646 wdr->cmd_iohs[wd_cyl_lo], 0); 647 if (cl != 0x01) { 648 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 649 "got 0x%x != 0x01\n", 650 chp->ch_atac->atac_dev.dv_xname, 651 chp->ch_channel, cl), 652 DEBUG_PROBE); 653 ret_value &= ~0x02; 654 } 655 } 656 657 if (ret_value == 0) { 658 splx(s); 659 return 0; 660 } 661 } 662 663 664 #if 0 /* XXX this break some ATA or ATAPI devices */ 665 /* 666 * reset bus. Also send an ATAPI_RESET to devices, in case there are 667 * ATAPI device out there which don't react to the bus reset 668 */ 669 if (ret_value & 0x01) { 670 if (wdc->select) 671 wdc->select(chp,0); 672 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 673 0, WDSD_IBM); 674 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 675 ATAPI_SOFT_RESET); 676 } 677 if (ret_value & 0x02) { 678 if (wdc->select) 679 wdc->select(chp,0); 680 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 681 0, WDSD_IBM | 0x10); 682 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 683 ATAPI_SOFT_RESET); 684 } 685 686 delay(5000); 687 #endif 688 689 wdc->reset(chp, RESET_POLL); 690 DELAY(2000); 691 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 692 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 693 splx(s); 694 695 ret_value = __wdcwait_reset(chp, ret_value, poll); 696 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 697 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 698 ret_value), DEBUG_PROBE); 699 700 /* if reset failed, there's nothing here */ 701 if (ret_value == 0) 702 return 0; 703 704 /* 705 * Test presence of drives. First test register signatures looking 706 * for ATAPI devices. If it's not an ATAPI and reset said there may 707 * be something here assume it's ATA or OLD. Ghost will be killed 708 * later in attach routine. 709 */ 710 for (drive = 0; drive < chp->ch_ndrive; drive++) { 711 if ((ret_value & (0x01 << drive)) == 0) 712 continue; 713 if (wdc->select) 714 wdc->select(chp,drive); 715 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 716 WDSD_IBM | (drive << 4)); 717 delay(10); /* 400ns delay */ 718 /* Save registers contents */ 719 sc = bus_space_read_1(wdr->cmd_iot, 720 wdr->cmd_iohs[wd_seccnt], 0); 721 sn = bus_space_read_1(wdr->cmd_iot, 722 wdr->cmd_iohs[wd_sector], 0); 723 cl = bus_space_read_1(wdr->cmd_iot, 724 wdr->cmd_iohs[wd_cyl_lo], 0); 725 ch = bus_space_read_1(wdr->cmd_iot, 726 wdr->cmd_iohs[wd_cyl_hi], 0); 727 728 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 729 "cl=0x%x ch=0x%x\n", 730 chp->ch_atac->atac_dev.dv_xname, 731 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 732 /* 733 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 734 * we get wrong values here, so ignore it. 735 */ 736 s = splbio(); 737 if (cl == 0x14 && ch == 0xeb) { 738 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 739 } else { 740 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 741 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 742 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 743 } 744 splx(s); 745 } 746 return (ret_value); 747 } 748 749 void 750 wdcattach(struct ata_channel *chp) 751 { 752 struct atac_softc *atac = chp->ch_atac; 753 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 754 755 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 756 757 /* default data transfer methods */ 758 if (wdc->datain_pio == NULL) 759 wdc->datain_pio = wdc_datain_pio; 760 if (wdc->dataout_pio == NULL) 761 wdc->dataout_pio = wdc_dataout_pio; 762 /* default reset method */ 763 if (wdc->reset == NULL) 764 wdc->reset = wdc_do_reset; 765 766 /* initialise global data */ 767 if (atac->atac_bustype_ata == NULL) 768 atac->atac_bustype_ata = &wdc_ata_bustype; 769 if (atac->atac_probe == NULL) 770 atac->atac_probe = wdc_drvprobe; 771 #if NATAPIBUS > 0 772 if (atac->atac_atapibus_attach == NULL) 773 atac->atac_atapibus_attach = wdc_atapibus_attach; 774 #endif 775 776 ata_channel_attach(chp); 777 } 778 779 int 780 wdcactivate(device_t self, enum devact act) 781 { 782 struct atac_softc *atac = device_private(self); 783 struct ata_channel *chp; 784 int s, i, error = 0; 785 786 s = splbio(); 787 switch (act) { 788 case DVACT_ACTIVATE: 789 error = EOPNOTSUPP; 790 break; 791 792 case DVACT_DEACTIVATE: 793 for (i = 0; i < atac->atac_nchannels; i++) { 794 chp = atac->atac_channels[i]; 795 if (chp->atabus == NULL) 796 continue; 797 error = config_deactivate(chp->atabus); 798 if (error) 799 break; 800 } 801 break; 802 } 803 splx(s); 804 return (error); 805 } 806 807 void 808 wdc_childdetached(device_t self, device_t child) 809 { 810 struct atac_softc *atac = device_private(self); 811 struct ata_channel *chp; 812 int i; 813 814 for (i = 0; i < atac->atac_nchannels; i++) { 815 chp = atac->atac_channels[i]; 816 if (child == chp->atabus) { 817 chp->atabus = NULL; 818 return; 819 } 820 } 821 } 822 823 int 824 wdcdetach(device_t self, int flags) 825 { 826 struct atac_softc *atac = device_private(self); 827 struct ata_channel *chp; 828 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 829 int i, error = 0; 830 831 for (i = 0; i < atac->atac_nchannels; i++) { 832 chp = atac->atac_channels[i]; 833 if (chp->atabus == NULL) 834 continue; 835 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 836 atac->atac_dev.dv_xname, chp->atabus->dv_xname), 837 DEBUG_DETACH); 838 if ((error = config_detach(chp->atabus, flags)) != 0) 839 return error; 840 } 841 if (adapt->adapt_refcnt != 0) { 842 #ifdef DIAGNOSTIC 843 printf("wdcdetach: refcnt should be 0 here??\n"); 844 #endif 845 (void) (*adapt->adapt_enable)(&atac->atac_dev, 0); 846 } 847 return 0; 848 } 849 850 /* restart an interrupted I/O */ 851 void 852 wdcrestart(void *v) 853 { 854 struct ata_channel *chp = v; 855 int s; 856 857 s = splbio(); 858 atastart(chp); 859 splx(s); 860 } 861 862 863 /* 864 * Interrupt routine for the controller. Acknowledge the interrupt, check for 865 * errors on the current operation, mark it done if necessary, and start the 866 * next request. Also check for a partially done transfer, and continue with 867 * the next chunk if so. 868 */ 869 int 870 wdcintr(void *arg) 871 { 872 struct ata_channel *chp = arg; 873 struct atac_softc *atac = chp->ch_atac; 874 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 875 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 876 struct ata_xfer *xfer; 877 int ret; 878 879 if (!device_is_active(&atac->atac_dev)) { 880 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 881 DEBUG_INTR); 882 return (0); 883 } 884 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 885 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 886 /* try to clear the pending interrupt anyway */ 887 (void)bus_space_read_1(wdr->cmd_iot, 888 wdr->cmd_iohs[wd_status], 0); 889 return (0); 890 } 891 892 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 893 xfer = chp->ch_queue->active_xfer; 894 #ifdef DIAGNOSTIC 895 if (xfer == NULL) 896 panic("wdcintr: no xfer"); 897 if (xfer->c_chp != chp) { 898 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 899 chp->ch_channel); 900 panic("wdcintr: wrong channel"); 901 } 902 #endif 903 #if NATA_DMA || NATA_PIOBM 904 if (chp->ch_flags & ATACH_DMA_WAIT) { 905 wdc->dma_status = 906 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 907 xfer->c_drive, WDC_DMAEND_END); 908 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 909 /* IRQ not for us, not detected by DMA engine */ 910 return 0; 911 } 912 chp->ch_flags &= ~ATACH_DMA_WAIT; 913 } 914 #endif 915 chp->ch_flags &= ~ATACH_IRQ_WAIT; 916 ret = xfer->c_intr(chp, xfer, 1); 917 if (ret == 0) /* irq was not for us, still waiting for irq */ 918 chp->ch_flags |= ATACH_IRQ_WAIT; 919 return (ret); 920 } 921 922 /* Put all disk in RESET state */ 923 void 924 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 925 { 926 struct ata_channel *chp = drvp->chnl_softc; 927 928 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 929 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 930 DEBUG_FUNCS); 931 932 ata_reset_channel(chp, flags); 933 } 934 935 void 936 wdc_reset_channel(struct ata_channel *chp, int flags) 937 { 938 TAILQ_HEAD(, ata_xfer) reset_xfer; 939 struct ata_xfer *xfer, *next_xfer; 940 #if NATA_DMA || NATA_PIOBM 941 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 942 #endif 943 944 TAILQ_INIT(&reset_xfer); 945 946 chp->ch_flags &= ~ATACH_IRQ_WAIT; 947 948 /* 949 * if the current command if on an ATAPI device, issue a 950 * ATAPI_SOFT_RESET 951 */ 952 xfer = chp->ch_queue->active_xfer; 953 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 954 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 955 if (flags & AT_WAIT) 956 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 957 else 958 delay(1000); 959 } 960 961 /* reset the channel */ 962 if (flags & AT_WAIT) 963 (void) wdcreset(chp, RESET_SLEEP); 964 else 965 (void) wdcreset(chp, RESET_POLL); 966 967 /* 968 * wait a bit after reset; in case the DMA engines needs some time 969 * to recover. 970 */ 971 if (flags & AT_WAIT) 972 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 973 else 974 delay(1000); 975 /* 976 * look for pending xfers. If we have a shared queue, we'll also reset 977 * the other channel if the current xfer is running on it. 978 * Then we'll dequeue only the xfers for this channel. 979 */ 980 if ((flags & AT_RST_NOCMD) == 0) { 981 /* 982 * move all xfers queued for this channel to the reset queue, 983 * and then process the current xfer and then the reset queue. 984 * We have to use a temporary queue because c_kill_xfer() 985 * may requeue commands. 986 */ 987 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 988 xfer != NULL; xfer = next_xfer) { 989 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 990 if (xfer->c_chp != chp) 991 continue; 992 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 993 xfer, c_xferchain); 994 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 995 } 996 xfer = chp->ch_queue->active_xfer; 997 if (xfer) { 998 if (xfer->c_chp != chp) 999 ata_reset_channel(xfer->c_chp, flags); 1000 else { 1001 callout_stop(&chp->ch_callout); 1002 #if NATA_DMA || NATA_PIOBM 1003 /* 1004 * If we're waiting for DMA, stop the 1005 * DMA engine 1006 */ 1007 if (chp->ch_flags & ATACH_DMA_WAIT) { 1008 (*wdc->dma_finish)( 1009 wdc->dma_arg, 1010 chp->ch_channel, 1011 xfer->c_drive, 1012 WDC_DMAEND_ABRT_QUIET); 1013 chp->ch_flags &= ~ATACH_DMA_WAIT; 1014 } 1015 #endif 1016 chp->ch_queue->active_xfer = NULL; 1017 if ((flags & AT_RST_EMERG) == 0) 1018 xfer->c_kill_xfer( 1019 chp, xfer, KILL_RESET); 1020 } 1021 } 1022 1023 for (xfer = TAILQ_FIRST(&reset_xfer); 1024 xfer != NULL; xfer = next_xfer) { 1025 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1026 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1027 if ((flags & AT_RST_EMERG) == 0) 1028 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1029 } 1030 } 1031 } 1032 1033 static int 1034 wdcreset(struct ata_channel *chp, int poll) 1035 { 1036 struct atac_softc *atac = chp->ch_atac; 1037 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1038 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1039 int drv_mask1, drv_mask2; 1040 1041 wdc->reset(chp, poll); 1042 1043 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1044 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1045 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1046 (poll == RESET_SLEEP) ? 0 : 1); 1047 if (drv_mask2 != drv_mask1) { 1048 printf("%s channel %d: reset failed for", 1049 atac->atac_dev.dv_xname, chp->ch_channel); 1050 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1051 printf(" drive 0"); 1052 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1053 printf(" drive 1"); 1054 printf("\n"); 1055 } 1056 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1057 return (drv_mask1 != drv_mask2) ? 1 : 0; 1058 } 1059 1060 void 1061 wdc_do_reset(struct ata_channel *chp, int poll) 1062 { 1063 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1064 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1065 int s = 0; 1066 1067 if (poll != RESET_SLEEP) 1068 s = splbio(); 1069 if (wdc->select) 1070 wdc->select(chp,0); 1071 /* master */ 1072 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1073 delay(10); /* 400ns delay */ 1074 /* assert SRST, wait for reset to complete */ 1075 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1076 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1077 delay(2000); 1078 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1079 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1080 WDCTL_4BIT | WDCTL_IDS); 1081 delay(10); /* 400ns delay */ 1082 if (poll != RESET_SLEEP) { 1083 /* ACK interrupt in case there is one pending left */ 1084 if (wdc->irqack) 1085 wdc->irqack(chp); 1086 splx(s); 1087 } 1088 } 1089 1090 static int 1091 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1092 { 1093 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1094 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1095 int timeout, nloop; 1096 u_int8_t st0 = 0, st1 = 0; 1097 #ifdef ATADEBUG 1098 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1099 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1100 #endif 1101 1102 if (poll) 1103 nloop = WDCNDELAY_RST; 1104 else 1105 nloop = WDC_RESET_WAIT * hz / 1000; 1106 /* wait for BSY to deassert */ 1107 for (timeout = 0; timeout < nloop; timeout++) { 1108 if ((drv_mask & 0x01) != 0) { 1109 if (wdc->select) 1110 wdc->select(chp,0); 1111 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1112 0, WDSD_IBM); /* master */ 1113 delay(10); 1114 st0 = bus_space_read_1(wdr->cmd_iot, 1115 wdr->cmd_iohs[wd_status], 0); 1116 #ifdef ATADEBUG 1117 sc0 = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_seccnt], 0); 1119 sn0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_sector], 0); 1121 cl0 = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_cyl_lo], 0); 1123 ch0 = bus_space_read_1(wdr->cmd_iot, 1124 wdr->cmd_iohs[wd_cyl_hi], 0); 1125 #endif 1126 } 1127 if ((drv_mask & 0x02) != 0) { 1128 if (wdc->select) 1129 wdc->select(chp,1); 1130 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1131 0, WDSD_IBM | 0x10); /* slave */ 1132 delay(10); 1133 st1 = bus_space_read_1(wdr->cmd_iot, 1134 wdr->cmd_iohs[wd_status], 0); 1135 #ifdef ATADEBUG 1136 sc1 = bus_space_read_1(wdr->cmd_iot, 1137 wdr->cmd_iohs[wd_seccnt], 0); 1138 sn1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_sector], 0); 1140 cl1 = bus_space_read_1(wdr->cmd_iot, 1141 wdr->cmd_iohs[wd_cyl_lo], 0); 1142 ch1 = bus_space_read_1(wdr->cmd_iot, 1143 wdr->cmd_iohs[wd_cyl_hi], 0); 1144 #endif 1145 } 1146 1147 if ((drv_mask & 0x01) == 0) { 1148 /* no master */ 1149 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1150 /* No master, slave is ready, it's done */ 1151 goto end; 1152 } 1153 if ((drv_mask & 0x02) == 0) { 1154 /* No master, no slave: it's done */ 1155 goto end; 1156 } 1157 } else if ((drv_mask & 0x02) == 0) { 1158 /* no slave */ 1159 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1160 /* No slave, master is ready, it's done */ 1161 goto end; 1162 } 1163 } else { 1164 /* Wait for both master and slave to be ready */ 1165 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1166 goto end; 1167 } 1168 } 1169 if (poll) 1170 delay(WDCDELAY); 1171 else 1172 tsleep(&nloop, PRIBIO, "atarst", 1); 1173 } 1174 /* Reset timed out. Maybe it's because drv_mask was not right */ 1175 if (st0 & WDCS_BSY) 1176 drv_mask &= ~0x01; 1177 if (st1 & WDCS_BSY) 1178 drv_mask &= ~0x02; 1179 end: 1180 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1181 "cl=0x%x ch=0x%x\n", 1182 chp->ch_atac->atac_dev.dv_xname, 1183 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1184 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1185 "cl=0x%x ch=0x%x\n", 1186 chp->ch_atac->atac_dev.dv_xname, 1187 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1188 1189 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1190 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1191 st0, st1), DEBUG_PROBE); 1192 1193 return drv_mask; 1194 } 1195 1196 /* 1197 * Wait for a drive to be !BSY, and have mask in its status register. 1198 * return -1 for a timeout after "timeout" ms. 1199 */ 1200 static int 1201 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1202 { 1203 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1204 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1205 u_char status; 1206 int xtime = 0; 1207 1208 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1209 chp->ch_atac->atac_dev.dv_xname, 1210 chp->ch_channel), DEBUG_STATUS); 1211 chp->ch_error = 0; 1212 1213 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1214 1215 for (;;) { 1216 chp->ch_status = status = 1217 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1218 if ((status & (WDCS_BSY | mask)) == bits) 1219 break; 1220 if (++xtime > timeout) { 1221 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1222 "status %x error %x (mask 0x%x bits 0x%x)\n", 1223 xtime, status, 1224 bus_space_read_1(wdr->cmd_iot, 1225 wdr->cmd_iohs[wd_error], 0), mask, bits), 1226 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1227 return(WDCWAIT_TOUT); 1228 } 1229 delay(WDCDELAY); 1230 } 1231 #ifdef ATADEBUG 1232 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1233 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1234 #endif 1235 if (status & WDCS_ERR) 1236 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1237 wdr->cmd_iohs[wd_error], 0); 1238 #ifdef WDCNDELAY_DEBUG 1239 /* After autoconfig, there should be no long delays. */ 1240 if (!cold && xtime > WDCNDELAY_DEBUG) { 1241 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1242 if (xfer == NULL) 1243 printf("%s channel %d: warning: busy-wait took %dus\n", 1244 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1245 WDCDELAY * xtime); 1246 else 1247 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1248 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, 1249 xfer->c_drive, 1250 WDCDELAY * xtime); 1251 } 1252 #endif 1253 return(WDCWAIT_OK); 1254 } 1255 1256 /* 1257 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1258 * thread if possible 1259 */ 1260 int 1261 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1262 { 1263 int error, i, timeout_hz = mstohz(timeout); 1264 1265 if (timeout_hz == 0 || 1266 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1267 error = __wdcwait(chp, mask, bits, timeout); 1268 else { 1269 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1270 if (error != 0) { 1271 if ((chp->ch_flags & ATACH_TH_RUN) || 1272 (flags & AT_WAIT)) { 1273 /* 1274 * we're running in the channel thread 1275 * or some userland thread context 1276 */ 1277 for (i = 0; i < timeout_hz; i++) { 1278 if (__wdcwait(chp, mask, bits, 1279 WDCDELAY_POLL) == 0) { 1280 error = 0; 1281 break; 1282 } 1283 tsleep(&chp, PRIBIO, "atapoll", 1); 1284 } 1285 } else { 1286 /* 1287 * we're probably in interrupt context, 1288 * ask the thread to come back here 1289 */ 1290 #ifdef DIAGNOSTIC 1291 if (chp->ch_queue->queue_freeze > 0) 1292 panic("wdcwait: queue_freeze"); 1293 #endif 1294 chp->ch_queue->queue_freeze++; 1295 wakeup(&chp->ch_thread); 1296 return(WDCWAIT_THR); 1297 } 1298 } 1299 } 1300 return (error); 1301 } 1302 1303 1304 #if NATA_DMA 1305 /* 1306 * Busy-wait for DMA to complete 1307 */ 1308 int 1309 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1310 { 1311 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1312 int xtime; 1313 1314 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1315 wdc->dma_status = 1316 (*wdc->dma_finish)(wdc->dma_arg, 1317 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1318 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1319 return 0; 1320 delay(WDCDELAY); 1321 } 1322 /* timeout, force a DMA halt */ 1323 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1324 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1325 return 1; 1326 } 1327 #endif 1328 1329 void 1330 wdctimeout(void *arg) 1331 { 1332 struct ata_channel *chp = (struct ata_channel *)arg; 1333 #if NATA_DMA || NATA_PIOBM 1334 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1335 #endif 1336 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1337 int s; 1338 1339 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1340 1341 s = splbio(); 1342 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1343 __wdcerror(chp, "lost interrupt"); 1344 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1345 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1346 xfer->c_bcount, 1347 xfer->c_skip); 1348 #if NATA_DMA || NATA_PIOBM 1349 if (chp->ch_flags & ATACH_DMA_WAIT) { 1350 wdc->dma_status = 1351 (*wdc->dma_finish)(wdc->dma_arg, 1352 chp->ch_channel, xfer->c_drive, 1353 WDC_DMAEND_ABRT); 1354 chp->ch_flags &= ~ATACH_DMA_WAIT; 1355 } 1356 #endif 1357 /* 1358 * Call the interrupt routine. If we just missed an interrupt, 1359 * it will do what's needed. Else, it will take the needed 1360 * action (reset the device). 1361 * Before that we need to reinstall the timeout callback, 1362 * in case it will miss another irq while in this transfer 1363 * We arbitray chose it to be 1s 1364 */ 1365 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1366 xfer->c_flags |= C_TIMEOU; 1367 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1368 xfer->c_intr(chp, xfer, 1); 1369 } else 1370 __wdcerror(chp, "missing untimeout"); 1371 splx(s); 1372 } 1373 1374 int 1375 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1376 { 1377 struct ata_channel *chp = drvp->chnl_softc; 1378 struct ata_xfer *xfer; 1379 int s, ret; 1380 1381 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1382 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drvp->drive), 1383 DEBUG_FUNCS); 1384 1385 /* set up an xfer and queue. Wait for completion */ 1386 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1387 ATAXF_NOSLEEP); 1388 if (xfer == NULL) { 1389 return ATACMD_TRY_AGAIN; 1390 } 1391 1392 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1393 ata_c->flags |= AT_POLL; 1394 if (ata_c->flags & AT_POLL) 1395 xfer->c_flags |= C_POLL; 1396 if (ata_c->flags & AT_WAIT) 1397 xfer->c_flags |= C_WAIT; 1398 xfer->c_drive = drvp->drive; 1399 xfer->c_databuf = ata_c->data; 1400 xfer->c_bcount = ata_c->bcount; 1401 xfer->c_cmd = ata_c; 1402 xfer->c_start = __wdccommand_start; 1403 xfer->c_intr = __wdccommand_intr; 1404 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1405 1406 s = splbio(); 1407 ata_exec_xfer(chp, xfer); 1408 #ifdef DIAGNOSTIC 1409 if ((ata_c->flags & AT_POLL) != 0 && 1410 (ata_c->flags & AT_DONE) == 0) 1411 panic("wdc_exec_command: polled command not done"); 1412 #endif 1413 if (ata_c->flags & AT_DONE) { 1414 ret = ATACMD_COMPLETE; 1415 } else { 1416 if (ata_c->flags & AT_WAIT) { 1417 while ((ata_c->flags & AT_DONE) == 0) { 1418 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1419 } 1420 ret = ATACMD_COMPLETE; 1421 } else { 1422 ret = ATACMD_QUEUED; 1423 } 1424 } 1425 splx(s); 1426 return ret; 1427 } 1428 1429 static void 1430 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1431 { 1432 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1433 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1434 int drive = xfer->c_drive; 1435 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1436 struct ata_command *ata_c = xfer->c_cmd; 1437 1438 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1439 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1440 DEBUG_FUNCS); 1441 1442 if (wdc->select) 1443 wdc->select(chp,drive); 1444 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1445 WDSD_IBM | (drive << 4)); 1446 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1447 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1448 case WDCWAIT_OK: 1449 break; 1450 case WDCWAIT_TOUT: 1451 ata_c->flags |= AT_TIMEOU; 1452 __wdccommand_done(chp, xfer); 1453 return; 1454 case WDCWAIT_THR: 1455 return; 1456 } 1457 if (ata_c->flags & AT_POLL) { 1458 /* polled command, disable interrupts */ 1459 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1460 WDCTL_4BIT | WDCTL_IDS); 1461 } 1462 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1463 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1464 1465 if ((ata_c->flags & AT_POLL) == 0) { 1466 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1467 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1468 wdctimeout, chp); 1469 return; 1470 } 1471 /* 1472 * Polled command. Wait for drive ready or drq. Done in intr(). 1473 * Wait for at last 400ns for status bit to be valid. 1474 */ 1475 delay(10); /* 400ns delay */ 1476 __wdccommand_intr(chp, xfer, 0); 1477 } 1478 1479 static int 1480 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1481 { 1482 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1483 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1484 struct ata_command *ata_c = xfer->c_cmd; 1485 int bcount = ata_c->bcount; 1486 char *data = ata_c->data; 1487 int wflags; 1488 int drive_flags; 1489 1490 if (ata_c->r_command == WDCC_IDENTIFY || 1491 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1492 /* 1493 * The IDENTIFY data has been designed as an array of 1494 * u_int16_t, so we can byteswap it on the fly. 1495 * Historically it's what we have always done so keeping it 1496 * here ensure binary backward compatibility. 1497 */ 1498 drive_flags = DRIVE_NOSTREAM | 1499 chp->ch_drive[xfer->c_drive].drive_flags; 1500 } else { 1501 /* 1502 * Other data structure are opaque and should be transfered 1503 * as is. 1504 */ 1505 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1506 } 1507 1508 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1509 /* both wait and poll, we can tsleep here */ 1510 wflags = AT_WAIT | AT_POLL; 1511 } else { 1512 wflags = AT_POLL; 1513 } 1514 1515 again: 1516 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1517 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1518 DEBUG_INTR); 1519 /* 1520 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1521 * Reselect again, it doesn't hurt for others commands, and the time 1522 * penalty for the extra regiter write is acceptable, 1523 * wdc_exec_command() isn't called often (mosly for autoconfig) 1524 */ 1525 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1526 WDSD_IBM | (xfer->c_drive << 4)); 1527 if ((ata_c->flags & AT_XFDONE) != 0) { 1528 /* 1529 * We have completed a data xfer. The drive should now be 1530 * in its initial state 1531 */ 1532 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1533 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1534 wflags) == WDCWAIT_TOUT) { 1535 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1536 return 0; /* IRQ was not for us */ 1537 ata_c->flags |= AT_TIMEOU; 1538 } 1539 goto out; 1540 } 1541 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1542 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1543 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1544 return 0; /* IRQ was not for us */ 1545 ata_c->flags |= AT_TIMEOU; 1546 goto out; 1547 } 1548 if (wdc->irqack) 1549 wdc->irqack(chp); 1550 if (ata_c->flags & AT_READ) { 1551 if ((chp->ch_status & WDCS_DRQ) == 0) { 1552 ata_c->flags |= AT_TIMEOU; 1553 goto out; 1554 } 1555 wdc->datain_pio(chp, drive_flags, data, bcount); 1556 /* at this point the drive should be in its initial state */ 1557 ata_c->flags |= AT_XFDONE; 1558 /* 1559 * XXX checking the status register again here cause some 1560 * hardware to timeout. 1561 */ 1562 } else if (ata_c->flags & AT_WRITE) { 1563 if ((chp->ch_status & WDCS_DRQ) == 0) { 1564 ata_c->flags |= AT_TIMEOU; 1565 goto out; 1566 } 1567 wdc->dataout_pio(chp, drive_flags, data, bcount); 1568 ata_c->flags |= AT_XFDONE; 1569 if ((ata_c->flags & AT_POLL) == 0) { 1570 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1571 callout_reset(&chp->ch_callout, 1572 mstohz(ata_c->timeout), wdctimeout, chp); 1573 return 1; 1574 } else { 1575 goto again; 1576 } 1577 } 1578 out: 1579 __wdccommand_done(chp, xfer); 1580 return 1; 1581 } 1582 1583 static void 1584 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1585 { 1586 struct atac_softc *atac = chp->ch_atac; 1587 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1588 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1589 struct ata_command *ata_c = xfer->c_cmd; 1590 1591 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1592 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 1593 ata_c->flags), DEBUG_FUNCS); 1594 1595 1596 if (chp->ch_status & WDCS_DWF) 1597 ata_c->flags |= AT_DF; 1598 if (chp->ch_status & WDCS_ERR) { 1599 ata_c->flags |= AT_ERROR; 1600 ata_c->r_error = chp->ch_error; 1601 } 1602 if ((ata_c->flags & AT_READREG) != 0 && 1603 device_is_active(&atac->atac_dev) && 1604 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1605 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1606 wdr->cmd_iohs[wd_sdh], 0); 1607 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1608 wdr->cmd_iohs[wd_seccnt], 0); 1609 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1610 wdr->cmd_iohs[wd_sector], 0); 1611 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1612 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1613 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1614 wdr->cmd_iohs[wd_cyl_lo], 0); 1615 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1616 wdr->cmd_iohs[wd_error], 0); 1617 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1618 wdr->cmd_iohs[wd_features], 0); 1619 } 1620 callout_stop(&chp->ch_callout); 1621 chp->ch_queue->active_xfer = NULL; 1622 if (ata_c->flags & AT_POLL) { 1623 /* enable interrupts */ 1624 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1625 WDCTL_4BIT); 1626 delay(10); /* some drives need a little delay here */ 1627 } 1628 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1629 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1630 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1631 wakeup(&chp->ch_queue->active_xfer); 1632 } else 1633 __wdccommand_done_end(chp, xfer); 1634 } 1635 1636 static void 1637 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1638 { 1639 struct ata_command *ata_c = xfer->c_cmd; 1640 1641 ata_c->flags |= AT_DONE; 1642 ata_free_xfer(chp, xfer); 1643 if (ata_c->flags & AT_WAIT) 1644 wakeup(ata_c); 1645 else if (ata_c->callback) 1646 ata_c->callback(ata_c->callback_arg); 1647 atastart(chp); 1648 return; 1649 } 1650 1651 static void 1652 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1653 int reason) 1654 { 1655 struct ata_command *ata_c = xfer->c_cmd; 1656 1657 switch (reason) { 1658 case KILL_GONE: 1659 ata_c->flags |= AT_GONE; 1660 break; 1661 case KILL_RESET: 1662 ata_c->flags |= AT_RESET; 1663 break; 1664 default: 1665 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1666 reason); 1667 panic("__wdccommand_kill_xfer"); 1668 } 1669 __wdccommand_done_end(chp, xfer); 1670 } 1671 1672 /* 1673 * Send a command. The drive should be ready. 1674 * Assumes interrupts are blocked. 1675 */ 1676 void 1677 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1678 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1679 u_int8_t features) 1680 { 1681 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1682 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1683 1684 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1685 "sector=%d count=%d features=%d\n", chp->ch_atac->atac_dev.dv_xname, 1686 chp->ch_channel, drive, command, cylin, head, sector, count, 1687 features), DEBUG_FUNCS); 1688 1689 if (wdc->select) 1690 wdc->select(chp,drive); 1691 1692 /* Select drive, head, and addressing mode. */ 1693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1694 WDSD_IBM | (drive << 4) | head); 1695 /* Load parameters into the wd_features register. */ 1696 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1697 features); 1698 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1699 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1701 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1702 0, cylin >> 8); 1703 1704 /* Send command. */ 1705 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1706 return; 1707 } 1708 1709 /* 1710 * Send a 48-bit addressing command. The drive should be ready. 1711 * Assumes interrupts are blocked. 1712 */ 1713 void 1714 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1715 u_int64_t blkno, u_int16_t count) 1716 { 1717 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1718 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1719 1720 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1721 "count=%d\n", chp->ch_atac->atac_dev.dv_xname, 1722 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1723 DEBUG_FUNCS); 1724 1725 if (wdc->select) 1726 wdc->select(chp,drive); 1727 1728 /* Select drive, head, and addressing mode. */ 1729 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1730 (drive << 4) | WDSD_LBA); 1731 1732 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1733 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1734 0); 1735 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1736 0, count); 1737 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1738 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1739 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1740 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1741 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1742 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1743 } else { 1744 /* previous */ 1745 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1746 0); 1747 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1748 0, count >> 8); 1749 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1750 0, blkno >> 24); 1751 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1752 0, blkno >> 32); 1753 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1754 0, blkno >> 40); 1755 1756 /* current */ 1757 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1758 0); 1759 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1760 count); 1761 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1762 blkno); 1763 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1764 0, blkno >> 8); 1765 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1766 0, blkno >> 16); 1767 } 1768 1769 /* Send command. */ 1770 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1771 return; 1772 } 1773 1774 /* 1775 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1776 * tested by the caller. 1777 */ 1778 void 1779 wdccommandshort(struct ata_channel *chp, int drive, int command) 1780 { 1781 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1782 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1783 1784 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1785 chp->ch_atac->atac_dev.dv_xname, chp->ch_channel, drive, command), 1786 DEBUG_FUNCS); 1787 1788 if (wdc->select) 1789 wdc->select(chp,drive); 1790 1791 /* Select drive. */ 1792 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1793 WDSD_IBM | (drive << 4)); 1794 1795 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1796 } 1797 1798 static void 1799 __wdcerror(struct ata_channel *chp, const char *msg) 1800 { 1801 struct atac_softc *atac = chp->ch_atac; 1802 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1803 1804 if (xfer == NULL) 1805 printf("%s:%d: %s\n", atac->atac_dev.dv_xname, chp->ch_channel, 1806 msg); 1807 else 1808 printf("%s:%d:%d: %s\n", atac->atac_dev.dv_xname, 1809 chp->ch_channel, xfer->c_drive, msg); 1810 } 1811 1812 /* 1813 * the bit bucket 1814 */ 1815 void 1816 wdcbit_bucket(struct ata_channel *chp, int size) 1817 { 1818 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1819 1820 for (; size >= 2; size -= 2) 1821 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1822 if (size) 1823 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1824 } 1825 1826 static void 1827 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1828 { 1829 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1830 1831 #ifndef __NO_STRICT_ALIGNMENT 1832 if ((uintptr_t)bf & 1) 1833 goto unaligned; 1834 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1835 goto unaligned; 1836 #endif 1837 1838 if (flags & DRIVE_NOSTREAM) { 1839 if (flags & DRIVE_CAP32) { 1840 bus_space_read_multi_4(wdr->data32iot, 1841 wdr->data32ioh, 0, bf, len >> 2); 1842 bf = (char *)bf + (len & ~3); 1843 len &= 3; 1844 } 1845 if (len) { 1846 bus_space_read_multi_2(wdr->cmd_iot, 1847 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1848 } 1849 } else { 1850 if (flags & DRIVE_CAP32) { 1851 bus_space_read_multi_stream_4(wdr->data32iot, 1852 wdr->data32ioh, 0, bf, len >> 2); 1853 bf = (char *)bf + (len & ~3); 1854 len &= 3; 1855 } 1856 if (len) { 1857 bus_space_read_multi_stream_2(wdr->cmd_iot, 1858 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1859 } 1860 } 1861 return; 1862 1863 #ifndef __NO_STRICT_ALIGNMENT 1864 unaligned: 1865 if (flags & DRIVE_NOSTREAM) { 1866 if (flags & DRIVE_CAP32) { 1867 while (len > 3) { 1868 uint32_t val; 1869 1870 val = bus_space_read_4(wdr->data32iot, 1871 wdr->data32ioh, 0); 1872 memcpy(bf, &val, 4); 1873 bf = (char *)bf + 4; 1874 len -= 4; 1875 } 1876 } 1877 while (len > 1) { 1878 uint16_t val; 1879 1880 val = bus_space_read_2(wdr->cmd_iot, 1881 wdr->cmd_iohs[wd_data], 0); 1882 memcpy(bf, &val, 2); 1883 bf = (char *)bf + 2; 1884 len -= 2; 1885 } 1886 } else { 1887 if (flags & DRIVE_CAP32) { 1888 while (len > 3) { 1889 uint32_t val; 1890 1891 val = bus_space_read_stream_4(wdr->data32iot, 1892 wdr->data32ioh, 0); 1893 memcpy(bf, &val, 4); 1894 bf = (char *)bf + 4; 1895 len -= 4; 1896 } 1897 } 1898 while (len > 1) { 1899 uint16_t val; 1900 1901 val = bus_space_read_stream_2(wdr->cmd_iot, 1902 wdr->cmd_iohs[wd_data], 0); 1903 memcpy(bf, &val, 2); 1904 bf = (char *)bf + 2; 1905 len -= 2; 1906 } 1907 } 1908 #endif 1909 } 1910 1911 static void 1912 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1913 { 1914 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1915 1916 #ifndef __NO_STRICT_ALIGNMENT 1917 if ((uintptr_t)bf & 1) 1918 goto unaligned; 1919 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1920 goto unaligned; 1921 #endif 1922 1923 if (flags & DRIVE_NOSTREAM) { 1924 if (flags & DRIVE_CAP32) { 1925 bus_space_write_multi_4(wdr->data32iot, 1926 wdr->data32ioh, 0, bf, len >> 2); 1927 bf = (char *)bf + (len & ~3); 1928 len &= 3; 1929 } 1930 if (len) { 1931 bus_space_write_multi_2(wdr->cmd_iot, 1932 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1933 } 1934 } else { 1935 if (flags & DRIVE_CAP32) { 1936 bus_space_write_multi_stream_4(wdr->data32iot, 1937 wdr->data32ioh, 0, bf, len >> 2); 1938 bf = (char *)bf + (len & ~3); 1939 len &= 3; 1940 } 1941 if (len) { 1942 bus_space_write_multi_stream_2(wdr->cmd_iot, 1943 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1944 } 1945 } 1946 return; 1947 1948 #ifndef __NO_STRICT_ALIGNMENT 1949 unaligned: 1950 if (flags & DRIVE_NOSTREAM) { 1951 if (flags & DRIVE_CAP32) { 1952 while (len > 3) { 1953 uint32_t val; 1954 1955 memcpy(&val, bf, 4); 1956 bus_space_write_4(wdr->data32iot, 1957 wdr->data32ioh, 0, val); 1958 bf = (char *)bf + 4; 1959 len -= 4; 1960 } 1961 } 1962 while (len > 1) { 1963 uint16_t val; 1964 1965 memcpy(&val, bf, 2); 1966 bus_space_write_2(wdr->cmd_iot, 1967 wdr->cmd_iohs[wd_data], 0, val); 1968 bf = (char *)bf + 2; 1969 len -= 2; 1970 } 1971 } else { 1972 if (flags & DRIVE_CAP32) { 1973 while (len > 3) { 1974 uint32_t val; 1975 1976 memcpy(&val, bf, 4); 1977 bus_space_write_stream_4(wdr->data32iot, 1978 wdr->data32ioh, 0, val); 1979 bf = (char *)bf + 4; 1980 len -= 4; 1981 } 1982 } 1983 while (len > 1) { 1984 uint16_t val; 1985 1986 memcpy(&val, bf, 2); 1987 bus_space_write_stream_2(wdr->cmd_iot, 1988 wdr->cmd_iohs[wd_data], 0, val); 1989 bf = (char *)bf + 2; 1990 len -= 2; 1991 } 1992 } 1993 #endif 1994 } 1995
Indexes created Wed Sep 24 02:09:48 GMT 2025