wdc.c revision 1.253
1 /* $NetBSD: wdc.c,v 1.253 2008/03/18 20:46:36 cube Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.253 2008/03/18 20:46:36 cube Exp $"); 74 75 #include "opt_ata.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/conf.h> 81 #include <sys/buf.h> 82 #include <sys/device.h> 83 #include <sys/malloc.h> 84 #include <sys/syslog.h> 85 #include <sys/proc.h> 86 87 #include <sys/intr.h> 88 #include <sys/bus.h> 89 90 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 91 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 92 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 93 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 94 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 95 #define bus_space_read_stream_2 bus_space_read_2 96 #define bus_space_read_stream_4 bus_space_read_4 97 #define bus_space_write_stream_2 bus_space_write_2 98 #define bus_space_write_stream_4 bus_space_write_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ata/satareg.h> 104 #include <dev/ata/satavar.h> 105 #include <dev/ic/wdcreg.h> 106 #include <dev/ic/wdcvar.h> 107 108 #include "locators.h" 109 110 #include "atapibus.h" 111 #include "wd.h" 112 #include "sata.h" 113 114 #define WDCDELAY 100 /* 100 microseconds */ 115 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 116 #if 0 117 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 118 #define WDCNDELAY_DEBUG 50 119 #endif 120 121 /* When polling wait that much and then tsleep for 1/hz seconds */ 122 #define WDCDELAY_POLL 1 /* ms */ 123 124 /* timeout for the control commands */ 125 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 126 127 /* 128 * timeout when waiting for BSY to deassert when probing. 129 * set to 5s. From the standards this could be up to 31, but we can't 130 * wait that much at boot time, and 5s seems to be enouth. 131 */ 132 #define WDC_PROBE_WAIT 5 133 134 135 #if NWD > 0 136 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 137 #else 138 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 139 const struct ata_bustype wdc_ata_bustype = { 140 SCSIPI_BUSTYPE_ATA, 141 NULL, /* wdc_ata_bio */ 142 NULL, /* wdc_reset_drive */ 143 wdc_reset_channel, 144 wdc_exec_command, 145 NULL, /* ata_get_params */ 146 NULL, /* wdc_ata_addref */ 147 NULL, /* wdc_ata_delref */ 148 NULL /* ata_kill_pending */ 149 }; 150 #endif 151 152 /* Flags to wdcreset(). */ 153 #define RESET_POLL 1 154 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 155 156 static int wdcprobe1(struct ata_channel *, int); 157 static int wdcreset(struct ata_channel *, int); 158 static void __wdcerror(struct ata_channel *, const char *); 159 static int __wdcwait_reset(struct ata_channel *, int, int); 160 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 161 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 162 static void __wdccommand_kill_xfer(struct ata_channel *, 163 struct ata_xfer *, int); 164 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 165 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 166 static int __wdcwait(struct ata_channel *, int, int, int); 167 168 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 169 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 170 171 #define DEBUG_INTR 0x01 172 #define DEBUG_XFERS 0x02 173 #define DEBUG_STATUS 0x04 174 #define DEBUG_FUNCS 0x08 175 #define DEBUG_PROBE 0x10 176 #define DEBUG_DETACH 0x20 177 #define DEBUG_DELAY 0x40 178 #ifdef ATADEBUG 179 extern int atadebug_mask; /* init'ed in ata.c */ 180 int wdc_nxfer = 0; 181 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 182 #else 183 #define ATADEBUG_PRINT(args, level) 184 #endif 185 186 /* 187 * Initialize the "shadow register" handles for a standard wdc controller. 188 */ 189 void 190 wdc_init_shadow_regs(struct ata_channel *chp) 191 { 192 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 193 194 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 195 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 196 } 197 198 /* 199 * Allocate a wdc_regs array, based on the number of channels. 200 */ 201 void 202 wdc_allocate_regs(struct wdc_softc *wdc) 203 { 204 205 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 206 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 207 } 208 209 #if NSATA > 0 210 /* 211 * probe drives on SATA controllers with standard SATA registers: 212 * bring the PHYs online, read the drive signature and set drive flags 213 * appropriately. 214 */ 215 void 216 wdc_sataprobe(struct ata_channel *chp) 217 { 218 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 219 uint16_t scnt, sn, cl, ch; 220 int i, s; 221 222 /* XXX This should be done by other code. */ 223 for (i = 0; i < chp->ch_ndrive; i++) { 224 chp->ch_drive[i].chnl_softc = chp; 225 chp->ch_drive[i].drive = i; 226 } 227 228 /* reset the PHY and bring online */ 229 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 230 wdr->sata_status)) { 231 case SStatus_DET_DEV: 232 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 233 WDSD_IBM); 234 delay(10); /* 400ns delay */ 235 scnt = bus_space_read_2(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_seccnt], 0); 237 sn = bus_space_read_2(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_sector], 0); 239 cl = bus_space_read_2(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_lo], 0); 241 ch = bus_space_read_2(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_hi], 0); 243 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 244 "cl=0x%x ch=0x%x\n", 245 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 246 scnt, sn, cl, ch), DEBUG_PROBE); 247 /* 248 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 s = splbio(); 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 254 else 255 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 256 splx(s); 257 258 /* 259 * issue a reset in case only the interface part of the drive 260 * is up 261 */ 262 if (wdcreset(chp, RESET_SLEEP) != 0) 263 chp->ch_drive[0].drive_flags = 0; 264 break; 265 266 default: 267 break; 268 } 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, s; 296 297 if (wdcprobe1(chp, 0) == 0) { 298 /* No drives, abort the attach here. */ 299 return; 300 } 301 302 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 303 for (i = 0; i < mstohz(3000); i++) { 304 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 305 if (wdc->select) 306 wdc->select(chp,0); 307 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 308 0, WDSD_IBM); 309 delay(10); /* 400ns delay */ 310 st0 = bus_space_read_1(wdr->cmd_iot, 311 wdr->cmd_iohs[wd_status], 0); 312 } 313 314 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 315 if (wdc->select) 316 wdc->select(chp,1); 317 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 318 0, WDSD_IBM | 0x10); 319 delay(10); /* 400ns delay */ 320 st1 = bus_space_read_1(wdr->cmd_iot, 321 wdr->cmd_iohs[wd_status], 0); 322 } 323 324 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 325 == 0 || 326 (st0 & WDCS_DRDY)) && 327 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 328 == 0 || 329 (st1 & WDCS_DRDY))) 330 break; 331 tsleep(¶ms, PRIBIO, "atadrdy", 1); 332 } 333 s = splbio(); 334 if ((st0 & WDCS_DRDY) == 0) 335 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 336 if ((st1 & WDCS_DRDY) == 0) 337 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 338 splx(s); 339 340 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 341 device_xname(atac->atac_dev), 342 chp->ch_channel, st0, st1), DEBUG_PROBE); 343 344 /* Wait a bit, some devices are weird just after a reset. */ 345 delay(5000); 346 347 for (i = 0; i < chp->ch_ndrive; i++) { 348 /* XXX This should be done by other code. */ 349 chp->ch_drive[i].chnl_softc = chp; 350 chp->ch_drive[i].drive = i; 351 352 #if NATA_DMA 353 /* 354 * Init error counter so that an error withing the first xfers 355 * will trigger a downgrade 356 */ 357 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 358 #endif 359 360 /* If controller can't do 16bit flag the drives as 32bit */ 361 if ((atac->atac_cap & 362 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 363 s = splbio(); 364 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 365 splx(s); 366 } 367 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 368 continue; 369 370 /* Shortcut in case we've been shutdown */ 371 if (chp->ch_flags & ATACH_SHUTDOWN) 372 return; 373 374 /* 375 * Issue an identify, to try to detect ghosts. 376 * Note that we can't use interrupts here, because if there 377 * is no devices, we will get a command aborted without 378 * interrupts. 379 */ 380 error = ata_get_params(&chp->ch_drive[i], 381 AT_WAIT | AT_POLL, ¶ms); 382 if (error != CMD_OK) { 383 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 384 385 /* Shortcut in case we've been shutdown */ 386 if (chp->ch_flags & ATACH_SHUTDOWN) 387 return; 388 389 error = ata_get_params(&chp->ch_drive[i], 390 AT_WAIT | AT_POLL, ¶ms); 391 } 392 if (error == CMD_OK) { 393 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 394 s = splbio(); 395 for (j = 0; j < chp->ch_ndrive; j++) 396 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 397 splx(s); 398 } else { 399 s = splbio(); 400 chp->ch_drive[i].drive_flags &= 401 ~(DRIVE_ATA | DRIVE_ATAPI); 402 splx(s); 403 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 404 device_xname(atac->atac_dev), 405 chp->ch_channel, i, error), DEBUG_PROBE); 406 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 407 continue; 408 /* 409 * Pre-ATA drive ? 410 * Test registers writability (Error register not 411 * writable, but cyllo is), then try an ATA command. 412 */ 413 if (wdc->select) 414 wdc->select(chp,i); 415 bus_space_write_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 417 delay(10); /* 400ns delay */ 418 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 419 0, 0x58); 420 bus_space_write_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 422 if (bus_space_read_1(wdr->cmd_iot, 423 wdr->cmd_iohs[wd_error], 0) == 0x58 || 424 bus_space_read_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 426 ATADEBUG_PRINT(("%s:%d:%d: register " 427 "writability failed\n", 428 device_xname(atac->atac_dev), 429 chp->ch_channel, i), DEBUG_PROBE); 430 s = splbio(); 431 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 432 splx(s); 433 continue; 434 } 435 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 436 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 437 device_xname(atac->atac_dev), 438 chp->ch_channel, i), DEBUG_PROBE); 439 s = splbio(); 440 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 441 splx(s); 442 continue; 443 } 444 bus_space_write_1(wdr->cmd_iot, 445 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 446 delay(10); /* 400ns delay */ 447 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 448 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 449 device_xname(atac->atac_dev), 450 chp->ch_channel, i), DEBUG_PROBE); 451 s = splbio(); 452 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 453 splx(s); 454 } else { 455 s = splbio(); 456 for (j = 0; j < chp->ch_ndrive; j++) 457 chp->ch_drive[j].drive_flags &= 458 ~(DRIVE_ATA | DRIVE_ATAPI); 459 splx(s); 460 } 461 } 462 } 463 } 464 465 int 466 wdcprobe(struct ata_channel *chp) 467 { 468 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 469 /* default reset method */ 470 if (wdc->reset == NULL) 471 wdc->reset = wdc_do_reset; 472 473 return (wdcprobe1(chp, 1)); 474 } 475 476 static int 477 wdcprobe1(struct ata_channel *chp, int poll) 478 { 479 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 480 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 481 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 482 u_int8_t ret_value = 0x03; 483 u_int8_t drive; 484 int s; 485 /* XXX if poll, wdc_probe_count is 0. */ 486 int wdc_probe_count = 487 poll ? (WDC_PROBE_WAIT / WDCDELAY) 488 : (WDC_PROBE_WAIT * hz); 489 490 /* 491 * Sanity check to see if the wdc channel responds at all. 492 */ 493 494 s = splbio(); 495 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 496 while (wdc_probe_count-- > 0) { 497 if (wdc->select) 498 wdc->select(chp,0); 499 500 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 501 0, WDSD_IBM); 502 delay(10); /* 400ns delay */ 503 st0 = bus_space_read_1(wdr->cmd_iot, 504 wdr->cmd_iohs[wd_status], 0); 505 506 if (wdc->select) 507 wdc->select(chp,1); 508 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM | 0x10); 511 delay(10); /* 400ns delay */ 512 st1 = bus_space_read_1(wdr->cmd_iot, 513 wdr->cmd_iohs[wd_status], 0); 514 if ((st0 & WDCS_BSY) == 0) 515 break; 516 } 517 518 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 519 device_xname(chp->ch_atac->atac_dev), 520 chp->ch_channel, st0, st1), DEBUG_PROBE); 521 522 if (st0 == 0xff || st0 == WDSD_IBM) 523 ret_value &= ~0x01; 524 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 525 ret_value &= ~0x02; 526 /* Register writability test, drive 0. */ 527 if (ret_value & 0x01) { 528 if (wdc->select) 529 wdc->select(chp,0); 530 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 531 0, WDSD_IBM); 532 bus_space_write_1(wdr->cmd_iot, 533 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 534 cl = bus_space_read_1(wdr->cmd_iot, 535 wdr->cmd_iohs[wd_cyl_lo], 0); 536 if (cl != 0x02) { 537 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 538 "got 0x%x != 0x02\n", 539 device_xname(chp->ch_atac->atac_dev), 540 chp->ch_channel, cl), 541 DEBUG_PROBE); 542 ret_value &= ~0x01; 543 } 544 bus_space_write_1(wdr->cmd_iot, 545 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 546 cl = bus_space_read_1(wdr->cmd_iot, 547 wdr->cmd_iohs[wd_cyl_lo], 0); 548 if (cl != 0x01) { 549 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 550 "got 0x%x != 0x01\n", 551 device_xname(chp->ch_atac->atac_dev), 552 chp->ch_channel, cl), 553 DEBUG_PROBE); 554 ret_value &= ~0x01; 555 } 556 bus_space_write_1(wdr->cmd_iot, 557 wdr->cmd_iohs[wd_sector], 0, 0x01); 558 cl = bus_space_read_1(wdr->cmd_iot, 559 wdr->cmd_iohs[wd_sector], 0); 560 if (cl != 0x01) { 561 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 562 "got 0x%x != 0x01\n", 563 device_xname(chp->ch_atac->atac_dev), 564 chp->ch_channel, cl), 565 DEBUG_PROBE); 566 ret_value &= ~0x01; 567 } 568 bus_space_write_1(wdr->cmd_iot, 569 wdr->cmd_iohs[wd_sector], 0, 0x02); 570 cl = bus_space_read_1(wdr->cmd_iot, 571 wdr->cmd_iohs[wd_sector], 0); 572 if (cl != 0x02) { 573 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 574 "got 0x%x != 0x02\n", 575 device_xname(chp->ch_atac->atac_dev), 576 chp->ch_channel, cl), 577 DEBUG_PROBE); 578 ret_value &= ~0x01; 579 } 580 cl = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_cyl_lo], 0); 582 if (cl != 0x01) { 583 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 584 "got 0x%x != 0x01\n", 585 device_xname(chp->ch_atac->atac_dev), 586 chp->ch_channel, cl), 587 DEBUG_PROBE); 588 ret_value &= ~0x01; 589 } 590 } 591 /* Register writability test, drive 1. */ 592 if (ret_value & 0x02) { 593 if (wdc->select) 594 wdc->select(chp,1); 595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 596 0, WDSD_IBM | 0x10); 597 bus_space_write_1(wdr->cmd_iot, 598 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_lo], 0); 601 if (cl != 0x02) { 602 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 603 "got 0x%x != 0x02\n", 604 device_xname(chp->ch_atac->atac_dev), 605 chp->ch_channel, cl), 606 DEBUG_PROBE); 607 ret_value &= ~0x02; 608 } 609 bus_space_write_1(wdr->cmd_iot, 610 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 611 cl = bus_space_read_1(wdr->cmd_iot, 612 wdr->cmd_iohs[wd_cyl_lo], 0); 613 if (cl != 0x01) { 614 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 615 "got 0x%x != 0x01\n", 616 device_xname(chp->ch_atac->atac_dev), 617 chp->ch_channel, cl), 618 DEBUG_PROBE); 619 ret_value &= ~0x02; 620 } 621 bus_space_write_1(wdr->cmd_iot, 622 wdr->cmd_iohs[wd_sector], 0, 0x01); 623 cl = bus_space_read_1(wdr->cmd_iot, 624 wdr->cmd_iohs[wd_sector], 0); 625 if (cl != 0x01) { 626 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 627 "got 0x%x != 0x01\n", 628 device_xname(chp->ch_atac->atac_dev), 629 chp->ch_channel, cl), 630 DEBUG_PROBE); 631 ret_value &= ~0x02; 632 } 633 bus_space_write_1(wdr->cmd_iot, 634 wdr->cmd_iohs[wd_sector], 0, 0x02); 635 cl = bus_space_read_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_sector], 0); 637 if (cl != 0x02) { 638 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 639 "got 0x%x != 0x02\n", 640 device_xname(chp->ch_atac->atac_dev), 641 chp->ch_channel, cl), 642 DEBUG_PROBE); 643 ret_value &= ~0x02; 644 } 645 cl = bus_space_read_1(wdr->cmd_iot, 646 wdr->cmd_iohs[wd_cyl_lo], 0); 647 if (cl != 0x01) { 648 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 649 "got 0x%x != 0x01\n", 650 device_xname(chp->ch_atac->atac_dev), 651 chp->ch_channel, cl), 652 DEBUG_PROBE); 653 ret_value &= ~0x02; 654 } 655 } 656 657 if (ret_value == 0) { 658 splx(s); 659 return 0; 660 } 661 } 662 663 664 #if 0 /* XXX this break some ATA or ATAPI devices */ 665 /* 666 * reset bus. Also send an ATAPI_RESET to devices, in case there are 667 * ATAPI device out there which don't react to the bus reset 668 */ 669 if (ret_value & 0x01) { 670 if (wdc->select) 671 wdc->select(chp,0); 672 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 673 0, WDSD_IBM); 674 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 675 ATAPI_SOFT_RESET); 676 } 677 if (ret_value & 0x02) { 678 if (wdc->select) 679 wdc->select(chp,0); 680 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 681 0, WDSD_IBM | 0x10); 682 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 683 ATAPI_SOFT_RESET); 684 } 685 686 delay(5000); 687 #endif 688 689 wdc->reset(chp, RESET_POLL); 690 DELAY(2000); 691 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 692 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 693 splx(s); 694 695 ret_value = __wdcwait_reset(chp, ret_value, poll); 696 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 697 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 698 ret_value), DEBUG_PROBE); 699 700 /* if reset failed, there's nothing here */ 701 if (ret_value == 0) 702 return 0; 703 704 /* 705 * Test presence of drives. First test register signatures looking 706 * for ATAPI devices. If it's not an ATAPI and reset said there may 707 * be something here assume it's ATA or OLD. Ghost will be killed 708 * later in attach routine. 709 */ 710 for (drive = 0; drive < chp->ch_ndrive; drive++) { 711 if ((ret_value & (0x01 << drive)) == 0) 712 continue; 713 if (wdc->select) 714 wdc->select(chp,drive); 715 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 716 WDSD_IBM | (drive << 4)); 717 delay(10); /* 400ns delay */ 718 /* Save registers contents */ 719 sc = bus_space_read_1(wdr->cmd_iot, 720 wdr->cmd_iohs[wd_seccnt], 0); 721 sn = bus_space_read_1(wdr->cmd_iot, 722 wdr->cmd_iohs[wd_sector], 0); 723 cl = bus_space_read_1(wdr->cmd_iot, 724 wdr->cmd_iohs[wd_cyl_lo], 0); 725 ch = bus_space_read_1(wdr->cmd_iot, 726 wdr->cmd_iohs[wd_cyl_hi], 0); 727 728 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 729 "cl=0x%x ch=0x%x\n", 730 device_xname(chp->ch_atac->atac_dev), 731 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 732 /* 733 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 734 * we get wrong values here, so ignore it. 735 */ 736 s = splbio(); 737 if (cl == 0x14 && ch == 0xeb) { 738 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 739 } else { 740 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 741 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 742 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 743 } 744 splx(s); 745 } 746 return (ret_value); 747 } 748 749 void 750 wdcattach(struct ata_channel *chp) 751 { 752 struct atac_softc *atac = chp->ch_atac; 753 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 754 755 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 756 757 /* default data transfer methods */ 758 if (wdc->datain_pio == NULL) 759 wdc->datain_pio = wdc_datain_pio; 760 if (wdc->dataout_pio == NULL) 761 wdc->dataout_pio = wdc_dataout_pio; 762 /* default reset method */ 763 if (wdc->reset == NULL) 764 wdc->reset = wdc_do_reset; 765 766 /* initialise global data */ 767 if (atac->atac_bustype_ata == NULL) 768 atac->atac_bustype_ata = &wdc_ata_bustype; 769 if (atac->atac_probe == NULL) 770 atac->atac_probe = wdc_drvprobe; 771 #if NATAPIBUS > 0 772 if (atac->atac_atapibus_attach == NULL) 773 atac->atac_atapibus_attach = wdc_atapibus_attach; 774 #endif 775 776 ata_channel_attach(chp); 777 } 778 779 int 780 wdcactivate(device_t self, enum devact act) 781 { 782 struct atac_softc *atac = device_private(self); 783 struct ata_channel *chp; 784 int s, i, error = 0; 785 786 s = splbio(); 787 switch (act) { 788 case DVACT_ACTIVATE: 789 error = EOPNOTSUPP; 790 break; 791 792 case DVACT_DEACTIVATE: 793 for (i = 0; i < atac->atac_nchannels; i++) { 794 chp = atac->atac_channels[i]; 795 if (chp->atabus == NULL) 796 continue; 797 error = config_deactivate(chp->atabus); 798 if (error) 799 break; 800 } 801 break; 802 } 803 splx(s); 804 return (error); 805 } 806 807 void 808 wdc_childdetached(device_t self, device_t child) 809 { 810 struct atac_softc *atac = device_private(self); 811 struct ata_channel *chp; 812 int i; 813 814 for (i = 0; i < atac->atac_nchannels; i++) { 815 chp = atac->atac_channels[i]; 816 if (child == chp->atabus) { 817 chp->atabus = NULL; 818 return; 819 } 820 } 821 } 822 823 int 824 wdcdetach(device_t self, int flags) 825 { 826 struct atac_softc *atac = device_private(self); 827 struct ata_channel *chp; 828 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 829 int i, error = 0; 830 831 for (i = 0; i < atac->atac_nchannels; i++) { 832 chp = atac->atac_channels[i]; 833 if (chp->atabus == NULL) 834 continue; 835 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 836 device_xname(atac->atac_dev), device_xname(chp->atabus)), 837 DEBUG_DETACH); 838 if ((error = config_detach(chp->atabus, flags)) != 0) 839 return error; 840 } 841 if (adapt->adapt_refcnt != 0) 842 return EBUSY; 843 return 0; 844 } 845 846 /* restart an interrupted I/O */ 847 void 848 wdcrestart(void *v) 849 { 850 struct ata_channel *chp = v; 851 int s; 852 853 s = splbio(); 854 atastart(chp); 855 splx(s); 856 } 857 858 859 /* 860 * Interrupt routine for the controller. Acknowledge the interrupt, check for 861 * errors on the current operation, mark it done if necessary, and start the 862 * next request. Also check for a partially done transfer, and continue with 863 * the next chunk if so. 864 */ 865 int 866 wdcintr(void *arg) 867 { 868 struct ata_channel *chp = arg; 869 struct atac_softc *atac = chp->ch_atac; 870 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 871 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 872 struct ata_xfer *xfer; 873 int ret; 874 875 if (!device_is_active(atac->atac_dev)) { 876 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 877 DEBUG_INTR); 878 return (0); 879 } 880 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 881 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 882 /* try to clear the pending interrupt anyway */ 883 (void)bus_space_read_1(wdr->cmd_iot, 884 wdr->cmd_iohs[wd_status], 0); 885 return (0); 886 } 887 888 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 889 xfer = chp->ch_queue->active_xfer; 890 #ifdef DIAGNOSTIC 891 if (xfer == NULL) 892 panic("wdcintr: no xfer"); 893 if (xfer->c_chp != chp) { 894 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 895 chp->ch_channel); 896 panic("wdcintr: wrong channel"); 897 } 898 #endif 899 #if NATA_DMA || NATA_PIOBM 900 if (chp->ch_flags & ATACH_DMA_WAIT) { 901 wdc->dma_status = 902 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 903 xfer->c_drive, WDC_DMAEND_END); 904 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 905 /* IRQ not for us, not detected by DMA engine */ 906 return 0; 907 } 908 chp->ch_flags &= ~ATACH_DMA_WAIT; 909 } 910 #endif 911 chp->ch_flags &= ~ATACH_IRQ_WAIT; 912 ret = xfer->c_intr(chp, xfer, 1); 913 if (ret == 0) /* irq was not for us, still waiting for irq */ 914 chp->ch_flags |= ATACH_IRQ_WAIT; 915 return (ret); 916 } 917 918 /* Put all disk in RESET state */ 919 void 920 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 921 { 922 struct ata_channel *chp = drvp->chnl_softc; 923 924 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 925 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 926 drvp->drive), DEBUG_FUNCS); 927 928 ata_reset_channel(chp, flags); 929 } 930 931 void 932 wdc_reset_channel(struct ata_channel *chp, int flags) 933 { 934 TAILQ_HEAD(, ata_xfer) reset_xfer; 935 struct ata_xfer *xfer, *next_xfer; 936 #if NATA_DMA || NATA_PIOBM 937 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 938 #endif 939 940 TAILQ_INIT(&reset_xfer); 941 942 chp->ch_flags &= ~ATACH_IRQ_WAIT; 943 944 /* 945 * if the current command if on an ATAPI device, issue a 946 * ATAPI_SOFT_RESET 947 */ 948 xfer = chp->ch_queue->active_xfer; 949 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 950 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 951 if (flags & AT_WAIT) 952 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 953 else 954 delay(1000); 955 } 956 957 /* reset the channel */ 958 if (flags & AT_WAIT) 959 (void) wdcreset(chp, RESET_SLEEP); 960 else 961 (void) wdcreset(chp, RESET_POLL); 962 963 /* 964 * wait a bit after reset; in case the DMA engines needs some time 965 * to recover. 966 */ 967 if (flags & AT_WAIT) 968 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 969 else 970 delay(1000); 971 /* 972 * look for pending xfers. If we have a shared queue, we'll also reset 973 * the other channel if the current xfer is running on it. 974 * Then we'll dequeue only the xfers for this channel. 975 */ 976 if ((flags & AT_RST_NOCMD) == 0) { 977 /* 978 * move all xfers queued for this channel to the reset queue, 979 * and then process the current xfer and then the reset queue. 980 * We have to use a temporary queue because c_kill_xfer() 981 * may requeue commands. 982 */ 983 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 984 xfer != NULL; xfer = next_xfer) { 985 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 986 if (xfer->c_chp != chp) 987 continue; 988 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 989 xfer, c_xferchain); 990 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 991 } 992 xfer = chp->ch_queue->active_xfer; 993 if (xfer) { 994 if (xfer->c_chp != chp) 995 ata_reset_channel(xfer->c_chp, flags); 996 else { 997 callout_stop(&chp->ch_callout); 998 #if NATA_DMA || NATA_PIOBM 999 /* 1000 * If we're waiting for DMA, stop the 1001 * DMA engine 1002 */ 1003 if (chp->ch_flags & ATACH_DMA_WAIT) { 1004 (*wdc->dma_finish)( 1005 wdc->dma_arg, 1006 chp->ch_channel, 1007 xfer->c_drive, 1008 WDC_DMAEND_ABRT_QUIET); 1009 chp->ch_flags &= ~ATACH_DMA_WAIT; 1010 } 1011 #endif 1012 chp->ch_queue->active_xfer = NULL; 1013 if ((flags & AT_RST_EMERG) == 0) 1014 xfer->c_kill_xfer( 1015 chp, xfer, KILL_RESET); 1016 } 1017 } 1018 1019 for (xfer = TAILQ_FIRST(&reset_xfer); 1020 xfer != NULL; xfer = next_xfer) { 1021 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1022 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1023 if ((flags & AT_RST_EMERG) == 0) 1024 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1025 } 1026 } 1027 } 1028 1029 static int 1030 wdcreset(struct ata_channel *chp, int poll) 1031 { 1032 struct atac_softc *atac = chp->ch_atac; 1033 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1034 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1035 int drv_mask1, drv_mask2; 1036 1037 wdc->reset(chp, poll); 1038 1039 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1040 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1041 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1042 (poll == RESET_SLEEP) ? 0 : 1); 1043 if (drv_mask2 != drv_mask1) { 1044 aprint_error("%s channel %d: reset failed for", 1045 device_xname(atac->atac_dev), chp->ch_channel); 1046 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1047 aprint_normal(" drive 0"); 1048 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1049 aprint_normal(" drive 1"); 1050 aprint_normal("\n"); 1051 } 1052 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1053 return (drv_mask1 != drv_mask2) ? 1 : 0; 1054 } 1055 1056 void 1057 wdc_do_reset(struct ata_channel *chp, int poll) 1058 { 1059 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1060 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1061 int s = 0; 1062 1063 if (poll != RESET_SLEEP) 1064 s = splbio(); 1065 if (wdc->select) 1066 wdc->select(chp,0); 1067 /* master */ 1068 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1069 delay(10); /* 400ns delay */ 1070 /* assert SRST, wait for reset to complete */ 1071 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1072 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1073 delay(2000); 1074 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1075 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1076 WDCTL_4BIT | WDCTL_IDS); 1077 delay(10); /* 400ns delay */ 1078 if (poll != RESET_SLEEP) { 1079 /* ACK interrupt in case there is one pending left */ 1080 if (wdc->irqack) 1081 wdc->irqack(chp); 1082 splx(s); 1083 } 1084 } 1085 1086 static int 1087 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1088 { 1089 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1090 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1091 int timeout, nloop; 1092 u_int8_t st0 = 0, st1 = 0; 1093 #ifdef ATADEBUG 1094 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1095 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1096 #endif 1097 1098 if (poll) 1099 nloop = WDCNDELAY_RST; 1100 else 1101 nloop = WDC_RESET_WAIT * hz / 1000; 1102 /* wait for BSY to deassert */ 1103 for (timeout = 0; timeout < nloop; timeout++) { 1104 if ((drv_mask & 0x01) != 0) { 1105 if (wdc->select) 1106 wdc->select(chp,0); 1107 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1108 0, WDSD_IBM); /* master */ 1109 delay(10); 1110 st0 = bus_space_read_1(wdr->cmd_iot, 1111 wdr->cmd_iohs[wd_status], 0); 1112 #ifdef ATADEBUG 1113 sc0 = bus_space_read_1(wdr->cmd_iot, 1114 wdr->cmd_iohs[wd_seccnt], 0); 1115 sn0 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_sector], 0); 1117 cl0 = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_cyl_lo], 0); 1119 ch0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_cyl_hi], 0); 1121 #endif 1122 } 1123 if ((drv_mask & 0x02) != 0) { 1124 if (wdc->select) 1125 wdc->select(chp,1); 1126 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1127 0, WDSD_IBM | 0x10); /* slave */ 1128 delay(10); 1129 st1 = bus_space_read_1(wdr->cmd_iot, 1130 wdr->cmd_iohs[wd_status], 0); 1131 #ifdef ATADEBUG 1132 sc1 = bus_space_read_1(wdr->cmd_iot, 1133 wdr->cmd_iohs[wd_seccnt], 0); 1134 sn1 = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_sector], 0); 1136 cl1 = bus_space_read_1(wdr->cmd_iot, 1137 wdr->cmd_iohs[wd_cyl_lo], 0); 1138 ch1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_cyl_hi], 0); 1140 #endif 1141 } 1142 1143 if ((drv_mask & 0x01) == 0) { 1144 /* no master */ 1145 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1146 /* No master, slave is ready, it's done */ 1147 goto end; 1148 } 1149 if ((drv_mask & 0x02) == 0) { 1150 /* No master, no slave: it's done */ 1151 goto end; 1152 } 1153 } else if ((drv_mask & 0x02) == 0) { 1154 /* no slave */ 1155 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1156 /* No slave, master is ready, it's done */ 1157 goto end; 1158 } 1159 } else { 1160 /* Wait for both master and slave to be ready */ 1161 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1162 goto end; 1163 } 1164 } 1165 if (poll) 1166 delay(WDCDELAY); 1167 else 1168 tsleep(&nloop, PRIBIO, "atarst", 1); 1169 } 1170 /* Reset timed out. Maybe it's because drv_mask was not right */ 1171 if (st0 & WDCS_BSY) 1172 drv_mask &= ~0x01; 1173 if (st1 & WDCS_BSY) 1174 drv_mask &= ~0x02; 1175 end: 1176 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1177 "cl=0x%x ch=0x%x\n", 1178 device_xname(chp->ch_atac->atac_dev), 1179 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1180 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1181 "cl=0x%x ch=0x%x\n", 1182 device_xname(chp->ch_atac->atac_dev), 1183 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1184 1185 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1186 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1187 st0, st1), DEBUG_PROBE); 1188 1189 return drv_mask; 1190 } 1191 1192 /* 1193 * Wait for a drive to be !BSY, and have mask in its status register. 1194 * return -1 for a timeout after "timeout" ms. 1195 */ 1196 static int 1197 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1198 { 1199 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1200 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1201 u_char status; 1202 int xtime = 0; 1203 1204 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1205 device_xname(chp->ch_atac->atac_dev), 1206 chp->ch_channel), DEBUG_STATUS); 1207 chp->ch_error = 0; 1208 1209 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1210 1211 for (;;) { 1212 chp->ch_status = status = 1213 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1214 if ((status & (WDCS_BSY | mask)) == bits) 1215 break; 1216 if (++xtime > timeout) { 1217 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1218 "status %x error %x (mask 0x%x bits 0x%x)\n", 1219 xtime, status, 1220 bus_space_read_1(wdr->cmd_iot, 1221 wdr->cmd_iohs[wd_error], 0), mask, bits), 1222 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1223 return(WDCWAIT_TOUT); 1224 } 1225 delay(WDCDELAY); 1226 } 1227 #ifdef ATADEBUG 1228 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1229 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1230 #endif 1231 if (status & WDCS_ERR) 1232 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1233 wdr->cmd_iohs[wd_error], 0); 1234 #ifdef WDCNDELAY_DEBUG 1235 /* After autoconfig, there should be no long delays. */ 1236 if (!cold && xtime > WDCNDELAY_DEBUG) { 1237 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1238 if (xfer == NULL) 1239 printf("%s channel %d: warning: busy-wait took %dus\n", 1240 device_xname(chp->ch_atac->atac_dev), 1241 chp->ch_channel, WDCDELAY * xtime); 1242 else 1243 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1244 device_xname(chp->ch_atac->atac_dev), 1245 chp->ch_channel, xfer->c_drive, 1246 WDCDELAY * xtime); 1247 } 1248 #endif 1249 return(WDCWAIT_OK); 1250 } 1251 1252 /* 1253 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1254 * thread if possible 1255 */ 1256 int 1257 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1258 { 1259 int error, i, timeout_hz = mstohz(timeout); 1260 1261 if (timeout_hz == 0 || 1262 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1263 error = __wdcwait(chp, mask, bits, timeout); 1264 else { 1265 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1266 if (error != 0) { 1267 if ((chp->ch_flags & ATACH_TH_RUN) || 1268 (flags & AT_WAIT)) { 1269 /* 1270 * we're running in the channel thread 1271 * or some userland thread context 1272 */ 1273 for (i = 0; i < timeout_hz; i++) { 1274 if (__wdcwait(chp, mask, bits, 1275 WDCDELAY_POLL) == 0) { 1276 error = 0; 1277 break; 1278 } 1279 tsleep(&chp, PRIBIO, "atapoll", 1); 1280 } 1281 } else { 1282 /* 1283 * we're probably in interrupt context, 1284 * ask the thread to come back here 1285 */ 1286 #ifdef DIAGNOSTIC 1287 if (chp->ch_queue->queue_freeze > 0) 1288 panic("wdcwait: queue_freeze"); 1289 #endif 1290 chp->ch_queue->queue_freeze++; 1291 wakeup(&chp->ch_thread); 1292 return(WDCWAIT_THR); 1293 } 1294 } 1295 } 1296 return (error); 1297 } 1298 1299 1300 #if NATA_DMA 1301 /* 1302 * Busy-wait for DMA to complete 1303 */ 1304 int 1305 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1306 { 1307 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1308 int xtime; 1309 1310 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1311 wdc->dma_status = 1312 (*wdc->dma_finish)(wdc->dma_arg, 1313 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1314 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1315 return 0; 1316 delay(WDCDELAY); 1317 } 1318 /* timeout, force a DMA halt */ 1319 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1320 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1321 return 1; 1322 } 1323 #endif 1324 1325 void 1326 wdctimeout(void *arg) 1327 { 1328 struct ata_channel *chp = (struct ata_channel *)arg; 1329 #if NATA_DMA || NATA_PIOBM 1330 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1331 #endif 1332 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1333 int s; 1334 1335 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1336 1337 s = splbio(); 1338 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1339 __wdcerror(chp, "lost interrupt"); 1340 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1341 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1342 xfer->c_bcount, 1343 xfer->c_skip); 1344 #if NATA_DMA || NATA_PIOBM 1345 if (chp->ch_flags & ATACH_DMA_WAIT) { 1346 wdc->dma_status = 1347 (*wdc->dma_finish)(wdc->dma_arg, 1348 chp->ch_channel, xfer->c_drive, 1349 WDC_DMAEND_ABRT); 1350 chp->ch_flags &= ~ATACH_DMA_WAIT; 1351 } 1352 #endif 1353 /* 1354 * Call the interrupt routine. If we just missed an interrupt, 1355 * it will do what's needed. Else, it will take the needed 1356 * action (reset the device). 1357 * Before that we need to reinstall the timeout callback, 1358 * in case it will miss another irq while in this transfer 1359 * We arbitray chose it to be 1s 1360 */ 1361 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1362 xfer->c_flags |= C_TIMEOU; 1363 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1364 xfer->c_intr(chp, xfer, 1); 1365 } else 1366 __wdcerror(chp, "missing untimeout"); 1367 splx(s); 1368 } 1369 1370 int 1371 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1372 { 1373 struct ata_channel *chp = drvp->chnl_softc; 1374 struct ata_xfer *xfer; 1375 int s, ret; 1376 1377 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1378 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1379 drvp->drive), DEBUG_FUNCS); 1380 1381 /* set up an xfer and queue. Wait for completion */ 1382 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1383 ATAXF_NOSLEEP); 1384 if (xfer == NULL) { 1385 return ATACMD_TRY_AGAIN; 1386 } 1387 1388 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1389 ata_c->flags |= AT_POLL; 1390 if (ata_c->flags & AT_POLL) 1391 xfer->c_flags |= C_POLL; 1392 if (ata_c->flags & AT_WAIT) 1393 xfer->c_flags |= C_WAIT; 1394 xfer->c_drive = drvp->drive; 1395 xfer->c_databuf = ata_c->data; 1396 xfer->c_bcount = ata_c->bcount; 1397 xfer->c_cmd = ata_c; 1398 xfer->c_start = __wdccommand_start; 1399 xfer->c_intr = __wdccommand_intr; 1400 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1401 1402 s = splbio(); 1403 ata_exec_xfer(chp, xfer); 1404 #ifdef DIAGNOSTIC 1405 if ((ata_c->flags & AT_POLL) != 0 && 1406 (ata_c->flags & AT_DONE) == 0) 1407 panic("wdc_exec_command: polled command not done"); 1408 #endif 1409 if (ata_c->flags & AT_DONE) { 1410 ret = ATACMD_COMPLETE; 1411 } else { 1412 if (ata_c->flags & AT_WAIT) { 1413 while ((ata_c->flags & AT_DONE) == 0) { 1414 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1415 } 1416 ret = ATACMD_COMPLETE; 1417 } else { 1418 ret = ATACMD_QUEUED; 1419 } 1420 } 1421 splx(s); 1422 return ret; 1423 } 1424 1425 static void 1426 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1427 { 1428 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1429 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1430 int drive = xfer->c_drive; 1431 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1432 struct ata_command *ata_c = xfer->c_cmd; 1433 1434 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1435 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1436 xfer->c_drive), 1437 DEBUG_FUNCS); 1438 1439 if (wdc->select) 1440 wdc->select(chp,drive); 1441 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1442 WDSD_IBM | (drive << 4)); 1443 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1444 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1445 case WDCWAIT_OK: 1446 break; 1447 case WDCWAIT_TOUT: 1448 ata_c->flags |= AT_TIMEOU; 1449 __wdccommand_done(chp, xfer); 1450 return; 1451 case WDCWAIT_THR: 1452 return; 1453 } 1454 if (ata_c->flags & AT_POLL) { 1455 /* polled command, disable interrupts */ 1456 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1457 WDCTL_4BIT | WDCTL_IDS); 1458 } 1459 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1460 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1461 1462 if ((ata_c->flags & AT_POLL) == 0) { 1463 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1464 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1465 wdctimeout, chp); 1466 return; 1467 } 1468 /* 1469 * Polled command. Wait for drive ready or drq. Done in intr(). 1470 * Wait for at last 400ns for status bit to be valid. 1471 */ 1472 delay(10); /* 400ns delay */ 1473 __wdccommand_intr(chp, xfer, 0); 1474 } 1475 1476 static int 1477 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1478 { 1479 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1480 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1481 struct ata_command *ata_c = xfer->c_cmd; 1482 int bcount = ata_c->bcount; 1483 char *data = ata_c->data; 1484 int wflags; 1485 int drive_flags; 1486 1487 if (ata_c->r_command == WDCC_IDENTIFY || 1488 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1489 /* 1490 * The IDENTIFY data has been designed as an array of 1491 * u_int16_t, so we can byteswap it on the fly. 1492 * Historically it's what we have always done so keeping it 1493 * here ensure binary backward compatibility. 1494 */ 1495 drive_flags = DRIVE_NOSTREAM | 1496 chp->ch_drive[xfer->c_drive].drive_flags; 1497 } else { 1498 /* 1499 * Other data structure are opaque and should be transfered 1500 * as is. 1501 */ 1502 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1503 } 1504 1505 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1506 /* both wait and poll, we can tsleep here */ 1507 wflags = AT_WAIT | AT_POLL; 1508 } else { 1509 wflags = AT_POLL; 1510 } 1511 1512 again: 1513 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1514 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1515 xfer->c_drive), DEBUG_INTR); 1516 /* 1517 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1518 * Reselect again, it doesn't hurt for others commands, and the time 1519 * penalty for the extra regiter write is acceptable, 1520 * wdc_exec_command() isn't called often (mosly for autoconfig) 1521 */ 1522 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1523 WDSD_IBM | (xfer->c_drive << 4)); 1524 if ((ata_c->flags & AT_XFDONE) != 0) { 1525 /* 1526 * We have completed a data xfer. The drive should now be 1527 * in its initial state 1528 */ 1529 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1530 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1531 wflags) == WDCWAIT_TOUT) { 1532 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1533 return 0; /* IRQ was not for us */ 1534 ata_c->flags |= AT_TIMEOU; 1535 } 1536 goto out; 1537 } 1538 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1539 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1540 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1541 return 0; /* IRQ was not for us */ 1542 ata_c->flags |= AT_TIMEOU; 1543 goto out; 1544 } 1545 if (wdc->irqack) 1546 wdc->irqack(chp); 1547 if (ata_c->flags & AT_READ) { 1548 if ((chp->ch_status & WDCS_DRQ) == 0) { 1549 ata_c->flags |= AT_TIMEOU; 1550 goto out; 1551 } 1552 wdc->datain_pio(chp, drive_flags, data, bcount); 1553 /* at this point the drive should be in its initial state */ 1554 ata_c->flags |= AT_XFDONE; 1555 /* 1556 * XXX checking the status register again here cause some 1557 * hardware to timeout. 1558 */ 1559 } else if (ata_c->flags & AT_WRITE) { 1560 if ((chp->ch_status & WDCS_DRQ) == 0) { 1561 ata_c->flags |= AT_TIMEOU; 1562 goto out; 1563 } 1564 wdc->dataout_pio(chp, drive_flags, data, bcount); 1565 ata_c->flags |= AT_XFDONE; 1566 if ((ata_c->flags & AT_POLL) == 0) { 1567 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1568 callout_reset(&chp->ch_callout, 1569 mstohz(ata_c->timeout), wdctimeout, chp); 1570 return 1; 1571 } else { 1572 goto again; 1573 } 1574 } 1575 out: 1576 __wdccommand_done(chp, xfer); 1577 return 1; 1578 } 1579 1580 static void 1581 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1582 { 1583 struct atac_softc *atac = chp->ch_atac; 1584 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1585 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1586 struct ata_command *ata_c = xfer->c_cmd; 1587 1588 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1589 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1590 ata_c->flags), DEBUG_FUNCS); 1591 1592 1593 if (chp->ch_status & WDCS_DWF) 1594 ata_c->flags |= AT_DF; 1595 if (chp->ch_status & WDCS_ERR) { 1596 ata_c->flags |= AT_ERROR; 1597 ata_c->r_error = chp->ch_error; 1598 } 1599 if ((ata_c->flags & AT_READREG) != 0 && 1600 device_is_active(atac->atac_dev) && 1601 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1602 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1603 wdr->cmd_iohs[wd_sdh], 0); 1604 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1605 wdr->cmd_iohs[wd_seccnt], 0); 1606 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1607 wdr->cmd_iohs[wd_sector], 0); 1608 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1609 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1610 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1611 wdr->cmd_iohs[wd_cyl_lo], 0); 1612 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1613 wdr->cmd_iohs[wd_error], 0); 1614 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1615 wdr->cmd_iohs[wd_features], 0); 1616 } 1617 callout_stop(&chp->ch_callout); 1618 chp->ch_queue->active_xfer = NULL; 1619 if (ata_c->flags & AT_POLL) { 1620 /* enable interrupts */ 1621 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1622 WDCTL_4BIT); 1623 delay(10); /* some drives need a little delay here */ 1624 } 1625 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1626 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1627 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1628 wakeup(&chp->ch_queue->active_xfer); 1629 } else 1630 __wdccommand_done_end(chp, xfer); 1631 } 1632 1633 static void 1634 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1635 { 1636 struct ata_command *ata_c = xfer->c_cmd; 1637 1638 ata_c->flags |= AT_DONE; 1639 ata_free_xfer(chp, xfer); 1640 if (ata_c->flags & AT_WAIT) 1641 wakeup(ata_c); 1642 else if (ata_c->callback) 1643 ata_c->callback(ata_c->callback_arg); 1644 atastart(chp); 1645 return; 1646 } 1647 1648 static void 1649 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1650 int reason) 1651 { 1652 struct ata_command *ata_c = xfer->c_cmd; 1653 1654 switch (reason) { 1655 case KILL_GONE: 1656 ata_c->flags |= AT_GONE; 1657 break; 1658 case KILL_RESET: 1659 ata_c->flags |= AT_RESET; 1660 break; 1661 default: 1662 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1663 reason); 1664 panic("__wdccommand_kill_xfer"); 1665 } 1666 __wdccommand_done_end(chp, xfer); 1667 } 1668 1669 /* 1670 * Send a command. The drive should be ready. 1671 * Assumes interrupts are blocked. 1672 */ 1673 void 1674 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1675 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1676 u_int8_t features) 1677 { 1678 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1679 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1680 1681 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1682 "sector=%d count=%d features=%d\n", 1683 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1684 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1685 1686 if (wdc->select) 1687 wdc->select(chp,drive); 1688 1689 /* Select drive, head, and addressing mode. */ 1690 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1691 WDSD_IBM | (drive << 4) | head); 1692 /* Load parameters into the wd_features register. */ 1693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1694 features); 1695 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1696 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1698 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1699 0, cylin >> 8); 1700 1701 /* Send command. */ 1702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1703 return; 1704 } 1705 1706 /* 1707 * Send a 48-bit addressing command. The drive should be ready. 1708 * Assumes interrupts are blocked. 1709 */ 1710 void 1711 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1712 u_int64_t blkno, u_int16_t count) 1713 { 1714 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1715 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1716 1717 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1718 "count=%d\n", device_xname(chp->ch_atac->atac_dev), 1719 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1720 DEBUG_FUNCS); 1721 1722 if (wdc->select) 1723 wdc->select(chp,drive); 1724 1725 /* Select drive, head, and addressing mode. */ 1726 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1727 (drive << 4) | WDSD_LBA); 1728 1729 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1730 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1731 0); 1732 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1733 0, count); 1734 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1735 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1736 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1737 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1738 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1739 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1740 } else { 1741 /* previous */ 1742 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1743 0); 1744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1745 0, count >> 8); 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1747 0, blkno >> 24); 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1749 0, blkno >> 32); 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1751 0, blkno >> 40); 1752 1753 /* current */ 1754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1755 0); 1756 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1757 count); 1758 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1759 blkno); 1760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1761 0, blkno >> 8); 1762 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1763 0, blkno >> 16); 1764 } 1765 1766 /* Send command. */ 1767 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1768 return; 1769 } 1770 1771 /* 1772 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1773 * tested by the caller. 1774 */ 1775 void 1776 wdccommandshort(struct ata_channel *chp, int drive, int command) 1777 { 1778 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1779 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1780 1781 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1782 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1783 command), DEBUG_FUNCS); 1784 1785 if (wdc->select) 1786 wdc->select(chp,drive); 1787 1788 /* Select drive. */ 1789 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1790 WDSD_IBM | (drive << 4)); 1791 1792 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1793 } 1794 1795 static void 1796 __wdcerror(struct ata_channel *chp, const char *msg) 1797 { 1798 struct atac_softc *atac = chp->ch_atac; 1799 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1800 1801 if (xfer == NULL) 1802 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1803 chp->ch_channel, msg); 1804 else 1805 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1806 chp->ch_channel, xfer->c_drive, msg); 1807 } 1808 1809 /* 1810 * the bit bucket 1811 */ 1812 void 1813 wdcbit_bucket(struct ata_channel *chp, int size) 1814 { 1815 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1816 1817 for (; size >= 2; size -= 2) 1818 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1819 if (size) 1820 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1821 } 1822 1823 static void 1824 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1825 { 1826 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1827 1828 #ifndef __NO_STRICT_ALIGNMENT 1829 if ((uintptr_t)bf & 1) 1830 goto unaligned; 1831 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1832 goto unaligned; 1833 #endif 1834 1835 if (flags & DRIVE_NOSTREAM) { 1836 if (flags & DRIVE_CAP32) { 1837 bus_space_read_multi_4(wdr->data32iot, 1838 wdr->data32ioh, 0, bf, len >> 2); 1839 bf = (char *)bf + (len & ~3); 1840 len &= 3; 1841 } 1842 if (len) { 1843 bus_space_read_multi_2(wdr->cmd_iot, 1844 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1845 } 1846 } else { 1847 if (flags & DRIVE_CAP32) { 1848 bus_space_read_multi_stream_4(wdr->data32iot, 1849 wdr->data32ioh, 0, bf, len >> 2); 1850 bf = (char *)bf + (len & ~3); 1851 len &= 3; 1852 } 1853 if (len) { 1854 bus_space_read_multi_stream_2(wdr->cmd_iot, 1855 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1856 } 1857 } 1858 return; 1859 1860 #ifndef __NO_STRICT_ALIGNMENT 1861 unaligned: 1862 if (flags & DRIVE_NOSTREAM) { 1863 if (flags & DRIVE_CAP32) { 1864 while (len > 3) { 1865 uint32_t val; 1866 1867 val = bus_space_read_4(wdr->data32iot, 1868 wdr->data32ioh, 0); 1869 memcpy(bf, &val, 4); 1870 bf = (char *)bf + 4; 1871 len -= 4; 1872 } 1873 } 1874 while (len > 1) { 1875 uint16_t val; 1876 1877 val = bus_space_read_2(wdr->cmd_iot, 1878 wdr->cmd_iohs[wd_data], 0); 1879 memcpy(bf, &val, 2); 1880 bf = (char *)bf + 2; 1881 len -= 2; 1882 } 1883 } else { 1884 if (flags & DRIVE_CAP32) { 1885 while (len > 3) { 1886 uint32_t val; 1887 1888 val = bus_space_read_stream_4(wdr->data32iot, 1889 wdr->data32ioh, 0); 1890 memcpy(bf, &val, 4); 1891 bf = (char *)bf + 4; 1892 len -= 4; 1893 } 1894 } 1895 while (len > 1) { 1896 uint16_t val; 1897 1898 val = bus_space_read_stream_2(wdr->cmd_iot, 1899 wdr->cmd_iohs[wd_data], 0); 1900 memcpy(bf, &val, 2); 1901 bf = (char *)bf + 2; 1902 len -= 2; 1903 } 1904 } 1905 #endif 1906 } 1907 1908 static void 1909 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1910 { 1911 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1912 1913 #ifndef __NO_STRICT_ALIGNMENT 1914 if ((uintptr_t)bf & 1) 1915 goto unaligned; 1916 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1917 goto unaligned; 1918 #endif 1919 1920 if (flags & DRIVE_NOSTREAM) { 1921 if (flags & DRIVE_CAP32) { 1922 bus_space_write_multi_4(wdr->data32iot, 1923 wdr->data32ioh, 0, bf, len >> 2); 1924 bf = (char *)bf + (len & ~3); 1925 len &= 3; 1926 } 1927 if (len) { 1928 bus_space_write_multi_2(wdr->cmd_iot, 1929 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1930 } 1931 } else { 1932 if (flags & DRIVE_CAP32) { 1933 bus_space_write_multi_stream_4(wdr->data32iot, 1934 wdr->data32ioh, 0, bf, len >> 2); 1935 bf = (char *)bf + (len & ~3); 1936 len &= 3; 1937 } 1938 if (len) { 1939 bus_space_write_multi_stream_2(wdr->cmd_iot, 1940 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1941 } 1942 } 1943 return; 1944 1945 #ifndef __NO_STRICT_ALIGNMENT 1946 unaligned: 1947 if (flags & DRIVE_NOSTREAM) { 1948 if (flags & DRIVE_CAP32) { 1949 while (len > 3) { 1950 uint32_t val; 1951 1952 memcpy(&val, bf, 4); 1953 bus_space_write_4(wdr->data32iot, 1954 wdr->data32ioh, 0, val); 1955 bf = (char *)bf + 4; 1956 len -= 4; 1957 } 1958 } 1959 while (len > 1) { 1960 uint16_t val; 1961 1962 memcpy(&val, bf, 2); 1963 bus_space_write_2(wdr->cmd_iot, 1964 wdr->cmd_iohs[wd_data], 0, val); 1965 bf = (char *)bf + 2; 1966 len -= 2; 1967 } 1968 } else { 1969 if (flags & DRIVE_CAP32) { 1970 while (len > 3) { 1971 uint32_t val; 1972 1973 memcpy(&val, bf, 4); 1974 bus_space_write_stream_4(wdr->data32iot, 1975 wdr->data32ioh, 0, val); 1976 bf = (char *)bf + 4; 1977 len -= 4; 1978 } 1979 } 1980 while (len > 1) { 1981 uint16_t val; 1982 1983 memcpy(&val, bf, 2); 1984 bus_space_write_stream_2(wdr->cmd_iot, 1985 wdr->cmd_iohs[wd_data], 0, val); 1986 bf = (char *)bf + 2; 1987 len -= 2; 1988 } 1989 } 1990 #endif 1991 } 1992
Indexes created Fri Sep 26 20:09:58 GMT 2025