wdc.c revision 1.257
1 /* $NetBSD: wdc.c,v 1.257 2008/12/08 11:23:39 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * CODE UNTESTED IN THE CURRENT REVISION: 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.257 2008/12/08 11:23:39 pooka Exp $"); 67 68 #include "opt_ata.h" 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/conf.h> 74 #include <sys/buf.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/syslog.h> 78 #include <sys/proc.h> 79 80 #include <sys/intr.h> 81 #include <sys/bus.h> 82 83 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 84 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 85 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 86 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 87 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 88 #define bus_space_read_stream_2 bus_space_read_2 89 #define bus_space_read_stream_4 bus_space_read_4 90 #define bus_space_write_stream_2 bus_space_write_2 91 #define bus_space_write_stream_4 bus_space_write_4 92 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 93 94 #include <dev/ata/atavar.h> 95 #include <dev/ata/atareg.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satavar.h> 98 #include <dev/ic/wdcreg.h> 99 #include <dev/ic/wdcvar.h> 100 101 #include "locators.h" 102 103 #include "atapibus.h" 104 #include "wd.h" 105 #include "sata.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 /* When polling wait that much and then tsleep for 1/hz seconds */ 115 #define WDCDELAY_POLL 1 /* ms */ 116 117 /* timeout for the control commands */ 118 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 119 120 /* 121 * timeout when waiting for BSY to deassert when probing. 122 * set to 5s. From the standards this could be up to 31, but we can't 123 * wait that much at boot time, and 5s seems to be enouth. 124 */ 125 #define WDC_PROBE_WAIT 5 126 127 128 #if NWD > 0 129 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 130 #else 131 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 132 const struct ata_bustype wdc_ata_bustype = { 133 SCSIPI_BUSTYPE_ATA, 134 NULL, /* wdc_ata_bio */ 135 NULL, /* wdc_reset_drive */ 136 wdc_reset_channel, 137 wdc_exec_command, 138 NULL, /* ata_get_params */ 139 NULL, /* wdc_ata_addref */ 140 NULL, /* wdc_ata_delref */ 141 NULL /* ata_kill_pending */ 142 }; 143 #endif 144 145 /* Flags to wdcreset(). */ 146 #define RESET_POLL 1 147 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 148 149 static int wdcprobe1(struct ata_channel *, int); 150 static int wdcreset(struct ata_channel *, int); 151 static void __wdcerror(struct ata_channel *, const char *); 152 static int __wdcwait_reset(struct ata_channel *, int, int); 153 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 154 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 155 static void __wdccommand_kill_xfer(struct ata_channel *, 156 struct ata_xfer *, int); 157 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 158 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 159 static int __wdcwait(struct ata_channel *, int, int, int); 160 161 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 162 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 163 164 #define DEBUG_INTR 0x01 165 #define DEBUG_XFERS 0x02 166 #define DEBUG_STATUS 0x04 167 #define DEBUG_FUNCS 0x08 168 #define DEBUG_PROBE 0x10 169 #define DEBUG_DETACH 0x20 170 #define DEBUG_DELAY 0x40 171 #ifdef ATADEBUG 172 extern int atadebug_mask; /* init'ed in ata.c */ 173 int wdc_nxfer = 0; 174 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 175 #else 176 #define ATADEBUG_PRINT(args, level) 177 #endif 178 179 /* 180 * Initialize the "shadow register" handles for a standard wdc controller. 181 */ 182 void 183 wdc_init_shadow_regs(struct ata_channel *chp) 184 { 185 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 186 187 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 188 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 189 } 190 191 /* 192 * Allocate a wdc_regs array, based on the number of channels. 193 */ 194 void 195 wdc_allocate_regs(struct wdc_softc *wdc) 196 { 197 198 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 199 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 200 } 201 202 #if NSATA > 0 203 /* 204 * probe drives on SATA controllers with standard SATA registers: 205 * bring the PHYs online, read the drive signature and set drive flags 206 * appropriately. 207 */ 208 void 209 wdc_sataprobe(struct ata_channel *chp) 210 { 211 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 212 uint16_t scnt, sn, cl, ch; 213 int i, s; 214 215 /* XXX This should be done by other code. */ 216 for (i = 0; i < chp->ch_ndrive; i++) { 217 chp->ch_drive[i].chnl_softc = chp; 218 chp->ch_drive[i].drive = i; 219 } 220 221 /* reset the PHY and bring online */ 222 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 223 wdr->sata_status)) { 224 case SStatus_DET_DEV: 225 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 226 WDSD_IBM); 227 delay(10); /* 400ns delay */ 228 scnt = bus_space_read_2(wdr->cmd_iot, 229 wdr->cmd_iohs[wd_seccnt], 0); 230 sn = bus_space_read_2(wdr->cmd_iot, 231 wdr->cmd_iohs[wd_sector], 0); 232 cl = bus_space_read_2(wdr->cmd_iot, 233 wdr->cmd_iohs[wd_cyl_lo], 0); 234 ch = bus_space_read_2(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_cyl_hi], 0); 236 ATADEBUG_PRINT(("%s: port %d: scnt=0x%x sn=0x%x " 237 "cl=0x%x ch=0x%x\n", 238 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 239 scnt, sn, cl, ch), DEBUG_PROBE); 240 /* 241 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 242 * cases we get wrong values here, so ignore it. 243 */ 244 s = splbio(); 245 if (cl == 0x14 && ch == 0xeb) 246 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 247 else 248 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 249 splx(s); 250 251 /* 252 * issue a reset in case only the interface part of the drive 253 * is up 254 */ 255 if (wdcreset(chp, RESET_SLEEP) != 0) 256 chp->ch_drive[0].drive_flags = 0; 257 break; 258 259 default: 260 break; 261 } 262 } 263 #endif /* NSATA > 0 */ 264 265 266 /* Test to see controller with at last one attached drive is there. 267 * Returns a bit for each possible drive found (0x01 for drive 0, 268 * 0x02 for drive 1). 269 * Logic: 270 * - If a status register is at 0xff, assume there is no drive here 271 * (ISA has pull-up resistors). Similarly if the status register has 272 * the value we last wrote to the bus (for IDE interfaces without pullups). 273 * If no drive at all -> return. 274 * - reset the controller, wait for it to complete (may take up to 31s !). 275 * If timeout -> return. 276 * - test ATA/ATAPI signatures. If at last one drive found -> return. 277 * - try an ATA command on the master. 278 */ 279 280 void 281 wdc_drvprobe(struct ata_channel *chp) 282 { 283 struct ataparams params; /* XXX: large struct */ 284 struct atac_softc *atac = chp->ch_atac; 285 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 286 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 287 u_int8_t st0 = 0, st1 = 0; 288 int i, j, error, s; 289 290 if (wdcprobe1(chp, 0) == 0) { 291 /* No drives, abort the attach here. */ 292 return; 293 } 294 295 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 296 for (i = 0; i < mstohz(3000); i++) { 297 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 298 if (wdc->select) 299 wdc->select(chp,0); 300 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 301 0, WDSD_IBM); 302 delay(10); /* 400ns delay */ 303 st0 = bus_space_read_1(wdr->cmd_iot, 304 wdr->cmd_iohs[wd_status], 0); 305 } 306 307 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 308 if (wdc->select) 309 wdc->select(chp,1); 310 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 311 0, WDSD_IBM | 0x10); 312 delay(10); /* 400ns delay */ 313 st1 = bus_space_read_1(wdr->cmd_iot, 314 wdr->cmd_iohs[wd_status], 0); 315 } 316 317 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 318 == 0 || 319 (st0 & WDCS_DRDY)) && 320 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 321 == 0 || 322 (st1 & WDCS_DRDY))) 323 break; 324 tsleep(¶ms, PRIBIO, "atadrdy", 1); 325 } 326 s = splbio(); 327 if ((st0 & WDCS_DRDY) == 0) 328 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 329 if ((st1 & WDCS_DRDY) == 0) 330 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 331 splx(s); 332 333 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 334 device_xname(atac->atac_dev), 335 chp->ch_channel, st0, st1), DEBUG_PROBE); 336 337 /* Wait a bit, some devices are weird just after a reset. */ 338 delay(5000); 339 340 for (i = 0; i < chp->ch_ndrive; i++) { 341 /* XXX This should be done by other code. */ 342 chp->ch_drive[i].chnl_softc = chp; 343 chp->ch_drive[i].drive = i; 344 345 #if NATA_DMA 346 /* 347 * Init error counter so that an error withing the first xfers 348 * will trigger a downgrade 349 */ 350 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 351 #endif 352 353 /* If controller can't do 16bit flag the drives as 32bit */ 354 if ((atac->atac_cap & 355 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 356 s = splbio(); 357 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 358 splx(s); 359 } 360 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 361 continue; 362 363 /* Shortcut in case we've been shutdown */ 364 if (chp->ch_flags & ATACH_SHUTDOWN) 365 return; 366 367 /* 368 * Issue an identify, to try to detect ghosts. 369 * Note that we can't use interrupts here, because if there 370 * is no devices, we will get a command aborted without 371 * interrupts. 372 */ 373 error = ata_get_params(&chp->ch_drive[i], 374 AT_WAIT | AT_POLL, ¶ms); 375 if (error != CMD_OK) { 376 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 377 378 /* Shortcut in case we've been shutdown */ 379 if (chp->ch_flags & ATACH_SHUTDOWN) 380 return; 381 382 error = ata_get_params(&chp->ch_drive[i], 383 AT_WAIT | AT_POLL, ¶ms); 384 } 385 if (error == CMD_OK) { 386 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 387 s = splbio(); 388 for (j = 0; j < chp->ch_ndrive; j++) 389 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 390 splx(s); 391 } else { 392 s = splbio(); 393 chp->ch_drive[i].drive_flags &= 394 ~(DRIVE_ATA | DRIVE_ATAPI); 395 splx(s); 396 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 397 device_xname(atac->atac_dev), 398 chp->ch_channel, i, error), DEBUG_PROBE); 399 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 400 continue; 401 /* 402 * Pre-ATA drive ? 403 * Test registers writability (Error register not 404 * writable, but cyllo is), then try an ATA command. 405 */ 406 if (wdc->select) 407 wdc->select(chp,i); 408 bus_space_write_1(wdr->cmd_iot, 409 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 410 delay(10); /* 400ns delay */ 411 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 412 0, 0x58); 413 bus_space_write_1(wdr->cmd_iot, 414 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 415 if (bus_space_read_1(wdr->cmd_iot, 416 wdr->cmd_iohs[wd_error], 0) == 0x58 || 417 bus_space_read_1(wdr->cmd_iot, 418 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 419 ATADEBUG_PRINT(("%s:%d:%d: register " 420 "writability failed\n", 421 device_xname(atac->atac_dev), 422 chp->ch_channel, i), DEBUG_PROBE); 423 s = splbio(); 424 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 425 splx(s); 426 continue; 427 } 428 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 429 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 430 device_xname(atac->atac_dev), 431 chp->ch_channel, i), DEBUG_PROBE); 432 s = splbio(); 433 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 434 splx(s); 435 continue; 436 } 437 bus_space_write_1(wdr->cmd_iot, 438 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 439 delay(10); /* 400ns delay */ 440 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 441 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 442 device_xname(atac->atac_dev), 443 chp->ch_channel, i), DEBUG_PROBE); 444 s = splbio(); 445 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 446 splx(s); 447 } else { 448 s = splbio(); 449 for (j = 0; j < chp->ch_ndrive; j++) 450 chp->ch_drive[j].drive_flags &= 451 ~(DRIVE_ATA | DRIVE_ATAPI); 452 splx(s); 453 } 454 } 455 } 456 } 457 458 int 459 wdcprobe(struct ata_channel *chp) 460 { 461 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 462 /* default reset method */ 463 if (wdc->reset == NULL) 464 wdc->reset = wdc_do_reset; 465 466 return (wdcprobe1(chp, 1)); 467 } 468 469 static int 470 wdcprobe1(struct ata_channel *chp, int poll) 471 { 472 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 473 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 474 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 475 u_int8_t ret_value = 0x03; 476 u_int8_t drive; 477 int s; 478 /* XXX if poll, wdc_probe_count is 0. */ 479 int wdc_probe_count = 480 poll ? (WDC_PROBE_WAIT / WDCDELAY) 481 : (WDC_PROBE_WAIT * hz); 482 483 /* 484 * Sanity check to see if the wdc channel responds at all. 485 */ 486 487 s = splbio(); 488 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 489 while (wdc_probe_count-- > 0) { 490 if (wdc->select) 491 wdc->select(chp,0); 492 493 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 494 0, WDSD_IBM); 495 delay(10); /* 400ns delay */ 496 st0 = bus_space_read_1(wdr->cmd_iot, 497 wdr->cmd_iohs[wd_status], 0); 498 499 if (wdc->select) 500 wdc->select(chp,1); 501 502 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 503 0, WDSD_IBM | 0x10); 504 delay(10); /* 400ns delay */ 505 st1 = bus_space_read_1(wdr->cmd_iot, 506 wdr->cmd_iohs[wd_status], 0); 507 if ((st0 & WDCS_BSY) == 0) 508 break; 509 } 510 511 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 512 device_xname(chp->ch_atac->atac_dev), 513 chp->ch_channel, st0, st1), DEBUG_PROBE); 514 515 if (st0 == 0xff || st0 == WDSD_IBM) 516 ret_value &= ~0x01; 517 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 518 ret_value &= ~0x02; 519 /* Register writability test, drive 0. */ 520 if (ret_value & 0x01) { 521 if (wdc->select) 522 wdc->select(chp,0); 523 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 524 0, WDSD_IBM); 525 bus_space_write_1(wdr->cmd_iot, 526 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 527 cl = bus_space_read_1(wdr->cmd_iot, 528 wdr->cmd_iohs[wd_cyl_lo], 0); 529 if (cl != 0x02) { 530 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 531 "got 0x%x != 0x02\n", 532 device_xname(chp->ch_atac->atac_dev), 533 chp->ch_channel, cl), 534 DEBUG_PROBE); 535 ret_value &= ~0x01; 536 } 537 bus_space_write_1(wdr->cmd_iot, 538 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 539 cl = bus_space_read_1(wdr->cmd_iot, 540 wdr->cmd_iohs[wd_cyl_lo], 0); 541 if (cl != 0x01) { 542 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 543 "got 0x%x != 0x01\n", 544 device_xname(chp->ch_atac->atac_dev), 545 chp->ch_channel, cl), 546 DEBUG_PROBE); 547 ret_value &= ~0x01; 548 } 549 bus_space_write_1(wdr->cmd_iot, 550 wdr->cmd_iohs[wd_sector], 0, 0x01); 551 cl = bus_space_read_1(wdr->cmd_iot, 552 wdr->cmd_iohs[wd_sector], 0); 553 if (cl != 0x01) { 554 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 555 "got 0x%x != 0x01\n", 556 device_xname(chp->ch_atac->atac_dev), 557 chp->ch_channel, cl), 558 DEBUG_PROBE); 559 ret_value &= ~0x01; 560 } 561 bus_space_write_1(wdr->cmd_iot, 562 wdr->cmd_iohs[wd_sector], 0, 0x02); 563 cl = bus_space_read_1(wdr->cmd_iot, 564 wdr->cmd_iohs[wd_sector], 0); 565 if (cl != 0x02) { 566 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 567 "got 0x%x != 0x02\n", 568 device_xname(chp->ch_atac->atac_dev), 569 chp->ch_channel, cl), 570 DEBUG_PROBE); 571 ret_value &= ~0x01; 572 } 573 cl = bus_space_read_1(wdr->cmd_iot, 574 wdr->cmd_iohs[wd_cyl_lo], 0); 575 if (cl != 0x01) { 576 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 577 "got 0x%x != 0x01\n", 578 device_xname(chp->ch_atac->atac_dev), 579 chp->ch_channel, cl), 580 DEBUG_PROBE); 581 ret_value &= ~0x01; 582 } 583 } 584 /* Register writability test, drive 1. */ 585 if (ret_value & 0x02) { 586 if (wdc->select) 587 wdc->select(chp,1); 588 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 589 0, WDSD_IBM | 0x10); 590 bus_space_write_1(wdr->cmd_iot, 591 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 592 cl = bus_space_read_1(wdr->cmd_iot, 593 wdr->cmd_iohs[wd_cyl_lo], 0); 594 if (cl != 0x02) { 595 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 596 "got 0x%x != 0x02\n", 597 device_xname(chp->ch_atac->atac_dev), 598 chp->ch_channel, cl), 599 DEBUG_PROBE); 600 ret_value &= ~0x02; 601 } 602 bus_space_write_1(wdr->cmd_iot, 603 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 604 cl = bus_space_read_1(wdr->cmd_iot, 605 wdr->cmd_iohs[wd_cyl_lo], 0); 606 if (cl != 0x01) { 607 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 608 "got 0x%x != 0x01\n", 609 device_xname(chp->ch_atac->atac_dev), 610 chp->ch_channel, cl), 611 DEBUG_PROBE); 612 ret_value &= ~0x02; 613 } 614 bus_space_write_1(wdr->cmd_iot, 615 wdr->cmd_iohs[wd_sector], 0, 0x01); 616 cl = bus_space_read_1(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_sector], 0); 618 if (cl != 0x01) { 619 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 620 "got 0x%x != 0x01\n", 621 device_xname(chp->ch_atac->atac_dev), 622 chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x02; 625 } 626 bus_space_write_1(wdr->cmd_iot, 627 wdr->cmd_iohs[wd_sector], 0, 0x02); 628 cl = bus_space_read_1(wdr->cmd_iot, 629 wdr->cmd_iohs[wd_sector], 0); 630 if (cl != 0x02) { 631 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 632 "got 0x%x != 0x02\n", 633 device_xname(chp->ch_atac->atac_dev), 634 chp->ch_channel, cl), 635 DEBUG_PROBE); 636 ret_value &= ~0x02; 637 } 638 cl = bus_space_read_1(wdr->cmd_iot, 639 wdr->cmd_iohs[wd_cyl_lo], 0); 640 if (cl != 0x01) { 641 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 642 "got 0x%x != 0x01\n", 643 device_xname(chp->ch_atac->atac_dev), 644 chp->ch_channel, cl), 645 DEBUG_PROBE); 646 ret_value &= ~0x02; 647 } 648 } 649 650 if (ret_value == 0) { 651 splx(s); 652 return 0; 653 } 654 } 655 656 657 #if 0 /* XXX this break some ATA or ATAPI devices */ 658 /* 659 * reset bus. Also send an ATAPI_RESET to devices, in case there are 660 * ATAPI device out there which don't react to the bus reset 661 */ 662 if (ret_value & 0x01) { 663 if (wdc->select) 664 wdc->select(chp,0); 665 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 666 0, WDSD_IBM); 667 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 668 ATAPI_SOFT_RESET); 669 } 670 if (ret_value & 0x02) { 671 if (wdc->select) 672 wdc->select(chp,0); 673 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 674 0, WDSD_IBM | 0x10); 675 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 676 ATAPI_SOFT_RESET); 677 } 678 679 delay(5000); 680 #endif 681 682 wdc->reset(chp, RESET_POLL); 683 DELAY(2000); 684 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 685 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 686 splx(s); 687 688 ret_value = __wdcwait_reset(chp, ret_value, poll); 689 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 690 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 691 ret_value), DEBUG_PROBE); 692 693 /* if reset failed, there's nothing here */ 694 if (ret_value == 0) 695 return 0; 696 697 /* 698 * Test presence of drives. First test register signatures looking 699 * for ATAPI devices. If it's not an ATAPI and reset said there may 700 * be something here assume it's ATA or OLD. Ghost will be killed 701 * later in attach routine. 702 */ 703 for (drive = 0; drive < chp->ch_ndrive; drive++) { 704 if ((ret_value & (0x01 << drive)) == 0) 705 continue; 706 if (wdc->select) 707 wdc->select(chp,drive); 708 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 709 WDSD_IBM | (drive << 4)); 710 delay(10); /* 400ns delay */ 711 /* Save registers contents */ 712 sc = bus_space_read_1(wdr->cmd_iot, 713 wdr->cmd_iohs[wd_seccnt], 0); 714 sn = bus_space_read_1(wdr->cmd_iot, 715 wdr->cmd_iohs[wd_sector], 0); 716 cl = bus_space_read_1(wdr->cmd_iot, 717 wdr->cmd_iohs[wd_cyl_lo], 0); 718 ch = bus_space_read_1(wdr->cmd_iot, 719 wdr->cmd_iohs[wd_cyl_hi], 0); 720 721 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 722 "cl=0x%x ch=0x%x\n", 723 device_xname(chp->ch_atac->atac_dev), 724 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 725 /* 726 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 727 * we get wrong values here, so ignore it. 728 */ 729 s = splbio(); 730 if (cl == 0x14 && ch == 0xeb) { 731 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 732 } else { 733 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 734 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 735 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 736 } 737 splx(s); 738 } 739 return (ret_value); 740 } 741 742 void 743 wdcattach(struct ata_channel *chp) 744 { 745 struct atac_softc *atac = chp->ch_atac; 746 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 747 748 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 749 750 /* default data transfer methods */ 751 if (wdc->datain_pio == NULL) 752 wdc->datain_pio = wdc_datain_pio; 753 if (wdc->dataout_pio == NULL) 754 wdc->dataout_pio = wdc_dataout_pio; 755 /* default reset method */ 756 if (wdc->reset == NULL) 757 wdc->reset = wdc_do_reset; 758 759 /* initialise global data */ 760 if (atac->atac_bustype_ata == NULL) 761 atac->atac_bustype_ata = &wdc_ata_bustype; 762 if (atac->atac_probe == NULL) 763 atac->atac_probe = wdc_drvprobe; 764 #if NATAPIBUS > 0 765 if (atac->atac_atapibus_attach == NULL) 766 atac->atac_atapibus_attach = wdc_atapibus_attach; 767 #endif 768 769 ata_channel_attach(chp); 770 } 771 772 int 773 wdcactivate(device_t self, enum devact act) 774 { 775 struct atac_softc *atac = device_private(self); 776 struct ata_channel *chp; 777 int s, i, error = 0; 778 779 s = splbio(); 780 switch (act) { 781 case DVACT_ACTIVATE: 782 error = EOPNOTSUPP; 783 break; 784 785 case DVACT_DEACTIVATE: 786 for (i = 0; i < atac->atac_nchannels; i++) { 787 chp = atac->atac_channels[i]; 788 if (chp->atabus == NULL) 789 continue; 790 error = config_deactivate(chp->atabus); 791 if (error) 792 break; 793 } 794 break; 795 } 796 splx(s); 797 return (error); 798 } 799 800 void 801 wdc_childdetached(device_t self, device_t child) 802 { 803 struct atac_softc *atac = device_private(self); 804 struct ata_channel *chp; 805 int i; 806 807 for (i = 0; i < atac->atac_nchannels; i++) { 808 chp = atac->atac_channels[i]; 809 if (child == chp->atabus) { 810 chp->atabus = NULL; 811 return; 812 } 813 } 814 } 815 816 int 817 wdcdetach(device_t self, int flags) 818 { 819 struct atac_softc *atac = device_private(self); 820 struct ata_channel *chp; 821 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 822 int i, error = 0; 823 824 for (i = 0; i < atac->atac_nchannels; i++) { 825 chp = atac->atac_channels[i]; 826 if (chp->atabus == NULL) 827 continue; 828 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 829 device_xname(atac->atac_dev), device_xname(chp->atabus)), 830 DEBUG_DETACH); 831 if ((error = config_detach(chp->atabus, flags)) != 0) 832 return error; 833 } 834 if (adapt->adapt_refcnt != 0) 835 return EBUSY; 836 return 0; 837 } 838 839 /* restart an interrupted I/O */ 840 void 841 wdcrestart(void *v) 842 { 843 struct ata_channel *chp = v; 844 int s; 845 846 s = splbio(); 847 atastart(chp); 848 splx(s); 849 } 850 851 852 /* 853 * Interrupt routine for the controller. Acknowledge the interrupt, check for 854 * errors on the current operation, mark it done if necessary, and start the 855 * next request. Also check for a partially done transfer, and continue with 856 * the next chunk if so. 857 */ 858 int 859 wdcintr(void *arg) 860 { 861 struct ata_channel *chp = arg; 862 struct atac_softc *atac = chp->ch_atac; 863 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 864 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 865 struct ata_xfer *xfer; 866 int ret; 867 868 if (!device_is_active(atac->atac_dev)) { 869 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 870 DEBUG_INTR); 871 return (0); 872 } 873 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 874 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 875 /* try to clear the pending interrupt anyway */ 876 (void)bus_space_read_1(wdr->cmd_iot, 877 wdr->cmd_iohs[wd_status], 0); 878 return (0); 879 } 880 881 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 882 xfer = chp->ch_queue->active_xfer; 883 #ifdef DIAGNOSTIC 884 if (xfer == NULL) 885 panic("wdcintr: no xfer"); 886 if (xfer->c_chp != chp) { 887 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 888 chp->ch_channel); 889 panic("wdcintr: wrong channel"); 890 } 891 #endif 892 #if NATA_DMA || NATA_PIOBM 893 if (chp->ch_flags & ATACH_DMA_WAIT) { 894 wdc->dma_status = 895 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 896 xfer->c_drive, WDC_DMAEND_END); 897 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 898 /* IRQ not for us, not detected by DMA engine */ 899 return 0; 900 } 901 chp->ch_flags &= ~ATACH_DMA_WAIT; 902 } 903 #endif 904 chp->ch_flags &= ~ATACH_IRQ_WAIT; 905 ret = xfer->c_intr(chp, xfer, 1); 906 if (ret == 0) /* irq was not for us, still waiting for irq */ 907 chp->ch_flags |= ATACH_IRQ_WAIT; 908 return (ret); 909 } 910 911 /* Put all disk in RESET state */ 912 void 913 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 914 { 915 struct ata_channel *chp = drvp->chnl_softc; 916 917 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 918 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 919 drvp->drive), DEBUG_FUNCS); 920 921 ata_reset_channel(chp, flags); 922 } 923 924 void 925 wdc_reset_channel(struct ata_channel *chp, int flags) 926 { 927 TAILQ_HEAD(, ata_xfer) reset_xfer; 928 struct ata_xfer *xfer, *next_xfer; 929 #if NATA_DMA || NATA_PIOBM 930 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 931 #endif 932 933 TAILQ_INIT(&reset_xfer); 934 935 chp->ch_flags &= ~ATACH_IRQ_WAIT; 936 937 /* 938 * if the current command if on an ATAPI device, issue a 939 * ATAPI_SOFT_RESET 940 */ 941 xfer = chp->ch_queue->active_xfer; 942 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 943 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 944 if (flags & AT_WAIT) 945 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 946 else 947 delay(1000); 948 } 949 950 /* reset the channel */ 951 if (flags & AT_WAIT) 952 (void) wdcreset(chp, RESET_SLEEP); 953 else 954 (void) wdcreset(chp, RESET_POLL); 955 956 /* 957 * wait a bit after reset; in case the DMA engines needs some time 958 * to recover. 959 */ 960 if (flags & AT_WAIT) 961 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 962 else 963 delay(1000); 964 /* 965 * look for pending xfers. If we have a shared queue, we'll also reset 966 * the other channel if the current xfer is running on it. 967 * Then we'll dequeue only the xfers for this channel. 968 */ 969 if ((flags & AT_RST_NOCMD) == 0) { 970 /* 971 * move all xfers queued for this channel to the reset queue, 972 * and then process the current xfer and then the reset queue. 973 * We have to use a temporary queue because c_kill_xfer() 974 * may requeue commands. 975 */ 976 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 977 xfer != NULL; xfer = next_xfer) { 978 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 979 if (xfer->c_chp != chp) 980 continue; 981 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 982 xfer, c_xferchain); 983 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 984 } 985 xfer = chp->ch_queue->active_xfer; 986 if (xfer) { 987 if (xfer->c_chp != chp) 988 ata_reset_channel(xfer->c_chp, flags); 989 else { 990 callout_stop(&chp->ch_callout); 991 #if NATA_DMA || NATA_PIOBM 992 /* 993 * If we're waiting for DMA, stop the 994 * DMA engine 995 */ 996 if (chp->ch_flags & ATACH_DMA_WAIT) { 997 (*wdc->dma_finish)( 998 wdc->dma_arg, 999 chp->ch_channel, 1000 xfer->c_drive, 1001 WDC_DMAEND_ABRT_QUIET); 1002 chp->ch_flags &= ~ATACH_DMA_WAIT; 1003 } 1004 #endif 1005 chp->ch_queue->active_xfer = NULL; 1006 if ((flags & AT_RST_EMERG) == 0) 1007 xfer->c_kill_xfer( 1008 chp, xfer, KILL_RESET); 1009 } 1010 } 1011 1012 for (xfer = TAILQ_FIRST(&reset_xfer); 1013 xfer != NULL; xfer = next_xfer) { 1014 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1015 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1016 if ((flags & AT_RST_EMERG) == 0) 1017 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1018 } 1019 } 1020 } 1021 1022 static int 1023 wdcreset(struct ata_channel *chp, int poll) 1024 { 1025 struct atac_softc *atac = chp->ch_atac; 1026 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1027 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1028 int drv_mask1, drv_mask2; 1029 1030 wdc->reset(chp, poll); 1031 1032 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1033 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1034 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1035 (poll == RESET_SLEEP) ? 0 : 1); 1036 if (drv_mask2 != drv_mask1) { 1037 aprint_error("%s channel %d: reset failed for", 1038 device_xname(atac->atac_dev), chp->ch_channel); 1039 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1040 aprint_normal(" drive 0"); 1041 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1042 aprint_normal(" drive 1"); 1043 aprint_normal("\n"); 1044 } 1045 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1046 return (drv_mask1 != drv_mask2) ? 1 : 0; 1047 } 1048 1049 void 1050 wdc_do_reset(struct ata_channel *chp, int poll) 1051 { 1052 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1053 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1054 int s = 0; 1055 1056 if (poll != RESET_SLEEP) 1057 s = splbio(); 1058 if (wdc->select) 1059 wdc->select(chp,0); 1060 /* master */ 1061 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1062 delay(10); /* 400ns delay */ 1063 /* assert SRST, wait for reset to complete */ 1064 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1065 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1066 delay(2000); 1067 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1068 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1069 WDCTL_4BIT | WDCTL_IDS); 1070 delay(10); /* 400ns delay */ 1071 if (poll != RESET_SLEEP) { 1072 /* ACK interrupt in case there is one pending left */ 1073 if (wdc->irqack) 1074 wdc->irqack(chp); 1075 splx(s); 1076 } 1077 } 1078 1079 static int 1080 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1081 { 1082 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1083 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1084 int timeout, nloop; 1085 u_int8_t st0 = 0, st1 = 0; 1086 #ifdef ATADEBUG 1087 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1088 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1089 #endif 1090 1091 if (poll) 1092 nloop = WDCNDELAY_RST; 1093 else 1094 nloop = WDC_RESET_WAIT * hz / 1000; 1095 /* wait for BSY to deassert */ 1096 for (timeout = 0; timeout < nloop; timeout++) { 1097 if ((drv_mask & 0x01) != 0) { 1098 if (wdc->select) 1099 wdc->select(chp,0); 1100 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1101 0, WDSD_IBM); /* master */ 1102 delay(10); 1103 st0 = bus_space_read_1(wdr->cmd_iot, 1104 wdr->cmd_iohs[wd_status], 0); 1105 #ifdef ATADEBUG 1106 sc0 = bus_space_read_1(wdr->cmd_iot, 1107 wdr->cmd_iohs[wd_seccnt], 0); 1108 sn0 = bus_space_read_1(wdr->cmd_iot, 1109 wdr->cmd_iohs[wd_sector], 0); 1110 cl0 = bus_space_read_1(wdr->cmd_iot, 1111 wdr->cmd_iohs[wd_cyl_lo], 0); 1112 ch0 = bus_space_read_1(wdr->cmd_iot, 1113 wdr->cmd_iohs[wd_cyl_hi], 0); 1114 #endif 1115 } 1116 if ((drv_mask & 0x02) != 0) { 1117 if (wdc->select) 1118 wdc->select(chp,1); 1119 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1120 0, WDSD_IBM | 0x10); /* slave */ 1121 delay(10); 1122 st1 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_status], 0); 1124 #ifdef ATADEBUG 1125 sc1 = bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_seccnt], 0); 1127 sn1 = bus_space_read_1(wdr->cmd_iot, 1128 wdr->cmd_iohs[wd_sector], 0); 1129 cl1 = bus_space_read_1(wdr->cmd_iot, 1130 wdr->cmd_iohs[wd_cyl_lo], 0); 1131 ch1 = bus_space_read_1(wdr->cmd_iot, 1132 wdr->cmd_iohs[wd_cyl_hi], 0); 1133 #endif 1134 } 1135 1136 if ((drv_mask & 0x01) == 0) { 1137 /* no master */ 1138 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1139 /* No master, slave is ready, it's done */ 1140 goto end; 1141 } 1142 if ((drv_mask & 0x02) == 0) { 1143 /* No master, no slave: it's done */ 1144 goto end; 1145 } 1146 } else if ((drv_mask & 0x02) == 0) { 1147 /* no slave */ 1148 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1149 /* No slave, master is ready, it's done */ 1150 goto end; 1151 } 1152 } else { 1153 /* Wait for both master and slave to be ready */ 1154 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1155 goto end; 1156 } 1157 } 1158 if (poll) 1159 delay(WDCDELAY); 1160 else 1161 tsleep(&nloop, PRIBIO, "atarst", 1); 1162 } 1163 /* Reset timed out. Maybe it's because drv_mask was not right */ 1164 if (st0 & WDCS_BSY) 1165 drv_mask &= ~0x01; 1166 if (st1 & WDCS_BSY) 1167 drv_mask &= ~0x02; 1168 end: 1169 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1170 "cl=0x%x ch=0x%x\n", 1171 device_xname(chp->ch_atac->atac_dev), 1172 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1173 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1174 "cl=0x%x ch=0x%x\n", 1175 device_xname(chp->ch_atac->atac_dev), 1176 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1177 1178 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1179 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1180 st0, st1), DEBUG_PROBE); 1181 1182 return drv_mask; 1183 } 1184 1185 /* 1186 * Wait for a drive to be !BSY, and have mask in its status register. 1187 * return -1 for a timeout after "timeout" ms. 1188 */ 1189 static int 1190 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1191 { 1192 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1193 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1194 u_char status; 1195 int xtime = 0; 1196 1197 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1198 device_xname(chp->ch_atac->atac_dev), 1199 chp->ch_channel), DEBUG_STATUS); 1200 chp->ch_error = 0; 1201 1202 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1203 1204 for (;;) { 1205 chp->ch_status = status = 1206 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1207 if ((status & (WDCS_BSY | mask)) == bits) 1208 break; 1209 if (++xtime > timeout) { 1210 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1211 "status %x error %x (mask 0x%x bits 0x%x)\n", 1212 xtime, status, 1213 bus_space_read_1(wdr->cmd_iot, 1214 wdr->cmd_iohs[wd_error], 0), mask, bits), 1215 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1216 return(WDCWAIT_TOUT); 1217 } 1218 delay(WDCDELAY); 1219 } 1220 #ifdef ATADEBUG 1221 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1222 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1223 #endif 1224 if (status & WDCS_ERR) 1225 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1226 wdr->cmd_iohs[wd_error], 0); 1227 #ifdef WDCNDELAY_DEBUG 1228 /* After autoconfig, there should be no long delays. */ 1229 if (!cold && xtime > WDCNDELAY_DEBUG) { 1230 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1231 if (xfer == NULL) 1232 printf("%s channel %d: warning: busy-wait took %dus\n", 1233 device_xname(chp->ch_atac->atac_dev), 1234 chp->ch_channel, WDCDELAY * xtime); 1235 else 1236 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1237 device_xname(chp->ch_atac->atac_dev), 1238 chp->ch_channel, xfer->c_drive, 1239 WDCDELAY * xtime); 1240 } 1241 #endif 1242 return(WDCWAIT_OK); 1243 } 1244 1245 /* 1246 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1247 * thread if possible 1248 */ 1249 int 1250 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1251 { 1252 int error, i, timeout_hz = mstohz(timeout); 1253 1254 if (timeout_hz == 0 || 1255 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1256 error = __wdcwait(chp, mask, bits, timeout); 1257 else { 1258 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1259 if (error != 0) { 1260 if ((chp->ch_flags & ATACH_TH_RUN) || 1261 (flags & AT_WAIT)) { 1262 /* 1263 * we're running in the channel thread 1264 * or some userland thread context 1265 */ 1266 for (i = 0; i < timeout_hz; i++) { 1267 if (__wdcwait(chp, mask, bits, 1268 WDCDELAY_POLL) == 0) { 1269 error = 0; 1270 break; 1271 } 1272 tsleep(&chp, PRIBIO, "atapoll", 1); 1273 } 1274 } else { 1275 /* 1276 * we're probably in interrupt context, 1277 * ask the thread to come back here 1278 */ 1279 #ifdef DIAGNOSTIC 1280 if (chp->ch_queue->queue_freeze > 0) 1281 panic("wdcwait: queue_freeze"); 1282 #endif 1283 chp->ch_queue->queue_freeze++; 1284 wakeup(&chp->ch_thread); 1285 return(WDCWAIT_THR); 1286 } 1287 } 1288 } 1289 return (error); 1290 } 1291 1292 1293 #if NATA_DMA 1294 /* 1295 * Busy-wait for DMA to complete 1296 */ 1297 int 1298 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1299 { 1300 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1301 int xtime; 1302 1303 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1304 wdc->dma_status = 1305 (*wdc->dma_finish)(wdc->dma_arg, 1306 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1307 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1308 return 0; 1309 delay(WDCDELAY); 1310 } 1311 /* timeout, force a DMA halt */ 1312 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1313 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1314 return 1; 1315 } 1316 #endif 1317 1318 void 1319 wdctimeout(void *arg) 1320 { 1321 struct ata_channel *chp = (struct ata_channel *)arg; 1322 #if NATA_DMA || NATA_PIOBM 1323 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1324 #endif 1325 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1326 int s; 1327 1328 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1329 1330 s = splbio(); 1331 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1332 __wdcerror(chp, "lost interrupt"); 1333 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1334 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1335 xfer->c_bcount, 1336 xfer->c_skip); 1337 #if NATA_DMA || NATA_PIOBM 1338 if (chp->ch_flags & ATACH_DMA_WAIT) { 1339 wdc->dma_status = 1340 (*wdc->dma_finish)(wdc->dma_arg, 1341 chp->ch_channel, xfer->c_drive, 1342 WDC_DMAEND_ABRT); 1343 chp->ch_flags &= ~ATACH_DMA_WAIT; 1344 } 1345 #endif 1346 /* 1347 * Call the interrupt routine. If we just missed an interrupt, 1348 * it will do what's needed. Else, it will take the needed 1349 * action (reset the device). 1350 * Before that we need to reinstall the timeout callback, 1351 * in case it will miss another irq while in this transfer 1352 * We arbitray chose it to be 1s 1353 */ 1354 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1355 xfer->c_flags |= C_TIMEOU; 1356 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1357 xfer->c_intr(chp, xfer, 1); 1358 } else 1359 __wdcerror(chp, "missing untimeout"); 1360 splx(s); 1361 } 1362 1363 int 1364 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1365 { 1366 struct ata_channel *chp = drvp->chnl_softc; 1367 struct ata_xfer *xfer; 1368 int s, ret; 1369 1370 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1371 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1372 drvp->drive), DEBUG_FUNCS); 1373 1374 /* set up an xfer and queue. Wait for completion */ 1375 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1376 ATAXF_NOSLEEP); 1377 if (xfer == NULL) { 1378 return ATACMD_TRY_AGAIN; 1379 } 1380 1381 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1382 ata_c->flags |= AT_POLL; 1383 if (ata_c->flags & AT_POLL) 1384 xfer->c_flags |= C_POLL; 1385 if (ata_c->flags & AT_WAIT) 1386 xfer->c_flags |= C_WAIT; 1387 xfer->c_drive = drvp->drive; 1388 xfer->c_databuf = ata_c->data; 1389 xfer->c_bcount = ata_c->bcount; 1390 xfer->c_cmd = ata_c; 1391 xfer->c_start = __wdccommand_start; 1392 xfer->c_intr = __wdccommand_intr; 1393 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1394 1395 s = splbio(); 1396 ata_exec_xfer(chp, xfer); 1397 #ifdef DIAGNOSTIC 1398 if ((ata_c->flags & AT_POLL) != 0 && 1399 (ata_c->flags & AT_DONE) == 0) 1400 panic("wdc_exec_command: polled command not done"); 1401 #endif 1402 if (ata_c->flags & AT_DONE) { 1403 ret = ATACMD_COMPLETE; 1404 } else { 1405 if (ata_c->flags & AT_WAIT) { 1406 while ((ata_c->flags & AT_DONE) == 0) { 1407 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1408 } 1409 ret = ATACMD_COMPLETE; 1410 } else { 1411 ret = ATACMD_QUEUED; 1412 } 1413 } 1414 splx(s); 1415 return ret; 1416 } 1417 1418 static void 1419 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1420 { 1421 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1422 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1423 int drive = xfer->c_drive; 1424 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1425 struct ata_command *ata_c = xfer->c_cmd; 1426 1427 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1428 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1429 xfer->c_drive), 1430 DEBUG_FUNCS); 1431 1432 if (wdc->select) 1433 wdc->select(chp,drive); 1434 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1435 WDSD_IBM | (drive << 4)); 1436 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1437 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1438 case WDCWAIT_OK: 1439 break; 1440 case WDCWAIT_TOUT: 1441 ata_c->flags |= AT_TIMEOU; 1442 __wdccommand_done(chp, xfer); 1443 return; 1444 case WDCWAIT_THR: 1445 return; 1446 } 1447 if (ata_c->flags & AT_POLL) { 1448 /* polled command, disable interrupts */ 1449 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1450 WDCTL_4BIT | WDCTL_IDS); 1451 } 1452 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1453 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1454 1455 if ((ata_c->flags & AT_POLL) == 0) { 1456 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1457 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1458 wdctimeout, chp); 1459 return; 1460 } 1461 /* 1462 * Polled command. Wait for drive ready or drq. Done in intr(). 1463 * Wait for at last 400ns for status bit to be valid. 1464 */ 1465 delay(10); /* 400ns delay */ 1466 __wdccommand_intr(chp, xfer, 0); 1467 } 1468 1469 static int 1470 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1471 { 1472 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1473 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1474 struct ata_command *ata_c = xfer->c_cmd; 1475 int bcount = ata_c->bcount; 1476 char *data = ata_c->data; 1477 int wflags; 1478 int drive_flags; 1479 1480 if (ata_c->r_command == WDCC_IDENTIFY || 1481 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1482 /* 1483 * The IDENTIFY data has been designed as an array of 1484 * u_int16_t, so we can byteswap it on the fly. 1485 * Historically it's what we have always done so keeping it 1486 * here ensure binary backward compatibility. 1487 */ 1488 drive_flags = DRIVE_NOSTREAM | 1489 chp->ch_drive[xfer->c_drive].drive_flags; 1490 } else { 1491 /* 1492 * Other data structure are opaque and should be transfered 1493 * as is. 1494 */ 1495 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1496 } 1497 1498 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1499 /* both wait and poll, we can tsleep here */ 1500 wflags = AT_WAIT | AT_POLL; 1501 } else { 1502 wflags = AT_POLL; 1503 } 1504 1505 again: 1506 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1507 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1508 xfer->c_drive), DEBUG_INTR); 1509 /* 1510 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1511 * Reselect again, it doesn't hurt for others commands, and the time 1512 * penalty for the extra regiter write is acceptable, 1513 * wdc_exec_command() isn't called often (mosly for autoconfig) 1514 */ 1515 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1516 WDSD_IBM | (xfer->c_drive << 4)); 1517 if ((ata_c->flags & AT_XFDONE) != 0) { 1518 /* 1519 * We have completed a data xfer. The drive should now be 1520 * in its initial state 1521 */ 1522 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1523 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1524 wflags) == WDCWAIT_TOUT) { 1525 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1526 return 0; /* IRQ was not for us */ 1527 ata_c->flags |= AT_TIMEOU; 1528 } 1529 goto out; 1530 } 1531 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1532 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1533 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1534 return 0; /* IRQ was not for us */ 1535 ata_c->flags |= AT_TIMEOU; 1536 goto out; 1537 } 1538 if (wdc->irqack) 1539 wdc->irqack(chp); 1540 if (ata_c->flags & AT_READ) { 1541 if ((chp->ch_status & WDCS_DRQ) == 0) { 1542 ata_c->flags |= AT_TIMEOU; 1543 goto out; 1544 } 1545 wdc->datain_pio(chp, drive_flags, data, bcount); 1546 /* at this point the drive should be in its initial state */ 1547 ata_c->flags |= AT_XFDONE; 1548 /* 1549 * XXX checking the status register again here cause some 1550 * hardware to timeout. 1551 */ 1552 } else if (ata_c->flags & AT_WRITE) { 1553 if ((chp->ch_status & WDCS_DRQ) == 0) { 1554 ata_c->flags |= AT_TIMEOU; 1555 goto out; 1556 } 1557 wdc->dataout_pio(chp, drive_flags, data, bcount); 1558 ata_c->flags |= AT_XFDONE; 1559 if ((ata_c->flags & AT_POLL) == 0) { 1560 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1561 callout_reset(&chp->ch_callout, 1562 mstohz(ata_c->timeout), wdctimeout, chp); 1563 return 1; 1564 } else { 1565 goto again; 1566 } 1567 } 1568 out: 1569 __wdccommand_done(chp, xfer); 1570 return 1; 1571 } 1572 1573 static void 1574 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1575 { 1576 struct atac_softc *atac = chp->ch_atac; 1577 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1578 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1579 struct ata_command *ata_c = xfer->c_cmd; 1580 1581 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1582 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1583 ata_c->flags), DEBUG_FUNCS); 1584 1585 1586 if (chp->ch_status & WDCS_DWF) 1587 ata_c->flags |= AT_DF; 1588 if (chp->ch_status & WDCS_ERR) { 1589 ata_c->flags |= AT_ERROR; 1590 ata_c->r_error = chp->ch_error; 1591 } 1592 if ((ata_c->flags & AT_READREG) != 0 && 1593 device_is_active(atac->atac_dev) && 1594 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1595 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1596 wdr->cmd_iohs[wd_sdh], 0); 1597 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1598 wdr->cmd_iohs[wd_seccnt], 0); 1599 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1600 wdr->cmd_iohs[wd_sector], 0); 1601 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1602 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1603 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1604 wdr->cmd_iohs[wd_cyl_lo], 0); 1605 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1606 wdr->cmd_iohs[wd_error], 0); 1607 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1608 wdr->cmd_iohs[wd_features], 0); 1609 } 1610 callout_stop(&chp->ch_callout); 1611 chp->ch_queue->active_xfer = NULL; 1612 if (ata_c->flags & AT_POLL) { 1613 /* enable interrupts */ 1614 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1615 WDCTL_4BIT); 1616 delay(10); /* some drives need a little delay here */ 1617 } 1618 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1619 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1620 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1621 wakeup(&chp->ch_queue->active_xfer); 1622 } else 1623 __wdccommand_done_end(chp, xfer); 1624 } 1625 1626 static void 1627 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1628 { 1629 struct ata_command *ata_c = xfer->c_cmd; 1630 1631 ata_c->flags |= AT_DONE; 1632 ata_free_xfer(chp, xfer); 1633 if (ata_c->flags & AT_WAIT) 1634 wakeup(ata_c); 1635 else if (ata_c->callback) 1636 ata_c->callback(ata_c->callback_arg); 1637 atastart(chp); 1638 return; 1639 } 1640 1641 static void 1642 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1643 int reason) 1644 { 1645 struct ata_command *ata_c = xfer->c_cmd; 1646 1647 switch (reason) { 1648 case KILL_GONE: 1649 ata_c->flags |= AT_GONE; 1650 break; 1651 case KILL_RESET: 1652 ata_c->flags |= AT_RESET; 1653 break; 1654 default: 1655 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1656 reason); 1657 panic("__wdccommand_kill_xfer"); 1658 } 1659 __wdccommand_done_end(chp, xfer); 1660 } 1661 1662 /* 1663 * Send a command. The drive should be ready. 1664 * Assumes interrupts are blocked. 1665 */ 1666 void 1667 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1668 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1669 u_int8_t features) 1670 { 1671 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1672 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1673 1674 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1675 "sector=%d count=%d features=%d\n", 1676 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1677 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1678 1679 if (wdc->select) 1680 wdc->select(chp,drive); 1681 1682 /* Select drive, head, and addressing mode. */ 1683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1684 WDSD_IBM | (drive << 4) | head); 1685 /* Load parameters into the wd_features register. */ 1686 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1687 features); 1688 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1689 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1690 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1692 0, cylin >> 8); 1693 1694 /* Send command. */ 1695 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1696 return; 1697 } 1698 1699 /* 1700 * Send a 48-bit addressing command. The drive should be ready. 1701 * Assumes interrupts are blocked. 1702 */ 1703 void 1704 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1705 u_int64_t blkno, u_int16_t count) 1706 { 1707 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1708 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1709 1710 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1711 "count=%d\n", device_xname(chp->ch_atac->atac_dev), 1712 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1713 DEBUG_FUNCS); 1714 1715 if (wdc->select) 1716 wdc->select(chp,drive); 1717 1718 /* Select drive, head, and addressing mode. */ 1719 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1720 (drive << 4) | WDSD_LBA); 1721 1722 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1723 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1724 0); 1725 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1726 0, count); 1727 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1728 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1729 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1730 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1731 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1732 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1733 } else { 1734 /* previous */ 1735 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1736 0); 1737 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1738 0, count >> 8); 1739 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1740 0, blkno >> 24); 1741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1742 0, blkno >> 32); 1743 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1744 0, blkno >> 40); 1745 1746 /* current */ 1747 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1748 0); 1749 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1750 count); 1751 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1752 blkno); 1753 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1754 0, blkno >> 8); 1755 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1756 0, blkno >> 16); 1757 } 1758 1759 /* Send command. */ 1760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1761 return; 1762 } 1763 1764 /* 1765 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1766 * tested by the caller. 1767 */ 1768 void 1769 wdccommandshort(struct ata_channel *chp, int drive, int command) 1770 { 1771 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1772 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1773 1774 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1775 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1776 command), DEBUG_FUNCS); 1777 1778 if (wdc->select) 1779 wdc->select(chp,drive); 1780 1781 /* Select drive. */ 1782 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1783 WDSD_IBM | (drive << 4)); 1784 1785 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1786 } 1787 1788 static void 1789 __wdcerror(struct ata_channel *chp, const char *msg) 1790 { 1791 struct atac_softc *atac = chp->ch_atac; 1792 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1793 1794 if (xfer == NULL) 1795 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1796 chp->ch_channel, msg); 1797 else 1798 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1799 chp->ch_channel, xfer->c_drive, msg); 1800 } 1801 1802 /* 1803 * the bit bucket 1804 */ 1805 void 1806 wdcbit_bucket(struct ata_channel *chp, int size) 1807 { 1808 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1809 1810 for (; size >= 2; size -= 2) 1811 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1812 if (size) 1813 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1814 } 1815 1816 static void 1817 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1818 { 1819 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1820 1821 #ifndef __NO_STRICT_ALIGNMENT 1822 if ((uintptr_t)bf & 1) 1823 goto unaligned; 1824 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1825 goto unaligned; 1826 #endif 1827 1828 if (flags & DRIVE_NOSTREAM) { 1829 if (flags & DRIVE_CAP32) { 1830 bus_space_read_multi_4(wdr->data32iot, 1831 wdr->data32ioh, 0, bf, len >> 2); 1832 bf = (char *)bf + (len & ~3); 1833 len &= 3; 1834 } 1835 if (len) { 1836 bus_space_read_multi_2(wdr->cmd_iot, 1837 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1838 } 1839 } else { 1840 if (flags & DRIVE_CAP32) { 1841 bus_space_read_multi_stream_4(wdr->data32iot, 1842 wdr->data32ioh, 0, bf, len >> 2); 1843 bf = (char *)bf + (len & ~3); 1844 len &= 3; 1845 } 1846 if (len) { 1847 bus_space_read_multi_stream_2(wdr->cmd_iot, 1848 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1849 } 1850 } 1851 return; 1852 1853 #ifndef __NO_STRICT_ALIGNMENT 1854 unaligned: 1855 if (flags & DRIVE_NOSTREAM) { 1856 if (flags & DRIVE_CAP32) { 1857 while (len > 3) { 1858 uint32_t val; 1859 1860 val = bus_space_read_4(wdr->data32iot, 1861 wdr->data32ioh, 0); 1862 memcpy(bf, &val, 4); 1863 bf = (char *)bf + 4; 1864 len -= 4; 1865 } 1866 } 1867 while (len > 1) { 1868 uint16_t val; 1869 1870 val = bus_space_read_2(wdr->cmd_iot, 1871 wdr->cmd_iohs[wd_data], 0); 1872 memcpy(bf, &val, 2); 1873 bf = (char *)bf + 2; 1874 len -= 2; 1875 } 1876 } else { 1877 if (flags & DRIVE_CAP32) { 1878 while (len > 3) { 1879 uint32_t val; 1880 1881 val = bus_space_read_stream_4(wdr->data32iot, 1882 wdr->data32ioh, 0); 1883 memcpy(bf, &val, 4); 1884 bf = (char *)bf + 4; 1885 len -= 4; 1886 } 1887 } 1888 while (len > 1) { 1889 uint16_t val; 1890 1891 val = bus_space_read_stream_2(wdr->cmd_iot, 1892 wdr->cmd_iohs[wd_data], 0); 1893 memcpy(bf, &val, 2); 1894 bf = (char *)bf + 2; 1895 len -= 2; 1896 } 1897 } 1898 #endif 1899 } 1900 1901 static void 1902 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1903 { 1904 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1905 1906 #ifndef __NO_STRICT_ALIGNMENT 1907 if ((uintptr_t)bf & 1) 1908 goto unaligned; 1909 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1910 goto unaligned; 1911 #endif 1912 1913 if (flags & DRIVE_NOSTREAM) { 1914 if (flags & DRIVE_CAP32) { 1915 bus_space_write_multi_4(wdr->data32iot, 1916 wdr->data32ioh, 0, bf, len >> 2); 1917 bf = (char *)bf + (len & ~3); 1918 len &= 3; 1919 } 1920 if (len) { 1921 bus_space_write_multi_2(wdr->cmd_iot, 1922 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1923 } 1924 } else { 1925 if (flags & DRIVE_CAP32) { 1926 bus_space_write_multi_stream_4(wdr->data32iot, 1927 wdr->data32ioh, 0, bf, len >> 2); 1928 bf = (char *)bf + (len & ~3); 1929 len &= 3; 1930 } 1931 if (len) { 1932 bus_space_write_multi_stream_2(wdr->cmd_iot, 1933 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1934 } 1935 } 1936 return; 1937 1938 #ifndef __NO_STRICT_ALIGNMENT 1939 unaligned: 1940 if (flags & DRIVE_NOSTREAM) { 1941 if (flags & DRIVE_CAP32) { 1942 while (len > 3) { 1943 uint32_t val; 1944 1945 memcpy(&val, bf, 4); 1946 bus_space_write_4(wdr->data32iot, 1947 wdr->data32ioh, 0, val); 1948 bf = (char *)bf + 4; 1949 len -= 4; 1950 } 1951 } 1952 while (len > 1) { 1953 uint16_t val; 1954 1955 memcpy(&val, bf, 2); 1956 bus_space_write_2(wdr->cmd_iot, 1957 wdr->cmd_iohs[wd_data], 0, val); 1958 bf = (char *)bf + 2; 1959 len -= 2; 1960 } 1961 } else { 1962 if (flags & DRIVE_CAP32) { 1963 while (len > 3) { 1964 uint32_t val; 1965 1966 memcpy(&val, bf, 4); 1967 bus_space_write_stream_4(wdr->data32iot, 1968 wdr->data32ioh, 0, val); 1969 bf = (char *)bf + 4; 1970 len -= 4; 1971 } 1972 } 1973 while (len > 1) { 1974 uint16_t val; 1975 1976 memcpy(&val, bf, 2); 1977 bus_space_write_stream_2(wdr->cmd_iot, 1978 wdr->cmd_iohs[wd_data], 0, val); 1979 bf = (char *)bf + 2; 1980 len -= 2; 1981 } 1982 } 1983 #endif 1984 } 1985
Indexes created Mon Sep 22 13:09:51 GMT 2025