wdc.c revision 1.261
1 /* $NetBSD: wdc.c,v 1.261 2010/03/28 20:46:18 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.261 2010/03/28 20:46:18 snj Exp $"); 62 63 #include "opt_ata.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/kernel.h> 68 #include <sys/conf.h> 69 #include <sys/buf.h> 70 #include <sys/device.h> 71 #include <sys/malloc.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 78 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 79 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 80 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 81 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 82 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 83 #define bus_space_read_stream_2 bus_space_read_2 84 #define bus_space_read_stream_4 bus_space_read_4 85 #define bus_space_write_stream_2 bus_space_write_2 86 #define bus_space_write_stream_4 bus_space_write_4 87 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 88 89 #include <dev/ata/atavar.h> 90 #include <dev/ata/atareg.h> 91 #include <dev/ata/satareg.h> 92 #include <dev/ata/satavar.h> 93 #include <dev/ic/wdcreg.h> 94 #include <dev/ic/wdcvar.h> 95 96 #include "locators.h" 97 98 #include "atapibus.h" 99 #include "wd.h" 100 #include "sata.h" 101 102 #define WDCDELAY 100 /* 100 microseconds */ 103 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 104 #if 0 105 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 106 #define WDCNDELAY_DEBUG 50 107 #endif 108 109 /* When polling wait that much and then tsleep for 1/hz seconds */ 110 #define WDCDELAY_POLL 1 /* ms */ 111 112 /* timeout for the control commands */ 113 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 114 115 /* 116 * timeout when waiting for BSY to deassert when probing. 117 * set to 5s. From the standards this could be up to 31, but we can't 118 * wait that much at boot time, and 5s seems to be enough. 119 */ 120 #define WDC_PROBE_WAIT 5 121 122 123 #if NWD > 0 124 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 125 #else 126 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 127 const struct ata_bustype wdc_ata_bustype = { 128 SCSIPI_BUSTYPE_ATA, 129 NULL, /* wdc_ata_bio */ 130 NULL, /* wdc_reset_drive */ 131 wdc_reset_channel, 132 wdc_exec_command, 133 NULL, /* ata_get_params */ 134 NULL, /* wdc_ata_addref */ 135 NULL, /* wdc_ata_delref */ 136 NULL /* ata_kill_pending */ 137 }; 138 #endif 139 140 /* Flags to wdcreset(). */ 141 #define RESET_POLL 1 142 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 143 144 static int wdcprobe1(struct ata_channel *, int); 145 static int wdcreset(struct ata_channel *, int); 146 static void __wdcerror(struct ata_channel *, const char *); 147 static int __wdcwait_reset(struct ata_channel *, int, int); 148 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 149 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 150 static void __wdccommand_kill_xfer(struct ata_channel *, 151 struct ata_xfer *, int); 152 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 153 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 154 static int __wdcwait(struct ata_channel *, int, int, int); 155 156 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 157 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 158 159 #define DEBUG_INTR 0x01 160 #define DEBUG_XFERS 0x02 161 #define DEBUG_STATUS 0x04 162 #define DEBUG_FUNCS 0x08 163 #define DEBUG_PROBE 0x10 164 #define DEBUG_DETACH 0x20 165 #define DEBUG_DELAY 0x40 166 #ifdef ATADEBUG 167 extern int atadebug_mask; /* init'ed in ata.c */ 168 int wdc_nxfer = 0; 169 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 170 #else 171 #define ATADEBUG_PRINT(args, level) 172 #endif 173 174 /* 175 * Initialize the "shadow register" handles for a standard wdc controller. 176 */ 177 void 178 wdc_init_shadow_regs(struct ata_channel *chp) 179 { 180 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 181 182 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 183 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 184 } 185 186 /* 187 * Allocate a wdc_regs array, based on the number of channels. 188 */ 189 void 190 wdc_allocate_regs(struct wdc_softc *wdc) 191 { 192 193 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 194 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 195 } 196 197 #if NSATA > 0 198 /* 199 * probe drives on SATA controllers with standard SATA registers: 200 * bring the PHYs online, read the drive signature and set drive flags 201 * appropriately. 202 */ 203 void 204 wdc_sataprobe(struct ata_channel *chp) 205 { 206 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 207 uint8_t st = 0, sc, sn, cl, ch; 208 int i, s; 209 210 /* XXX This should be done by other code. */ 211 for (i = 0; i < chp->ch_ndrive; i++) { 212 chp->ch_drive[i].chnl_softc = chp; 213 chp->ch_drive[i].drive = i; 214 } 215 216 /* reset the PHY and bring online */ 217 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 218 wdr->sata_status)) { 219 case SStatus_DET_DEV: 220 /* wait 5s for BSY to clear */ 221 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 222 bus_space_write_1(wdr->cmd_iot, 223 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 224 delay(10); /* 400ns delay */ 225 st = bus_space_read_1(wdr->cmd_iot, 226 wdr->cmd_iohs[wd_status], 0); 227 if ((st & WDCS_BSY) == 0) 228 break; 229 tsleep(&chp, PRIBIO, "sataprb", 1); 230 } 231 if (i == WDC_PROBE_WAIT * hz) 232 aprint_error_dev(chp->ch_atac->atac_dev, 233 "BSY never cleared, status 0x%02x\n", st); 234 sc = bus_space_read_1(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_seccnt], 0); 236 sn = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_sector], 0); 238 cl = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_cyl_lo], 0); 240 ch = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_hi], 0); 242 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 243 "cl=0x%x ch=0x%x\n", 244 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 245 sc, sn, cl, ch), DEBUG_PROBE); 246 /* 247 * sc and sn are supposed to be 0x1 for ATAPI, but in some 248 * cases we get wrong values here, so ignore it. 249 */ 250 s = splbio(); 251 if (cl == 0x14 && ch == 0xeb) 252 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 253 else 254 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 255 splx(s); 256 257 /* 258 * issue a reset in case only the interface part of the drive 259 * is up 260 */ 261 if (wdcreset(chp, RESET_SLEEP) != 0) 262 chp->ch_drive[0].drive_flags = 0; 263 break; 264 265 default: 266 break; 267 } 268 } 269 #endif /* NSATA > 0 */ 270 271 272 /* Test to see controller with at last one attached drive is there. 273 * Returns a bit for each possible drive found (0x01 for drive 0, 274 * 0x02 for drive 1). 275 * Logic: 276 * - If a status register is at 0xff, assume there is no drive here 277 * (ISA has pull-up resistors). Similarly if the status register has 278 * the value we last wrote to the bus (for IDE interfaces without pullups). 279 * If no drive at all -> return. 280 * - reset the controller, wait for it to complete (may take up to 31s !). 281 * If timeout -> return. 282 * - test ATA/ATAPI signatures. If at last one drive found -> return. 283 * - try an ATA command on the master. 284 */ 285 286 void 287 wdc_drvprobe(struct ata_channel *chp) 288 { 289 struct ataparams params; /* XXX: large struct */ 290 struct atac_softc *atac = chp->ch_atac; 291 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 292 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 293 u_int8_t st0 = 0, st1 = 0; 294 int i, j, error, s; 295 296 if (wdcprobe1(chp, 0) == 0) { 297 /* No drives, abort the attach here. */ 298 return; 299 } 300 301 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 302 for (i = 0; i < mstohz(3000); i++) { 303 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 304 if (wdc->select) 305 wdc->select(chp,0); 306 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 307 0, WDSD_IBM); 308 delay(10); /* 400ns delay */ 309 st0 = bus_space_read_1(wdr->cmd_iot, 310 wdr->cmd_iohs[wd_status], 0); 311 } 312 313 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 314 if (wdc->select) 315 wdc->select(chp,1); 316 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 317 0, WDSD_IBM | 0x10); 318 delay(10); /* 400ns delay */ 319 st1 = bus_space_read_1(wdr->cmd_iot, 320 wdr->cmd_iohs[wd_status], 0); 321 } 322 323 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 324 == 0 || 325 (st0 & WDCS_DRDY)) && 326 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 327 == 0 || 328 (st1 & WDCS_DRDY))) 329 break; 330 tsleep(¶ms, PRIBIO, "atadrdy", 1); 331 } 332 s = splbio(); 333 if ((st0 & WDCS_DRDY) == 0) 334 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 335 if ((st1 & WDCS_DRDY) == 0) 336 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 337 splx(s); 338 339 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 340 device_xname(atac->atac_dev), 341 chp->ch_channel, st0, st1), DEBUG_PROBE); 342 343 /* Wait a bit, some devices are weird just after a reset. */ 344 delay(5000); 345 346 for (i = 0; i < chp->ch_ndrive; i++) { 347 /* XXX This should be done by other code. */ 348 chp->ch_drive[i].chnl_softc = chp; 349 chp->ch_drive[i].drive = i; 350 351 #if NATA_DMA 352 /* 353 * Init error counter so that an error withing the first xfers 354 * will trigger a downgrade 355 */ 356 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 357 #endif 358 359 /* If controller can't do 16bit flag the drives as 32bit */ 360 if ((atac->atac_cap & 361 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 362 s = splbio(); 363 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 364 splx(s); 365 } 366 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 367 continue; 368 369 /* Shortcut in case we've been shutdown */ 370 if (chp->ch_flags & ATACH_SHUTDOWN) 371 return; 372 373 /* 374 * Issue an identify, to try to detect ghosts. 375 * Note that we can't use interrupts here, because if there 376 * is no devices, we will get a command aborted without 377 * interrupts. 378 */ 379 error = ata_get_params(&chp->ch_drive[i], 380 AT_WAIT | AT_POLL, ¶ms); 381 if (error != CMD_OK) { 382 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 383 384 /* Shortcut in case we've been shutdown */ 385 if (chp->ch_flags & ATACH_SHUTDOWN) 386 return; 387 388 error = ata_get_params(&chp->ch_drive[i], 389 AT_WAIT | AT_POLL, ¶ms); 390 } 391 if (error == CMD_OK) { 392 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 393 s = splbio(); 394 for (j = 0; j < chp->ch_ndrive; j++) 395 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 396 splx(s); 397 } else { 398 s = splbio(); 399 chp->ch_drive[i].drive_flags &= 400 ~(DRIVE_ATA | DRIVE_ATAPI); 401 splx(s); 402 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 403 device_xname(atac->atac_dev), 404 chp->ch_channel, i, error), DEBUG_PROBE); 405 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 406 continue; 407 /* 408 * Pre-ATA drive ? 409 * Test registers writability (Error register not 410 * writable, but cyllo is), then try an ATA command. 411 */ 412 if (wdc->select) 413 wdc->select(chp,i); 414 bus_space_write_1(wdr->cmd_iot, 415 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 416 delay(10); /* 400ns delay */ 417 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 418 0, 0x58); 419 bus_space_write_1(wdr->cmd_iot, 420 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 421 if (bus_space_read_1(wdr->cmd_iot, 422 wdr->cmd_iohs[wd_error], 0) == 0x58 || 423 bus_space_read_1(wdr->cmd_iot, 424 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 425 ATADEBUG_PRINT(("%s:%d:%d: register " 426 "writability failed\n", 427 device_xname(atac->atac_dev), 428 chp->ch_channel, i), DEBUG_PROBE); 429 s = splbio(); 430 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 431 splx(s); 432 continue; 433 } 434 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 435 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 436 device_xname(atac->atac_dev), 437 chp->ch_channel, i), DEBUG_PROBE); 438 s = splbio(); 439 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 440 splx(s); 441 continue; 442 } 443 bus_space_write_1(wdr->cmd_iot, 444 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 445 delay(10); /* 400ns delay */ 446 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 447 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 448 device_xname(atac->atac_dev), 449 chp->ch_channel, i), DEBUG_PROBE); 450 s = splbio(); 451 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 452 splx(s); 453 } else { 454 s = splbio(); 455 for (j = 0; j < chp->ch_ndrive; j++) 456 chp->ch_drive[j].drive_flags &= 457 ~(DRIVE_ATA | DRIVE_ATAPI); 458 splx(s); 459 } 460 } 461 } 462 } 463 464 int 465 wdcprobe(struct ata_channel *chp) 466 { 467 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 468 /* default reset method */ 469 if (wdc->reset == NULL) 470 wdc->reset = wdc_do_reset; 471 472 return (wdcprobe1(chp, 1)); 473 } 474 475 static int 476 wdcprobe1(struct ata_channel *chp, int poll) 477 { 478 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 479 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 480 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 481 u_int8_t ret_value = 0x03; 482 u_int8_t drive; 483 int s; 484 /* XXX if poll, wdc_probe_count is 0. */ 485 int wdc_probe_count = 486 poll ? (WDC_PROBE_WAIT / WDCDELAY) 487 : (WDC_PROBE_WAIT * hz); 488 489 /* 490 * Sanity check to see if the wdc channel responds at all. 491 */ 492 493 s = splbio(); 494 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 495 while (wdc_probe_count-- > 0) { 496 if (wdc->select) 497 wdc->select(chp,0); 498 499 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 500 0, WDSD_IBM); 501 delay(10); /* 400ns delay */ 502 st0 = bus_space_read_1(wdr->cmd_iot, 503 wdr->cmd_iohs[wd_status], 0); 504 505 if (wdc->select) 506 wdc->select(chp,1); 507 508 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 509 0, WDSD_IBM | 0x10); 510 delay(10); /* 400ns delay */ 511 st1 = bus_space_read_1(wdr->cmd_iot, 512 wdr->cmd_iohs[wd_status], 0); 513 if ((st0 & WDCS_BSY) == 0) 514 break; 515 } 516 517 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 518 device_xname(chp->ch_atac->atac_dev), 519 chp->ch_channel, st0, st1), DEBUG_PROBE); 520 521 if (st0 == 0xff || st0 == WDSD_IBM) 522 ret_value &= ~0x01; 523 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 524 ret_value &= ~0x02; 525 /* Register writability test, drive 0. */ 526 if (ret_value & 0x01) { 527 if (wdc->select) 528 wdc->select(chp,0); 529 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 530 0, WDSD_IBM); 531 bus_space_write_1(wdr->cmd_iot, 532 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 533 cl = bus_space_read_1(wdr->cmd_iot, 534 wdr->cmd_iohs[wd_cyl_lo], 0); 535 if (cl != 0x02) { 536 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 537 "got 0x%x != 0x02\n", 538 device_xname(chp->ch_atac->atac_dev), 539 chp->ch_channel, cl), 540 DEBUG_PROBE); 541 ret_value &= ~0x01; 542 } 543 bus_space_write_1(wdr->cmd_iot, 544 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 545 cl = bus_space_read_1(wdr->cmd_iot, 546 wdr->cmd_iohs[wd_cyl_lo], 0); 547 if (cl != 0x01) { 548 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 549 "got 0x%x != 0x01\n", 550 device_xname(chp->ch_atac->atac_dev), 551 chp->ch_channel, cl), 552 DEBUG_PROBE); 553 ret_value &= ~0x01; 554 } 555 bus_space_write_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_sector], 0, 0x01); 557 cl = bus_space_read_1(wdr->cmd_iot, 558 wdr->cmd_iohs[wd_sector], 0); 559 if (cl != 0x01) { 560 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 561 "got 0x%x != 0x01\n", 562 device_xname(chp->ch_atac->atac_dev), 563 chp->ch_channel, cl), 564 DEBUG_PROBE); 565 ret_value &= ~0x01; 566 } 567 bus_space_write_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_sector], 0, 0x02); 569 cl = bus_space_read_1(wdr->cmd_iot, 570 wdr->cmd_iohs[wd_sector], 0); 571 if (cl != 0x02) { 572 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 573 "got 0x%x != 0x02\n", 574 device_xname(chp->ch_atac->atac_dev), 575 chp->ch_channel, cl), 576 DEBUG_PROBE); 577 ret_value &= ~0x01; 578 } 579 cl = bus_space_read_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_cyl_lo], 0); 581 if (cl != 0x01) { 582 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 583 "got 0x%x != 0x01\n", 584 device_xname(chp->ch_atac->atac_dev), 585 chp->ch_channel, cl), 586 DEBUG_PROBE); 587 ret_value &= ~0x01; 588 } 589 } 590 /* Register writability test, drive 1. */ 591 if (ret_value & 0x02) { 592 if (wdc->select) 593 wdc->select(chp,1); 594 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 595 0, WDSD_IBM | 0x10); 596 bus_space_write_1(wdr->cmd_iot, 597 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 598 cl = bus_space_read_1(wdr->cmd_iot, 599 wdr->cmd_iohs[wd_cyl_lo], 0); 600 if (cl != 0x02) { 601 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 602 "got 0x%x != 0x02\n", 603 device_xname(chp->ch_atac->atac_dev), 604 chp->ch_channel, cl), 605 DEBUG_PROBE); 606 ret_value &= ~0x02; 607 } 608 bus_space_write_1(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 610 cl = bus_space_read_1(wdr->cmd_iot, 611 wdr->cmd_iohs[wd_cyl_lo], 0); 612 if (cl != 0x01) { 613 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 614 "got 0x%x != 0x01\n", 615 device_xname(chp->ch_atac->atac_dev), 616 chp->ch_channel, cl), 617 DEBUG_PROBE); 618 ret_value &= ~0x02; 619 } 620 bus_space_write_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_sector], 0, 0x01); 622 cl = bus_space_read_1(wdr->cmd_iot, 623 wdr->cmd_iohs[wd_sector], 0); 624 if (cl != 0x01) { 625 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 626 "got 0x%x != 0x01\n", 627 device_xname(chp->ch_atac->atac_dev), 628 chp->ch_channel, cl), 629 DEBUG_PROBE); 630 ret_value &= ~0x02; 631 } 632 bus_space_write_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_sector], 0, 0x02); 634 cl = bus_space_read_1(wdr->cmd_iot, 635 wdr->cmd_iohs[wd_sector], 0); 636 if (cl != 0x02) { 637 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 638 "got 0x%x != 0x02\n", 639 device_xname(chp->ch_atac->atac_dev), 640 chp->ch_channel, cl), 641 DEBUG_PROBE); 642 ret_value &= ~0x02; 643 } 644 cl = bus_space_read_1(wdr->cmd_iot, 645 wdr->cmd_iohs[wd_cyl_lo], 0); 646 if (cl != 0x01) { 647 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 648 "got 0x%x != 0x01\n", 649 device_xname(chp->ch_atac->atac_dev), 650 chp->ch_channel, cl), 651 DEBUG_PROBE); 652 ret_value &= ~0x02; 653 } 654 } 655 656 if (ret_value == 0) { 657 splx(s); 658 return 0; 659 } 660 } 661 662 663 #if 0 /* XXX this break some ATA or ATAPI devices */ 664 /* 665 * reset bus. Also send an ATAPI_RESET to devices, in case there are 666 * ATAPI device out there which don't react to the bus reset 667 */ 668 if (ret_value & 0x01) { 669 if (wdc->select) 670 wdc->select(chp,0); 671 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 672 0, WDSD_IBM); 673 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 674 ATAPI_SOFT_RESET); 675 } 676 if (ret_value & 0x02) { 677 if (wdc->select) 678 wdc->select(chp,0); 679 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 680 0, WDSD_IBM | 0x10); 681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 682 ATAPI_SOFT_RESET); 683 } 684 685 delay(5000); 686 #endif 687 688 wdc->reset(chp, RESET_POLL); 689 DELAY(2000); 690 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 691 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 692 splx(s); 693 694 ret_value = __wdcwait_reset(chp, ret_value, poll); 695 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 696 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 697 ret_value), DEBUG_PROBE); 698 699 /* if reset failed, there's nothing here */ 700 if (ret_value == 0) 701 return 0; 702 703 /* 704 * Test presence of drives. First test register signatures looking 705 * for ATAPI devices. If it's not an ATAPI and reset said there may 706 * be something here assume it's ATA or OLD. Ghost will be killed 707 * later in attach routine. 708 */ 709 for (drive = 0; drive < chp->ch_ndrive; drive++) { 710 if ((ret_value & (0x01 << drive)) == 0) 711 continue; 712 if (wdc->select) 713 wdc->select(chp,drive); 714 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 715 WDSD_IBM | (drive << 4)); 716 delay(10); /* 400ns delay */ 717 /* Save registers contents */ 718 sc = bus_space_read_1(wdr->cmd_iot, 719 wdr->cmd_iohs[wd_seccnt], 0); 720 sn = bus_space_read_1(wdr->cmd_iot, 721 wdr->cmd_iohs[wd_sector], 0); 722 cl = bus_space_read_1(wdr->cmd_iot, 723 wdr->cmd_iohs[wd_cyl_lo], 0); 724 ch = bus_space_read_1(wdr->cmd_iot, 725 wdr->cmd_iohs[wd_cyl_hi], 0); 726 727 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 728 "cl=0x%x ch=0x%x\n", 729 device_xname(chp->ch_atac->atac_dev), 730 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 731 /* 732 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 733 * we get wrong values here, so ignore it. 734 */ 735 s = splbio(); 736 if (cl == 0x14 && ch == 0xeb) { 737 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 738 } else { 739 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 740 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 741 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 742 } 743 splx(s); 744 } 745 return (ret_value); 746 } 747 748 void 749 wdcattach(struct ata_channel *chp) 750 { 751 struct atac_softc *atac = chp->ch_atac; 752 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 753 754 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 755 756 /* default data transfer methods */ 757 if (wdc->datain_pio == NULL) 758 wdc->datain_pio = wdc_datain_pio; 759 if (wdc->dataout_pio == NULL) 760 wdc->dataout_pio = wdc_dataout_pio; 761 /* default reset method */ 762 if (wdc->reset == NULL) 763 wdc->reset = wdc_do_reset; 764 765 /* initialise global data */ 766 if (atac->atac_bustype_ata == NULL) 767 atac->atac_bustype_ata = &wdc_ata_bustype; 768 if (atac->atac_probe == NULL) 769 atac->atac_probe = wdc_drvprobe; 770 #if NATAPIBUS > 0 771 if (atac->atac_atapibus_attach == NULL) 772 atac->atac_atapibus_attach = wdc_atapibus_attach; 773 #endif 774 775 ata_channel_attach(chp); 776 } 777 778 void 779 wdc_childdetached(device_t self, device_t child) 780 { 781 struct atac_softc *atac = device_private(self); 782 struct ata_channel *chp; 783 int i; 784 785 for (i = 0; i < atac->atac_nchannels; i++) { 786 chp = atac->atac_channels[i]; 787 if (child == chp->atabus) { 788 chp->atabus = NULL; 789 return; 790 } 791 } 792 } 793 794 int 795 wdcdetach(device_t self, int flags) 796 { 797 struct atac_softc *atac = device_private(self); 798 struct ata_channel *chp; 799 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 800 int i, error = 0; 801 802 for (i = 0; i < atac->atac_nchannels; i++) { 803 chp = atac->atac_channels[i]; 804 if (chp->atabus == NULL) 805 continue; 806 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 807 device_xname(atac->atac_dev), device_xname(chp->atabus)), 808 DEBUG_DETACH); 809 if ((error = config_detach(chp->atabus, flags)) != 0) 810 return error; 811 } 812 if (adapt->adapt_refcnt != 0) 813 return EBUSY; 814 return 0; 815 } 816 817 /* restart an interrupted I/O */ 818 void 819 wdcrestart(void *v) 820 { 821 struct ata_channel *chp = v; 822 int s; 823 824 s = splbio(); 825 atastart(chp); 826 splx(s); 827 } 828 829 830 /* 831 * Interrupt routine for the controller. Acknowledge the interrupt, check for 832 * errors on the current operation, mark it done if necessary, and start the 833 * next request. Also check for a partially done transfer, and continue with 834 * the next chunk if so. 835 */ 836 int 837 wdcintr(void *arg) 838 { 839 struct ata_channel *chp = arg; 840 struct atac_softc *atac = chp->ch_atac; 841 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 842 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 843 struct ata_xfer *xfer; 844 int ret; 845 846 if (!device_is_active(atac->atac_dev)) { 847 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 848 DEBUG_INTR); 849 return (0); 850 } 851 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 852 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 853 /* try to clear the pending interrupt anyway */ 854 (void)bus_space_read_1(wdr->cmd_iot, 855 wdr->cmd_iohs[wd_status], 0); 856 return (0); 857 } 858 859 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 860 xfer = chp->ch_queue->active_xfer; 861 #ifdef DIAGNOSTIC 862 if (xfer == NULL) 863 panic("wdcintr: no xfer"); 864 if (xfer->c_chp != chp) { 865 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 866 chp->ch_channel); 867 panic("wdcintr: wrong channel"); 868 } 869 #endif 870 #if NATA_DMA || NATA_PIOBM 871 if (chp->ch_flags & ATACH_DMA_WAIT) { 872 wdc->dma_status = 873 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 874 xfer->c_drive, WDC_DMAEND_END); 875 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 876 /* IRQ not for us, not detected by DMA engine */ 877 return 0; 878 } 879 chp->ch_flags &= ~ATACH_DMA_WAIT; 880 } 881 #endif 882 chp->ch_flags &= ~ATACH_IRQ_WAIT; 883 ret = xfer->c_intr(chp, xfer, 1); 884 if (ret == 0) /* irq was not for us, still waiting for irq */ 885 chp->ch_flags |= ATACH_IRQ_WAIT; 886 return (ret); 887 } 888 889 /* Put all disk in RESET state */ 890 void 891 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 892 { 893 struct ata_channel *chp = drvp->chnl_softc; 894 895 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 896 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 897 drvp->drive), DEBUG_FUNCS); 898 899 ata_reset_channel(chp, flags); 900 } 901 902 void 903 wdc_reset_channel(struct ata_channel *chp, int flags) 904 { 905 TAILQ_HEAD(, ata_xfer) reset_xfer; 906 struct ata_xfer *xfer, *next_xfer; 907 #if NATA_DMA || NATA_PIOBM 908 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 909 #endif 910 911 TAILQ_INIT(&reset_xfer); 912 913 chp->ch_flags &= ~ATACH_IRQ_WAIT; 914 915 /* 916 * if the current command if on an ATAPI device, issue a 917 * ATAPI_SOFT_RESET 918 */ 919 xfer = chp->ch_queue->active_xfer; 920 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 921 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 922 if (flags & AT_WAIT) 923 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 924 else 925 delay(1000); 926 } 927 928 /* reset the channel */ 929 if (flags & AT_WAIT) 930 (void) wdcreset(chp, RESET_SLEEP); 931 else 932 (void) wdcreset(chp, RESET_POLL); 933 934 /* 935 * wait a bit after reset; in case the DMA engines needs some time 936 * to recover. 937 */ 938 if (flags & AT_WAIT) 939 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 940 else 941 delay(1000); 942 /* 943 * look for pending xfers. If we have a shared queue, we'll also reset 944 * the other channel if the current xfer is running on it. 945 * Then we'll dequeue only the xfers for this channel. 946 */ 947 if ((flags & AT_RST_NOCMD) == 0) { 948 /* 949 * move all xfers queued for this channel to the reset queue, 950 * and then process the current xfer and then the reset queue. 951 * We have to use a temporary queue because c_kill_xfer() 952 * may requeue commands. 953 */ 954 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 955 xfer != NULL; xfer = next_xfer) { 956 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 957 if (xfer->c_chp != chp) 958 continue; 959 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 960 xfer, c_xferchain); 961 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 962 } 963 xfer = chp->ch_queue->active_xfer; 964 if (xfer) { 965 if (xfer->c_chp != chp) 966 ata_reset_channel(xfer->c_chp, flags); 967 else { 968 callout_stop(&chp->ch_callout); 969 #if NATA_DMA || NATA_PIOBM 970 /* 971 * If we're waiting for DMA, stop the 972 * DMA engine 973 */ 974 if (chp->ch_flags & ATACH_DMA_WAIT) { 975 (*wdc->dma_finish)( 976 wdc->dma_arg, 977 chp->ch_channel, 978 xfer->c_drive, 979 WDC_DMAEND_ABRT_QUIET); 980 chp->ch_flags &= ~ATACH_DMA_WAIT; 981 } 982 #endif 983 chp->ch_queue->active_xfer = NULL; 984 if ((flags & AT_RST_EMERG) == 0) 985 xfer->c_kill_xfer( 986 chp, xfer, KILL_RESET); 987 } 988 } 989 990 for (xfer = TAILQ_FIRST(&reset_xfer); 991 xfer != NULL; xfer = next_xfer) { 992 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 993 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 994 if ((flags & AT_RST_EMERG) == 0) 995 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 996 } 997 } 998 } 999 1000 static int 1001 wdcreset(struct ata_channel *chp, int poll) 1002 { 1003 struct atac_softc *atac = chp->ch_atac; 1004 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1005 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1006 int drv_mask1, drv_mask2; 1007 1008 wdc->reset(chp, poll); 1009 1010 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1011 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1012 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1013 (poll == RESET_SLEEP) ? 0 : 1); 1014 if (drv_mask2 != drv_mask1) { 1015 aprint_error("%s channel %d: reset failed for", 1016 device_xname(atac->atac_dev), chp->ch_channel); 1017 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1018 aprint_normal(" drive 0"); 1019 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1020 aprint_normal(" drive 1"); 1021 aprint_normal("\n"); 1022 } 1023 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1024 return (drv_mask1 != drv_mask2) ? 1 : 0; 1025 } 1026 1027 void 1028 wdc_do_reset(struct ata_channel *chp, int poll) 1029 { 1030 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1031 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1032 int s = 0; 1033 1034 if (poll != RESET_SLEEP) 1035 s = splbio(); 1036 if (wdc->select) 1037 wdc->select(chp,0); 1038 /* master */ 1039 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1040 delay(10); /* 400ns delay */ 1041 /* assert SRST, wait for reset to complete */ 1042 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1043 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1044 delay(2000); 1045 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1046 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1047 WDCTL_4BIT | WDCTL_IDS); 1048 delay(10); /* 400ns delay */ 1049 if (poll != RESET_SLEEP) { 1050 /* ACK interrupt in case there is one pending left */ 1051 if (wdc->irqack) 1052 wdc->irqack(chp); 1053 splx(s); 1054 } 1055 } 1056 1057 static int 1058 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1059 { 1060 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1061 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1062 int timeout, nloop; 1063 u_int8_t st0 = 0, st1 = 0; 1064 #ifdef ATADEBUG 1065 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1066 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1067 #endif 1068 1069 if (poll) 1070 nloop = WDCNDELAY_RST; 1071 else 1072 nloop = WDC_RESET_WAIT * hz / 1000; 1073 /* wait for BSY to deassert */ 1074 for (timeout = 0; timeout < nloop; timeout++) { 1075 if ((drv_mask & 0x01) != 0) { 1076 if (wdc->select) 1077 wdc->select(chp,0); 1078 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1079 0, WDSD_IBM); /* master */ 1080 delay(10); 1081 st0 = bus_space_read_1(wdr->cmd_iot, 1082 wdr->cmd_iohs[wd_status], 0); 1083 #ifdef ATADEBUG 1084 sc0 = bus_space_read_1(wdr->cmd_iot, 1085 wdr->cmd_iohs[wd_seccnt], 0); 1086 sn0 = bus_space_read_1(wdr->cmd_iot, 1087 wdr->cmd_iohs[wd_sector], 0); 1088 cl0 = bus_space_read_1(wdr->cmd_iot, 1089 wdr->cmd_iohs[wd_cyl_lo], 0); 1090 ch0 = bus_space_read_1(wdr->cmd_iot, 1091 wdr->cmd_iohs[wd_cyl_hi], 0); 1092 #endif 1093 } 1094 if ((drv_mask & 0x02) != 0) { 1095 if (wdc->select) 1096 wdc->select(chp,1); 1097 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1098 0, WDSD_IBM | 0x10); /* slave */ 1099 delay(10); 1100 st1 = bus_space_read_1(wdr->cmd_iot, 1101 wdr->cmd_iohs[wd_status], 0); 1102 #ifdef ATADEBUG 1103 sc1 = bus_space_read_1(wdr->cmd_iot, 1104 wdr->cmd_iohs[wd_seccnt], 0); 1105 sn1 = bus_space_read_1(wdr->cmd_iot, 1106 wdr->cmd_iohs[wd_sector], 0); 1107 cl1 = bus_space_read_1(wdr->cmd_iot, 1108 wdr->cmd_iohs[wd_cyl_lo], 0); 1109 ch1 = bus_space_read_1(wdr->cmd_iot, 1110 wdr->cmd_iohs[wd_cyl_hi], 0); 1111 #endif 1112 } 1113 1114 if ((drv_mask & 0x01) == 0) { 1115 /* no master */ 1116 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1117 /* No master, slave is ready, it's done */ 1118 goto end; 1119 } 1120 if ((drv_mask & 0x02) == 0) { 1121 /* No master, no slave: it's done */ 1122 goto end; 1123 } 1124 } else if ((drv_mask & 0x02) == 0) { 1125 /* no slave */ 1126 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1127 /* No slave, master is ready, it's done */ 1128 goto end; 1129 } 1130 } else { 1131 /* Wait for both master and slave to be ready */ 1132 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1133 goto end; 1134 } 1135 } 1136 if (poll) 1137 delay(WDCDELAY); 1138 else 1139 tsleep(&nloop, PRIBIO, "atarst", 1); 1140 } 1141 /* Reset timed out. Maybe it's because drv_mask was not right */ 1142 if (st0 & WDCS_BSY) 1143 drv_mask &= ~0x01; 1144 if (st1 & WDCS_BSY) 1145 drv_mask &= ~0x02; 1146 end: 1147 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1148 "cl=0x%x ch=0x%x\n", 1149 device_xname(chp->ch_atac->atac_dev), 1150 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1151 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1152 "cl=0x%x ch=0x%x\n", 1153 device_xname(chp->ch_atac->atac_dev), 1154 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1155 1156 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1157 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1158 st0, st1), DEBUG_PROBE); 1159 1160 return drv_mask; 1161 } 1162 1163 /* 1164 * Wait for a drive to be !BSY, and have mask in its status register. 1165 * return -1 for a timeout after "timeout" ms. 1166 */ 1167 static int 1168 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1169 { 1170 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1171 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1172 u_char status; 1173 int xtime = 0; 1174 1175 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1176 device_xname(chp->ch_atac->atac_dev), 1177 chp->ch_channel), DEBUG_STATUS); 1178 chp->ch_error = 0; 1179 1180 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1181 1182 for (;;) { 1183 chp->ch_status = status = 1184 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1185 if ((status & (WDCS_BSY | mask)) == bits) 1186 break; 1187 if (++xtime > timeout) { 1188 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1189 "status %x error %x (mask 0x%x bits 0x%x)\n", 1190 xtime, status, 1191 bus_space_read_1(wdr->cmd_iot, 1192 wdr->cmd_iohs[wd_error], 0), mask, bits), 1193 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1194 return(WDCWAIT_TOUT); 1195 } 1196 delay(WDCDELAY); 1197 } 1198 #ifdef ATADEBUG 1199 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1200 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1201 #endif 1202 if (status & WDCS_ERR) 1203 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1204 wdr->cmd_iohs[wd_error], 0); 1205 #ifdef WDCNDELAY_DEBUG 1206 /* After autoconfig, there should be no long delays. */ 1207 if (!cold && xtime > WDCNDELAY_DEBUG) { 1208 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1209 if (xfer == NULL) 1210 printf("%s channel %d: warning: busy-wait took %dus\n", 1211 device_xname(chp->ch_atac->atac_dev), 1212 chp->ch_channel, WDCDELAY * xtime); 1213 else 1214 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1215 device_xname(chp->ch_atac->atac_dev), 1216 chp->ch_channel, xfer->c_drive, 1217 WDCDELAY * xtime); 1218 } 1219 #endif 1220 return(WDCWAIT_OK); 1221 } 1222 1223 /* 1224 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1225 * thread if possible 1226 */ 1227 int 1228 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1229 { 1230 int error, i, timeout_hz = mstohz(timeout); 1231 1232 if (timeout_hz == 0 || 1233 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1234 error = __wdcwait(chp, mask, bits, timeout); 1235 else { 1236 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1237 if (error != 0) { 1238 if ((chp->ch_flags & ATACH_TH_RUN) || 1239 (flags & AT_WAIT)) { 1240 /* 1241 * we're running in the channel thread 1242 * or some userland thread context 1243 */ 1244 for (i = 0; i < timeout_hz; i++) { 1245 if (__wdcwait(chp, mask, bits, 1246 WDCDELAY_POLL) == 0) { 1247 error = 0; 1248 break; 1249 } 1250 tsleep(&chp, PRIBIO, "atapoll", 1); 1251 } 1252 } else { 1253 /* 1254 * we're probably in interrupt context, 1255 * ask the thread to come back here 1256 */ 1257 #ifdef DIAGNOSTIC 1258 if (chp->ch_queue->queue_freeze > 0) 1259 panic("wdcwait: queue_freeze"); 1260 #endif 1261 chp->ch_queue->queue_freeze++; 1262 wakeup(&chp->ch_thread); 1263 return(WDCWAIT_THR); 1264 } 1265 } 1266 } 1267 return (error); 1268 } 1269 1270 1271 #if NATA_DMA 1272 /* 1273 * Busy-wait for DMA to complete 1274 */ 1275 int 1276 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1277 { 1278 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1279 int xtime; 1280 1281 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1282 wdc->dma_status = 1283 (*wdc->dma_finish)(wdc->dma_arg, 1284 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1285 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1286 return 0; 1287 delay(WDCDELAY); 1288 } 1289 /* timeout, force a DMA halt */ 1290 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1291 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1292 return 1; 1293 } 1294 #endif 1295 1296 void 1297 wdctimeout(void *arg) 1298 { 1299 struct ata_channel *chp = (struct ata_channel *)arg; 1300 #if NATA_DMA || NATA_PIOBM 1301 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1302 #endif 1303 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1304 int s; 1305 1306 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1307 1308 s = splbio(); 1309 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1310 __wdcerror(chp, "lost interrupt"); 1311 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1312 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1313 xfer->c_bcount, 1314 xfer->c_skip); 1315 #if NATA_DMA || NATA_PIOBM 1316 if (chp->ch_flags & ATACH_DMA_WAIT) { 1317 wdc->dma_status = 1318 (*wdc->dma_finish)(wdc->dma_arg, 1319 chp->ch_channel, xfer->c_drive, 1320 WDC_DMAEND_ABRT); 1321 chp->ch_flags &= ~ATACH_DMA_WAIT; 1322 } 1323 #endif 1324 /* 1325 * Call the interrupt routine. If we just missed an interrupt, 1326 * it will do what's needed. Else, it will take the needed 1327 * action (reset the device). 1328 * Before that we need to reinstall the timeout callback, 1329 * in case it will miss another irq while in this transfer 1330 * We arbitray chose it to be 1s 1331 */ 1332 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1333 xfer->c_flags |= C_TIMEOU; 1334 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1335 xfer->c_intr(chp, xfer, 1); 1336 } else 1337 __wdcerror(chp, "missing untimeout"); 1338 splx(s); 1339 } 1340 1341 int 1342 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1343 { 1344 struct ata_channel *chp = drvp->chnl_softc; 1345 struct ata_xfer *xfer; 1346 int s, ret; 1347 1348 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1349 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1350 drvp->drive), DEBUG_FUNCS); 1351 1352 /* set up an xfer and queue. Wait for completion */ 1353 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1354 ATAXF_NOSLEEP); 1355 if (xfer == NULL) { 1356 return ATACMD_TRY_AGAIN; 1357 } 1358 1359 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1360 ata_c->flags |= AT_POLL; 1361 if (ata_c->flags & AT_POLL) 1362 xfer->c_flags |= C_POLL; 1363 if (ata_c->flags & AT_WAIT) 1364 xfer->c_flags |= C_WAIT; 1365 xfer->c_drive = drvp->drive; 1366 xfer->c_databuf = ata_c->data; 1367 xfer->c_bcount = ata_c->bcount; 1368 xfer->c_cmd = ata_c; 1369 xfer->c_start = __wdccommand_start; 1370 xfer->c_intr = __wdccommand_intr; 1371 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1372 1373 s = splbio(); 1374 ata_exec_xfer(chp, xfer); 1375 #ifdef DIAGNOSTIC 1376 if ((ata_c->flags & AT_POLL) != 0 && 1377 (ata_c->flags & AT_DONE) == 0) 1378 panic("wdc_exec_command: polled command not done"); 1379 #endif 1380 if (ata_c->flags & AT_DONE) { 1381 ret = ATACMD_COMPLETE; 1382 } else { 1383 if (ata_c->flags & AT_WAIT) { 1384 while ((ata_c->flags & AT_DONE) == 0) { 1385 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1386 } 1387 ret = ATACMD_COMPLETE; 1388 } else { 1389 ret = ATACMD_QUEUED; 1390 } 1391 } 1392 splx(s); 1393 return ret; 1394 } 1395 1396 static void 1397 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1398 { 1399 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1400 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1401 int drive = xfer->c_drive; 1402 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1403 struct ata_command *ata_c = xfer->c_cmd; 1404 1405 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1406 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1407 xfer->c_drive), 1408 DEBUG_FUNCS); 1409 1410 if (wdc->select) 1411 wdc->select(chp,drive); 1412 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1413 WDSD_IBM | (drive << 4)); 1414 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1415 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1416 case WDCWAIT_OK: 1417 break; 1418 case WDCWAIT_TOUT: 1419 ata_c->flags |= AT_TIMEOU; 1420 __wdccommand_done(chp, xfer); 1421 return; 1422 case WDCWAIT_THR: 1423 return; 1424 } 1425 if (ata_c->flags & AT_POLL) { 1426 /* polled command, disable interrupts */ 1427 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1428 WDCTL_4BIT | WDCTL_IDS); 1429 } 1430 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1431 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1432 1433 if ((ata_c->flags & AT_POLL) == 0) { 1434 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1435 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1436 wdctimeout, chp); 1437 return; 1438 } 1439 /* 1440 * Polled command. Wait for drive ready or drq. Done in intr(). 1441 * Wait for at last 400ns for status bit to be valid. 1442 */ 1443 delay(10); /* 400ns delay */ 1444 __wdccommand_intr(chp, xfer, 0); 1445 } 1446 1447 static int 1448 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1449 { 1450 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1451 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1452 struct ata_command *ata_c = xfer->c_cmd; 1453 int bcount = ata_c->bcount; 1454 char *data = ata_c->data; 1455 int wflags; 1456 int drive_flags; 1457 1458 if (ata_c->r_command == WDCC_IDENTIFY || 1459 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1460 /* 1461 * The IDENTIFY data has been designed as an array of 1462 * u_int16_t, so we can byteswap it on the fly. 1463 * Historically it's what we have always done so keeping it 1464 * here ensure binary backward compatibility. 1465 */ 1466 drive_flags = DRIVE_NOSTREAM | 1467 chp->ch_drive[xfer->c_drive].drive_flags; 1468 } else { 1469 /* 1470 * Other data structure are opaque and should be transfered 1471 * as is. 1472 */ 1473 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1474 } 1475 1476 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1477 /* both wait and poll, we can tsleep here */ 1478 wflags = AT_WAIT | AT_POLL; 1479 } else { 1480 wflags = AT_POLL; 1481 } 1482 1483 again: 1484 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1485 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1486 xfer->c_drive), DEBUG_INTR); 1487 /* 1488 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1489 * Reselect again, it doesn't hurt for others commands, and the time 1490 * penalty for the extra regiter write is acceptable, 1491 * wdc_exec_command() isn't called often (mosly for autoconfig) 1492 */ 1493 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1494 WDSD_IBM | (xfer->c_drive << 4)); 1495 if ((ata_c->flags & AT_XFDONE) != 0) { 1496 /* 1497 * We have completed a data xfer. The drive should now be 1498 * in its initial state 1499 */ 1500 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1501 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1502 wflags) == WDCWAIT_TOUT) { 1503 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1504 return 0; /* IRQ was not for us */ 1505 ata_c->flags |= AT_TIMEOU; 1506 } 1507 goto out; 1508 } 1509 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1510 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1511 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1512 return 0; /* IRQ was not for us */ 1513 ata_c->flags |= AT_TIMEOU; 1514 goto out; 1515 } 1516 if (wdc->irqack) 1517 wdc->irqack(chp); 1518 if (ata_c->flags & AT_READ) { 1519 if ((chp->ch_status & WDCS_DRQ) == 0) { 1520 ata_c->flags |= AT_TIMEOU; 1521 goto out; 1522 } 1523 wdc->datain_pio(chp, drive_flags, data, bcount); 1524 /* at this point the drive should be in its initial state */ 1525 ata_c->flags |= AT_XFDONE; 1526 /* 1527 * XXX checking the status register again here cause some 1528 * hardware to timeout. 1529 */ 1530 } else if (ata_c->flags & AT_WRITE) { 1531 if ((chp->ch_status & WDCS_DRQ) == 0) { 1532 ata_c->flags |= AT_TIMEOU; 1533 goto out; 1534 } 1535 wdc->dataout_pio(chp, drive_flags, data, bcount); 1536 ata_c->flags |= AT_XFDONE; 1537 if ((ata_c->flags & AT_POLL) == 0) { 1538 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1539 callout_reset(&chp->ch_callout, 1540 mstohz(ata_c->timeout), wdctimeout, chp); 1541 return 1; 1542 } else { 1543 goto again; 1544 } 1545 } 1546 out: 1547 __wdccommand_done(chp, xfer); 1548 return 1; 1549 } 1550 1551 static void 1552 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1553 { 1554 struct atac_softc *atac = chp->ch_atac; 1555 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1556 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1557 struct ata_command *ata_c = xfer->c_cmd; 1558 1559 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1560 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1561 ata_c->flags), DEBUG_FUNCS); 1562 1563 1564 if (chp->ch_status & WDCS_DWF) 1565 ata_c->flags |= AT_DF; 1566 if (chp->ch_status & WDCS_ERR) { 1567 ata_c->flags |= AT_ERROR; 1568 ata_c->r_error = chp->ch_error; 1569 } 1570 if ((ata_c->flags & AT_READREG) != 0 && 1571 device_is_active(atac->atac_dev) && 1572 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1573 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1574 wdr->cmd_iohs[wd_sdh], 0); 1575 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1576 wdr->cmd_iohs[wd_seccnt], 0); 1577 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1578 wdr->cmd_iohs[wd_sector], 0); 1579 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1580 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1581 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1582 wdr->cmd_iohs[wd_cyl_lo], 0); 1583 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1584 wdr->cmd_iohs[wd_error], 0); 1585 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1586 wdr->cmd_iohs[wd_features], 0); 1587 } 1588 callout_stop(&chp->ch_callout); 1589 chp->ch_queue->active_xfer = NULL; 1590 if (ata_c->flags & AT_POLL) { 1591 /* enable interrupts */ 1592 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1593 WDCTL_4BIT); 1594 delay(10); /* some drives need a little delay here */ 1595 } 1596 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1597 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1598 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1599 wakeup(&chp->ch_queue->active_xfer); 1600 } else 1601 __wdccommand_done_end(chp, xfer); 1602 } 1603 1604 static void 1605 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1606 { 1607 struct ata_command *ata_c = xfer->c_cmd; 1608 1609 ata_c->flags |= AT_DONE; 1610 ata_free_xfer(chp, xfer); 1611 if (ata_c->flags & AT_WAIT) 1612 wakeup(ata_c); 1613 else if (ata_c->callback) 1614 ata_c->callback(ata_c->callback_arg); 1615 atastart(chp); 1616 return; 1617 } 1618 1619 static void 1620 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1621 int reason) 1622 { 1623 struct ata_command *ata_c = xfer->c_cmd; 1624 1625 switch (reason) { 1626 case KILL_GONE: 1627 ata_c->flags |= AT_GONE; 1628 break; 1629 case KILL_RESET: 1630 ata_c->flags |= AT_RESET; 1631 break; 1632 default: 1633 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1634 reason); 1635 panic("__wdccommand_kill_xfer"); 1636 } 1637 __wdccommand_done_end(chp, xfer); 1638 } 1639 1640 /* 1641 * Send a command. The drive should be ready. 1642 * Assumes interrupts are blocked. 1643 */ 1644 void 1645 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1646 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1647 u_int8_t features) 1648 { 1649 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1650 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1651 1652 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1653 "sector=%d count=%d features=%d\n", 1654 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1655 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1656 1657 if (wdc->select) 1658 wdc->select(chp,drive); 1659 1660 /* Select drive, head, and addressing mode. */ 1661 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1662 WDSD_IBM | (drive << 4) | head); 1663 /* Load parameters into the wd_features register. */ 1664 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1665 features); 1666 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1667 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1668 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1669 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1670 0, cylin >> 8); 1671 1672 /* Send command. */ 1673 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1674 return; 1675 } 1676 1677 /* 1678 * Send a 48-bit addressing command. The drive should be ready. 1679 * Assumes interrupts are blocked. 1680 */ 1681 void 1682 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1683 u_int64_t blkno, u_int16_t count) 1684 { 1685 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1686 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1687 1688 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1689 "count=%d\n", device_xname(chp->ch_atac->atac_dev), 1690 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1691 DEBUG_FUNCS); 1692 1693 if (wdc->select) 1694 wdc->select(chp,drive); 1695 1696 /* Select drive, head, and addressing mode. */ 1697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1698 (drive << 4) | WDSD_LBA); 1699 1700 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1701 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1702 0); 1703 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1704 0, count); 1705 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1706 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1707 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1708 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1709 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1710 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1711 } else { 1712 /* previous */ 1713 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1714 0); 1715 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1716 0, count >> 8); 1717 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1718 0, blkno >> 24); 1719 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1720 0, blkno >> 32); 1721 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1722 0, blkno >> 40); 1723 1724 /* current */ 1725 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1726 0); 1727 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1728 count); 1729 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1730 blkno); 1731 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1732 0, blkno >> 8); 1733 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1734 0, blkno >> 16); 1735 } 1736 1737 /* Send command. */ 1738 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1739 return; 1740 } 1741 1742 /* 1743 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1744 * tested by the caller. 1745 */ 1746 void 1747 wdccommandshort(struct ata_channel *chp, int drive, int command) 1748 { 1749 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1750 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1751 1752 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1753 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1754 command), DEBUG_FUNCS); 1755 1756 if (wdc->select) 1757 wdc->select(chp,drive); 1758 1759 /* Select drive. */ 1760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1761 WDSD_IBM | (drive << 4)); 1762 1763 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1764 } 1765 1766 static void 1767 __wdcerror(struct ata_channel *chp, const char *msg) 1768 { 1769 struct atac_softc *atac = chp->ch_atac; 1770 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1771 1772 if (xfer == NULL) 1773 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1774 chp->ch_channel, msg); 1775 else 1776 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1777 chp->ch_channel, xfer->c_drive, msg); 1778 } 1779 1780 /* 1781 * the bit bucket 1782 */ 1783 void 1784 wdcbit_bucket(struct ata_channel *chp, int size) 1785 { 1786 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1787 1788 for (; size >= 2; size -= 2) 1789 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1790 if (size) 1791 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1792 } 1793 1794 static void 1795 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1796 { 1797 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1798 1799 #ifndef __NO_STRICT_ALIGNMENT 1800 if ((uintptr_t)bf & 1) 1801 goto unaligned; 1802 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1803 goto unaligned; 1804 #endif 1805 1806 if (flags & DRIVE_NOSTREAM) { 1807 if (flags & DRIVE_CAP32) { 1808 bus_space_read_multi_4(wdr->data32iot, 1809 wdr->data32ioh, 0, bf, len >> 2); 1810 bf = (char *)bf + (len & ~3); 1811 len &= 3; 1812 } 1813 if (len) { 1814 bus_space_read_multi_2(wdr->cmd_iot, 1815 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1816 } 1817 } else { 1818 if (flags & DRIVE_CAP32) { 1819 bus_space_read_multi_stream_4(wdr->data32iot, 1820 wdr->data32ioh, 0, bf, len >> 2); 1821 bf = (char *)bf + (len & ~3); 1822 len &= 3; 1823 } 1824 if (len) { 1825 bus_space_read_multi_stream_2(wdr->cmd_iot, 1826 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1827 } 1828 } 1829 return; 1830 1831 #ifndef __NO_STRICT_ALIGNMENT 1832 unaligned: 1833 if (flags & DRIVE_NOSTREAM) { 1834 if (flags & DRIVE_CAP32) { 1835 while (len > 3) { 1836 uint32_t val; 1837 1838 val = bus_space_read_4(wdr->data32iot, 1839 wdr->data32ioh, 0); 1840 memcpy(bf, &val, 4); 1841 bf = (char *)bf + 4; 1842 len -= 4; 1843 } 1844 } 1845 while (len > 1) { 1846 uint16_t val; 1847 1848 val = bus_space_read_2(wdr->cmd_iot, 1849 wdr->cmd_iohs[wd_data], 0); 1850 memcpy(bf, &val, 2); 1851 bf = (char *)bf + 2; 1852 len -= 2; 1853 } 1854 } else { 1855 if (flags & DRIVE_CAP32) { 1856 while (len > 3) { 1857 uint32_t val; 1858 1859 val = bus_space_read_stream_4(wdr->data32iot, 1860 wdr->data32ioh, 0); 1861 memcpy(bf, &val, 4); 1862 bf = (char *)bf + 4; 1863 len -= 4; 1864 } 1865 } 1866 while (len > 1) { 1867 uint16_t val; 1868 1869 val = bus_space_read_stream_2(wdr->cmd_iot, 1870 wdr->cmd_iohs[wd_data], 0); 1871 memcpy(bf, &val, 2); 1872 bf = (char *)bf + 2; 1873 len -= 2; 1874 } 1875 } 1876 #endif 1877 } 1878 1879 static void 1880 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1881 { 1882 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1883 1884 #ifndef __NO_STRICT_ALIGNMENT 1885 if ((uintptr_t)bf & 1) 1886 goto unaligned; 1887 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1888 goto unaligned; 1889 #endif 1890 1891 if (flags & DRIVE_NOSTREAM) { 1892 if (flags & DRIVE_CAP32) { 1893 bus_space_write_multi_4(wdr->data32iot, 1894 wdr->data32ioh, 0, bf, len >> 2); 1895 bf = (char *)bf + (len & ~3); 1896 len &= 3; 1897 } 1898 if (len) { 1899 bus_space_write_multi_2(wdr->cmd_iot, 1900 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1901 } 1902 } else { 1903 if (flags & DRIVE_CAP32) { 1904 bus_space_write_multi_stream_4(wdr->data32iot, 1905 wdr->data32ioh, 0, bf, len >> 2); 1906 bf = (char *)bf + (len & ~3); 1907 len &= 3; 1908 } 1909 if (len) { 1910 bus_space_write_multi_stream_2(wdr->cmd_iot, 1911 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1912 } 1913 } 1914 return; 1915 1916 #ifndef __NO_STRICT_ALIGNMENT 1917 unaligned: 1918 if (flags & DRIVE_NOSTREAM) { 1919 if (flags & DRIVE_CAP32) { 1920 while (len > 3) { 1921 uint32_t val; 1922 1923 memcpy(&val, bf, 4); 1924 bus_space_write_4(wdr->data32iot, 1925 wdr->data32ioh, 0, val); 1926 bf = (char *)bf + 4; 1927 len -= 4; 1928 } 1929 } 1930 while (len > 1) { 1931 uint16_t val; 1932 1933 memcpy(&val, bf, 2); 1934 bus_space_write_2(wdr->cmd_iot, 1935 wdr->cmd_iohs[wd_data], 0, val); 1936 bf = (char *)bf + 2; 1937 len -= 2; 1938 } 1939 } else { 1940 if (flags & DRIVE_CAP32) { 1941 while (len > 3) { 1942 uint32_t val; 1943 1944 memcpy(&val, bf, 4); 1945 bus_space_write_stream_4(wdr->data32iot, 1946 wdr->data32ioh, 0, val); 1947 bf = (char *)bf + 4; 1948 len -= 4; 1949 } 1950 } 1951 while (len > 1) { 1952 uint16_t val; 1953 1954 memcpy(&val, bf, 2); 1955 bus_space_write_stream_2(wdr->cmd_iot, 1956 wdr->cmd_iohs[wd_data], 0, val); 1957 bf = (char *)bf + 2; 1958 len -= 2; 1959 } 1960 } 1961 #endif 1962 } 1963
Indexes created Thu Sep 25 02:09:54 GMT 2025