wdc.c revision 1.273
1 /* $NetBSD: wdc.c,v 1.273 2012/07/29 18:20:13 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.273 2012/07/29 18:20:13 christos Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then tsleep for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 SCSIPI_BUSTYPE_ATA, 130 NULL, /* wdc_ata_bio */ 131 NULL, /* wdc_reset_drive */ 132 wdc_reset_channel, 133 wdc_exec_command, 134 NULL, /* ata_get_params */ 135 NULL, /* wdc_ata_addref */ 136 NULL, /* wdc_ata_delref */ 137 NULL /* ata_kill_pending */ 138 }; 139 #endif 140 141 /* Flags to wdcreset(). */ 142 #define RESET_POLL 1 143 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 144 145 static int wdcprobe1(struct ata_channel *, int); 146 static int wdcreset(struct ata_channel *, int); 147 static void __wdcerror(struct ata_channel *, const char *); 148 static int __wdcwait_reset(struct ata_channel *, int, int); 149 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 150 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_kill_xfer(struct ata_channel *, 152 struct ata_xfer *, int); 153 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 154 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 155 static int __wdcwait(struct ata_channel *, int, int, int); 156 157 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 158 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 159 160 #define DEBUG_INTR 0x01 161 #define DEBUG_XFERS 0x02 162 #define DEBUG_STATUS 0x04 163 #define DEBUG_FUNCS 0x08 164 #define DEBUG_PROBE 0x10 165 #define DEBUG_DETACH 0x20 166 #define DEBUG_DELAY 0x40 167 #ifdef ATADEBUG 168 extern int atadebug_mask; /* init'ed in ata.c */ 169 int wdc_nxfer = 0; 170 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 171 #else 172 #define ATADEBUG_PRINT(args, level) 173 #endif 174 175 /* 176 * Initialize the "shadow register" handles for a standard wdc controller. 177 */ 178 void 179 wdc_init_shadow_regs(struct ata_channel *chp) 180 { 181 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 182 183 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 184 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 185 } 186 187 /* 188 * Allocate a wdc_regs array, based on the number of channels. 189 */ 190 void 191 wdc_allocate_regs(struct wdc_softc *wdc) 192 { 193 194 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 195 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 196 } 197 198 #if NSATA > 0 199 /* 200 * probe drives on SATA controllers with standard SATA registers: 201 * bring the PHYs online, read the drive signature and set drive flags 202 * appropriately. 203 */ 204 void 205 wdc_sataprobe(struct ata_channel *chp) 206 { 207 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 208 uint8_t st = 0, sc, sn, cl, ch; 209 int i, s; 210 211 /* XXX This should be done by other code. */ 212 for (i = 0; i < chp->ch_ndrive; i++) { 213 chp->ch_drive[i].chnl_softc = chp; 214 chp->ch_drive[i].drive = i; 215 } 216 217 /* reset the PHY and bring online */ 218 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 219 wdr->sata_status)) { 220 case SStatus_DET_DEV: 221 /* wait 5s for BSY to clear */ 222 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 223 bus_space_write_1(wdr->cmd_iot, 224 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 225 delay(10); /* 400ns delay */ 226 st = bus_space_read_1(wdr->cmd_iot, 227 wdr->cmd_iohs[wd_status], 0); 228 if ((st & WDCS_BSY) == 0) 229 break; 230 tsleep(&chp, PRIBIO, "sataprb", 1); 231 } 232 if (i == WDC_PROBE_WAIT * hz) 233 aprint_error_dev(chp->ch_atac->atac_dev, 234 "BSY never cleared, status 0x%02x\n", st); 235 sc = bus_space_read_1(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_seccnt], 0); 237 sn = bus_space_read_1(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_sector], 0); 239 cl = bus_space_read_1(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_lo], 0); 241 ch = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_hi], 0); 243 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 244 "cl=0x%x ch=0x%x\n", 245 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 246 sc, sn, cl, ch), DEBUG_PROBE); 247 /* 248 * sc and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 s = splbio(); 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 254 else 255 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 256 splx(s); 257 258 /* 259 * issue a reset in case only the interface part of the drive 260 * is up 261 */ 262 if (wdcreset(chp, RESET_SLEEP) != 0) 263 chp->ch_drive[0].drive_flags = 0; 264 break; 265 266 default: 267 break; 268 } 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; /* XXX: large struct */ 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, s; 296 297 if (wdcprobe1(chp, 0) == 0) { 298 /* No drives, abort the attach here. */ 299 return; 300 } 301 302 s = splbio(); 303 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 304 for (i = 0; i < mstohz(3000); i++) { 305 /* 306 * select drive 1 first, so that master is selected on 307 * exit from the loop 308 */ 309 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 310 if (wdc->select) 311 wdc->select(chp,1); 312 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 313 0, WDSD_IBM | 0x10); 314 delay(10); /* 400ns delay */ 315 st1 = bus_space_read_1(wdr->cmd_iot, 316 wdr->cmd_iohs[wd_status], 0); 317 } 318 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 319 if (wdc->select) 320 wdc->select(chp,0); 321 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 322 0, WDSD_IBM); 323 delay(10); /* 400ns delay */ 324 st0 = bus_space_read_1(wdr->cmd_iot, 325 wdr->cmd_iohs[wd_status], 0); 326 } 327 328 329 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 330 == 0 || 331 (st0 & WDCS_DRDY)) && 332 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 333 == 0 || 334 (st1 & WDCS_DRDY))) 335 break; 336 #ifdef WDC_NO_IDS 337 /* cannot tsleep here (can't enable IPL_BIO interrups), 338 * delay instead 339 */ 340 delay(1000000 / hz); 341 #else 342 tsleep(¶ms, PRIBIO, "atadrdy", 1); 343 #endif 344 } 345 if ((st0 & WDCS_DRDY) == 0) 346 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 347 if ((st1 & WDCS_DRDY) == 0) 348 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 349 splx(s); 350 351 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 352 device_xname(atac->atac_dev), 353 chp->ch_channel, st0, st1), DEBUG_PROBE); 354 355 /* Wait a bit, some devices are weird just after a reset. */ 356 delay(5000); 357 358 for (i = 0; i < chp->ch_ndrive; i++) { 359 /* XXX This should be done by other code. */ 360 chp->ch_drive[i].chnl_softc = chp; 361 chp->ch_drive[i].drive = i; 362 363 #if NATA_DMA 364 /* 365 * Init error counter so that an error withing the first xfers 366 * will trigger a downgrade 367 */ 368 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 369 #endif 370 371 /* If controller can't do 16bit flag the drives as 32bit */ 372 if ((atac->atac_cap & 373 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 374 s = splbio(); 375 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 376 splx(s); 377 } 378 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 379 continue; 380 381 /* Shortcut in case we've been shutdown */ 382 if (chp->ch_flags & ATACH_SHUTDOWN) 383 return; 384 385 /* 386 * Issue an identify, to try to detect ghosts. 387 * Note that we can't use interrupts here, because if there 388 * is no devices, we will get a command aborted without 389 * interrupts. 390 */ 391 error = ata_get_params(&chp->ch_drive[i], 392 AT_WAIT | AT_POLL, ¶ms); 393 if (error != CMD_OK) { 394 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 395 396 /* Shortcut in case we've been shutdown */ 397 if (chp->ch_flags & ATACH_SHUTDOWN) 398 return; 399 400 error = ata_get_params(&chp->ch_drive[i], 401 AT_WAIT | AT_POLL, ¶ms); 402 } 403 if (error == CMD_OK) { 404 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 405 s = splbio(); 406 for (j = 0; j < chp->ch_ndrive; j++) 407 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 408 splx(s); 409 } else { 410 s = splbio(); 411 chp->ch_drive[i].drive_flags &= 412 ~(DRIVE_ATA | DRIVE_ATAPI); 413 splx(s); 414 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 415 device_xname(atac->atac_dev), 416 chp->ch_channel, i, error), DEBUG_PROBE); 417 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 418 continue; 419 /* 420 * Pre-ATA drive ? 421 * Test registers writability (Error register not 422 * writable, but cyllo is), then try an ATA command. 423 */ 424 if (wdc->select) 425 wdc->select(chp,i); 426 bus_space_write_1(wdr->cmd_iot, 427 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 428 delay(10); /* 400ns delay */ 429 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 430 0, 0x58); 431 bus_space_write_1(wdr->cmd_iot, 432 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 433 if (bus_space_read_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_error], 0) == 0x58 || 435 bus_space_read_1(wdr->cmd_iot, 436 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 437 ATADEBUG_PRINT(("%s:%d:%d: register " 438 "writability failed\n", 439 device_xname(atac->atac_dev), 440 chp->ch_channel, i), DEBUG_PROBE); 441 s = splbio(); 442 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 443 splx(s); 444 continue; 445 } 446 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 447 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 448 device_xname(atac->atac_dev), 449 chp->ch_channel, i), DEBUG_PROBE); 450 s = splbio(); 451 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 452 splx(s); 453 continue; 454 } 455 bus_space_write_1(wdr->cmd_iot, 456 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 457 delay(10); /* 400ns delay */ 458 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 459 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 460 device_xname(atac->atac_dev), 461 chp->ch_channel, i), DEBUG_PROBE); 462 s = splbio(); 463 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 464 splx(s); 465 } else { 466 s = splbio(); 467 for (j = 0; j < chp->ch_ndrive; j++) 468 chp->ch_drive[j].drive_flags &= 469 ~(DRIVE_ATA | DRIVE_ATAPI); 470 splx(s); 471 } 472 } 473 } 474 } 475 476 int 477 wdcprobe(struct ata_channel *chp) 478 { 479 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 480 /* default reset method */ 481 if (wdc->reset == NULL) 482 wdc->reset = wdc_do_reset; 483 484 return (wdcprobe1(chp, 1)); 485 } 486 487 static int 488 wdcprobe1(struct ata_channel *chp, int poll) 489 { 490 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 491 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 492 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 493 u_int8_t ret_value = 0x03; 494 u_int8_t drive; 495 int s; 496 /* XXX if poll, wdc_probe_count is 0. */ 497 int wdc_probe_count = 498 poll ? (WDC_PROBE_WAIT / WDCDELAY) 499 : (WDC_PROBE_WAIT * hz); 500 501 /* 502 * Sanity check to see if the wdc channel responds at all. 503 */ 504 505 s = splbio(); 506 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 507 while (wdc_probe_count-- > 0) { 508 if (wdc->select) 509 wdc->select(chp,0); 510 511 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 512 0, WDSD_IBM); 513 delay(10); /* 400ns delay */ 514 st0 = bus_space_read_1(wdr->cmd_iot, 515 wdr->cmd_iohs[wd_status], 0); 516 517 if (wdc->select) 518 wdc->select(chp,1); 519 520 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 521 0, WDSD_IBM | 0x10); 522 delay(10); /* 400ns delay */ 523 st1 = bus_space_read_1(wdr->cmd_iot, 524 wdr->cmd_iohs[wd_status], 0); 525 if ((st0 & WDCS_BSY) == 0) 526 break; 527 } 528 529 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 530 device_xname(chp->ch_atac->atac_dev), 531 chp->ch_channel, st0, st1), DEBUG_PROBE); 532 533 if (st0 == 0xff || st0 == WDSD_IBM) 534 ret_value &= ~0x01; 535 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 536 ret_value &= ~0x02; 537 /* Register writability test, drive 0. */ 538 if (ret_value & 0x01) { 539 if (wdc->select) 540 wdc->select(chp,0); 541 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 542 0, WDSD_IBM); 543 bus_space_write_1(wdr->cmd_iot, 544 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 545 cl = bus_space_read_1(wdr->cmd_iot, 546 wdr->cmd_iohs[wd_cyl_lo], 0); 547 if (cl != 0x02) { 548 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 549 "got 0x%x != 0x02\n", 550 device_xname(chp->ch_atac->atac_dev), 551 chp->ch_channel, cl), 552 DEBUG_PROBE); 553 ret_value &= ~0x01; 554 } 555 bus_space_write_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 557 cl = bus_space_read_1(wdr->cmd_iot, 558 wdr->cmd_iohs[wd_cyl_lo], 0); 559 if (cl != 0x01) { 560 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 561 "got 0x%x != 0x01\n", 562 device_xname(chp->ch_atac->atac_dev), 563 chp->ch_channel, cl), 564 DEBUG_PROBE); 565 ret_value &= ~0x01; 566 } 567 bus_space_write_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_sector], 0, 0x01); 569 cl = bus_space_read_1(wdr->cmd_iot, 570 wdr->cmd_iohs[wd_sector], 0); 571 if (cl != 0x01) { 572 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 573 "got 0x%x != 0x01\n", 574 device_xname(chp->ch_atac->atac_dev), 575 chp->ch_channel, cl), 576 DEBUG_PROBE); 577 ret_value &= ~0x01; 578 } 579 bus_space_write_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_sector], 0, 0x02); 581 cl = bus_space_read_1(wdr->cmd_iot, 582 wdr->cmd_iohs[wd_sector], 0); 583 if (cl != 0x02) { 584 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 585 "got 0x%x != 0x02\n", 586 device_xname(chp->ch_atac->atac_dev), 587 chp->ch_channel, cl), 588 DEBUG_PROBE); 589 ret_value &= ~0x01; 590 } 591 cl = bus_space_read_1(wdr->cmd_iot, 592 wdr->cmd_iohs[wd_cyl_lo], 0); 593 if (cl != 0x01) { 594 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 595 "got 0x%x != 0x01\n", 596 device_xname(chp->ch_atac->atac_dev), 597 chp->ch_channel, cl), 598 DEBUG_PROBE); 599 ret_value &= ~0x01; 600 } 601 } 602 /* Register writability test, drive 1. */ 603 if (ret_value & 0x02) { 604 if (wdc->select) 605 wdc->select(chp,1); 606 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 607 0, WDSD_IBM | 0x10); 608 bus_space_write_1(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 610 cl = bus_space_read_1(wdr->cmd_iot, 611 wdr->cmd_iohs[wd_cyl_lo], 0); 612 if (cl != 0x02) { 613 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 614 "got 0x%x != 0x02\n", 615 device_xname(chp->ch_atac->atac_dev), 616 chp->ch_channel, cl), 617 DEBUG_PROBE); 618 ret_value &= ~0x02; 619 } 620 bus_space_write_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 622 cl = bus_space_read_1(wdr->cmd_iot, 623 wdr->cmd_iohs[wd_cyl_lo], 0); 624 if (cl != 0x01) { 625 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 626 "got 0x%x != 0x01\n", 627 device_xname(chp->ch_atac->atac_dev), 628 chp->ch_channel, cl), 629 DEBUG_PROBE); 630 ret_value &= ~0x02; 631 } 632 bus_space_write_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_sector], 0, 0x01); 634 cl = bus_space_read_1(wdr->cmd_iot, 635 wdr->cmd_iohs[wd_sector], 0); 636 if (cl != 0x01) { 637 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 638 "got 0x%x != 0x01\n", 639 device_xname(chp->ch_atac->atac_dev), 640 chp->ch_channel, cl), 641 DEBUG_PROBE); 642 ret_value &= ~0x02; 643 } 644 bus_space_write_1(wdr->cmd_iot, 645 wdr->cmd_iohs[wd_sector], 0, 0x02); 646 cl = bus_space_read_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_sector], 0); 648 if (cl != 0x02) { 649 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 650 "got 0x%x != 0x02\n", 651 device_xname(chp->ch_atac->atac_dev), 652 chp->ch_channel, cl), 653 DEBUG_PROBE); 654 ret_value &= ~0x02; 655 } 656 cl = bus_space_read_1(wdr->cmd_iot, 657 wdr->cmd_iohs[wd_cyl_lo], 0); 658 if (cl != 0x01) { 659 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 660 "got 0x%x != 0x01\n", 661 device_xname(chp->ch_atac->atac_dev), 662 chp->ch_channel, cl), 663 DEBUG_PROBE); 664 ret_value &= ~0x02; 665 } 666 } 667 668 if (ret_value == 0) { 669 splx(s); 670 return 0; 671 } 672 } 673 674 675 #if 0 /* XXX this break some ATA or ATAPI devices */ 676 /* 677 * reset bus. Also send an ATAPI_RESET to devices, in case there are 678 * ATAPI device out there which don't react to the bus reset 679 */ 680 if (ret_value & 0x01) { 681 if (wdc->select) 682 wdc->select(chp,0); 683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 684 0, WDSD_IBM); 685 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 686 ATAPI_SOFT_RESET); 687 } 688 if (ret_value & 0x02) { 689 if (wdc->select) 690 wdc->select(chp,0); 691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 692 0, WDSD_IBM | 0x10); 693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 694 ATAPI_SOFT_RESET); 695 } 696 697 delay(5000); 698 #endif 699 700 wdc->reset(chp, RESET_POLL); 701 DELAY(2000); 702 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 703 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 704 #ifdef WDC_NO_IDS 705 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 706 #else 707 splx(s); 708 ret_value = __wdcwait_reset(chp, ret_value, poll); 709 s = splbio(); 710 #endif 711 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 712 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 713 ret_value), DEBUG_PROBE); 714 715 /* if reset failed, there's nothing here */ 716 if (ret_value == 0) { 717 splx(s); 718 return 0; 719 } 720 721 /* 722 * Test presence of drives. First test register signatures looking 723 * for ATAPI devices. If it's not an ATAPI and reset said there may 724 * be something here assume it's ATA or OLD. Ghost will be killed 725 * later in attach routine. 726 */ 727 for (drive = 0; drive < chp->ch_ndrive; drive++) { 728 if ((ret_value & (0x01 << drive)) == 0) 729 continue; 730 if (wdc->select) 731 wdc->select(chp,drive); 732 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 733 WDSD_IBM | (drive << 4)); 734 delay(10); /* 400ns delay */ 735 /* Save registers contents */ 736 sc = bus_space_read_1(wdr->cmd_iot, 737 wdr->cmd_iohs[wd_seccnt], 0); 738 sn = bus_space_read_1(wdr->cmd_iot, 739 wdr->cmd_iohs[wd_sector], 0); 740 cl = bus_space_read_1(wdr->cmd_iot, 741 wdr->cmd_iohs[wd_cyl_lo], 0); 742 ch = bus_space_read_1(wdr->cmd_iot, 743 wdr->cmd_iohs[wd_cyl_hi], 0); 744 745 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 746 "cl=0x%x ch=0x%x\n", 747 device_xname(chp->ch_atac->atac_dev), 748 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 749 /* 750 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 751 * we get wrong values here, so ignore it. 752 */ 753 if (cl == 0x14 && ch == 0xeb) { 754 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 755 } else { 756 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 757 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 758 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 759 } 760 } 761 /* 762 * Select an existing drive before lowering spl, some WDC_NO_IDS 763 * devices incorrectly assert IRQ on nonexistent slave 764 */ 765 if (ret_value & 0x01) { 766 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 767 WDSD_IBM); 768 (void)bus_space_read_1(wdr->cmd_iot, 769 wdr->cmd_iohs[wd_status], 0); 770 } 771 splx(s); 772 return (ret_value); 773 } 774 775 void 776 wdcattach(struct ata_channel *chp) 777 { 778 struct atac_softc *atac = chp->ch_atac; 779 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 780 781 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 782 783 /* default data transfer methods */ 784 if (wdc->datain_pio == NULL) 785 wdc->datain_pio = wdc_datain_pio; 786 if (wdc->dataout_pio == NULL) 787 wdc->dataout_pio = wdc_dataout_pio; 788 /* default reset method */ 789 if (wdc->reset == NULL) 790 wdc->reset = wdc_do_reset; 791 792 /* initialise global data */ 793 if (atac->atac_bustype_ata == NULL) 794 atac->atac_bustype_ata = &wdc_ata_bustype; 795 if (atac->atac_probe == NULL) 796 atac->atac_probe = wdc_drvprobe; 797 #if NATAPIBUS > 0 798 if (atac->atac_atapibus_attach == NULL) 799 atac->atac_atapibus_attach = wdc_atapibus_attach; 800 #endif 801 802 ata_channel_attach(chp); 803 } 804 805 void 806 wdc_childdetached(device_t self, device_t child) 807 { 808 struct atac_softc *atac = device_private(self); 809 struct ata_channel *chp; 810 int i; 811 812 for (i = 0; i < atac->atac_nchannels; i++) { 813 chp = atac->atac_channels[i]; 814 if (child == chp->atabus) { 815 chp->atabus = NULL; 816 return; 817 } 818 } 819 } 820 821 int 822 wdcdetach(device_t self, int flags) 823 { 824 struct atac_softc *atac = device_private(self); 825 struct ata_channel *chp; 826 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 827 int i, error = 0; 828 829 for (i = 0; i < atac->atac_nchannels; i++) { 830 chp = atac->atac_channels[i]; 831 if (chp->atabus == NULL) 832 continue; 833 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 834 device_xname(atac->atac_dev), device_xname(chp->atabus)), 835 DEBUG_DETACH); 836 if ((error = config_detach(chp->atabus, flags)) != 0) 837 return error; 838 } 839 if (adapt->adapt_refcnt != 0) 840 return EBUSY; 841 return 0; 842 } 843 844 /* restart an interrupted I/O */ 845 void 846 wdcrestart(void *v) 847 { 848 struct ata_channel *chp = v; 849 int s; 850 851 s = splbio(); 852 atastart(chp); 853 splx(s); 854 } 855 856 857 /* 858 * Interrupt routine for the controller. Acknowledge the interrupt, check for 859 * errors on the current operation, mark it done if necessary, and start the 860 * next request. Also check for a partially done transfer, and continue with 861 * the next chunk if so. 862 */ 863 int 864 wdcintr(void *arg) 865 { 866 struct ata_channel *chp = arg; 867 struct atac_softc *atac = chp->ch_atac; 868 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 869 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 870 struct ata_xfer *xfer; 871 int ret; 872 873 if (!device_is_active(atac->atac_dev)) { 874 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 875 DEBUG_INTR); 876 return (0); 877 } 878 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 879 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 880 /* try to clear the pending interrupt anyway */ 881 (void)bus_space_read_1(wdr->cmd_iot, 882 wdr->cmd_iohs[wd_status], 0); 883 return (0); 884 } 885 886 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 887 xfer = chp->ch_queue->active_xfer; 888 #ifdef DIAGNOSTIC 889 if (xfer == NULL) 890 panic("wdcintr: no xfer"); 891 if (xfer->c_chp != chp) { 892 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 893 chp->ch_channel); 894 panic("wdcintr: wrong channel"); 895 } 896 #endif 897 #if NATA_DMA || NATA_PIOBM 898 if (chp->ch_flags & ATACH_DMA_WAIT) { 899 wdc->dma_status = 900 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 901 xfer->c_drive, WDC_DMAEND_END); 902 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 903 /* IRQ not for us, not detected by DMA engine */ 904 return 0; 905 } 906 chp->ch_flags &= ~ATACH_DMA_WAIT; 907 } 908 #endif 909 chp->ch_flags &= ~ATACH_IRQ_WAIT; 910 KASSERT(xfer->c_intr != NULL); 911 ret = xfer->c_intr(chp, xfer, 1); 912 if (ret == 0) /* irq was not for us, still waiting for irq */ 913 chp->ch_flags |= ATACH_IRQ_WAIT; 914 return (ret); 915 } 916 917 /* Put all disk in RESET state */ 918 void 919 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 920 { 921 struct ata_channel *chp = drvp->chnl_softc; 922 923 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 924 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 925 drvp->drive), DEBUG_FUNCS); 926 927 ata_reset_channel(chp, flags); 928 } 929 930 void 931 wdc_reset_channel(struct ata_channel *chp, int flags) 932 { 933 TAILQ_HEAD(, ata_xfer) reset_xfer; 934 struct ata_xfer *xfer, *next_xfer; 935 #if NATA_DMA || NATA_PIOBM 936 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 937 #endif 938 TAILQ_INIT(&reset_xfer); 939 940 chp->ch_flags &= ~ATACH_IRQ_WAIT; 941 942 /* 943 * if the current command if on an ATAPI device, issue a 944 * ATAPI_SOFT_RESET 945 */ 946 xfer = chp->ch_queue->active_xfer; 947 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 948 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 949 if (flags & AT_WAIT) 950 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 951 else 952 delay(1000); 953 } 954 955 /* reset the channel */ 956 if (flags & AT_WAIT) 957 (void) wdcreset(chp, RESET_SLEEP); 958 else 959 (void) wdcreset(chp, RESET_POLL); 960 961 /* 962 * wait a bit after reset; in case the DMA engines needs some time 963 * to recover. 964 */ 965 if (flags & AT_WAIT) 966 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 967 else 968 delay(1000); 969 /* 970 * look for pending xfers. If we have a shared queue, we'll also reset 971 * the other channel if the current xfer is running on it. 972 * Then we'll dequeue only the xfers for this channel. 973 */ 974 if ((flags & AT_RST_NOCMD) == 0) { 975 /* 976 * move all xfers queued for this channel to the reset queue, 977 * and then process the current xfer and then the reset queue. 978 * We have to use a temporary queue because c_kill_xfer() 979 * may requeue commands. 980 */ 981 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 982 xfer != NULL; xfer = next_xfer) { 983 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 984 if (xfer->c_chp != chp) 985 continue; 986 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 987 xfer, c_xferchain); 988 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 989 } 990 xfer = chp->ch_queue->active_xfer; 991 if (xfer) { 992 if (xfer->c_chp != chp) 993 ata_reset_channel(xfer->c_chp, flags); 994 else { 995 callout_stop(&chp->ch_callout); 996 #if NATA_DMA || NATA_PIOBM 997 /* 998 * If we're waiting for DMA, stop the 999 * DMA engine 1000 */ 1001 if (chp->ch_flags & ATACH_DMA_WAIT) { 1002 (*wdc->dma_finish)( 1003 wdc->dma_arg, 1004 chp->ch_channel, 1005 xfer->c_drive, 1006 WDC_DMAEND_ABRT_QUIET); 1007 chp->ch_flags &= ~ATACH_DMA_WAIT; 1008 } 1009 #endif 1010 chp->ch_queue->active_xfer = NULL; 1011 if ((flags & AT_RST_EMERG) == 0) 1012 xfer->c_kill_xfer( 1013 chp, xfer, KILL_RESET); 1014 } 1015 } 1016 1017 for (xfer = TAILQ_FIRST(&reset_xfer); 1018 xfer != NULL; xfer = next_xfer) { 1019 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1020 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1021 if ((flags & AT_RST_EMERG) == 0) 1022 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1023 } 1024 } 1025 } 1026 1027 static int 1028 wdcreset(struct ata_channel *chp, int poll) 1029 { 1030 struct atac_softc *atac = chp->ch_atac; 1031 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1032 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1033 int drv_mask1, drv_mask2; 1034 1035 #ifdef WDC_NO_IDS 1036 poll = RESET_POLL; 1037 #endif 1038 wdc->reset(chp, poll); 1039 1040 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1041 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1042 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1043 (poll == RESET_SLEEP) ? 0 : 1); 1044 if (drv_mask2 != drv_mask1) { 1045 aprint_error("%s channel %d: reset failed for", 1046 device_xname(atac->atac_dev), chp->ch_channel); 1047 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1048 aprint_normal(" drive 0"); 1049 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1050 aprint_normal(" drive 1"); 1051 aprint_normal("\n"); 1052 } 1053 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1054 return (drv_mask1 != drv_mask2) ? 1 : 0; 1055 } 1056 1057 void 1058 wdc_do_reset(struct ata_channel *chp, int poll) 1059 { 1060 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1061 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1062 int s = 0; 1063 1064 if (poll != RESET_SLEEP) 1065 s = splbio(); 1066 if (wdc->select) 1067 wdc->select(chp,0); 1068 /* master */ 1069 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1070 delay(10); /* 400ns delay */ 1071 /* assert SRST, wait for reset to complete */ 1072 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1073 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1074 delay(2000); 1075 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1076 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1077 WDCTL_4BIT | WDCTL_IDS); 1078 delay(10); /* 400ns delay */ 1079 if (poll != RESET_SLEEP) { 1080 /* ACK interrupt in case there is one pending left */ 1081 if (wdc->irqack) 1082 wdc->irqack(chp); 1083 splx(s); 1084 } 1085 } 1086 1087 static int 1088 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1089 { 1090 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1091 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1092 int timeout, nloop; 1093 u_int8_t st0 = 0, st1 = 0; 1094 #ifdef ATADEBUG 1095 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1096 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1097 #endif 1098 if (poll) 1099 nloop = WDCNDELAY_RST; 1100 else 1101 nloop = WDC_RESET_WAIT * hz / 1000; 1102 /* wait for BSY to deassert */ 1103 for (timeout = 0; timeout < nloop; timeout++) { 1104 if ((drv_mask & 0x01) != 0) { 1105 if (wdc->select) 1106 wdc->select(chp,0); 1107 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1108 0, WDSD_IBM); /* master */ 1109 delay(10); 1110 st0 = bus_space_read_1(wdr->cmd_iot, 1111 wdr->cmd_iohs[wd_status], 0); 1112 #ifdef ATADEBUG 1113 sc0 = bus_space_read_1(wdr->cmd_iot, 1114 wdr->cmd_iohs[wd_seccnt], 0); 1115 sn0 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_sector], 0); 1117 cl0 = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_cyl_lo], 0); 1119 ch0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_cyl_hi], 0); 1121 #endif 1122 } 1123 if ((drv_mask & 0x02) != 0) { 1124 if (wdc->select) 1125 wdc->select(chp,1); 1126 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1127 0, WDSD_IBM | 0x10); /* slave */ 1128 delay(10); 1129 st1 = bus_space_read_1(wdr->cmd_iot, 1130 wdr->cmd_iohs[wd_status], 0); 1131 #ifdef ATADEBUG 1132 sc1 = bus_space_read_1(wdr->cmd_iot, 1133 wdr->cmd_iohs[wd_seccnt], 0); 1134 sn1 = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_sector], 0); 1136 cl1 = bus_space_read_1(wdr->cmd_iot, 1137 wdr->cmd_iohs[wd_cyl_lo], 0); 1138 ch1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_cyl_hi], 0); 1140 #endif 1141 } 1142 1143 if ((drv_mask & 0x01) == 0) { 1144 /* no master */ 1145 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1146 /* No master, slave is ready, it's done */ 1147 goto end; 1148 } 1149 if ((drv_mask & 0x02) == 0) { 1150 /* No master, no slave: it's done */ 1151 goto end; 1152 } 1153 } else if ((drv_mask & 0x02) == 0) { 1154 /* no slave */ 1155 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1156 /* No slave, master is ready, it's done */ 1157 goto end; 1158 } 1159 } else { 1160 /* Wait for both master and slave to be ready */ 1161 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1162 goto end; 1163 } 1164 } 1165 if (poll) 1166 delay(WDCDELAY); 1167 else 1168 tsleep(&nloop, PRIBIO, "atarst", 1); 1169 } 1170 /* Reset timed out. Maybe it's because drv_mask was not right */ 1171 if (st0 & WDCS_BSY) 1172 drv_mask &= ~0x01; 1173 if (st1 & WDCS_BSY) 1174 drv_mask &= ~0x02; 1175 end: 1176 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1177 "cl=0x%x ch=0x%x\n", 1178 device_xname(chp->ch_atac->atac_dev), 1179 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1180 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1181 "cl=0x%x ch=0x%x\n", 1182 device_xname(chp->ch_atac->atac_dev), 1183 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1184 1185 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1186 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1187 st0, st1), DEBUG_PROBE); 1188 1189 return drv_mask; 1190 } 1191 1192 /* 1193 * Wait for a drive to be !BSY, and have mask in its status register. 1194 * return -1 for a timeout after "timeout" ms. 1195 */ 1196 static int 1197 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1198 { 1199 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1200 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1201 u_char status; 1202 int xtime = 0; 1203 1204 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1205 device_xname(chp->ch_atac->atac_dev), 1206 chp->ch_channel), DEBUG_STATUS); 1207 chp->ch_error = 0; 1208 1209 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1210 1211 for (;;) { 1212 chp->ch_status = status = 1213 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1214 if ((status & (WDCS_BSY | mask)) == bits) 1215 break; 1216 if (++xtime > timeout) { 1217 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1218 "status %x error %x (mask 0x%x bits 0x%x)\n", 1219 xtime, status, 1220 bus_space_read_1(wdr->cmd_iot, 1221 wdr->cmd_iohs[wd_error], 0), mask, bits), 1222 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1223 return(WDCWAIT_TOUT); 1224 } 1225 delay(WDCDELAY); 1226 } 1227 #ifdef ATADEBUG 1228 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1229 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1230 #endif 1231 if (status & WDCS_ERR) 1232 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1233 wdr->cmd_iohs[wd_error], 0); 1234 #ifdef WDCNDELAY_DEBUG 1235 /* After autoconfig, there should be no long delays. */ 1236 if (!cold && xtime > WDCNDELAY_DEBUG) { 1237 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1238 if (xfer == NULL) 1239 printf("%s channel %d: warning: busy-wait took %dus\n", 1240 device_xname(chp->ch_atac->atac_dev), 1241 chp->ch_channel, WDCDELAY * xtime); 1242 else 1243 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1244 device_xname(chp->ch_atac->atac_dev), 1245 chp->ch_channel, xfer->c_drive, 1246 WDCDELAY * xtime); 1247 } 1248 #endif 1249 return(WDCWAIT_OK); 1250 } 1251 1252 /* 1253 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1254 * thread if possible 1255 */ 1256 int 1257 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1258 { 1259 int error, i, timeout_hz = mstohz(timeout); 1260 1261 if (timeout_hz == 0 || 1262 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1263 error = __wdcwait(chp, mask, bits, timeout); 1264 else { 1265 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1266 if (error != 0) { 1267 if ((chp->ch_flags & ATACH_TH_RUN) || 1268 (flags & AT_WAIT)) { 1269 /* 1270 * we're running in the channel thread 1271 * or some userland thread context 1272 */ 1273 for (i = 0; i < timeout_hz; i++) { 1274 if (__wdcwait(chp, mask, bits, 1275 WDCDELAY_POLL) == 0) { 1276 error = 0; 1277 break; 1278 } 1279 tsleep(&chp, PRIBIO, "atapoll", 1); 1280 } 1281 } else { 1282 /* 1283 * we're probably in interrupt context, 1284 * ask the thread to come back here 1285 */ 1286 #ifdef DIAGNOSTIC 1287 if (chp->ch_queue->queue_freeze > 0) 1288 panic("wdcwait: queue_freeze"); 1289 #endif 1290 chp->ch_queue->queue_freeze++; 1291 wakeup(&chp->ch_thread); 1292 return(WDCWAIT_THR); 1293 } 1294 } 1295 } 1296 return (error); 1297 } 1298 1299 1300 #if NATA_DMA 1301 /* 1302 * Busy-wait for DMA to complete 1303 */ 1304 int 1305 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1306 { 1307 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1308 int xtime; 1309 1310 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1311 wdc->dma_status = 1312 (*wdc->dma_finish)(wdc->dma_arg, 1313 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1314 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1315 return 0; 1316 delay(WDCDELAY); 1317 } 1318 /* timeout, force a DMA halt */ 1319 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1320 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1321 return 1; 1322 } 1323 #endif 1324 1325 void 1326 wdctimeout(void *arg) 1327 { 1328 struct ata_channel *chp = (struct ata_channel *)arg; 1329 #if NATA_DMA || NATA_PIOBM 1330 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1331 #endif 1332 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1333 int s; 1334 1335 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1336 1337 s = splbio(); 1338 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1339 __wdcerror(chp, "lost interrupt"); 1340 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1341 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1342 xfer->c_bcount, 1343 xfer->c_skip); 1344 #if NATA_DMA || NATA_PIOBM 1345 if (chp->ch_flags & ATACH_DMA_WAIT) { 1346 wdc->dma_status = 1347 (*wdc->dma_finish)(wdc->dma_arg, 1348 chp->ch_channel, xfer->c_drive, 1349 WDC_DMAEND_ABRT); 1350 chp->ch_flags &= ~ATACH_DMA_WAIT; 1351 } 1352 #endif 1353 /* 1354 * Call the interrupt routine. If we just missed an interrupt, 1355 * it will do what's needed. Else, it will take the needed 1356 * action (reset the device). 1357 * Before that we need to reinstall the timeout callback, 1358 * in case it will miss another irq while in this transfer 1359 * We arbitray chose it to be 1s 1360 */ 1361 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1362 xfer->c_flags |= C_TIMEOU; 1363 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1364 KASSERT(xfer->c_intr != NULL); 1365 xfer->c_intr(chp, xfer, 1); 1366 } else 1367 __wdcerror(chp, "missing untimeout"); 1368 splx(s); 1369 } 1370 1371 int 1372 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1373 { 1374 struct ata_channel *chp = drvp->chnl_softc; 1375 struct ata_xfer *xfer; 1376 int s, ret; 1377 1378 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1379 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1380 drvp->drive), DEBUG_FUNCS); 1381 1382 /* set up an xfer and queue. Wait for completion */ 1383 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1384 ATAXF_NOSLEEP); 1385 if (xfer == NULL) { 1386 return ATACMD_TRY_AGAIN; 1387 } 1388 1389 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1390 ata_c->flags |= AT_POLL; 1391 if (ata_c->flags & AT_POLL) 1392 xfer->c_flags |= C_POLL; 1393 if (ata_c->flags & AT_WAIT) 1394 xfer->c_flags |= C_WAIT; 1395 xfer->c_drive = drvp->drive; 1396 xfer->c_databuf = ata_c->data; 1397 xfer->c_bcount = ata_c->bcount; 1398 xfer->c_cmd = ata_c; 1399 xfer->c_start = __wdccommand_start; 1400 xfer->c_intr = __wdccommand_intr; 1401 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1402 1403 s = splbio(); 1404 ata_exec_xfer(chp, xfer); 1405 #ifdef DIAGNOSTIC 1406 if ((ata_c->flags & AT_POLL) != 0 && 1407 (ata_c->flags & AT_DONE) == 0) 1408 panic("wdc_exec_command: polled command not done"); 1409 #endif 1410 if (ata_c->flags & AT_DONE) { 1411 ret = ATACMD_COMPLETE; 1412 } else { 1413 if (ata_c->flags & AT_WAIT) { 1414 while ((ata_c->flags & AT_DONE) == 0) { 1415 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1416 } 1417 ret = ATACMD_COMPLETE; 1418 } else { 1419 ret = ATACMD_QUEUED; 1420 } 1421 } 1422 splx(s); 1423 return ret; 1424 } 1425 1426 static void 1427 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1428 { 1429 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1430 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1431 int drive = xfer->c_drive; 1432 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1433 struct ata_command *ata_c = xfer->c_cmd; 1434 1435 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1436 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1437 xfer->c_drive), 1438 DEBUG_FUNCS); 1439 1440 if (wdc->select) 1441 wdc->select(chp,drive); 1442 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1443 WDSD_IBM | (drive << 4)); 1444 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1445 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1446 case WDCWAIT_OK: 1447 break; 1448 case WDCWAIT_TOUT: 1449 ata_c->flags |= AT_TIMEOU; 1450 __wdccommand_done(chp, xfer); 1451 return; 1452 case WDCWAIT_THR: 1453 return; 1454 } 1455 if (ata_c->flags & AT_POLL) { 1456 /* polled command, disable interrupts */ 1457 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1458 WDCTL_4BIT | WDCTL_IDS); 1459 } 1460 if ((ata_c->flags & AT_LBA48) != 0) { 1461 wdccommandext(chp, drive, ata_c->r_command, 1462 ata_c->r_lba, ata_c->r_count, ata_c->r_features); 1463 } else { 1464 wdccommand(chp, drive, ata_c->r_command, 1465 (ata_c->r_lba >> 8) & 0xffff, 1466 WDSD_IBM | (drive << 4) | 1467 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1468 ((ata_c->r_lba >> 24) & 0x0f), 1469 ata_c->r_lba & 0xff, 1470 ata_c->r_count & 0xff, 1471 ata_c->r_features & 0xff); 1472 } 1473 1474 if ((ata_c->flags & AT_POLL) == 0) { 1475 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1476 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1477 wdctimeout, chp); 1478 return; 1479 } 1480 /* 1481 * Polled command. Wait for drive ready or drq. Done in intr(). 1482 * Wait for at last 400ns for status bit to be valid. 1483 */ 1484 delay(10); /* 400ns delay */ 1485 __wdccommand_intr(chp, xfer, 0); 1486 } 1487 1488 static int 1489 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1490 { 1491 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1492 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1493 struct ata_command *ata_c = xfer->c_cmd; 1494 int bcount = ata_c->bcount; 1495 char *data = ata_c->data; 1496 int wflags; 1497 int drive_flags; 1498 1499 if (ata_c->r_command == WDCC_IDENTIFY || 1500 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1501 /* 1502 * The IDENTIFY data has been designed as an array of 1503 * u_int16_t, so we can byteswap it on the fly. 1504 * Historically it's what we have always done so keeping it 1505 * here ensure binary backward compatibility. 1506 */ 1507 drive_flags = DRIVE_NOSTREAM | 1508 chp->ch_drive[xfer->c_drive].drive_flags; 1509 } else { 1510 /* 1511 * Other data structure are opaque and should be transfered 1512 * as is. 1513 */ 1514 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1515 } 1516 1517 #ifdef WDC_NO_IDS 1518 wflags = AT_POLL; 1519 #else 1520 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1521 /* both wait and poll, we can tsleep here */ 1522 wflags = AT_WAIT | AT_POLL; 1523 } else { 1524 wflags = AT_POLL; 1525 } 1526 #endif 1527 1528 again: 1529 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1530 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1531 xfer->c_drive), DEBUG_INTR); 1532 /* 1533 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1534 * Reselect again, it doesn't hurt for others commands, and the time 1535 * penalty for the extra register write is acceptable, 1536 * wdc_exec_command() isn't called often (mostly for autoconfig) 1537 */ 1538 if ((xfer->c_flags & C_ATAPI) != 0) { 1539 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1540 WDSD_IBM | (xfer->c_drive << 4)); 1541 } 1542 if ((ata_c->flags & AT_XFDONE) != 0) { 1543 /* 1544 * We have completed a data xfer. The drive should now be 1545 * in its initial state 1546 */ 1547 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1548 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1549 wflags) == WDCWAIT_TOUT) { 1550 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1551 return 0; /* IRQ was not for us */ 1552 ata_c->flags |= AT_TIMEOU; 1553 } 1554 goto out; 1555 } 1556 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1557 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1558 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1559 return 0; /* IRQ was not for us */ 1560 ata_c->flags |= AT_TIMEOU; 1561 goto out; 1562 } 1563 if (wdc->irqack) 1564 wdc->irqack(chp); 1565 if (ata_c->flags & AT_READ) { 1566 if ((chp->ch_status & WDCS_DRQ) == 0) { 1567 ata_c->flags |= AT_TIMEOU; 1568 goto out; 1569 } 1570 wdc->datain_pio(chp, drive_flags, data, bcount); 1571 /* at this point the drive should be in its initial state */ 1572 ata_c->flags |= AT_XFDONE; 1573 /* 1574 * XXX checking the status register again here cause some 1575 * hardware to timeout. 1576 */ 1577 } else if (ata_c->flags & AT_WRITE) { 1578 if ((chp->ch_status & WDCS_DRQ) == 0) { 1579 ata_c->flags |= AT_TIMEOU; 1580 goto out; 1581 } 1582 wdc->dataout_pio(chp, drive_flags, data, bcount); 1583 ata_c->flags |= AT_XFDONE; 1584 if ((ata_c->flags & AT_POLL) == 0) { 1585 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1586 callout_reset(&chp->ch_callout, 1587 mstohz(ata_c->timeout), wdctimeout, chp); 1588 return 1; 1589 } else { 1590 goto again; 1591 } 1592 } 1593 out: 1594 __wdccommand_done(chp, xfer); 1595 return 1; 1596 } 1597 1598 static void 1599 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1600 { 1601 struct atac_softc *atac = chp->ch_atac; 1602 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1603 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1604 struct ata_command *ata_c = xfer->c_cmd; 1605 1606 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1607 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1608 ata_c->flags), DEBUG_FUNCS); 1609 1610 1611 if (chp->ch_status & WDCS_DWF) 1612 ata_c->flags |= AT_DF; 1613 if (chp->ch_status & WDCS_ERR) { 1614 ata_c->flags |= AT_ERROR; 1615 ata_c->r_error = chp->ch_error; 1616 } 1617 if ((ata_c->flags & AT_READREG) != 0 && 1618 device_is_active(atac->atac_dev) && 1619 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1620 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1621 wdr->cmd_iohs[wd_status], 0); 1622 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1623 wdr->cmd_iohs[wd_error], 0); 1624 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1625 wdr->cmd_iohs[wd_seccnt], 0); 1626 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1627 wdr->cmd_iohs[wd_sector], 0) << 0; 1628 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1629 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1630 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1631 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1632 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1633 wdr->cmd_iohs[wd_sdh], 0); 1634 1635 if ((ata_c->flags & AT_LBA48) != 0) { 1636 if ((ata_c->flags & AT_POLL) != 0) 1637 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1638 wd_aux_ctlr, 1639 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1640 else 1641 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1642 wd_aux_ctlr, WDCTL_HOB|WDCTL_4BIT); 1643 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1644 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1645 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1646 wdr->cmd_iohs[wd_sector], 0) << 24; 1647 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1649 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1651 if ((ata_c->flags & AT_POLL) != 0) 1652 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1653 wd_aux_ctlr, WDCTL_4BIT|WDCTL_IDS); 1654 else 1655 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1656 wd_aux_ctlr, WDCTL_4BIT); 1657 } else { 1658 ata_c->r_lba |= 1659 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1660 } 1661 ata_c->r_device &= 0xf0; 1662 } 1663 callout_stop(&chp->ch_callout); 1664 chp->ch_queue->active_xfer = NULL; 1665 if (ata_c->flags & AT_POLL) { 1666 /* enable interrupts */ 1667 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1668 WDCTL_4BIT); 1669 delay(10); /* some drives need a little delay here */ 1670 } 1671 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1672 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1673 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1674 wakeup(&chp->ch_queue->active_xfer); 1675 } else 1676 __wdccommand_done_end(chp, xfer); 1677 } 1678 1679 static void 1680 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1681 { 1682 struct ata_command *ata_c = xfer->c_cmd; 1683 1684 ata_c->flags |= AT_DONE; 1685 ata_free_xfer(chp, xfer); 1686 if (ata_c->flags & AT_WAIT) 1687 wakeup(ata_c); 1688 else if (ata_c->callback) 1689 ata_c->callback(ata_c->callback_arg); 1690 atastart(chp); 1691 return; 1692 } 1693 1694 static void 1695 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1696 int reason) 1697 { 1698 struct ata_command *ata_c = xfer->c_cmd; 1699 1700 switch (reason) { 1701 case KILL_GONE: 1702 ata_c->flags |= AT_GONE; 1703 break; 1704 case KILL_RESET: 1705 ata_c->flags |= AT_RESET; 1706 break; 1707 default: 1708 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1709 reason); 1710 panic("__wdccommand_kill_xfer"); 1711 } 1712 __wdccommand_done_end(chp, xfer); 1713 } 1714 1715 /* 1716 * Send a command. The drive should be ready. 1717 * Assumes interrupts are blocked. 1718 */ 1719 void 1720 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1721 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1722 u_int8_t features) 1723 { 1724 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1725 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1726 1727 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1728 "sector=%d count=%d features=%d\n", 1729 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1730 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1731 1732 if (wdc->select) 1733 wdc->select(chp,drive); 1734 1735 /* Select drive, head, and addressing mode. */ 1736 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1737 WDSD_IBM | (drive << 4) | head); 1738 /* Load parameters into the wd_features register. */ 1739 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1740 features); 1741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1742 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1743 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1745 0, cylin >> 8); 1746 1747 /* Send command. */ 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1749 return; 1750 } 1751 1752 /* 1753 * Send a 48-bit addressing command. The drive should be ready. 1754 * Assumes interrupts are blocked. 1755 */ 1756 void 1757 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1758 u_int64_t blkno, u_int16_t count, u_int16_t features) 1759 { 1760 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1761 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1762 1763 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1764 "count=%d\n", device_xname(chp->ch_atac->atac_dev), 1765 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1766 DEBUG_FUNCS); 1767 1768 if (wdc->select) 1769 wdc->select(chp,drive); 1770 1771 /* Select drive, head, and addressing mode. */ 1772 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1773 (drive << 4) | WDSD_LBA); 1774 1775 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1776 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1777 0, features); 1778 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1779 0, count); 1780 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1781 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1782 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1783 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1784 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1785 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1786 } else { 1787 /* previous */ 1788 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1789 0, features >> 8); 1790 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1791 0, count >> 8); 1792 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1793 0, blkno >> 24); 1794 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1795 0, blkno >> 32); 1796 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1797 0, blkno >> 40); 1798 1799 /* current */ 1800 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1801 0, features); 1802 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1803 0, count); 1804 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1805 0, blkno); 1806 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1807 0, blkno >> 8); 1808 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1809 0, blkno >> 16); 1810 } 1811 1812 /* Send command. */ 1813 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1814 return; 1815 } 1816 1817 /* 1818 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1819 * tested by the caller. 1820 */ 1821 void 1822 wdccommandshort(struct ata_channel *chp, int drive, int command) 1823 { 1824 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1825 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1826 1827 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1828 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1829 command), DEBUG_FUNCS); 1830 1831 if (wdc->select) 1832 wdc->select(chp,drive); 1833 1834 /* Select drive. */ 1835 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1836 WDSD_IBM | (drive << 4)); 1837 1838 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1839 } 1840 1841 static void 1842 __wdcerror(struct ata_channel *chp, const char *msg) 1843 { 1844 struct atac_softc *atac = chp->ch_atac; 1845 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1846 1847 if (xfer == NULL) 1848 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1849 chp->ch_channel, msg); 1850 else 1851 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1852 chp->ch_channel, xfer->c_drive, msg); 1853 } 1854 1855 /* 1856 * the bit bucket 1857 */ 1858 void 1859 wdcbit_bucket(struct ata_channel *chp, int size) 1860 { 1861 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1862 1863 for (; size >= 2; size -= 2) 1864 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1865 if (size) 1866 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1867 } 1868 1869 static void 1870 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1871 { 1872 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1873 1874 #ifndef __NO_STRICT_ALIGNMENT 1875 if ((uintptr_t)bf & 1) 1876 goto unaligned; 1877 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1878 goto unaligned; 1879 #endif 1880 1881 if (flags & DRIVE_NOSTREAM) { 1882 if ((flags & DRIVE_CAP32) && len > 3) { 1883 bus_space_read_multi_4(wdr->data32iot, 1884 wdr->data32ioh, 0, bf, len >> 2); 1885 bf = (char *)bf + (len & ~3); 1886 len &= 3; 1887 } 1888 if (len > 1) { 1889 bus_space_read_multi_2(wdr->cmd_iot, 1890 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1891 bf = (char *)bf + (len & ~1); 1892 len &= 1; 1893 } 1894 } else { 1895 if ((flags & DRIVE_CAP32) && len > 3) { 1896 bus_space_read_multi_stream_4(wdr->data32iot, 1897 wdr->data32ioh, 0, bf, len >> 2); 1898 bf = (char *)bf + (len & ~3); 1899 len &= 3; 1900 } 1901 if (len > 1) { 1902 bus_space_read_multi_stream_2(wdr->cmd_iot, 1903 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1904 bf = (char *)bf + (len & ~1); 1905 len &= 1; 1906 } 1907 } 1908 if (len) 1909 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1910 wdr->cmd_iohs[wd_data], 0); 1911 return; 1912 1913 #ifndef __NO_STRICT_ALIGNMENT 1914 unaligned: 1915 if (flags & DRIVE_NOSTREAM) { 1916 if (flags & DRIVE_CAP32) { 1917 while (len > 3) { 1918 uint32_t val; 1919 1920 val = bus_space_read_4(wdr->data32iot, 1921 wdr->data32ioh, 0); 1922 memcpy(bf, &val, 4); 1923 bf = (char *)bf + 4; 1924 len -= 4; 1925 } 1926 } 1927 while (len > 1) { 1928 uint16_t val; 1929 1930 val = bus_space_read_2(wdr->cmd_iot, 1931 wdr->cmd_iohs[wd_data], 0); 1932 memcpy(bf, &val, 2); 1933 bf = (char *)bf + 2; 1934 len -= 2; 1935 } 1936 } else { 1937 if (flags & DRIVE_CAP32) { 1938 while (len > 3) { 1939 uint32_t val; 1940 1941 val = bus_space_read_stream_4(wdr->data32iot, 1942 wdr->data32ioh, 0); 1943 memcpy(bf, &val, 4); 1944 bf = (char *)bf + 4; 1945 len -= 4; 1946 } 1947 } 1948 while (len > 1) { 1949 uint16_t val; 1950 1951 val = bus_space_read_stream_2(wdr->cmd_iot, 1952 wdr->cmd_iohs[wd_data], 0); 1953 memcpy(bf, &val, 2); 1954 bf = (char *)bf + 2; 1955 len -= 2; 1956 } 1957 } 1958 #endif 1959 } 1960 1961 static void 1962 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1963 { 1964 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1965 1966 #ifndef __NO_STRICT_ALIGNMENT 1967 if ((uintptr_t)bf & 1) 1968 goto unaligned; 1969 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1970 goto unaligned; 1971 #endif 1972 1973 if (flags & DRIVE_NOSTREAM) { 1974 if (flags & DRIVE_CAP32) { 1975 bus_space_write_multi_4(wdr->data32iot, 1976 wdr->data32ioh, 0, bf, len >> 2); 1977 bf = (char *)bf + (len & ~3); 1978 len &= 3; 1979 } 1980 if (len) { 1981 bus_space_write_multi_2(wdr->cmd_iot, 1982 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1983 } 1984 } else { 1985 if (flags & DRIVE_CAP32) { 1986 bus_space_write_multi_stream_4(wdr->data32iot, 1987 wdr->data32ioh, 0, bf, len >> 2); 1988 bf = (char *)bf + (len & ~3); 1989 len &= 3; 1990 } 1991 if (len) { 1992 bus_space_write_multi_stream_2(wdr->cmd_iot, 1993 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1994 } 1995 } 1996 return; 1997 1998 #ifndef __NO_STRICT_ALIGNMENT 1999 unaligned: 2000 if (flags & DRIVE_NOSTREAM) { 2001 if (flags & DRIVE_CAP32) { 2002 while (len > 3) { 2003 uint32_t val; 2004 2005 memcpy(&val, bf, 4); 2006 bus_space_write_4(wdr->data32iot, 2007 wdr->data32ioh, 0, val); 2008 bf = (char *)bf + 4; 2009 len -= 4; 2010 } 2011 } 2012 while (len > 1) { 2013 uint16_t val; 2014 2015 memcpy(&val, bf, 2); 2016 bus_space_write_2(wdr->cmd_iot, 2017 wdr->cmd_iohs[wd_data], 0, val); 2018 bf = (char *)bf + 2; 2019 len -= 2; 2020 } 2021 } else { 2022 if (flags & DRIVE_CAP32) { 2023 while (len > 3) { 2024 uint32_t val; 2025 2026 memcpy(&val, bf, 4); 2027 bus_space_write_stream_4(wdr->data32iot, 2028 wdr->data32ioh, 0, val); 2029 bf = (char *)bf + 4; 2030 len -= 4; 2031 } 2032 } 2033 while (len > 1) { 2034 uint16_t val; 2035 2036 memcpy(&val, bf, 2); 2037 bus_space_write_stream_2(wdr->cmd_iot, 2038 wdr->cmd_iohs[wd_data], 0, val); 2039 bf = (char *)bf + 2; 2040 len -= 2; 2041 } 2042 } 2043 #endif 2044 } 2045
Indexes created Tue Sep 23 23:09:58 GMT 2025