wdc.c revision 1.274
1 /* $NetBSD: wdc.c,v 1.274 2012/07/31 15:50:34 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.274 2012/07/31 15:50:34 bouyer Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then tsleep for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 SCSIPI_BUSTYPE_ATA, 130 NULL, /* wdc_ata_bio */ 131 NULL, /* wdc_reset_drive */ 132 wdc_reset_channel, 133 wdc_exec_command, 134 NULL, /* ata_get_params */ 135 NULL, /* wdc_ata_addref */ 136 NULL, /* wdc_ata_delref */ 137 NULL /* ata_kill_pending */ 138 }; 139 #endif 140 141 /* Flags to wdcreset(). */ 142 #define RESET_POLL 1 143 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 144 145 static int wdcprobe1(struct ata_channel *, int); 146 static int wdcreset(struct ata_channel *, int); 147 static void __wdcerror(struct ata_channel *, const char *); 148 static int __wdcwait_reset(struct ata_channel *, int, int); 149 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 150 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_kill_xfer(struct ata_channel *, 152 struct ata_xfer *, int); 153 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 154 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 155 static int __wdcwait(struct ata_channel *, int, int, int); 156 157 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 158 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 159 160 #define DEBUG_INTR 0x01 161 #define DEBUG_XFERS 0x02 162 #define DEBUG_STATUS 0x04 163 #define DEBUG_FUNCS 0x08 164 #define DEBUG_PROBE 0x10 165 #define DEBUG_DETACH 0x20 166 #define DEBUG_DELAY 0x40 167 #ifdef ATADEBUG 168 extern int atadebug_mask; /* init'ed in ata.c */ 169 int wdc_nxfer = 0; 170 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 171 #else 172 #define ATADEBUG_PRINT(args, level) 173 #endif 174 175 /* 176 * Initialize the "shadow register" handles for a standard wdc controller. 177 */ 178 void 179 wdc_init_shadow_regs(struct ata_channel *chp) 180 { 181 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 182 183 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 184 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 185 } 186 187 /* 188 * Allocate a wdc_regs array, based on the number of channels. 189 */ 190 void 191 wdc_allocate_regs(struct wdc_softc *wdc) 192 { 193 194 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 195 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 196 } 197 198 #if NSATA > 0 199 /* 200 * probe drives on SATA controllers with standard SATA registers: 201 * bring the PHYs online, read the drive signature and set drive flags 202 * appropriately. 203 */ 204 void 205 wdc_sataprobe(struct ata_channel *chp) 206 { 207 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 208 uint8_t st = 0, sc, sn, cl, ch; 209 int i, s; 210 211 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 212 213 /* reset the PHY and bring online */ 214 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 215 wdr->sata_status)) { 216 case SStatus_DET_DEV: 217 /* wait 5s for BSY to clear */ 218 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 219 bus_space_write_1(wdr->cmd_iot, 220 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 221 delay(10); /* 400ns delay */ 222 st = bus_space_read_1(wdr->cmd_iot, 223 wdr->cmd_iohs[wd_status], 0); 224 if ((st & WDCS_BSY) == 0) 225 break; 226 tsleep(&chp, PRIBIO, "sataprb", 1); 227 } 228 if (i == WDC_PROBE_WAIT * hz) 229 aprint_error_dev(chp->ch_atac->atac_dev, 230 "BSY never cleared, status 0x%02x\n", st); 231 sc = bus_space_read_1(wdr->cmd_iot, 232 wdr->cmd_iohs[wd_seccnt], 0); 233 sn = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_sector], 0); 235 cl = bus_space_read_1(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_cyl_lo], 0); 237 ch = bus_space_read_1(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_cyl_hi], 0); 239 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 240 "cl=0x%x ch=0x%x\n", 241 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 242 sc, sn, cl, ch), DEBUG_PROBE); 243 if (atabus_alloc_drives(chp, 1) != 0) 244 return; 245 /* 246 * sc and sn are supposed to be 0x1 for ATAPI, but in some 247 * cases we get wrong values here, so ignore it. 248 */ 249 s = splbio(); 250 if (cl == 0x14 && ch == 0xeb) 251 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 252 else 253 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 254 splx(s); 255 256 /* 257 * issue a reset in case only the interface part of the drive 258 * is up 259 */ 260 if (wdcreset(chp, RESET_SLEEP) != 0) 261 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 262 break; 263 264 default: 265 break; 266 } 267 } 268 #endif /* NSATA > 0 */ 269 270 271 /* Test to see controller with at last one attached drive is there. 272 * Returns a bit for each possible drive found (0x01 for drive 0, 273 * 0x02 for drive 1). 274 * Logic: 275 * - If a status register is at 0xff, assume there is no drive here 276 * (ISA has pull-up resistors). Similarly if the status register has 277 * the value we last wrote to the bus (for IDE interfaces without pullups). 278 * If no drive at all -> return. 279 * - reset the controller, wait for it to complete (may take up to 31s !). 280 * If timeout -> return. 281 * - test ATA/ATAPI signatures. If at last one drive found -> return. 282 * - try an ATA command on the master. 283 */ 284 285 void 286 wdc_drvprobe(struct ata_channel *chp) 287 { 288 struct ataparams params; /* XXX: large struct */ 289 struct atac_softc *atac = chp->ch_atac; 290 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 291 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 292 u_int8_t st0 = 0, st1 = 0; 293 int i, j, error, s; 294 295 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 296 return; 297 if (wdcprobe1(chp, 0) == 0) { 298 /* No drives, abort the attach here. */ 299 atabus_free_drives(chp); 300 return; 301 } 302 303 s = splbio(); 304 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 305 for (i = 0; i < mstohz(3000); i++) { 306 /* 307 * select drive 1 first, so that master is selected on 308 * exit from the loop 309 */ 310 if (chp->ch_ndrives > 1 && 311 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 312 if (wdc->select) 313 wdc->select(chp,1); 314 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 315 0, WDSD_IBM | 0x10); 316 delay(10); /* 400ns delay */ 317 st1 = bus_space_read_1(wdr->cmd_iot, 318 wdr->cmd_iohs[wd_status], 0); 319 } 320 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 321 if (wdc->select) 322 wdc->select(chp,0); 323 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 324 0, WDSD_IBM); 325 delay(10); /* 400ns delay */ 326 st0 = bus_space_read_1(wdr->cmd_iot, 327 wdr->cmd_iohs[wd_status], 0); 328 } 329 330 331 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 332 (st0 & WDCS_DRDY)) && 333 (chp->ch_ndrives < 2 || 334 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 335 (st1 & WDCS_DRDY))) 336 break; 337 #ifdef WDC_NO_IDS 338 /* cannot tsleep here (can't enable IPL_BIO interrups), 339 * delay instead 340 */ 341 delay(1000000 / hz); 342 #else 343 tsleep(¶ms, PRIBIO, "atadrdy", 1); 344 #endif 345 } 346 if ((st0 & WDCS_DRDY) == 0 && 347 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 348 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 349 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 350 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 351 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 352 splx(s); 353 354 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 355 device_xname(atac->atac_dev), 356 chp->ch_channel, st0, st1), DEBUG_PROBE); 357 358 /* Wait a bit, some devices are weird just after a reset. */ 359 delay(5000); 360 361 for (i = 0; i < chp->ch_ndrives; i++) { 362 #if NATA_DMA 363 /* 364 * Init error counter so that an error withing the first xfers 365 * will trigger a downgrade 366 */ 367 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 368 #endif 369 370 /* If controller can't do 16bit flag the drives as 32bit */ 371 if ((atac->atac_cap & 372 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 373 s = splbio(); 374 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 375 splx(s); 376 } 377 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 378 continue; 379 380 /* Shortcut in case we've been shutdown */ 381 if (chp->ch_flags & ATACH_SHUTDOWN) 382 return; 383 384 /* 385 * Issue an identify, to try to detect ghosts. 386 * Note that we can't use interrupts here, because if there 387 * is no devices, we will get a command aborted without 388 * interrupts. 389 */ 390 error = ata_get_params(&chp->ch_drive[i], 391 AT_WAIT | AT_POLL, ¶ms); 392 if (error != CMD_OK) { 393 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 394 395 /* Shortcut in case we've been shutdown */ 396 if (chp->ch_flags & ATACH_SHUTDOWN) 397 return; 398 399 error = ata_get_params(&chp->ch_drive[i], 400 AT_WAIT | AT_POLL, ¶ms); 401 } 402 if (error != CMD_OK) { 403 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 404 device_xname(atac->atac_dev), 405 chp->ch_channel, i, error), DEBUG_PROBE); 406 s = splbio(); 407 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 408 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 409 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 410 continue; 411 } 412 splx(s); 413 /* 414 * Pre-ATA drive ? 415 * Test registers writability (Error register not 416 * writable, but cyllo is), then try an ATA command. 417 */ 418 if (wdc->select) 419 wdc->select(chp,i); 420 bus_space_write_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 422 delay(10); /* 400ns delay */ 423 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 424 0, 0x58); 425 bus_space_write_1(wdr->cmd_iot, 426 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 427 if (bus_space_read_1(wdr->cmd_iot, 428 wdr->cmd_iohs[wd_error], 0) == 0x58 || 429 bus_space_read_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 431 ATADEBUG_PRINT(("%s:%d:%d: register " 432 "writability failed\n", 433 device_xname(atac->atac_dev), 434 chp->ch_channel, i), DEBUG_PROBE); 435 s = splbio(); 436 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 437 splx(s); 438 continue; 439 } 440 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 441 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 442 device_xname(atac->atac_dev), 443 chp->ch_channel, i), DEBUG_PROBE); 444 s = splbio(); 445 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 446 splx(s); 447 continue; 448 } 449 bus_space_write_1(wdr->cmd_iot, 450 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 451 delay(10); /* 400ns delay */ 452 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 453 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 454 device_xname(atac->atac_dev), 455 chp->ch_channel, i), DEBUG_PROBE); 456 s = splbio(); 457 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 458 splx(s); 459 } else { 460 s = splbio(); 461 for (j = 0; j < chp->ch_ndrives; j++) { 462 if (chp->ch_drive[i].drive_type != 463 ATA_DRIVET_NONE) { 464 chp->ch_drive[j].drive_type = 465 ATA_DRIVET_OLD; 466 } 467 } 468 splx(s); 469 } 470 } 471 } 472 } 473 474 int 475 wdcprobe(struct ata_channel *chp) 476 { 477 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 478 /* default reset method */ 479 if (wdc->reset == NULL) 480 wdc->reset = wdc_do_reset; 481 482 return (wdcprobe1(chp, 1)); 483 } 484 485 static int 486 wdcprobe1(struct ata_channel *chp, int poll) 487 { 488 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 489 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 490 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 491 u_int8_t ret_value = 0x03; 492 u_int8_t drive; 493 int s; 494 /* XXX if poll, wdc_probe_count is 0. */ 495 int wdc_probe_count = 496 poll ? (WDC_PROBE_WAIT / WDCDELAY) 497 : (WDC_PROBE_WAIT * hz); 498 499 /* 500 * Sanity check to see if the wdc channel responds at all. 501 */ 502 503 s = splbio(); 504 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 505 while (wdc_probe_count-- > 0) { 506 if (wdc->select) 507 wdc->select(chp,0); 508 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM); 511 delay(10); /* 400ns delay */ 512 st0 = bus_space_read_1(wdr->cmd_iot, 513 wdr->cmd_iohs[wd_status], 0); 514 515 if (wdc->select) 516 wdc->select(chp,1); 517 518 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 519 0, WDSD_IBM | 0x10); 520 delay(10); /* 400ns delay */ 521 st1 = bus_space_read_1(wdr->cmd_iot, 522 wdr->cmd_iohs[wd_status], 0); 523 if ((st0 & WDCS_BSY) == 0) 524 break; 525 } 526 527 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 528 device_xname(chp->ch_atac->atac_dev), 529 chp->ch_channel, st0, st1), DEBUG_PROBE); 530 531 if (st0 == 0xff || st0 == WDSD_IBM) 532 ret_value &= ~0x01; 533 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 534 ret_value &= ~0x02; 535 /* Register writability test, drive 0. */ 536 if (ret_value & 0x01) { 537 if (wdc->select) 538 wdc->select(chp,0); 539 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 540 0, WDSD_IBM); 541 bus_space_write_1(wdr->cmd_iot, 542 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 543 cl = bus_space_read_1(wdr->cmd_iot, 544 wdr->cmd_iohs[wd_cyl_lo], 0); 545 if (cl != 0x02) { 546 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 547 "got 0x%x != 0x02\n", 548 device_xname(chp->ch_atac->atac_dev), 549 chp->ch_channel, cl), 550 DEBUG_PROBE); 551 ret_value &= ~0x01; 552 } 553 bus_space_write_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 555 cl = bus_space_read_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_cyl_lo], 0); 557 if (cl != 0x01) { 558 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 559 "got 0x%x != 0x01\n", 560 device_xname(chp->ch_atac->atac_dev), 561 chp->ch_channel, cl), 562 DEBUG_PROBE); 563 ret_value &= ~0x01; 564 } 565 bus_space_write_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_sector], 0, 0x01); 567 cl = bus_space_read_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_sector], 0); 569 if (cl != 0x01) { 570 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 571 "got 0x%x != 0x01\n", 572 device_xname(chp->ch_atac->atac_dev), 573 chp->ch_channel, cl), 574 DEBUG_PROBE); 575 ret_value &= ~0x01; 576 } 577 bus_space_write_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_sector], 0, 0x02); 579 cl = bus_space_read_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_sector], 0); 581 if (cl != 0x02) { 582 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 583 "got 0x%x != 0x02\n", 584 device_xname(chp->ch_atac->atac_dev), 585 chp->ch_channel, cl), 586 DEBUG_PROBE); 587 ret_value &= ~0x01; 588 } 589 cl = bus_space_read_1(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_cyl_lo], 0); 591 if (cl != 0x01) { 592 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 593 "got 0x%x != 0x01\n", 594 device_xname(chp->ch_atac->atac_dev), 595 chp->ch_channel, cl), 596 DEBUG_PROBE); 597 ret_value &= ~0x01; 598 } 599 } 600 /* Register writability test, drive 1. */ 601 if (ret_value & 0x02) { 602 if (wdc->select) 603 wdc->select(chp,1); 604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 605 0, WDSD_IBM | 0x10); 606 bus_space_write_1(wdr->cmd_iot, 607 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 608 cl = bus_space_read_1(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_lo], 0); 610 if (cl != 0x02) { 611 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 612 "got 0x%x != 0x02\n", 613 device_xname(chp->ch_atac->atac_dev), 614 chp->ch_channel, cl), 615 DEBUG_PROBE); 616 ret_value &= ~0x02; 617 } 618 bus_space_write_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 620 cl = bus_space_read_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_lo], 0); 622 if (cl != 0x01) { 623 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 624 "got 0x%x != 0x01\n", 625 device_xname(chp->ch_atac->atac_dev), 626 chp->ch_channel, cl), 627 DEBUG_PROBE); 628 ret_value &= ~0x02; 629 } 630 bus_space_write_1(wdr->cmd_iot, 631 wdr->cmd_iohs[wd_sector], 0, 0x01); 632 cl = bus_space_read_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_sector], 0); 634 if (cl != 0x01) { 635 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 636 "got 0x%x != 0x01\n", 637 device_xname(chp->ch_atac->atac_dev), 638 chp->ch_channel, cl), 639 DEBUG_PROBE); 640 ret_value &= ~0x02; 641 } 642 bus_space_write_1(wdr->cmd_iot, 643 wdr->cmd_iohs[wd_sector], 0, 0x02); 644 cl = bus_space_read_1(wdr->cmd_iot, 645 wdr->cmd_iohs[wd_sector], 0); 646 if (cl != 0x02) { 647 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 648 "got 0x%x != 0x02\n", 649 device_xname(chp->ch_atac->atac_dev), 650 chp->ch_channel, cl), 651 DEBUG_PROBE); 652 ret_value &= ~0x02; 653 } 654 cl = bus_space_read_1(wdr->cmd_iot, 655 wdr->cmd_iohs[wd_cyl_lo], 0); 656 if (cl != 0x01) { 657 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 658 "got 0x%x != 0x01\n", 659 device_xname(chp->ch_atac->atac_dev), 660 chp->ch_channel, cl), 661 DEBUG_PROBE); 662 ret_value &= ~0x02; 663 } 664 } 665 666 if (ret_value == 0) { 667 splx(s); 668 return 0; 669 } 670 } 671 672 673 #if 0 /* XXX this break some ATA or ATAPI devices */ 674 /* 675 * reset bus. Also send an ATAPI_RESET to devices, in case there are 676 * ATAPI device out there which don't react to the bus reset 677 */ 678 if (ret_value & 0x01) { 679 if (wdc->select) 680 wdc->select(chp,0); 681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 682 0, WDSD_IBM); 683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 684 ATAPI_SOFT_RESET); 685 } 686 if (ret_value & 0x02) { 687 if (wdc->select) 688 wdc->select(chp,0); 689 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 690 0, WDSD_IBM | 0x10); 691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 692 ATAPI_SOFT_RESET); 693 } 694 695 delay(5000); 696 #endif 697 698 wdc->reset(chp, RESET_POLL); 699 DELAY(2000); 700 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 701 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 702 #ifdef WDC_NO_IDS 703 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 704 #else 705 splx(s); 706 ret_value = __wdcwait_reset(chp, ret_value, poll); 707 s = splbio(); 708 #endif 709 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 710 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 711 ret_value), DEBUG_PROBE); 712 713 /* if reset failed, there's nothing here */ 714 if (ret_value == 0) { 715 splx(s); 716 return 0; 717 } 718 719 /* 720 * Test presence of drives. First test register signatures looking 721 * for ATAPI devices. If it's not an ATAPI and reset said there may 722 * be something here assume it's ATA or OLD. Ghost will be killed 723 * later in attach routine. 724 */ 725 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 726 if ((ret_value & (0x01 << drive)) == 0) 727 continue; 728 if (wdc->select) 729 wdc->select(chp,drive); 730 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 731 WDSD_IBM | (drive << 4)); 732 delay(10); /* 400ns delay */ 733 /* Save registers contents */ 734 sc = bus_space_read_1(wdr->cmd_iot, 735 wdr->cmd_iohs[wd_seccnt], 0); 736 sn = bus_space_read_1(wdr->cmd_iot, 737 wdr->cmd_iohs[wd_sector], 0); 738 cl = bus_space_read_1(wdr->cmd_iot, 739 wdr->cmd_iohs[wd_cyl_lo], 0); 740 ch = bus_space_read_1(wdr->cmd_iot, 741 wdr->cmd_iohs[wd_cyl_hi], 0); 742 743 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 744 "cl=0x%x ch=0x%x\n", 745 device_xname(chp->ch_atac->atac_dev), 746 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 747 /* 748 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 749 * we get wrong values here, so ignore it. 750 */ 751 if (chp->ch_drive != NULL) { 752 if (cl == 0x14 && ch == 0xeb) { 753 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 754 } else { 755 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 756 } 757 } 758 } 759 /* 760 * Select an existing drive before lowering spl, some WDC_NO_IDS 761 * devices incorrectly assert IRQ on nonexistent slave 762 */ 763 if (ret_value & 0x01) { 764 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 765 WDSD_IBM); 766 (void)bus_space_read_1(wdr->cmd_iot, 767 wdr->cmd_iohs[wd_status], 0); 768 } 769 splx(s); 770 return (ret_value); 771 } 772 773 void 774 wdcattach(struct ata_channel *chp) 775 { 776 struct atac_softc *atac = chp->ch_atac; 777 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 778 779 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 780 781 /* default data transfer methods */ 782 if (wdc->datain_pio == NULL) 783 wdc->datain_pio = wdc_datain_pio; 784 if (wdc->dataout_pio == NULL) 785 wdc->dataout_pio = wdc_dataout_pio; 786 /* default reset method */ 787 if (wdc->reset == NULL) 788 wdc->reset = wdc_do_reset; 789 790 /* initialise global data */ 791 if (atac->atac_bustype_ata == NULL) 792 atac->atac_bustype_ata = &wdc_ata_bustype; 793 if (atac->atac_probe == NULL) 794 atac->atac_probe = wdc_drvprobe; 795 #if NATAPIBUS > 0 796 if (atac->atac_atapibus_attach == NULL) 797 atac->atac_atapibus_attach = wdc_atapibus_attach; 798 #endif 799 800 ata_channel_attach(chp); 801 } 802 803 void 804 wdc_childdetached(device_t self, device_t child) 805 { 806 struct atac_softc *atac = device_private(self); 807 struct ata_channel *chp; 808 int i; 809 810 for (i = 0; i < atac->atac_nchannels; i++) { 811 chp = atac->atac_channels[i]; 812 if (child == chp->atabus) { 813 chp->atabus = NULL; 814 return; 815 } 816 } 817 } 818 819 int 820 wdcdetach(device_t self, int flags) 821 { 822 struct atac_softc *atac = device_private(self); 823 struct ata_channel *chp; 824 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 825 int i, error = 0; 826 827 for (i = 0; i < atac->atac_nchannels; i++) { 828 chp = atac->atac_channels[i]; 829 if (chp->atabus == NULL) 830 continue; 831 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 832 device_xname(atac->atac_dev), device_xname(chp->atabus)), 833 DEBUG_DETACH); 834 if ((error = config_detach(chp->atabus, flags)) != 0) 835 return error; 836 } 837 if (adapt->adapt_refcnt != 0) 838 return EBUSY; 839 return 0; 840 } 841 842 /* restart an interrupted I/O */ 843 void 844 wdcrestart(void *v) 845 { 846 struct ata_channel *chp = v; 847 int s; 848 849 s = splbio(); 850 atastart(chp); 851 splx(s); 852 } 853 854 855 /* 856 * Interrupt routine for the controller. Acknowledge the interrupt, check for 857 * errors on the current operation, mark it done if necessary, and start the 858 * next request. Also check for a partially done transfer, and continue with 859 * the next chunk if so. 860 */ 861 int 862 wdcintr(void *arg) 863 { 864 struct ata_channel *chp = arg; 865 struct atac_softc *atac = chp->ch_atac; 866 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 867 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 868 struct ata_xfer *xfer; 869 int ret; 870 871 if (!device_is_active(atac->atac_dev)) { 872 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 873 DEBUG_INTR); 874 return (0); 875 } 876 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 877 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 878 /* try to clear the pending interrupt anyway */ 879 (void)bus_space_read_1(wdr->cmd_iot, 880 wdr->cmd_iohs[wd_status], 0); 881 return (0); 882 } 883 884 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 885 xfer = chp->ch_queue->active_xfer; 886 #ifdef DIAGNOSTIC 887 if (xfer == NULL) 888 panic("wdcintr: no xfer"); 889 if (xfer->c_chp != chp) { 890 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 891 chp->ch_channel); 892 panic("wdcintr: wrong channel"); 893 } 894 #endif 895 #if NATA_DMA || NATA_PIOBM 896 if (chp->ch_flags & ATACH_DMA_WAIT) { 897 wdc->dma_status = 898 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 899 xfer->c_drive, WDC_DMAEND_END); 900 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 901 /* IRQ not for us, not detected by DMA engine */ 902 return 0; 903 } 904 chp->ch_flags &= ~ATACH_DMA_WAIT; 905 } 906 #endif 907 chp->ch_flags &= ~ATACH_IRQ_WAIT; 908 KASSERT(xfer->c_intr != NULL); 909 ret = xfer->c_intr(chp, xfer, 1); 910 if (ret == 0) /* irq was not for us, still waiting for irq */ 911 chp->ch_flags |= ATACH_IRQ_WAIT; 912 return (ret); 913 } 914 915 /* Put all disk in RESET state */ 916 void 917 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 918 { 919 struct ata_channel *chp = drvp->chnl_softc; 920 921 KASSERT(sigp == NULL); 922 923 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 924 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 925 drvp->drive), DEBUG_FUNCS); 926 927 ata_reset_channel(chp, flags); 928 } 929 930 void 931 wdc_reset_channel(struct ata_channel *chp, int flags) 932 { 933 TAILQ_HEAD(, ata_xfer) reset_xfer; 934 struct ata_xfer *xfer, *next_xfer; 935 #if NATA_DMA || NATA_PIOBM 936 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 937 #endif 938 TAILQ_INIT(&reset_xfer); 939 940 chp->ch_flags &= ~ATACH_IRQ_WAIT; 941 942 /* 943 * if the current command if on an ATAPI device, issue a 944 * ATAPI_SOFT_RESET 945 */ 946 xfer = chp->ch_queue->active_xfer; 947 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 948 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 949 if (flags & AT_WAIT) 950 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 951 else 952 delay(1000); 953 } 954 955 /* reset the channel */ 956 if (flags & AT_WAIT) 957 (void) wdcreset(chp, RESET_SLEEP); 958 else 959 (void) wdcreset(chp, RESET_POLL); 960 961 /* 962 * wait a bit after reset; in case the DMA engines needs some time 963 * to recover. 964 */ 965 if (flags & AT_WAIT) 966 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 967 else 968 delay(1000); 969 /* 970 * look for pending xfers. If we have a shared queue, we'll also reset 971 * the other channel if the current xfer is running on it. 972 * Then we'll dequeue only the xfers for this channel. 973 */ 974 if ((flags & AT_RST_NOCMD) == 0) { 975 /* 976 * move all xfers queued for this channel to the reset queue, 977 * and then process the current xfer and then the reset queue. 978 * We have to use a temporary queue because c_kill_xfer() 979 * may requeue commands. 980 */ 981 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 982 xfer != NULL; xfer = next_xfer) { 983 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 984 if (xfer->c_chp != chp) 985 continue; 986 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 987 xfer, c_xferchain); 988 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 989 } 990 xfer = chp->ch_queue->active_xfer; 991 if (xfer) { 992 if (xfer->c_chp != chp) 993 ata_reset_channel(xfer->c_chp, flags); 994 else { 995 callout_stop(&chp->ch_callout); 996 #if NATA_DMA || NATA_PIOBM 997 /* 998 * If we're waiting for DMA, stop the 999 * DMA engine 1000 */ 1001 if (chp->ch_flags & ATACH_DMA_WAIT) { 1002 (*wdc->dma_finish)( 1003 wdc->dma_arg, 1004 chp->ch_channel, 1005 xfer->c_drive, 1006 WDC_DMAEND_ABRT_QUIET); 1007 chp->ch_flags &= ~ATACH_DMA_WAIT; 1008 } 1009 #endif 1010 chp->ch_queue->active_xfer = NULL; 1011 if ((flags & AT_RST_EMERG) == 0) 1012 xfer->c_kill_xfer( 1013 chp, xfer, KILL_RESET); 1014 } 1015 } 1016 1017 for (xfer = TAILQ_FIRST(&reset_xfer); 1018 xfer != NULL; xfer = next_xfer) { 1019 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1020 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1021 if ((flags & AT_RST_EMERG) == 0) 1022 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1023 } 1024 } 1025 } 1026 1027 static int 1028 wdcreset(struct ata_channel *chp, int poll) 1029 { 1030 struct atac_softc *atac = chp->ch_atac; 1031 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1032 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1033 int drv_mask1, drv_mask2; 1034 1035 #ifdef WDC_NO_IDS 1036 poll = RESET_POLL; 1037 #endif 1038 wdc->reset(chp, poll); 1039 1040 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) ? 0x01:0x00; 1041 if (chp->ch_ndrives > 1) 1042 drv_mask1 |= 1043 (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) ? 0x02:0x00; 1044 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1045 (poll == RESET_SLEEP) ? 0 : 1); 1046 if (drv_mask2 != drv_mask1) { 1047 aprint_error("%s channel %d: reset failed for", 1048 device_xname(atac->atac_dev), chp->ch_channel); 1049 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1050 aprint_normal(" drive 0"); 1051 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1052 aprint_normal(" drive 1"); 1053 aprint_normal("\n"); 1054 } 1055 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1056 return (drv_mask1 != drv_mask2) ? 1 : 0; 1057 } 1058 1059 void 1060 wdc_do_reset(struct ata_channel *chp, int poll) 1061 { 1062 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1063 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1064 int s = 0; 1065 1066 if (poll != RESET_SLEEP) 1067 s = splbio(); 1068 if (wdc->select) 1069 wdc->select(chp,0); 1070 /* master */ 1071 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1072 delay(10); /* 400ns delay */ 1073 /* assert SRST, wait for reset to complete */ 1074 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1075 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1076 delay(2000); 1077 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1078 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1079 WDCTL_4BIT | WDCTL_IDS); 1080 delay(10); /* 400ns delay */ 1081 if (poll != RESET_SLEEP) { 1082 /* ACK interrupt in case there is one pending left */ 1083 if (wdc->irqack) 1084 wdc->irqack(chp); 1085 splx(s); 1086 } 1087 } 1088 1089 static int 1090 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1091 { 1092 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1093 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1094 int timeout, nloop; 1095 u_int8_t st0 = 0, st1 = 0; 1096 #ifdef ATADEBUG 1097 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1098 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1099 #endif 1100 if (poll) 1101 nloop = WDCNDELAY_RST; 1102 else 1103 nloop = WDC_RESET_WAIT * hz / 1000; 1104 /* wait for BSY to deassert */ 1105 for (timeout = 0; timeout < nloop; timeout++) { 1106 if ((drv_mask & 0x01) != 0) { 1107 if (wdc->select) 1108 wdc->select(chp,0); 1109 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1110 0, WDSD_IBM); /* master */ 1111 delay(10); 1112 st0 = bus_space_read_1(wdr->cmd_iot, 1113 wdr->cmd_iohs[wd_status], 0); 1114 #ifdef ATADEBUG 1115 sc0 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_seccnt], 0); 1117 sn0 = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_sector], 0); 1119 cl0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_cyl_lo], 0); 1121 ch0 = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_cyl_hi], 0); 1123 #endif 1124 } 1125 if ((drv_mask & 0x02) != 0) { 1126 if (wdc->select) 1127 wdc->select(chp,1); 1128 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1129 0, WDSD_IBM | 0x10); /* slave */ 1130 delay(10); 1131 st1 = bus_space_read_1(wdr->cmd_iot, 1132 wdr->cmd_iohs[wd_status], 0); 1133 #ifdef ATADEBUG 1134 sc1 = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_seccnt], 0); 1136 sn1 = bus_space_read_1(wdr->cmd_iot, 1137 wdr->cmd_iohs[wd_sector], 0); 1138 cl1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_cyl_lo], 0); 1140 ch1 = bus_space_read_1(wdr->cmd_iot, 1141 wdr->cmd_iohs[wd_cyl_hi], 0); 1142 #endif 1143 } 1144 1145 if ((drv_mask & 0x01) == 0) { 1146 /* no master */ 1147 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1148 /* No master, slave is ready, it's done */ 1149 goto end; 1150 } 1151 if ((drv_mask & 0x02) == 0) { 1152 /* No master, no slave: it's done */ 1153 goto end; 1154 } 1155 } else if ((drv_mask & 0x02) == 0) { 1156 /* no slave */ 1157 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1158 /* No slave, master is ready, it's done */ 1159 goto end; 1160 } 1161 } else { 1162 /* Wait for both master and slave to be ready */ 1163 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1164 goto end; 1165 } 1166 } 1167 if (poll) 1168 delay(WDCDELAY); 1169 else 1170 tsleep(&nloop, PRIBIO, "atarst", 1); 1171 } 1172 /* Reset timed out. Maybe it's because drv_mask was not right */ 1173 if (st0 & WDCS_BSY) 1174 drv_mask &= ~0x01; 1175 if (st1 & WDCS_BSY) 1176 drv_mask &= ~0x02; 1177 end: 1178 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1179 "cl=0x%x ch=0x%x\n", 1180 device_xname(chp->ch_atac->atac_dev), 1181 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1182 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1183 "cl=0x%x ch=0x%x\n", 1184 device_xname(chp->ch_atac->atac_dev), 1185 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1186 1187 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1188 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1189 st0, st1), DEBUG_PROBE); 1190 1191 return drv_mask; 1192 } 1193 1194 /* 1195 * Wait for a drive to be !BSY, and have mask in its status register. 1196 * return -1 for a timeout after "timeout" ms. 1197 */ 1198 static int 1199 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1200 { 1201 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1202 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1203 u_char status; 1204 int xtime = 0; 1205 1206 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1207 device_xname(chp->ch_atac->atac_dev), 1208 chp->ch_channel), DEBUG_STATUS); 1209 chp->ch_error = 0; 1210 1211 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1212 1213 for (;;) { 1214 chp->ch_status = status = 1215 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1216 if ((status & (WDCS_BSY | mask)) == bits) 1217 break; 1218 if (++xtime > timeout) { 1219 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1220 "status %x error %x (mask 0x%x bits 0x%x)\n", 1221 xtime, status, 1222 bus_space_read_1(wdr->cmd_iot, 1223 wdr->cmd_iohs[wd_error], 0), mask, bits), 1224 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1225 return(WDCWAIT_TOUT); 1226 } 1227 delay(WDCDELAY); 1228 } 1229 #ifdef ATADEBUG 1230 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1231 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1232 #endif 1233 if (status & WDCS_ERR) 1234 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1235 wdr->cmd_iohs[wd_error], 0); 1236 #ifdef WDCNDELAY_DEBUG 1237 /* After autoconfig, there should be no long delays. */ 1238 if (!cold && xtime > WDCNDELAY_DEBUG) { 1239 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1240 if (xfer == NULL) 1241 printf("%s channel %d: warning: busy-wait took %dus\n", 1242 device_xname(chp->ch_atac->atac_dev), 1243 chp->ch_channel, WDCDELAY * xtime); 1244 else 1245 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1246 device_xname(chp->ch_atac->atac_dev), 1247 chp->ch_channel, xfer->c_drive, 1248 WDCDELAY * xtime); 1249 } 1250 #endif 1251 return(WDCWAIT_OK); 1252 } 1253 1254 /* 1255 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1256 * thread if possible 1257 */ 1258 int 1259 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1260 { 1261 int error, i, timeout_hz = mstohz(timeout); 1262 1263 if (timeout_hz == 0 || 1264 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1265 error = __wdcwait(chp, mask, bits, timeout); 1266 else { 1267 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1268 if (error != 0) { 1269 if ((chp->ch_flags & ATACH_TH_RUN) || 1270 (flags & AT_WAIT)) { 1271 /* 1272 * we're running in the channel thread 1273 * or some userland thread context 1274 */ 1275 for (i = 0; i < timeout_hz; i++) { 1276 if (__wdcwait(chp, mask, bits, 1277 WDCDELAY_POLL) == 0) { 1278 error = 0; 1279 break; 1280 } 1281 tsleep(&chp, PRIBIO, "atapoll", 1); 1282 } 1283 } else { 1284 /* 1285 * we're probably in interrupt context, 1286 * ask the thread to come back here 1287 */ 1288 #ifdef DIAGNOSTIC 1289 if (chp->ch_queue->queue_freeze > 0) 1290 panic("wdcwait: queue_freeze"); 1291 #endif 1292 chp->ch_queue->queue_freeze++; 1293 wakeup(&chp->ch_thread); 1294 return(WDCWAIT_THR); 1295 } 1296 } 1297 } 1298 return (error); 1299 } 1300 1301 1302 #if NATA_DMA 1303 /* 1304 * Busy-wait for DMA to complete 1305 */ 1306 int 1307 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1308 { 1309 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1310 int xtime; 1311 1312 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1313 wdc->dma_status = 1314 (*wdc->dma_finish)(wdc->dma_arg, 1315 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1316 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1317 return 0; 1318 delay(WDCDELAY); 1319 } 1320 /* timeout, force a DMA halt */ 1321 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1322 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1323 return 1; 1324 } 1325 #endif 1326 1327 void 1328 wdctimeout(void *arg) 1329 { 1330 struct ata_channel *chp = (struct ata_channel *)arg; 1331 #if NATA_DMA || NATA_PIOBM 1332 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1333 #endif 1334 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1335 int s; 1336 1337 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1338 1339 s = splbio(); 1340 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1341 __wdcerror(chp, "lost interrupt"); 1342 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1343 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1344 xfer->c_bcount, 1345 xfer->c_skip); 1346 #if NATA_DMA || NATA_PIOBM 1347 if (chp->ch_flags & ATACH_DMA_WAIT) { 1348 wdc->dma_status = 1349 (*wdc->dma_finish)(wdc->dma_arg, 1350 chp->ch_channel, xfer->c_drive, 1351 WDC_DMAEND_ABRT); 1352 chp->ch_flags &= ~ATACH_DMA_WAIT; 1353 } 1354 #endif 1355 /* 1356 * Call the interrupt routine. If we just missed an interrupt, 1357 * it will do what's needed. Else, it will take the needed 1358 * action (reset the device). 1359 * Before that we need to reinstall the timeout callback, 1360 * in case it will miss another irq while in this transfer 1361 * We arbitray chose it to be 1s 1362 */ 1363 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1364 xfer->c_flags |= C_TIMEOU; 1365 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1366 KASSERT(xfer->c_intr != NULL); 1367 xfer->c_intr(chp, xfer, 1); 1368 } else 1369 __wdcerror(chp, "missing untimeout"); 1370 splx(s); 1371 } 1372 1373 int 1374 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1375 { 1376 struct ata_channel *chp = drvp->chnl_softc; 1377 struct ata_xfer *xfer; 1378 int s, ret; 1379 1380 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1381 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1382 drvp->drive), DEBUG_FUNCS); 1383 1384 /* set up an xfer and queue. Wait for completion */ 1385 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1386 ATAXF_NOSLEEP); 1387 if (xfer == NULL) { 1388 return ATACMD_TRY_AGAIN; 1389 } 1390 1391 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1392 ata_c->flags |= AT_POLL; 1393 if (ata_c->flags & AT_POLL) 1394 xfer->c_flags |= C_POLL; 1395 if (ata_c->flags & AT_WAIT) 1396 xfer->c_flags |= C_WAIT; 1397 xfer->c_drive = drvp->drive; 1398 xfer->c_databuf = ata_c->data; 1399 xfer->c_bcount = ata_c->bcount; 1400 xfer->c_cmd = ata_c; 1401 xfer->c_start = __wdccommand_start; 1402 xfer->c_intr = __wdccommand_intr; 1403 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1404 1405 s = splbio(); 1406 ata_exec_xfer(chp, xfer); 1407 #ifdef DIAGNOSTIC 1408 if ((ata_c->flags & AT_POLL) != 0 && 1409 (ata_c->flags & AT_DONE) == 0) 1410 panic("wdc_exec_command: polled command not done"); 1411 #endif 1412 if (ata_c->flags & AT_DONE) { 1413 ret = ATACMD_COMPLETE; 1414 } else { 1415 if (ata_c->flags & AT_WAIT) { 1416 while ((ata_c->flags & AT_DONE) == 0) { 1417 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1418 } 1419 ret = ATACMD_COMPLETE; 1420 } else { 1421 ret = ATACMD_QUEUED; 1422 } 1423 } 1424 splx(s); 1425 return ret; 1426 } 1427 1428 static void 1429 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1430 { 1431 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1432 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1433 int drive = xfer->c_drive; 1434 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1435 struct ata_command *ata_c = xfer->c_cmd; 1436 1437 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1438 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1439 xfer->c_drive), 1440 DEBUG_FUNCS); 1441 1442 if (wdc->select) 1443 wdc->select(chp,drive); 1444 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1445 WDSD_IBM | (drive << 4)); 1446 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1447 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1448 case WDCWAIT_OK: 1449 break; 1450 case WDCWAIT_TOUT: 1451 ata_c->flags |= AT_TIMEOU; 1452 __wdccommand_done(chp, xfer); 1453 return; 1454 case WDCWAIT_THR: 1455 return; 1456 } 1457 if (ata_c->flags & AT_POLL) { 1458 /* polled command, disable interrupts */ 1459 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1460 WDCTL_4BIT | WDCTL_IDS); 1461 } 1462 if ((ata_c->flags & AT_LBA48) != 0) { 1463 wdccommandext(chp, drive, ata_c->r_command, 1464 ata_c->r_lba, ata_c->r_count, ata_c->r_features); 1465 } else { 1466 wdccommand(chp, drive, ata_c->r_command, 1467 (ata_c->r_lba >> 8) & 0xffff, 1468 WDSD_IBM | (drive << 4) | 1469 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1470 ((ata_c->r_lba >> 24) & 0x0f), 1471 ata_c->r_lba & 0xff, 1472 ata_c->r_count & 0xff, 1473 ata_c->r_features & 0xff); 1474 } 1475 1476 if ((ata_c->flags & AT_POLL) == 0) { 1477 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1478 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1479 wdctimeout, chp); 1480 return; 1481 } 1482 /* 1483 * Polled command. Wait for drive ready or drq. Done in intr(). 1484 * Wait for at last 400ns for status bit to be valid. 1485 */ 1486 delay(10); /* 400ns delay */ 1487 __wdccommand_intr(chp, xfer, 0); 1488 } 1489 1490 static int 1491 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1492 { 1493 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1494 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1495 struct ata_command *ata_c = xfer->c_cmd; 1496 int bcount = ata_c->bcount; 1497 char *data = ata_c->data; 1498 int wflags; 1499 int drive_flags; 1500 1501 if (ata_c->r_command == WDCC_IDENTIFY || 1502 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1503 /* 1504 * The IDENTIFY data has been designed as an array of 1505 * u_int16_t, so we can byteswap it on the fly. 1506 * Historically it's what we have always done so keeping it 1507 * here ensure binary backward compatibility. 1508 */ 1509 drive_flags = ATA_DRIVE_NOSTREAM | 1510 chp->ch_drive[xfer->c_drive].drive_flags; 1511 } else { 1512 /* 1513 * Other data structure are opaque and should be transfered 1514 * as is. 1515 */ 1516 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1517 } 1518 1519 #ifdef WDC_NO_IDS 1520 wflags = AT_POLL; 1521 #else 1522 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1523 /* both wait and poll, we can tsleep here */ 1524 wflags = AT_WAIT | AT_POLL; 1525 } else { 1526 wflags = AT_POLL; 1527 } 1528 #endif 1529 1530 again: 1531 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1532 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1533 xfer->c_drive), DEBUG_INTR); 1534 /* 1535 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1536 * Reselect again, it doesn't hurt for others commands, and the time 1537 * penalty for the extra register write is acceptable, 1538 * wdc_exec_command() isn't called often (mostly for autoconfig) 1539 */ 1540 if ((xfer->c_flags & C_ATAPI) != 0) { 1541 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1542 WDSD_IBM | (xfer->c_drive << 4)); 1543 } 1544 if ((ata_c->flags & AT_XFDONE) != 0) { 1545 /* 1546 * We have completed a data xfer. The drive should now be 1547 * in its initial state 1548 */ 1549 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1550 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1551 wflags) == WDCWAIT_TOUT) { 1552 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1553 return 0; /* IRQ was not for us */ 1554 ata_c->flags |= AT_TIMEOU; 1555 } 1556 goto out; 1557 } 1558 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1559 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1560 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1561 return 0; /* IRQ was not for us */ 1562 ata_c->flags |= AT_TIMEOU; 1563 goto out; 1564 } 1565 if (wdc->irqack) 1566 wdc->irqack(chp); 1567 if (ata_c->flags & AT_READ) { 1568 if ((chp->ch_status & WDCS_DRQ) == 0) { 1569 ata_c->flags |= AT_TIMEOU; 1570 goto out; 1571 } 1572 wdc->datain_pio(chp, drive_flags, data, bcount); 1573 /* at this point the drive should be in its initial state */ 1574 ata_c->flags |= AT_XFDONE; 1575 /* 1576 * XXX checking the status register again here cause some 1577 * hardware to timeout. 1578 */ 1579 } else if (ata_c->flags & AT_WRITE) { 1580 if ((chp->ch_status & WDCS_DRQ) == 0) { 1581 ata_c->flags |= AT_TIMEOU; 1582 goto out; 1583 } 1584 wdc->dataout_pio(chp, drive_flags, data, bcount); 1585 ata_c->flags |= AT_XFDONE; 1586 if ((ata_c->flags & AT_POLL) == 0) { 1587 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1588 callout_reset(&chp->ch_callout, 1589 mstohz(ata_c->timeout), wdctimeout, chp); 1590 return 1; 1591 } else { 1592 goto again; 1593 } 1594 } 1595 out: 1596 __wdccommand_done(chp, xfer); 1597 return 1; 1598 } 1599 1600 static void 1601 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1602 { 1603 struct atac_softc *atac = chp->ch_atac; 1604 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1605 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1606 struct ata_command *ata_c = xfer->c_cmd; 1607 1608 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1609 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1610 ata_c->flags), DEBUG_FUNCS); 1611 1612 1613 if (chp->ch_status & WDCS_DWF) 1614 ata_c->flags |= AT_DF; 1615 if (chp->ch_status & WDCS_ERR) { 1616 ata_c->flags |= AT_ERROR; 1617 ata_c->r_error = chp->ch_error; 1618 } 1619 if ((ata_c->flags & AT_READREG) != 0 && 1620 device_is_active(atac->atac_dev) && 1621 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1622 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1623 wdr->cmd_iohs[wd_status], 0); 1624 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1625 wdr->cmd_iohs[wd_error], 0); 1626 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1627 wdr->cmd_iohs[wd_seccnt], 0); 1628 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1629 wdr->cmd_iohs[wd_sector], 0) << 0; 1630 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1631 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1632 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1633 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1634 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1635 wdr->cmd_iohs[wd_sdh], 0); 1636 1637 if ((ata_c->flags & AT_LBA48) != 0) { 1638 if ((ata_c->flags & AT_POLL) != 0) 1639 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1640 wd_aux_ctlr, 1641 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1642 else 1643 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1644 wd_aux_ctlr, WDCTL_HOB|WDCTL_4BIT); 1645 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1646 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1647 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_sector], 0) << 24; 1649 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1651 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1652 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1653 if ((ata_c->flags & AT_POLL) != 0) 1654 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1655 wd_aux_ctlr, WDCTL_4BIT|WDCTL_IDS); 1656 else 1657 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1658 wd_aux_ctlr, WDCTL_4BIT); 1659 } else { 1660 ata_c->r_lba |= 1661 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1662 } 1663 ata_c->r_device &= 0xf0; 1664 } 1665 callout_stop(&chp->ch_callout); 1666 chp->ch_queue->active_xfer = NULL; 1667 if (ata_c->flags & AT_POLL) { 1668 /* enable interrupts */ 1669 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1670 WDCTL_4BIT); 1671 delay(10); /* some drives need a little delay here */ 1672 } 1673 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1674 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1675 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1676 wakeup(&chp->ch_queue->active_xfer); 1677 } else 1678 __wdccommand_done_end(chp, xfer); 1679 } 1680 1681 static void 1682 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1683 { 1684 struct ata_command *ata_c = xfer->c_cmd; 1685 1686 ata_c->flags |= AT_DONE; 1687 ata_free_xfer(chp, xfer); 1688 if (ata_c->flags & AT_WAIT) 1689 wakeup(ata_c); 1690 else if (ata_c->callback) 1691 ata_c->callback(ata_c->callback_arg); 1692 atastart(chp); 1693 return; 1694 } 1695 1696 static void 1697 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1698 int reason) 1699 { 1700 struct ata_command *ata_c = xfer->c_cmd; 1701 1702 switch (reason) { 1703 case KILL_GONE: 1704 ata_c->flags |= AT_GONE; 1705 break; 1706 case KILL_RESET: 1707 ata_c->flags |= AT_RESET; 1708 break; 1709 default: 1710 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1711 reason); 1712 panic("__wdccommand_kill_xfer"); 1713 } 1714 __wdccommand_done_end(chp, xfer); 1715 } 1716 1717 /* 1718 * Send a command. The drive should be ready. 1719 * Assumes interrupts are blocked. 1720 */ 1721 void 1722 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1723 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1724 u_int8_t features) 1725 { 1726 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1727 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1728 1729 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1730 "sector=%d count=%d features=%d\n", 1731 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1732 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1733 1734 if (wdc->select) 1735 wdc->select(chp,drive); 1736 1737 /* Select drive, head, and addressing mode. */ 1738 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1739 WDSD_IBM | (drive << 4) | head); 1740 /* Load parameters into the wd_features register. */ 1741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1742 features); 1743 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1745 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1747 0, cylin >> 8); 1748 1749 /* Send command. */ 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1751 return; 1752 } 1753 1754 /* 1755 * Send a 48-bit addressing command. The drive should be ready. 1756 * Assumes interrupts are blocked. 1757 */ 1758 void 1759 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1760 u_int64_t blkno, u_int16_t count, u_int16_t features) 1761 { 1762 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1763 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1764 1765 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1766 "count=%d\n", device_xname(chp->ch_atac->atac_dev), 1767 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1768 DEBUG_FUNCS); 1769 1770 if (wdc->select) 1771 wdc->select(chp,drive); 1772 1773 /* Select drive, head, and addressing mode. */ 1774 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1775 (drive << 4) | WDSD_LBA); 1776 1777 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1778 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1779 0, features); 1780 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1781 0, count); 1782 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1783 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1784 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1785 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1786 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1787 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1788 } else { 1789 /* previous */ 1790 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1791 0, features >> 8); 1792 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1793 0, count >> 8); 1794 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1795 0, blkno >> 24); 1796 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1797 0, blkno >> 32); 1798 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1799 0, blkno >> 40); 1800 1801 /* current */ 1802 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1803 0, features); 1804 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1805 0, count); 1806 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1807 0, blkno); 1808 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1809 0, blkno >> 8); 1810 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1811 0, blkno >> 16); 1812 } 1813 1814 /* Send command. */ 1815 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1816 return; 1817 } 1818 1819 /* 1820 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1821 * tested by the caller. 1822 */ 1823 void 1824 wdccommandshort(struct ata_channel *chp, int drive, int command) 1825 { 1826 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1827 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1828 1829 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1830 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1831 command), DEBUG_FUNCS); 1832 1833 if (wdc->select) 1834 wdc->select(chp,drive); 1835 1836 /* Select drive. */ 1837 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1838 WDSD_IBM | (drive << 4)); 1839 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1841 } 1842 1843 static void 1844 __wdcerror(struct ata_channel *chp, const char *msg) 1845 { 1846 struct atac_softc *atac = chp->ch_atac; 1847 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1848 1849 if (xfer == NULL) 1850 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1851 chp->ch_channel, msg); 1852 else 1853 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1854 chp->ch_channel, xfer->c_drive, msg); 1855 } 1856 1857 /* 1858 * the bit bucket 1859 */ 1860 void 1861 wdcbit_bucket(struct ata_channel *chp, int size) 1862 { 1863 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1864 1865 for (; size >= 2; size -= 2) 1866 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1867 if (size) 1868 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1869 } 1870 1871 static void 1872 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1873 { 1874 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1875 1876 #ifndef __NO_STRICT_ALIGNMENT 1877 if ((uintptr_t)bf & 1) 1878 goto unaligned; 1879 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1880 goto unaligned; 1881 #endif 1882 1883 if (flags & ATA_DRIVE_NOSTREAM) { 1884 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1885 bus_space_read_multi_4(wdr->data32iot, 1886 wdr->data32ioh, 0, bf, len >> 2); 1887 bf = (char *)bf + (len & ~3); 1888 len &= 3; 1889 } 1890 if (len > 1) { 1891 bus_space_read_multi_2(wdr->cmd_iot, 1892 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1893 bf = (char *)bf + (len & ~1); 1894 len &= 1; 1895 } 1896 } else { 1897 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1898 bus_space_read_multi_stream_4(wdr->data32iot, 1899 wdr->data32ioh, 0, bf, len >> 2); 1900 bf = (char *)bf + (len & ~3); 1901 len &= 3; 1902 } 1903 if (len > 1) { 1904 bus_space_read_multi_stream_2(wdr->cmd_iot, 1905 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1906 bf = (char *)bf + (len & ~1); 1907 len &= 1; 1908 } 1909 } 1910 if (len) 1911 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1912 wdr->cmd_iohs[wd_data], 0); 1913 return; 1914 1915 #ifndef __NO_STRICT_ALIGNMENT 1916 unaligned: 1917 if (flags & ATA_DRIVE_NOSTREAM) { 1918 if (flags & ATA_DRIVE_CAP32) { 1919 while (len > 3) { 1920 uint32_t val; 1921 1922 val = bus_space_read_4(wdr->data32iot, 1923 wdr->data32ioh, 0); 1924 memcpy(bf, &val, 4); 1925 bf = (char *)bf + 4; 1926 len -= 4; 1927 } 1928 } 1929 while (len > 1) { 1930 uint16_t val; 1931 1932 val = bus_space_read_2(wdr->cmd_iot, 1933 wdr->cmd_iohs[wd_data], 0); 1934 memcpy(bf, &val, 2); 1935 bf = (char *)bf + 2; 1936 len -= 2; 1937 } 1938 } else { 1939 if (flags & ATA_DRIVE_CAP32) { 1940 while (len > 3) { 1941 uint32_t val; 1942 1943 val = bus_space_read_stream_4(wdr->data32iot, 1944 wdr->data32ioh, 0); 1945 memcpy(bf, &val, 4); 1946 bf = (char *)bf + 4; 1947 len -= 4; 1948 } 1949 } 1950 while (len > 1) { 1951 uint16_t val; 1952 1953 val = bus_space_read_stream_2(wdr->cmd_iot, 1954 wdr->cmd_iohs[wd_data], 0); 1955 memcpy(bf, &val, 2); 1956 bf = (char *)bf + 2; 1957 len -= 2; 1958 } 1959 } 1960 #endif 1961 } 1962 1963 static void 1964 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1965 { 1966 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1967 1968 #ifndef __NO_STRICT_ALIGNMENT 1969 if ((uintptr_t)bf & 1) 1970 goto unaligned; 1971 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1972 goto unaligned; 1973 #endif 1974 1975 if (flags & ATA_DRIVE_NOSTREAM) { 1976 if (flags & ATA_DRIVE_CAP32) { 1977 bus_space_write_multi_4(wdr->data32iot, 1978 wdr->data32ioh, 0, bf, len >> 2); 1979 bf = (char *)bf + (len & ~3); 1980 len &= 3; 1981 } 1982 if (len) { 1983 bus_space_write_multi_2(wdr->cmd_iot, 1984 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1985 } 1986 } else { 1987 if (flags & ATA_DRIVE_CAP32) { 1988 bus_space_write_multi_stream_4(wdr->data32iot, 1989 wdr->data32ioh, 0, bf, len >> 2); 1990 bf = (char *)bf + (len & ~3); 1991 len &= 3; 1992 } 1993 if (len) { 1994 bus_space_write_multi_stream_2(wdr->cmd_iot, 1995 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1996 } 1997 } 1998 return; 1999 2000 #ifndef __NO_STRICT_ALIGNMENT 2001 unaligned: 2002 if (flags & ATA_DRIVE_NOSTREAM) { 2003 if (flags & ATA_DRIVE_CAP32) { 2004 while (len > 3) { 2005 uint32_t val; 2006 2007 memcpy(&val, bf, 4); 2008 bus_space_write_4(wdr->data32iot, 2009 wdr->data32ioh, 0, val); 2010 bf = (char *)bf + 4; 2011 len -= 4; 2012 } 2013 } 2014 while (len > 1) { 2015 uint16_t val; 2016 2017 memcpy(&val, bf, 2); 2018 bus_space_write_2(wdr->cmd_iot, 2019 wdr->cmd_iohs[wd_data], 0, val); 2020 bf = (char *)bf + 2; 2021 len -= 2; 2022 } 2023 } else { 2024 if (flags & ATA_DRIVE_CAP32) { 2025 while (len > 3) { 2026 uint32_t val; 2027 2028 memcpy(&val, bf, 4); 2029 bus_space_write_stream_4(wdr->data32iot, 2030 wdr->data32ioh, 0, val); 2031 bf = (char *)bf + 4; 2032 len -= 4; 2033 } 2034 } 2035 while (len > 1) { 2036 uint16_t val; 2037 2038 memcpy(&val, bf, 2); 2039 bus_space_write_stream_2(wdr->cmd_iot, 2040 wdr->cmd_iohs[wd_data], 0, val); 2041 bf = (char *)bf + 2; 2042 len -= 2; 2043 } 2044 } 2045 #endif 2046 } 2047
Indexes created Tue Sep 23 20:09:58 GMT 2025