wdc.c revision 1.277
1 /* $NetBSD: wdc.c,v 1.277 2013/02/03 20:13:28 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.277 2013/02/03 20:13:28 jakllsch Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then tsleep for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 SCSIPI_BUSTYPE_ATA, 130 NULL, /* wdc_ata_bio */ 131 NULL, /* wdc_reset_drive */ 132 wdc_reset_channel, 133 wdc_exec_command, 134 NULL, /* ata_get_params */ 135 NULL, /* wdc_ata_addref */ 136 NULL, /* wdc_ata_delref */ 137 NULL /* ata_kill_pending */ 138 }; 139 #endif 140 141 /* Flags to wdcreset(). */ 142 #define RESET_POLL 1 143 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 144 145 static int wdcprobe1(struct ata_channel *, int); 146 static int wdcreset(struct ata_channel *, int); 147 static void __wdcerror(struct ata_channel *, const char *); 148 static int __wdcwait_reset(struct ata_channel *, int, int); 149 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 150 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_kill_xfer(struct ata_channel *, 152 struct ata_xfer *, int); 153 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 154 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 155 static int __wdcwait(struct ata_channel *, int, int, int); 156 157 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 158 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 159 #define DEBUG_INTR 0x01 160 #define DEBUG_XFERS 0x02 161 #define DEBUG_STATUS 0x04 162 #define DEBUG_FUNCS 0x08 163 #define DEBUG_PROBE 0x10 164 #define DEBUG_DETACH 0x20 165 #define DEBUG_DELAY 0x40 166 #ifdef ATADEBUG 167 extern int atadebug_mask; /* init'ed in ata.c */ 168 int wdc_nxfer = 0; 169 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 170 #else 171 #define ATADEBUG_PRINT(args, level) 172 #endif 173 174 /* 175 * Initialize the "shadow register" handles for a standard wdc controller. 176 */ 177 void 178 wdc_init_shadow_regs(struct ata_channel *chp) 179 { 180 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 181 182 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 183 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 184 } 185 186 /* 187 * Allocate a wdc_regs array, based on the number of channels. 188 */ 189 void 190 wdc_allocate_regs(struct wdc_softc *wdc) 191 { 192 193 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 194 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 195 } 196 197 #if NSATA > 0 198 /* 199 * probe drives on SATA controllers with standard SATA registers: 200 * bring the PHYs online, read the drive signature and set drive flags 201 * appropriately. 202 */ 203 void 204 wdc_sataprobe(struct ata_channel *chp) 205 { 206 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 207 uint8_t st = 0, sc, sn, cl, ch; 208 int i, s; 209 210 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 211 212 /* reset the PHY and bring online */ 213 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 214 wdr->sata_status)) { 215 case SStatus_DET_DEV: 216 /* wait 5s for BSY to clear */ 217 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 218 bus_space_write_1(wdr->cmd_iot, 219 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 220 delay(10); /* 400ns delay */ 221 st = bus_space_read_1(wdr->cmd_iot, 222 wdr->cmd_iohs[wd_status], 0); 223 if ((st & WDCS_BSY) == 0) 224 break; 225 tsleep(&chp, PRIBIO, "sataprb", 1); 226 } 227 if (i == WDC_PROBE_WAIT * hz) 228 aprint_error_dev(chp->ch_atac->atac_dev, 229 "BSY never cleared, status 0x%02x\n", st); 230 sc = bus_space_read_1(wdr->cmd_iot, 231 wdr->cmd_iohs[wd_seccnt], 0); 232 sn = bus_space_read_1(wdr->cmd_iot, 233 wdr->cmd_iohs[wd_sector], 0); 234 cl = bus_space_read_1(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_cyl_lo], 0); 236 ch = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_cyl_hi], 0); 238 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 239 "cl=0x%x ch=0x%x\n", 240 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 241 sc, sn, cl, ch), DEBUG_PROBE); 242 if (atabus_alloc_drives(chp, 1) != 0) 243 return; 244 /* 245 * sc and sn are supposed to be 0x1 for ATAPI, but in some 246 * cases we get wrong values here, so ignore it. 247 */ 248 s = splbio(); 249 if (cl == 0x14 && ch == 0xeb) 250 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 251 else 252 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 253 splx(s); 254 255 /* 256 * issue a reset in case only the interface part of the drive 257 * is up 258 */ 259 if (wdcreset(chp, RESET_SLEEP) != 0) 260 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 261 break; 262 263 default: 264 break; 265 } 266 } 267 #endif /* NSATA > 0 */ 268 269 270 /* Test to see controller with at last one attached drive is there. 271 * Returns a bit for each possible drive found (0x01 for drive 0, 272 * 0x02 for drive 1). 273 * Logic: 274 * - If a status register is at 0xff, assume there is no drive here 275 * (ISA has pull-up resistors). Similarly if the status register has 276 * the value we last wrote to the bus (for IDE interfaces without pullups). 277 * If no drive at all -> return. 278 * - reset the controller, wait for it to complete (may take up to 31s !). 279 * If timeout -> return. 280 * - test ATA/ATAPI signatures. If at last one drive found -> return. 281 * - try an ATA command on the master. 282 */ 283 284 void 285 wdc_drvprobe(struct ata_channel *chp) 286 { 287 struct ataparams params; /* XXX: large struct */ 288 struct atac_softc *atac = chp->ch_atac; 289 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 290 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 291 u_int8_t st0 = 0, st1 = 0; 292 int i, j, error, s; 293 294 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 295 return; 296 if (wdcprobe1(chp, 0) == 0) { 297 /* No drives, abort the attach here. */ 298 atabus_free_drives(chp); 299 return; 300 } 301 302 s = splbio(); 303 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 304 for (i = 0; i < mstohz(3000); i++) { 305 /* 306 * select drive 1 first, so that master is selected on 307 * exit from the loop 308 */ 309 if (chp->ch_ndrives > 1 && 310 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 311 if (wdc->select) 312 wdc->select(chp,1); 313 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 314 0, WDSD_IBM | 0x10); 315 delay(10); /* 400ns delay */ 316 st1 = bus_space_read_1(wdr->cmd_iot, 317 wdr->cmd_iohs[wd_status], 0); 318 } 319 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 320 if (wdc->select) 321 wdc->select(chp,0); 322 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 323 0, WDSD_IBM); 324 delay(10); /* 400ns delay */ 325 st0 = bus_space_read_1(wdr->cmd_iot, 326 wdr->cmd_iohs[wd_status], 0); 327 } 328 329 330 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 331 (st0 & WDCS_DRDY)) && 332 (chp->ch_ndrives < 2 || 333 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 334 (st1 & WDCS_DRDY))) 335 break; 336 #ifdef WDC_NO_IDS 337 /* cannot tsleep here (can't enable IPL_BIO interrups), 338 * delay instead 339 */ 340 delay(1000000 / hz); 341 #else 342 tsleep(¶ms, PRIBIO, "atadrdy", 1); 343 #endif 344 } 345 if ((st0 & WDCS_DRDY) == 0 && 346 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 347 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 348 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 349 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 350 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 351 splx(s); 352 353 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 354 device_xname(atac->atac_dev), 355 chp->ch_channel, st0, st1), DEBUG_PROBE); 356 357 /* Wait a bit, some devices are weird just after a reset. */ 358 delay(5000); 359 360 for (i = 0; i < chp->ch_ndrives; i++) { 361 #if NATA_DMA 362 /* 363 * Init error counter so that an error withing the first xfers 364 * will trigger a downgrade 365 */ 366 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 367 #endif 368 369 /* If controller can't do 16bit flag the drives as 32bit */ 370 if ((atac->atac_cap & 371 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 372 s = splbio(); 373 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 374 splx(s); 375 } 376 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 377 continue; 378 379 /* Shortcut in case we've been shutdown */ 380 if (chp->ch_flags & ATACH_SHUTDOWN) 381 return; 382 383 /* 384 * Issue an identify, to try to detect ghosts. 385 * Note that we can't use interrupts here, because if there 386 * is no devices, we will get a command aborted without 387 * interrupts. 388 */ 389 error = ata_get_params(&chp->ch_drive[i], 390 AT_WAIT | AT_POLL, ¶ms); 391 if (error != CMD_OK) { 392 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 393 394 /* Shortcut in case we've been shutdown */ 395 if (chp->ch_flags & ATACH_SHUTDOWN) 396 return; 397 398 error = ata_get_params(&chp->ch_drive[i], 399 AT_WAIT | AT_POLL, ¶ms); 400 } 401 if (error != CMD_OK) { 402 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 403 device_xname(atac->atac_dev), 404 chp->ch_channel, i, error), DEBUG_PROBE); 405 s = splbio(); 406 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 407 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 408 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 409 splx(s); 410 continue; 411 } 412 splx(s); 413 /* 414 * Pre-ATA drive ? 415 * Test registers writability (Error register not 416 * writable, but cyllo is), then try an ATA command. 417 */ 418 if (wdc->select) 419 wdc->select(chp,i); 420 bus_space_write_1(wdr->cmd_iot, 421 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 422 delay(10); /* 400ns delay */ 423 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 424 0, 0x58); 425 bus_space_write_1(wdr->cmd_iot, 426 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 427 if (bus_space_read_1(wdr->cmd_iot, 428 wdr->cmd_iohs[wd_error], 0) == 0x58 || 429 bus_space_read_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 431 ATADEBUG_PRINT(("%s:%d:%d: register " 432 "writability failed\n", 433 device_xname(atac->atac_dev), 434 chp->ch_channel, i), DEBUG_PROBE); 435 s = splbio(); 436 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 437 splx(s); 438 continue; 439 } 440 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 441 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 442 device_xname(atac->atac_dev), 443 chp->ch_channel, i), DEBUG_PROBE); 444 s = splbio(); 445 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 446 splx(s); 447 continue; 448 } 449 bus_space_write_1(wdr->cmd_iot, 450 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 451 delay(10); /* 400ns delay */ 452 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 453 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 454 device_xname(atac->atac_dev), 455 chp->ch_channel, i), DEBUG_PROBE); 456 s = splbio(); 457 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 458 splx(s); 459 } else { 460 s = splbio(); 461 for (j = 0; j < chp->ch_ndrives; j++) { 462 if (chp->ch_drive[i].drive_type != 463 ATA_DRIVET_NONE) { 464 chp->ch_drive[j].drive_type = 465 ATA_DRIVET_OLD; 466 } 467 } 468 splx(s); 469 } 470 } 471 } 472 } 473 474 int 475 wdcprobe(struct ata_channel *chp) 476 { 477 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 478 /* default reset method */ 479 if (wdc->reset == NULL) 480 wdc->reset = wdc_do_reset; 481 482 return (wdcprobe1(chp, 1)); 483 } 484 485 static int 486 wdcprobe1(struct ata_channel *chp, int poll) 487 { 488 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 489 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 490 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 491 u_int8_t ret_value = 0x03; 492 u_int8_t drive; 493 int s; 494 /* XXX if poll, wdc_probe_count is 0. */ 495 int wdc_probe_count = 496 poll ? (WDC_PROBE_WAIT / WDCDELAY) 497 : (WDC_PROBE_WAIT * hz); 498 499 /* 500 * Sanity check to see if the wdc channel responds at all. 501 */ 502 503 s = splbio(); 504 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 505 while (wdc_probe_count-- > 0) { 506 if (wdc->select) 507 wdc->select(chp,0); 508 509 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 510 0, WDSD_IBM); 511 delay(10); /* 400ns delay */ 512 st0 = bus_space_read_1(wdr->cmd_iot, 513 wdr->cmd_iohs[wd_status], 0); 514 515 if (wdc->select) 516 wdc->select(chp,1); 517 518 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 519 0, WDSD_IBM | 0x10); 520 delay(10); /* 400ns delay */ 521 st1 = bus_space_read_1(wdr->cmd_iot, 522 wdr->cmd_iohs[wd_status], 0); 523 if ((st0 & WDCS_BSY) == 0) 524 break; 525 } 526 527 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 528 device_xname(chp->ch_atac->atac_dev), 529 chp->ch_channel, st0, st1), DEBUG_PROBE); 530 531 if (st0 == 0xff || st0 == WDSD_IBM) 532 ret_value &= ~0x01; 533 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 534 ret_value &= ~0x02; 535 /* Register writability test, drive 0. */ 536 if (ret_value & 0x01) { 537 if (wdc->select) 538 wdc->select(chp,0); 539 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 540 0, WDSD_IBM); 541 bus_space_write_1(wdr->cmd_iot, 542 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 543 cl = bus_space_read_1(wdr->cmd_iot, 544 wdr->cmd_iohs[wd_cyl_lo], 0); 545 if (cl != 0x02) { 546 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 547 "got 0x%x != 0x02\n", 548 device_xname(chp->ch_atac->atac_dev), 549 chp->ch_channel, cl), 550 DEBUG_PROBE); 551 ret_value &= ~0x01; 552 } 553 bus_space_write_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 555 cl = bus_space_read_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_cyl_lo], 0); 557 if (cl != 0x01) { 558 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 559 "got 0x%x != 0x01\n", 560 device_xname(chp->ch_atac->atac_dev), 561 chp->ch_channel, cl), 562 DEBUG_PROBE); 563 ret_value &= ~0x01; 564 } 565 bus_space_write_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_sector], 0, 0x01); 567 cl = bus_space_read_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_sector], 0); 569 if (cl != 0x01) { 570 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 571 "got 0x%x != 0x01\n", 572 device_xname(chp->ch_atac->atac_dev), 573 chp->ch_channel, cl), 574 DEBUG_PROBE); 575 ret_value &= ~0x01; 576 } 577 bus_space_write_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_sector], 0, 0x02); 579 cl = bus_space_read_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_sector], 0); 581 if (cl != 0x02) { 582 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 583 "got 0x%x != 0x02\n", 584 device_xname(chp->ch_atac->atac_dev), 585 chp->ch_channel, cl), 586 DEBUG_PROBE); 587 ret_value &= ~0x01; 588 } 589 cl = bus_space_read_1(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_cyl_lo], 0); 591 if (cl != 0x01) { 592 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 593 "got 0x%x != 0x01\n", 594 device_xname(chp->ch_atac->atac_dev), 595 chp->ch_channel, cl), 596 DEBUG_PROBE); 597 ret_value &= ~0x01; 598 } 599 } 600 /* Register writability test, drive 1. */ 601 if (ret_value & 0x02) { 602 if (wdc->select) 603 wdc->select(chp,1); 604 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 605 0, WDSD_IBM | 0x10); 606 bus_space_write_1(wdr->cmd_iot, 607 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 608 cl = bus_space_read_1(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_lo], 0); 610 if (cl != 0x02) { 611 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 612 "got 0x%x != 0x02\n", 613 device_xname(chp->ch_atac->atac_dev), 614 chp->ch_channel, cl), 615 DEBUG_PROBE); 616 ret_value &= ~0x02; 617 } 618 bus_space_write_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 620 cl = bus_space_read_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_lo], 0); 622 if (cl != 0x01) { 623 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 624 "got 0x%x != 0x01\n", 625 device_xname(chp->ch_atac->atac_dev), 626 chp->ch_channel, cl), 627 DEBUG_PROBE); 628 ret_value &= ~0x02; 629 } 630 bus_space_write_1(wdr->cmd_iot, 631 wdr->cmd_iohs[wd_sector], 0, 0x01); 632 cl = bus_space_read_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_sector], 0); 634 if (cl != 0x01) { 635 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 636 "got 0x%x != 0x01\n", 637 device_xname(chp->ch_atac->atac_dev), 638 chp->ch_channel, cl), 639 DEBUG_PROBE); 640 ret_value &= ~0x02; 641 } 642 bus_space_write_1(wdr->cmd_iot, 643 wdr->cmd_iohs[wd_sector], 0, 0x02); 644 cl = bus_space_read_1(wdr->cmd_iot, 645 wdr->cmd_iohs[wd_sector], 0); 646 if (cl != 0x02) { 647 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 648 "got 0x%x != 0x02\n", 649 device_xname(chp->ch_atac->atac_dev), 650 chp->ch_channel, cl), 651 DEBUG_PROBE); 652 ret_value &= ~0x02; 653 } 654 cl = bus_space_read_1(wdr->cmd_iot, 655 wdr->cmd_iohs[wd_cyl_lo], 0); 656 if (cl != 0x01) { 657 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 658 "got 0x%x != 0x01\n", 659 device_xname(chp->ch_atac->atac_dev), 660 chp->ch_channel, cl), 661 DEBUG_PROBE); 662 ret_value &= ~0x02; 663 } 664 } 665 666 if (ret_value == 0) { 667 splx(s); 668 return 0; 669 } 670 } 671 672 673 #if 0 /* XXX this break some ATA or ATAPI devices */ 674 /* 675 * reset bus. Also send an ATAPI_RESET to devices, in case there are 676 * ATAPI device out there which don't react to the bus reset 677 */ 678 if (ret_value & 0x01) { 679 if (wdc->select) 680 wdc->select(chp,0); 681 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 682 0, WDSD_IBM); 683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 684 ATAPI_SOFT_RESET); 685 } 686 if (ret_value & 0x02) { 687 if (wdc->select) 688 wdc->select(chp,0); 689 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 690 0, WDSD_IBM | 0x10); 691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 692 ATAPI_SOFT_RESET); 693 } 694 695 delay(5000); 696 #endif 697 698 wdc->reset(chp, RESET_POLL); 699 DELAY(2000); 700 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 701 702 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 703 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 704 WDCTL_4BIT); 705 706 #ifdef WDC_NO_IDS 707 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 708 #else 709 splx(s); 710 ret_value = __wdcwait_reset(chp, ret_value, poll); 711 s = splbio(); 712 #endif 713 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 714 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 715 ret_value), DEBUG_PROBE); 716 717 /* if reset failed, there's nothing here */ 718 if (ret_value == 0) { 719 splx(s); 720 return 0; 721 } 722 723 /* 724 * Test presence of drives. First test register signatures looking 725 * for ATAPI devices. If it's not an ATAPI and reset said there may 726 * be something here assume it's ATA or OLD. Ghost will be killed 727 * later in attach routine. 728 */ 729 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 730 if ((ret_value & (0x01 << drive)) == 0) 731 continue; 732 if (wdc->select) 733 wdc->select(chp,drive); 734 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 735 WDSD_IBM | (drive << 4)); 736 delay(10); /* 400ns delay */ 737 /* Save registers contents */ 738 sc = bus_space_read_1(wdr->cmd_iot, 739 wdr->cmd_iohs[wd_seccnt], 0); 740 sn = bus_space_read_1(wdr->cmd_iot, 741 wdr->cmd_iohs[wd_sector], 0); 742 cl = bus_space_read_1(wdr->cmd_iot, 743 wdr->cmd_iohs[wd_cyl_lo], 0); 744 ch = bus_space_read_1(wdr->cmd_iot, 745 wdr->cmd_iohs[wd_cyl_hi], 0); 746 747 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 748 "cl=0x%x ch=0x%x\n", 749 device_xname(chp->ch_atac->atac_dev), 750 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 751 /* 752 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 753 * we get wrong values here, so ignore it. 754 */ 755 if (chp->ch_drive != NULL) { 756 if (cl == 0x14 && ch == 0xeb) { 757 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 758 } else { 759 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 760 } 761 } 762 } 763 /* 764 * Select an existing drive before lowering spl, some WDC_NO_IDS 765 * devices incorrectly assert IRQ on nonexistent slave 766 */ 767 if (ret_value & 0x01) { 768 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 769 WDSD_IBM); 770 (void)bus_space_read_1(wdr->cmd_iot, 771 wdr->cmd_iohs[wd_status], 0); 772 } 773 splx(s); 774 return (ret_value); 775 } 776 777 void 778 wdcattach(struct ata_channel *chp) 779 { 780 struct atac_softc *atac = chp->ch_atac; 781 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 782 783 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 784 785 /* default data transfer methods */ 786 if (wdc->datain_pio == NULL) 787 wdc->datain_pio = wdc_datain_pio; 788 if (wdc->dataout_pio == NULL) 789 wdc->dataout_pio = wdc_dataout_pio; 790 /* default reset method */ 791 if (wdc->reset == NULL) 792 wdc->reset = wdc_do_reset; 793 794 /* initialise global data */ 795 if (atac->atac_bustype_ata == NULL) 796 atac->atac_bustype_ata = &wdc_ata_bustype; 797 if (atac->atac_probe == NULL) 798 atac->atac_probe = wdc_drvprobe; 799 #if NATAPIBUS > 0 800 if (atac->atac_atapibus_attach == NULL) 801 atac->atac_atapibus_attach = wdc_atapibus_attach; 802 #endif 803 804 ata_channel_attach(chp); 805 } 806 807 void 808 wdc_childdetached(device_t self, device_t child) 809 { 810 struct atac_softc *atac = device_private(self); 811 struct ata_channel *chp; 812 int i; 813 814 for (i = 0; i < atac->atac_nchannels; i++) { 815 chp = atac->atac_channels[i]; 816 if (child == chp->atabus) { 817 chp->atabus = NULL; 818 return; 819 } 820 } 821 } 822 823 int 824 wdcdetach(device_t self, int flags) 825 { 826 struct atac_softc *atac = device_private(self); 827 struct ata_channel *chp; 828 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 829 int i, error = 0; 830 831 for (i = 0; i < atac->atac_nchannels; i++) { 832 chp = atac->atac_channels[i]; 833 if (chp->atabus == NULL) 834 continue; 835 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 836 device_xname(atac->atac_dev), device_xname(chp->atabus)), 837 DEBUG_DETACH); 838 if ((error = config_detach(chp->atabus, flags)) != 0) 839 return error; 840 } 841 if (adapt->adapt_refcnt != 0) 842 return EBUSY; 843 return 0; 844 } 845 846 /* restart an interrupted I/O */ 847 void 848 wdcrestart(void *v) 849 { 850 struct ata_channel *chp = v; 851 int s; 852 853 s = splbio(); 854 atastart(chp); 855 splx(s); 856 } 857 858 859 /* 860 * Interrupt routine for the controller. Acknowledge the interrupt, check for 861 * errors on the current operation, mark it done if necessary, and start the 862 * next request. Also check for a partially done transfer, and continue with 863 * the next chunk if so. 864 */ 865 int 866 wdcintr(void *arg) 867 { 868 struct ata_channel *chp = arg; 869 struct atac_softc *atac = chp->ch_atac; 870 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 871 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 872 struct ata_xfer *xfer; 873 int ret; 874 875 if (!device_is_active(atac->atac_dev)) { 876 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 877 DEBUG_INTR); 878 return (0); 879 } 880 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 881 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 882 /* try to clear the pending interrupt anyway */ 883 (void)bus_space_read_1(wdr->cmd_iot, 884 wdr->cmd_iohs[wd_status], 0); 885 return (0); 886 } 887 888 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 889 xfer = chp->ch_queue->active_xfer; 890 #ifdef DIAGNOSTIC 891 if (xfer == NULL) 892 panic("wdcintr: no xfer"); 893 if (xfer->c_chp != chp) { 894 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 895 chp->ch_channel); 896 panic("wdcintr: wrong channel"); 897 } 898 #endif 899 #if NATA_DMA || NATA_PIOBM 900 if (chp->ch_flags & ATACH_DMA_WAIT) { 901 wdc->dma_status = 902 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 903 xfer->c_drive, WDC_DMAEND_END); 904 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 905 /* IRQ not for us, not detected by DMA engine */ 906 return 0; 907 } 908 chp->ch_flags &= ~ATACH_DMA_WAIT; 909 } 910 #endif 911 chp->ch_flags &= ~ATACH_IRQ_WAIT; 912 KASSERT(xfer->c_intr != NULL); 913 ret = xfer->c_intr(chp, xfer, 1); 914 if (ret == 0) /* irq was not for us, still waiting for irq */ 915 chp->ch_flags |= ATACH_IRQ_WAIT; 916 return (ret); 917 } 918 919 /* Put all disk in RESET state */ 920 void 921 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 922 { 923 struct ata_channel *chp = drvp->chnl_softc; 924 925 KASSERT(sigp == NULL); 926 927 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 928 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 929 drvp->drive), DEBUG_FUNCS); 930 931 ata_reset_channel(chp, flags); 932 } 933 934 void 935 wdc_reset_channel(struct ata_channel *chp, int flags) 936 { 937 TAILQ_HEAD(, ata_xfer) reset_xfer; 938 struct ata_xfer *xfer, *next_xfer; 939 #if NATA_DMA || NATA_PIOBM 940 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 941 #endif 942 TAILQ_INIT(&reset_xfer); 943 944 chp->ch_flags &= ~ATACH_IRQ_WAIT; 945 946 /* 947 * if the current command if on an ATAPI device, issue a 948 * ATAPI_SOFT_RESET 949 */ 950 xfer = chp->ch_queue->active_xfer; 951 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 952 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 953 if (flags & AT_WAIT) 954 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 955 else 956 delay(1000); 957 } 958 959 /* reset the channel */ 960 if (flags & AT_WAIT) 961 (void) wdcreset(chp, RESET_SLEEP); 962 else 963 (void) wdcreset(chp, RESET_POLL); 964 965 /* 966 * wait a bit after reset; in case the DMA engines needs some time 967 * to recover. 968 */ 969 if (flags & AT_WAIT) 970 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 971 else 972 delay(1000); 973 /* 974 * look for pending xfers. If we have a shared queue, we'll also reset 975 * the other channel if the current xfer is running on it. 976 * Then we'll dequeue only the xfers for this channel. 977 */ 978 if ((flags & AT_RST_NOCMD) == 0) { 979 /* 980 * move all xfers queued for this channel to the reset queue, 981 * and then process the current xfer and then the reset queue. 982 * We have to use a temporary queue because c_kill_xfer() 983 * may requeue commands. 984 */ 985 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 986 xfer != NULL; xfer = next_xfer) { 987 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 988 if (xfer->c_chp != chp) 989 continue; 990 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 991 xfer, c_xferchain); 992 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 993 } 994 xfer = chp->ch_queue->active_xfer; 995 if (xfer) { 996 if (xfer->c_chp != chp) 997 ata_reset_channel(xfer->c_chp, flags); 998 else { 999 callout_stop(&chp->ch_callout); 1000 #if NATA_DMA || NATA_PIOBM 1001 /* 1002 * If we're waiting for DMA, stop the 1003 * DMA engine 1004 */ 1005 if (chp->ch_flags & ATACH_DMA_WAIT) { 1006 (*wdc->dma_finish)( 1007 wdc->dma_arg, 1008 chp->ch_channel, 1009 xfer->c_drive, 1010 WDC_DMAEND_ABRT_QUIET); 1011 chp->ch_flags &= ~ATACH_DMA_WAIT; 1012 } 1013 #endif 1014 chp->ch_queue->active_xfer = NULL; 1015 if ((flags & AT_RST_EMERG) == 0) 1016 xfer->c_kill_xfer( 1017 chp, xfer, KILL_RESET); 1018 } 1019 } 1020 1021 for (xfer = TAILQ_FIRST(&reset_xfer); 1022 xfer != NULL; xfer = next_xfer) { 1023 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1024 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1025 if ((flags & AT_RST_EMERG) == 0) 1026 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1027 } 1028 } 1029 } 1030 1031 static int 1032 wdcreset(struct ata_channel *chp, int poll) 1033 { 1034 struct atac_softc *atac = chp->ch_atac; 1035 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1036 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1037 int drv_mask1, drv_mask2; 1038 1039 #ifdef WDC_NO_IDS 1040 poll = RESET_POLL; 1041 #endif 1042 wdc->reset(chp, poll); 1043 1044 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) ? 0x01:0x00; 1045 if (chp->ch_ndrives > 1) 1046 drv_mask1 |= 1047 (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) ? 0x02:0x00; 1048 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1049 (poll == RESET_SLEEP) ? 0 : 1); 1050 if (drv_mask2 != drv_mask1) { 1051 aprint_error("%s channel %d: reset failed for", 1052 device_xname(atac->atac_dev), chp->ch_channel); 1053 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1054 aprint_normal(" drive 0"); 1055 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1056 aprint_normal(" drive 1"); 1057 aprint_normal("\n"); 1058 } 1059 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1060 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1061 WDCTL_4BIT); 1062 1063 return (drv_mask1 != drv_mask2) ? 1 : 0; 1064 } 1065 1066 void 1067 wdc_do_reset(struct ata_channel *chp, int poll) 1068 { 1069 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1070 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1071 int s = 0; 1072 1073 if (poll != RESET_SLEEP) 1074 s = splbio(); 1075 if (wdc->select) 1076 wdc->select(chp,0); 1077 /* master */ 1078 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1079 delay(10); /* 400ns delay */ 1080 /* assert SRST, wait for reset to complete */ 1081 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1082 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1083 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1084 delay(2000); 1085 } 1086 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1087 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1088 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1089 WDCTL_4BIT | WDCTL_IDS); 1090 delay(10); /* 400ns delay */ 1091 if (poll != RESET_SLEEP) { 1092 /* ACK interrupt in case there is one pending left */ 1093 if (wdc->irqack) 1094 wdc->irqack(chp); 1095 splx(s); 1096 } 1097 } 1098 1099 static int 1100 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1101 { 1102 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1103 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1104 int timeout, nloop; 1105 u_int8_t st0 = 0, st1 = 0; 1106 #ifdef ATADEBUG 1107 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1108 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1109 #endif 1110 if (poll) 1111 nloop = WDCNDELAY_RST; 1112 else 1113 nloop = WDC_RESET_WAIT * hz / 1000; 1114 /* wait for BSY to deassert */ 1115 for (timeout = 0; timeout < nloop; timeout++) { 1116 if ((drv_mask & 0x01) != 0) { 1117 if (wdc->select) 1118 wdc->select(chp,0); 1119 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1120 0, WDSD_IBM); /* master */ 1121 delay(10); 1122 st0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_status], 0); 1124 #ifdef ATADEBUG 1125 sc0 = bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_seccnt], 0); 1127 sn0 = bus_space_read_1(wdr->cmd_iot, 1128 wdr->cmd_iohs[wd_sector], 0); 1129 cl0 = bus_space_read_1(wdr->cmd_iot, 1130 wdr->cmd_iohs[wd_cyl_lo], 0); 1131 ch0 = bus_space_read_1(wdr->cmd_iot, 1132 wdr->cmd_iohs[wd_cyl_hi], 0); 1133 #endif 1134 } 1135 if ((drv_mask & 0x02) != 0) { 1136 if (wdc->select) 1137 wdc->select(chp,1); 1138 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1139 0, WDSD_IBM | 0x10); /* slave */ 1140 delay(10); 1141 st1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_status], 0); 1143 #ifdef ATADEBUG 1144 sc1 = bus_space_read_1(wdr->cmd_iot, 1145 wdr->cmd_iohs[wd_seccnt], 0); 1146 sn1 = bus_space_read_1(wdr->cmd_iot, 1147 wdr->cmd_iohs[wd_sector], 0); 1148 cl1 = bus_space_read_1(wdr->cmd_iot, 1149 wdr->cmd_iohs[wd_cyl_lo], 0); 1150 ch1 = bus_space_read_1(wdr->cmd_iot, 1151 wdr->cmd_iohs[wd_cyl_hi], 0); 1152 #endif 1153 } 1154 1155 if ((drv_mask & 0x01) == 0) { 1156 /* no master */ 1157 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1158 /* No master, slave is ready, it's done */ 1159 goto end; 1160 } 1161 if ((drv_mask & 0x02) == 0) { 1162 /* No master, no slave: it's done */ 1163 goto end; 1164 } 1165 } else if ((drv_mask & 0x02) == 0) { 1166 /* no slave */ 1167 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1168 /* No slave, master is ready, it's done */ 1169 goto end; 1170 } 1171 } else { 1172 /* Wait for both master and slave to be ready */ 1173 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1174 goto end; 1175 } 1176 } 1177 if (poll) 1178 delay(WDCDELAY); 1179 else 1180 tsleep(&nloop, PRIBIO, "atarst", 1); 1181 } 1182 /* Reset timed out. Maybe it's because drv_mask was not right */ 1183 if (st0 & WDCS_BSY) 1184 drv_mask &= ~0x01; 1185 if (st1 & WDCS_BSY) 1186 drv_mask &= ~0x02; 1187 end: 1188 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1189 "cl=0x%x ch=0x%x\n", 1190 device_xname(chp->ch_atac->atac_dev), 1191 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1192 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1193 "cl=0x%x ch=0x%x\n", 1194 device_xname(chp->ch_atac->atac_dev), 1195 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1196 1197 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1198 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1199 st0, st1), DEBUG_PROBE); 1200 1201 return drv_mask; 1202 } 1203 1204 /* 1205 * Wait for a drive to be !BSY, and have mask in its status register. 1206 * return -1 for a timeout after "timeout" ms. 1207 */ 1208 static int 1209 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1210 { 1211 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1212 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1213 u_char status; 1214 int xtime = 0; 1215 1216 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1217 device_xname(chp->ch_atac->atac_dev), 1218 chp->ch_channel), DEBUG_STATUS); 1219 chp->ch_error = 0; 1220 1221 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1222 1223 for (;;) { 1224 chp->ch_status = status = 1225 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1226 if ((status & (WDCS_BSY | mask)) == bits) 1227 break; 1228 if (++xtime > timeout) { 1229 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1230 "status %x error %x (mask 0x%x bits 0x%x)\n", 1231 xtime, status, 1232 bus_space_read_1(wdr->cmd_iot, 1233 wdr->cmd_iohs[wd_error], 0), mask, bits), 1234 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1235 return(WDCWAIT_TOUT); 1236 } 1237 delay(WDCDELAY); 1238 } 1239 #ifdef ATADEBUG 1240 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1241 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1242 #endif 1243 if (status & WDCS_ERR) 1244 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1245 wdr->cmd_iohs[wd_error], 0); 1246 #ifdef WDCNDELAY_DEBUG 1247 /* After autoconfig, there should be no long delays. */ 1248 if (!cold && xtime > WDCNDELAY_DEBUG) { 1249 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1250 if (xfer == NULL) 1251 printf("%s channel %d: warning: busy-wait took %dus\n", 1252 device_xname(chp->ch_atac->atac_dev), 1253 chp->ch_channel, WDCDELAY * xtime); 1254 else 1255 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1256 device_xname(chp->ch_atac->atac_dev), 1257 chp->ch_channel, xfer->c_drive, 1258 WDCDELAY * xtime); 1259 } 1260 #endif 1261 return(WDCWAIT_OK); 1262 } 1263 1264 /* 1265 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1266 * thread if possible 1267 */ 1268 int 1269 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1270 { 1271 int error, i, timeout_hz = mstohz(timeout); 1272 1273 if (timeout_hz == 0 || 1274 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1275 error = __wdcwait(chp, mask, bits, timeout); 1276 else { 1277 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1278 if (error != 0) { 1279 if ((chp->ch_flags & ATACH_TH_RUN) || 1280 (flags & AT_WAIT)) { 1281 /* 1282 * we're running in the channel thread 1283 * or some userland thread context 1284 */ 1285 for (i = 0; i < timeout_hz; i++) { 1286 if (__wdcwait(chp, mask, bits, 1287 WDCDELAY_POLL) == 0) { 1288 error = 0; 1289 break; 1290 } 1291 tsleep(&chp, PRIBIO, "atapoll", 1); 1292 } 1293 } else { 1294 /* 1295 * we're probably in interrupt context, 1296 * ask the thread to come back here 1297 */ 1298 #ifdef DIAGNOSTIC 1299 if (chp->ch_queue->queue_freeze > 0) 1300 panic("wdcwait: queue_freeze"); 1301 #endif 1302 chp->ch_queue->queue_freeze++; 1303 wakeup(&chp->ch_thread); 1304 return(WDCWAIT_THR); 1305 } 1306 } 1307 } 1308 return (error); 1309 } 1310 1311 1312 #if NATA_DMA 1313 /* 1314 * Busy-wait for DMA to complete 1315 */ 1316 int 1317 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1318 { 1319 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1320 int xtime; 1321 1322 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1323 wdc->dma_status = 1324 (*wdc->dma_finish)(wdc->dma_arg, 1325 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1326 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1327 return 0; 1328 delay(WDCDELAY); 1329 } 1330 /* timeout, force a DMA halt */ 1331 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1332 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1333 return 1; 1334 } 1335 #endif 1336 1337 void 1338 wdctimeout(void *arg) 1339 { 1340 struct ata_channel *chp = (struct ata_channel *)arg; 1341 #if NATA_DMA || NATA_PIOBM 1342 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1343 #endif 1344 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1345 int s; 1346 1347 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1348 1349 s = splbio(); 1350 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1351 __wdcerror(chp, "lost interrupt"); 1352 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1353 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1354 xfer->c_bcount, 1355 xfer->c_skip); 1356 #if NATA_DMA || NATA_PIOBM 1357 if (chp->ch_flags & ATACH_DMA_WAIT) { 1358 wdc->dma_status = 1359 (*wdc->dma_finish)(wdc->dma_arg, 1360 chp->ch_channel, xfer->c_drive, 1361 WDC_DMAEND_ABRT); 1362 chp->ch_flags &= ~ATACH_DMA_WAIT; 1363 } 1364 #endif 1365 /* 1366 * Call the interrupt routine. If we just missed an interrupt, 1367 * it will do what's needed. Else, it will take the needed 1368 * action (reset the device). 1369 * Before that we need to reinstall the timeout callback, 1370 * in case it will miss another irq while in this transfer 1371 * We arbitray chose it to be 1s 1372 */ 1373 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1374 xfer->c_flags |= C_TIMEOU; 1375 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1376 KASSERT(xfer->c_intr != NULL); 1377 xfer->c_intr(chp, xfer, 1); 1378 } else 1379 __wdcerror(chp, "missing untimeout"); 1380 splx(s); 1381 } 1382 1383 int 1384 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1385 { 1386 struct ata_channel *chp = drvp->chnl_softc; 1387 struct ata_xfer *xfer; 1388 int s, ret; 1389 1390 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1391 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1392 drvp->drive), DEBUG_FUNCS); 1393 1394 /* set up an xfer and queue. Wait for completion */ 1395 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1396 ATAXF_NOSLEEP); 1397 if (xfer == NULL) { 1398 return ATACMD_TRY_AGAIN; 1399 } 1400 1401 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1402 ata_c->flags |= AT_POLL; 1403 if (ata_c->flags & AT_POLL) 1404 xfer->c_flags |= C_POLL; 1405 if (ata_c->flags & AT_WAIT) 1406 xfer->c_flags |= C_WAIT; 1407 xfer->c_drive = drvp->drive; 1408 xfer->c_databuf = ata_c->data; 1409 xfer->c_bcount = ata_c->bcount; 1410 xfer->c_cmd = ata_c; 1411 xfer->c_start = __wdccommand_start; 1412 xfer->c_intr = __wdccommand_intr; 1413 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1414 1415 s = splbio(); 1416 ata_exec_xfer(chp, xfer); 1417 #ifdef DIAGNOSTIC 1418 if ((ata_c->flags & AT_POLL) != 0 && 1419 (ata_c->flags & AT_DONE) == 0) 1420 panic("wdc_exec_command: polled command not done"); 1421 #endif 1422 if (ata_c->flags & AT_DONE) { 1423 ret = ATACMD_COMPLETE; 1424 } else { 1425 if (ata_c->flags & AT_WAIT) { 1426 while ((ata_c->flags & AT_DONE) == 0) { 1427 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1428 } 1429 ret = ATACMD_COMPLETE; 1430 } else { 1431 ret = ATACMD_QUEUED; 1432 } 1433 } 1434 splx(s); 1435 return ret; 1436 } 1437 1438 static void 1439 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1440 { 1441 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1442 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1443 int drive = xfer->c_drive; 1444 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1445 struct ata_command *ata_c = xfer->c_cmd; 1446 1447 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1448 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1449 xfer->c_drive), 1450 DEBUG_FUNCS); 1451 1452 if (wdc->select) 1453 wdc->select(chp,drive); 1454 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1455 WDSD_IBM | (drive << 4)); 1456 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1457 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1458 case WDCWAIT_OK: 1459 break; 1460 case WDCWAIT_TOUT: 1461 ata_c->flags |= AT_TIMEOU; 1462 __wdccommand_done(chp, xfer); 1463 return; 1464 case WDCWAIT_THR: 1465 return; 1466 } 1467 if (ata_c->flags & AT_POLL) { 1468 /* polled command, disable interrupts */ 1469 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1470 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1471 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1472 } 1473 if ((ata_c->flags & AT_LBA48) != 0) { 1474 wdccommandext(chp, drive, ata_c->r_command, 1475 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1476 ata_c->r_device & ~0x10); 1477 } else { 1478 wdccommand(chp, drive, ata_c->r_command, 1479 (ata_c->r_lba >> 8) & 0xffff, 1480 WDSD_IBM | (drive << 4) | 1481 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1482 ((ata_c->r_lba >> 24) & 0x0f), 1483 ata_c->r_lba & 0xff, 1484 ata_c->r_count & 0xff, 1485 ata_c->r_features & 0xff); 1486 } 1487 1488 if ((ata_c->flags & AT_POLL) == 0) { 1489 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1490 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1491 wdctimeout, chp); 1492 return; 1493 } 1494 /* 1495 * Polled command. Wait for drive ready or drq. Done in intr(). 1496 * Wait for at last 400ns for status bit to be valid. 1497 */ 1498 delay(10); /* 400ns delay */ 1499 __wdccommand_intr(chp, xfer, 0); 1500 } 1501 1502 static int 1503 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1504 { 1505 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1506 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1507 struct ata_command *ata_c = xfer->c_cmd; 1508 int bcount = ata_c->bcount; 1509 char *data = ata_c->data; 1510 int wflags; 1511 int drive_flags; 1512 1513 if (ata_c->r_command == WDCC_IDENTIFY || 1514 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1515 /* 1516 * The IDENTIFY data has been designed as an array of 1517 * u_int16_t, so we can byteswap it on the fly. 1518 * Historically it's what we have always done so keeping it 1519 * here ensure binary backward compatibility. 1520 */ 1521 drive_flags = ATA_DRIVE_NOSTREAM | 1522 chp->ch_drive[xfer->c_drive].drive_flags; 1523 } else { 1524 /* 1525 * Other data structure are opaque and should be transfered 1526 * as is. 1527 */ 1528 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1529 } 1530 1531 #ifdef WDC_NO_IDS 1532 wflags = AT_POLL; 1533 #else 1534 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1535 /* both wait and poll, we can tsleep here */ 1536 wflags = AT_WAIT | AT_POLL; 1537 } else { 1538 wflags = AT_POLL; 1539 } 1540 #endif 1541 1542 again: 1543 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1544 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1545 xfer->c_drive), DEBUG_INTR); 1546 /* 1547 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1548 * Reselect again, it doesn't hurt for others commands, and the time 1549 * penalty for the extra register write is acceptable, 1550 * wdc_exec_command() isn't called often (mostly for autoconfig) 1551 */ 1552 if ((xfer->c_flags & C_ATAPI) != 0) { 1553 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1554 WDSD_IBM | (xfer->c_drive << 4)); 1555 } 1556 if ((ata_c->flags & AT_XFDONE) != 0) { 1557 /* 1558 * We have completed a data xfer. The drive should now be 1559 * in its initial state 1560 */ 1561 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1562 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1563 wflags) == WDCWAIT_TOUT) { 1564 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1565 return 0; /* IRQ was not for us */ 1566 ata_c->flags |= AT_TIMEOU; 1567 } 1568 goto out; 1569 } 1570 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1571 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1572 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1573 return 0; /* IRQ was not for us */ 1574 ata_c->flags |= AT_TIMEOU; 1575 goto out; 1576 } 1577 if (wdc->irqack) 1578 wdc->irqack(chp); 1579 if (ata_c->flags & AT_READ) { 1580 if ((chp->ch_status & WDCS_DRQ) == 0) { 1581 ata_c->flags |= AT_TIMEOU; 1582 goto out; 1583 } 1584 wdc->datain_pio(chp, drive_flags, data, bcount); 1585 /* at this point the drive should be in its initial state */ 1586 ata_c->flags |= AT_XFDONE; 1587 /* 1588 * XXX checking the status register again here cause some 1589 * hardware to timeout. 1590 */ 1591 } else if (ata_c->flags & AT_WRITE) { 1592 if ((chp->ch_status & WDCS_DRQ) == 0) { 1593 ata_c->flags |= AT_TIMEOU; 1594 goto out; 1595 } 1596 wdc->dataout_pio(chp, drive_flags, data, bcount); 1597 ata_c->flags |= AT_XFDONE; 1598 if ((ata_c->flags & AT_POLL) == 0) { 1599 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1600 callout_reset(&chp->ch_callout, 1601 mstohz(ata_c->timeout), wdctimeout, chp); 1602 return 1; 1603 } else { 1604 goto again; 1605 } 1606 } 1607 out: 1608 __wdccommand_done(chp, xfer); 1609 return 1; 1610 } 1611 1612 static void 1613 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1614 { 1615 struct atac_softc *atac = chp->ch_atac; 1616 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1617 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1618 struct ata_command *ata_c = xfer->c_cmd; 1619 1620 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1621 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1622 ata_c->flags), DEBUG_FUNCS); 1623 1624 1625 if (chp->ch_status & WDCS_DWF) 1626 ata_c->flags |= AT_DF; 1627 if (chp->ch_status & WDCS_ERR) { 1628 ata_c->flags |= AT_ERROR; 1629 ata_c->r_error = chp->ch_error; 1630 } 1631 if ((ata_c->flags & AT_READREG) != 0 && 1632 device_is_active(atac->atac_dev) && 1633 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1634 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1635 wdr->cmd_iohs[wd_status], 0); 1636 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1637 wdr->cmd_iohs[wd_error], 0); 1638 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1639 wdr->cmd_iohs[wd_seccnt], 0); 1640 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1641 wdr->cmd_iohs[wd_sector], 0) << 0; 1642 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1643 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1644 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1645 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1646 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1647 wdr->cmd_iohs[wd_sdh], 0); 1648 1649 if ((ata_c->flags & AT_LBA48) != 0) { 1650 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1651 if ((ata_c->flags & AT_POLL) != 0) 1652 bus_space_write_1(wdr->ctl_iot, 1653 wdr->ctl_ioh, wd_aux_ctlr, 1654 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1655 else 1656 bus_space_write_1(wdr->ctl_iot, 1657 wdr->ctl_ioh, wd_aux_ctlr, 1658 WDCTL_HOB|WDCTL_4BIT); 1659 } 1660 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1661 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1662 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1663 wdr->cmd_iohs[wd_sector], 0) << 24; 1664 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1665 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1666 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1667 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1668 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1669 if ((ata_c->flags & AT_POLL) != 0) 1670 bus_space_write_1(wdr->ctl_iot, 1671 wdr->ctl_ioh, wd_aux_ctlr, 1672 WDCTL_4BIT|WDCTL_IDS); 1673 else 1674 bus_space_write_1(wdr->ctl_iot, 1675 wdr->ctl_ioh, wd_aux_ctlr, 1676 WDCTL_4BIT); 1677 } 1678 } else { 1679 ata_c->r_lba |= 1680 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1681 } 1682 ata_c->r_device &= 0xf0; 1683 } 1684 callout_stop(&chp->ch_callout); 1685 chp->ch_queue->active_xfer = NULL; 1686 if (ata_c->flags & AT_POLL) { 1687 /* enable interrupts */ 1688 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1689 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1690 wd_aux_ctlr, WDCTL_4BIT); 1691 delay(10); /* some drives need a little delay here */ 1692 } 1693 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1694 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1695 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1696 wakeup(&chp->ch_queue->active_xfer); 1697 } else 1698 __wdccommand_done_end(chp, xfer); 1699 } 1700 1701 static void 1702 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1703 { 1704 struct ata_command *ata_c = xfer->c_cmd; 1705 1706 ata_c->flags |= AT_DONE; 1707 ata_free_xfer(chp, xfer); 1708 if (ata_c->flags & AT_WAIT) 1709 wakeup(ata_c); 1710 else if (ata_c->callback) 1711 ata_c->callback(ata_c->callback_arg); 1712 atastart(chp); 1713 return; 1714 } 1715 1716 static void 1717 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1718 int reason) 1719 { 1720 struct ata_command *ata_c = xfer->c_cmd; 1721 1722 switch (reason) { 1723 case KILL_GONE: 1724 ata_c->flags |= AT_GONE; 1725 break; 1726 case KILL_RESET: 1727 ata_c->flags |= AT_RESET; 1728 break; 1729 default: 1730 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1731 reason); 1732 panic("__wdccommand_kill_xfer"); 1733 } 1734 __wdccommand_done_end(chp, xfer); 1735 } 1736 1737 /* 1738 * Send a command. The drive should be ready. 1739 * Assumes interrupts are blocked. 1740 */ 1741 void 1742 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1743 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1744 u_int8_t features) 1745 { 1746 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1747 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1748 1749 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1750 "sector=%d count=%d features=%d\n", 1751 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1752 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1753 1754 if (wdc->select) 1755 wdc->select(chp,drive); 1756 1757 /* Select drive, head, and addressing mode. */ 1758 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1759 WDSD_IBM | (drive << 4) | head); 1760 /* Load parameters into the wd_features register. */ 1761 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1762 features); 1763 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1764 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1765 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1766 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1767 0, cylin >> 8); 1768 1769 /* Send command. */ 1770 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1771 return; 1772 } 1773 1774 /* 1775 * Send a 48-bit addressing command. The drive should be ready. 1776 * Assumes interrupts are blocked. 1777 */ 1778 void 1779 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1780 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1781 { 1782 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1783 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1784 1785 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1786 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1787 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1788 chp->ch_channel, drive, command, blkno, count, features, device), 1789 DEBUG_FUNCS); 1790 1791 KASSERT(drive < wdc->wdc_maxdrives); 1792 1793 if (wdc->select) 1794 wdc->select(chp,drive); 1795 1796 /* Select drive, head, and addressing mode. */ 1797 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1798 (drive << 4) | device); 1799 1800 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1801 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1802 0, features); 1803 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1804 0, count); 1805 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1806 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1807 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1808 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1809 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1810 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1811 } else { 1812 /* previous */ 1813 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1814 0, features >> 8); 1815 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1816 0, count >> 8); 1817 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1818 0, blkno >> 24); 1819 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1820 0, blkno >> 32); 1821 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1822 0, blkno >> 40); 1823 1824 /* current */ 1825 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1826 0, features); 1827 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1828 0, count); 1829 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1830 0, blkno); 1831 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1832 0, blkno >> 8); 1833 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1834 0, blkno >> 16); 1835 } 1836 1837 /* Send command. */ 1838 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1839 return; 1840 } 1841 1842 /* 1843 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1844 * tested by the caller. 1845 */ 1846 void 1847 wdccommandshort(struct ata_channel *chp, int drive, int command) 1848 { 1849 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1850 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1851 1852 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1853 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1854 command), DEBUG_FUNCS); 1855 1856 if (wdc->select) 1857 wdc->select(chp,drive); 1858 1859 /* Select drive. */ 1860 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1861 WDSD_IBM | (drive << 4)); 1862 1863 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1864 } 1865 1866 static void 1867 __wdcerror(struct ata_channel *chp, const char *msg) 1868 { 1869 struct atac_softc *atac = chp->ch_atac; 1870 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1871 1872 if (xfer == NULL) 1873 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1874 chp->ch_channel, msg); 1875 else 1876 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1877 chp->ch_channel, xfer->c_drive, msg); 1878 } 1879 1880 /* 1881 * the bit bucket 1882 */ 1883 void 1884 wdcbit_bucket(struct ata_channel *chp, int size) 1885 { 1886 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1887 1888 for (; size >= 2; size -= 2) 1889 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1890 if (size) 1891 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1892 } 1893 1894 static void 1895 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1896 { 1897 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1898 1899 #ifndef __NO_STRICT_ALIGNMENT 1900 if ((uintptr_t)bf & 1) 1901 goto unaligned; 1902 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1903 goto unaligned; 1904 #endif 1905 1906 if (flags & ATA_DRIVE_NOSTREAM) { 1907 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1908 bus_space_read_multi_4(wdr->data32iot, 1909 wdr->data32ioh, 0, bf, len >> 2); 1910 bf = (char *)bf + (len & ~3); 1911 len &= 3; 1912 } 1913 if (len > 1) { 1914 bus_space_read_multi_2(wdr->cmd_iot, 1915 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1916 bf = (char *)bf + (len & ~1); 1917 len &= 1; 1918 } 1919 } else { 1920 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1921 bus_space_read_multi_stream_4(wdr->data32iot, 1922 wdr->data32ioh, 0, bf, len >> 2); 1923 bf = (char *)bf + (len & ~3); 1924 len &= 3; 1925 } 1926 if (len > 1) { 1927 bus_space_read_multi_stream_2(wdr->cmd_iot, 1928 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1929 bf = (char *)bf + (len & ~1); 1930 len &= 1; 1931 } 1932 } 1933 if (len) 1934 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1935 wdr->cmd_iohs[wd_data], 0); 1936 return; 1937 1938 #ifndef __NO_STRICT_ALIGNMENT 1939 unaligned: 1940 if (flags & ATA_DRIVE_NOSTREAM) { 1941 if (flags & ATA_DRIVE_CAP32) { 1942 while (len > 3) { 1943 uint32_t val; 1944 1945 val = bus_space_read_4(wdr->data32iot, 1946 wdr->data32ioh, 0); 1947 memcpy(bf, &val, 4); 1948 bf = (char *)bf + 4; 1949 len -= 4; 1950 } 1951 } 1952 while (len > 1) { 1953 uint16_t val; 1954 1955 val = bus_space_read_2(wdr->cmd_iot, 1956 wdr->cmd_iohs[wd_data], 0); 1957 memcpy(bf, &val, 2); 1958 bf = (char *)bf + 2; 1959 len -= 2; 1960 } 1961 } else { 1962 if (flags & ATA_DRIVE_CAP32) { 1963 while (len > 3) { 1964 uint32_t val; 1965 1966 val = bus_space_read_stream_4(wdr->data32iot, 1967 wdr->data32ioh, 0); 1968 memcpy(bf, &val, 4); 1969 bf = (char *)bf + 4; 1970 len -= 4; 1971 } 1972 } 1973 while (len > 1) { 1974 uint16_t val; 1975 1976 val = bus_space_read_stream_2(wdr->cmd_iot, 1977 wdr->cmd_iohs[wd_data], 0); 1978 memcpy(bf, &val, 2); 1979 bf = (char *)bf + 2; 1980 len -= 2; 1981 } 1982 } 1983 #endif 1984 } 1985 1986 static void 1987 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1988 { 1989 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1990 1991 #ifndef __NO_STRICT_ALIGNMENT 1992 if ((uintptr_t)bf & 1) 1993 goto unaligned; 1994 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1995 goto unaligned; 1996 #endif 1997 1998 if (flags & ATA_DRIVE_NOSTREAM) { 1999 if (flags & ATA_DRIVE_CAP32) { 2000 bus_space_write_multi_4(wdr->data32iot, 2001 wdr->data32ioh, 0, bf, len >> 2); 2002 bf = (char *)bf + (len & ~3); 2003 len &= 3; 2004 } 2005 if (len) { 2006 bus_space_write_multi_2(wdr->cmd_iot, 2007 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2008 } 2009 } else { 2010 if (flags & ATA_DRIVE_CAP32) { 2011 bus_space_write_multi_stream_4(wdr->data32iot, 2012 wdr->data32ioh, 0, bf, len >> 2); 2013 bf = (char *)bf + (len & ~3); 2014 len &= 3; 2015 } 2016 if (len) { 2017 bus_space_write_multi_stream_2(wdr->cmd_iot, 2018 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2019 } 2020 } 2021 return; 2022 2023 #ifndef __NO_STRICT_ALIGNMENT 2024 unaligned: 2025 if (flags & ATA_DRIVE_NOSTREAM) { 2026 if (flags & ATA_DRIVE_CAP32) { 2027 while (len > 3) { 2028 uint32_t val; 2029 2030 memcpy(&val, bf, 4); 2031 bus_space_write_4(wdr->data32iot, 2032 wdr->data32ioh, 0, val); 2033 bf = (char *)bf + 4; 2034 len -= 4; 2035 } 2036 } 2037 while (len > 1) { 2038 uint16_t val; 2039 2040 memcpy(&val, bf, 2); 2041 bus_space_write_2(wdr->cmd_iot, 2042 wdr->cmd_iohs[wd_data], 0, val); 2043 bf = (char *)bf + 2; 2044 len -= 2; 2045 } 2046 } else { 2047 if (flags & ATA_DRIVE_CAP32) { 2048 while (len > 3) { 2049 uint32_t val; 2050 2051 memcpy(&val, bf, 4); 2052 bus_space_write_stream_4(wdr->data32iot, 2053 wdr->data32ioh, 0, val); 2054 bf = (char *)bf + 4; 2055 len -= 4; 2056 } 2057 } 2058 while (len > 1) { 2059 uint16_t val; 2060 2061 memcpy(&val, bf, 2); 2062 bus_space_write_stream_2(wdr->cmd_iot, 2063 wdr->cmd_iohs[wd_data], 0, val); 2064 bf = (char *)bf + 2; 2065 len -= 2; 2066 } 2067 } 2068 #endif 2069 } 2070
Indexes created Thu Sep 25 06:09:39 GMT 2025