wdc.c revision 1.284
1 /* $NetBSD: wdc.c,v 1.284 2017/10/07 16:05:32 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.284 2017/10/07 16:05:32 jdolecek Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then kpause for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 SCSIPI_BUSTYPE_ATA, 130 NULL, /* wdc_ata_bio */ 131 NULL, /* wdc_reset_drive */ 132 wdc_reset_channel, 133 wdc_exec_command, 134 NULL, /* ata_get_params */ 135 NULL, /* wdc_ata_addref */ 136 NULL, /* wdc_ata_delref */ 137 NULL /* ata_kill_pending */ 138 }; 139 #endif 140 141 /* Flags to wdcreset(). */ 142 #define RESET_POLL 1 143 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 144 145 static int wdcprobe1(struct ata_channel *, int); 146 static int wdcreset(struct ata_channel *, int); 147 static void __wdcerror(struct ata_channel *, const char *); 148 static int __wdcwait_reset(struct ata_channel *, int, int); 149 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 150 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_kill_xfer(struct ata_channel *, 153 struct ata_xfer *, int); 154 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 155 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 156 static int __wdcwait(struct ata_channel *, int, int, int, int *); 157 158 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 159 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 160 #define DEBUG_INTR 0x01 161 #define DEBUG_XFERS 0x02 162 #define DEBUG_STATUS 0x04 163 #define DEBUG_FUNCS 0x08 164 #define DEBUG_PROBE 0x10 165 #define DEBUG_DETACH 0x20 166 #define DEBUG_DELAY 0x40 167 #ifdef ATADEBUG 168 extern int atadebug_mask; /* init'ed in ata.c */ 169 int wdc_nxfer = 0; 170 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 171 #else 172 #define ATADEBUG_PRINT(args, level) 173 #endif 174 175 /* 176 * Initialize the "shadow register" handles for a standard wdc controller. 177 */ 178 void 179 wdc_init_shadow_regs(struct wdc_regs *wdr) 180 { 181 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 182 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 183 } 184 185 /* 186 * Allocate a wdc_regs array, based on the number of channels. 187 */ 188 void 189 wdc_allocate_regs(struct wdc_softc *wdc) 190 { 191 192 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 193 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 194 } 195 196 #if NSATA > 0 197 /* 198 * probe drives on SATA controllers with standard SATA registers: 199 * bring the PHYs online, read the drive signature and set drive flags 200 * appropriately. 201 */ 202 void 203 wdc_sataprobe(struct ata_channel *chp) 204 { 205 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 206 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 207 int i; 208 209 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 210 211 /* do this before we take lock */ 212 213 ata_channel_lock(chp); 214 215 /* reset the PHY and bring online */ 216 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 217 wdr->sata_status, AT_WAIT)) { 218 case SStatus_DET_DEV: 219 /* wait 5s for BSY to clear */ 220 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 221 bus_space_write_1(wdr->cmd_iot, 222 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 223 delay(10); /* 400ns delay */ 224 st = bus_space_read_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_status], 0); 226 if ((st & WDCS_BSY) == 0) 227 break; 228 ata_delay(chp, 1, "sataprb", AT_WAIT); 229 } 230 if (i == WDC_PROBE_WAIT * hz) 231 aprint_error_dev(chp->ch_atac->atac_dev, 232 "BSY never cleared, status 0x%02x\n", st); 233 sc = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_seccnt], 0); 235 sn = bus_space_read_1(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_sector], 0); 237 cl = bus_space_read_1(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_cyl_lo], 0); 239 ch = bus_space_read_1(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_hi], 0); 241 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 242 "cl=0x%x ch=0x%x\n", 243 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 244 sc, sn, cl, ch), DEBUG_PROBE); 245 if (atabus_alloc_drives(chp, 1) != 0) 246 return; 247 /* 248 * sc and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 if (cl == 0x14 && ch == 0xeb) 252 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 253 else 254 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 255 256 /* 257 * issue a reset in case only the interface part of the drive 258 * is up 259 */ 260 if (wdcreset(chp, RESET_SLEEP) != 0) 261 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 262 break; 263 264 default: 265 break; 266 } 267 268 ata_channel_unlock(chp); 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; /* XXX: large struct */ 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, tfd; 296 297 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 298 return; 299 if (wdcprobe1(chp, 0) == 0) { 300 /* No drives, abort the attach here. */ 301 atabus_free_drives(chp); 302 return; 303 } 304 305 ata_channel_lock(chp); 306 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 307 for (i = 0; i < mstohz(3000); i++) { 308 /* 309 * select drive 1 first, so that master is selected on 310 * exit from the loop 311 */ 312 if (chp->ch_ndrives > 1 && 313 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 314 if (wdc->select) 315 wdc->select(chp,1); 316 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 317 0, WDSD_IBM | 0x10); 318 delay(10); /* 400ns delay */ 319 st1 = bus_space_read_1(wdr->cmd_iot, 320 wdr->cmd_iohs[wd_status], 0); 321 } 322 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 323 if (wdc->select) 324 wdc->select(chp,0); 325 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 326 0, WDSD_IBM); 327 delay(10); /* 400ns delay */ 328 st0 = bus_space_read_1(wdr->cmd_iot, 329 wdr->cmd_iohs[wd_status], 0); 330 } 331 332 333 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 334 (st0 & WDCS_DRDY)) && 335 (chp->ch_ndrives < 2 || 336 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 337 (st1 & WDCS_DRDY))) 338 break; 339 #ifdef WDC_NO_IDS 340 /* cannot kpause here (can't enable IPL_BIO interrups), 341 * delay instead 342 */ 343 delay(1000000 / hz); 344 #else 345 ata_delay(chp, 1, "atadrdy", AT_WAIT); 346 #endif 347 } 348 if ((st0 & WDCS_DRDY) == 0 && 349 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 350 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 351 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 352 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 353 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 354 ata_channel_unlock(chp); 355 356 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 357 device_xname(atac->atac_dev), 358 chp->ch_channel, st0, st1), DEBUG_PROBE); 359 360 /* Wait a bit, some devices are weird just after a reset. */ 361 delay(5000); 362 363 for (i = 0; i < chp->ch_ndrives; i++) { 364 #if NATA_DMA 365 /* 366 * Init error counter so that an error within the first xfers 367 * will trigger a downgrade 368 */ 369 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 370 #endif 371 372 /* If controller can't do 16bit flag the drives as 32bit */ 373 if ((atac->atac_cap & 374 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 375 ata_channel_lock(chp); 376 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 377 ata_channel_unlock(chp); 378 } 379 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 380 continue; 381 382 /* Shortcut in case we've been shutdown */ 383 if (chp->ch_flags & ATACH_SHUTDOWN) 384 return; 385 386 /* 387 * Issue an identify, to try to detect ghosts. 388 * Note that we can't use interrupts here, because if there 389 * is no devices, we will get a command aborted without 390 * interrupts. 391 */ 392 error = ata_get_params(&chp->ch_drive[i], 393 AT_WAIT | AT_POLL, ¶ms); 394 if (error != CMD_OK) { 395 ata_channel_lock(chp); 396 ata_delay(chp, 1000, "atacnf", AT_WAIT); 397 ata_channel_unlock(chp); 398 399 /* Shortcut in case we've been shutdown */ 400 if (chp->ch_flags & ATACH_SHUTDOWN) 401 return; 402 403 error = ata_get_params(&chp->ch_drive[i], 404 AT_WAIT | AT_POLL, ¶ms); 405 } 406 if (error != CMD_OK) { 407 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 408 device_xname(atac->atac_dev), 409 chp->ch_channel, i, error), DEBUG_PROBE); 410 ata_channel_lock(chp); 411 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 412 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 413 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 414 ata_channel_unlock(chp); 415 continue; 416 } 417 /* 418 * Pre-ATA drive ? 419 * Test registers writability (Error register not 420 * writable, but cyllo is), then try an ATA command. 421 */ 422 if (wdc->select) 423 wdc->select(chp,i); 424 bus_space_write_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 426 delay(10); /* 400ns delay */ 427 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 428 0, 0x58); 429 bus_space_write_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 431 if (bus_space_read_1(wdr->cmd_iot, 432 wdr->cmd_iohs[wd_error], 0) == 0x58 || 433 bus_space_read_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 435 ATADEBUG_PRINT(("%s:%d:%d: register " 436 "writability failed\n", 437 device_xname(atac->atac_dev), 438 chp->ch_channel, i), DEBUG_PROBE); 439 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 440 ata_channel_unlock(chp); 441 continue; 442 } 443 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 444 WDCWAIT_TOUT) { 445 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 446 device_xname(atac->atac_dev), 447 chp->ch_channel, i), DEBUG_PROBE); 448 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 449 ata_channel_unlock(chp); 450 continue; 451 } 452 bus_space_write_1(wdr->cmd_iot, 453 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 454 delay(10); /* 400ns delay */ 455 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 456 WDCWAIT_TOUT) { 457 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 458 device_xname(atac->atac_dev), 459 chp->ch_channel, i), DEBUG_PROBE); 460 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 461 ata_channel_unlock(chp); 462 } else { 463 for (j = 0; j < chp->ch_ndrives; j++) { 464 if (chp->ch_drive[i].drive_type != 465 ATA_DRIVET_NONE) { 466 chp->ch_drive[j].drive_type = 467 ATA_DRIVET_OLD; 468 } 469 } 470 ata_channel_unlock(chp); 471 } 472 } 473 } 474 } 475 476 int 477 wdcprobe(struct wdc_regs *wdr) 478 { 479 struct wdc_softc wdc; 480 struct ata_channel ch; 481 int rv; 482 483 memset(&wdc, 0, sizeof(wdc)); 484 memset(&ch, 0, sizeof(ch)); 485 ata_channel_init(&ch); 486 ch.ch_atac = &wdc.sc_atac; 487 ch.ch_queue = ata_queue_alloc(1); 488 wdc.regs = wdr; 489 490 /* default reset method */ 491 if (wdc.reset == NULL) 492 wdc.reset = wdc_do_reset; 493 494 rv = wdcprobe1(&ch, 1); 495 496 ata_queue_free(ch.ch_queue); 497 ata_channel_destroy(&ch); 498 499 return rv; 500 } 501 502 static int 503 wdcprobe1(struct ata_channel *chp, int poll) 504 { 505 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 506 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 507 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 508 u_int8_t ret_value = 0x03; 509 u_int8_t drive; 510 /* XXX if poll, wdc_probe_count is 0. */ 511 int wdc_probe_count = 512 poll ? (WDC_PROBE_WAIT / WDCDELAY) 513 : (WDC_PROBE_WAIT * hz); 514 515 /* 516 * Sanity check to see if the wdc channel responds at all. 517 */ 518 519 ata_channel_lock(chp); 520 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 521 while (wdc_probe_count-- > 0) { 522 if (wdc->select) 523 wdc->select(chp,0); 524 525 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 526 0, WDSD_IBM); 527 delay(10); /* 400ns delay */ 528 st0 = bus_space_read_1(wdr->cmd_iot, 529 wdr->cmd_iohs[wd_status], 0); 530 531 if (wdc->select) 532 wdc->select(chp,1); 533 534 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 535 0, WDSD_IBM | 0x10); 536 delay(10); /* 400ns delay */ 537 st1 = bus_space_read_1(wdr->cmd_iot, 538 wdr->cmd_iohs[wd_status], 0); 539 if ((st0 & WDCS_BSY) == 0) 540 break; 541 } 542 543 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 544 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 545 546 if (st0 == 0xff || st0 == WDSD_IBM) 547 ret_value &= ~0x01; 548 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 549 ret_value &= ~0x02; 550 /* Register writability test, drive 0. */ 551 if (ret_value & 0x01) { 552 if (wdc->select) 553 wdc->select(chp,0); 554 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 555 0, WDSD_IBM); 556 bus_space_write_1(wdr->cmd_iot, 557 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 558 cl = bus_space_read_1(wdr->cmd_iot, 559 wdr->cmd_iohs[wd_cyl_lo], 0); 560 if (cl != 0x02) { 561 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 562 "got 0x%x != 0x02\n", 563 __func__, chp->ch_channel, cl), 564 DEBUG_PROBE); 565 ret_value &= ~0x01; 566 } 567 bus_space_write_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 569 cl = bus_space_read_1(wdr->cmd_iot, 570 wdr->cmd_iohs[wd_cyl_lo], 0); 571 if (cl != 0x01) { 572 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 573 "got 0x%x != 0x01\n", 574 __func__, chp->ch_channel, cl), 575 DEBUG_PROBE); 576 ret_value &= ~0x01; 577 } 578 bus_space_write_1(wdr->cmd_iot, 579 wdr->cmd_iohs[wd_sector], 0, 0x01); 580 cl = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_sector], 0); 582 if (cl != 0x01) { 583 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 584 "got 0x%x != 0x01\n", 585 __func__, chp->ch_channel, cl), 586 DEBUG_PROBE); 587 ret_value &= ~0x01; 588 } 589 bus_space_write_1(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_sector], 0, 0x02); 591 cl = bus_space_read_1(wdr->cmd_iot, 592 wdr->cmd_iohs[wd_sector], 0); 593 if (cl != 0x02) { 594 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 595 "got 0x%x != 0x02\n", 596 __func__, chp->ch_channel, cl), 597 DEBUG_PROBE); 598 ret_value &= ~0x01; 599 } 600 cl = bus_space_read_1(wdr->cmd_iot, 601 wdr->cmd_iohs[wd_cyl_lo], 0); 602 if (cl != 0x01) { 603 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 604 "got 0x%x != 0x01\n", 605 __func__, chp->ch_channel, cl), 606 DEBUG_PROBE); 607 ret_value &= ~0x01; 608 } 609 } 610 /* Register writability test, drive 1. */ 611 if (ret_value & 0x02) { 612 if (wdc->select) 613 wdc->select(chp,1); 614 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 615 0, WDSD_IBM | 0x10); 616 bus_space_write_1(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 618 cl = bus_space_read_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0); 620 if (cl != 0x02) { 621 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 622 "got 0x%x != 0x02\n", 623 __func__, chp->ch_channel, cl), 624 DEBUG_PROBE); 625 ret_value &= ~0x02; 626 } 627 bus_space_write_1(wdr->cmd_iot, 628 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 629 cl = bus_space_read_1(wdr->cmd_iot, 630 wdr->cmd_iohs[wd_cyl_lo], 0); 631 if (cl != 0x01) { 632 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 633 "got 0x%x != 0x01\n", 634 __func__, chp->ch_channel, cl), 635 DEBUG_PROBE); 636 ret_value &= ~0x02; 637 } 638 bus_space_write_1(wdr->cmd_iot, 639 wdr->cmd_iohs[wd_sector], 0, 0x01); 640 cl = bus_space_read_1(wdr->cmd_iot, 641 wdr->cmd_iohs[wd_sector], 0); 642 if (cl != 0x01) { 643 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 644 "got 0x%x != 0x01\n", 645 __func__, chp->ch_channel, cl), 646 DEBUG_PROBE); 647 ret_value &= ~0x02; 648 } 649 bus_space_write_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_sector], 0, 0x02); 651 cl = bus_space_read_1(wdr->cmd_iot, 652 wdr->cmd_iohs[wd_sector], 0); 653 if (cl != 0x02) { 654 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 655 "got 0x%x != 0x02\n", 656 __func__, chp->ch_channel, cl), 657 DEBUG_PROBE); 658 ret_value &= ~0x02; 659 } 660 cl = bus_space_read_1(wdr->cmd_iot, 661 wdr->cmd_iohs[wd_cyl_lo], 0); 662 if (cl != 0x01) { 663 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 664 "got 0x%x != 0x01\n", 665 __func__, chp->ch_channel, cl), 666 DEBUG_PROBE); 667 ret_value &= ~0x02; 668 } 669 } 670 671 if (ret_value == 0) { 672 ata_channel_unlock(chp); 673 return 0; 674 } 675 } 676 677 #if 0 /* XXX this break some ATA or ATAPI devices */ 678 /* 679 * reset bus. Also send an ATAPI_RESET to devices, in case there are 680 * ATAPI device out there which don't react to the bus reset 681 */ 682 if (ret_value & 0x01) { 683 if (wdc->select) 684 wdc->select(chp,0); 685 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 686 0, WDSD_IBM); 687 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 688 ATAPI_SOFT_RESET); 689 } 690 if (ret_value & 0x02) { 691 if (wdc->select) 692 wdc->select(chp,0); 693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 694 0, WDSD_IBM | 0x10); 695 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 696 ATAPI_SOFT_RESET); 697 } 698 699 delay(5000); 700 #endif 701 702 wdc->reset(chp, RESET_POLL); 703 DELAY(2000); 704 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 705 706 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 707 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 708 WDCTL_4BIT); 709 710 #ifdef WDC_NO_IDS 711 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 712 #else 713 ret_value = __wdcwait_reset(chp, ret_value, poll); 714 #endif 715 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 716 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 717 718 /* if reset failed, there's nothing here */ 719 if (ret_value == 0) { 720 ata_channel_unlock(chp); 721 return 0; 722 } 723 724 /* 725 * Test presence of drives. First test register signatures looking 726 * for ATAPI devices. If it's not an ATAPI and reset said there may 727 * be something here assume it's ATA or OLD. Ghost will be killed 728 * later in attach routine. 729 */ 730 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 731 if ((ret_value & (0x01 << drive)) == 0) 732 continue; 733 if (wdc->select) 734 wdc->select(chp,drive); 735 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 736 WDSD_IBM | (drive << 4)); 737 delay(10); /* 400ns delay */ 738 /* Save registers contents */ 739 sc = bus_space_read_1(wdr->cmd_iot, 740 wdr->cmd_iohs[wd_seccnt], 0); 741 sn = bus_space_read_1(wdr->cmd_iot, 742 wdr->cmd_iohs[wd_sector], 0); 743 cl = bus_space_read_1(wdr->cmd_iot, 744 wdr->cmd_iohs[wd_cyl_lo], 0); 745 ch = bus_space_read_1(wdr->cmd_iot, 746 wdr->cmd_iohs[wd_cyl_hi], 0); 747 748 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 749 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 750 sn, cl, ch), DEBUG_PROBE); 751 /* 752 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 753 * we get wrong values here, so ignore it. 754 */ 755 if (chp->ch_drive != NULL) { 756 if (cl == 0x14 && ch == 0xeb) { 757 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 758 } else { 759 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 760 } 761 } 762 } 763 /* 764 * Select an existing drive before lowering spl, some WDC_NO_IDS 765 * devices incorrectly assert IRQ on nonexistent slave 766 */ 767 if (ret_value & 0x01) { 768 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 769 WDSD_IBM); 770 (void)bus_space_read_1(wdr->cmd_iot, 771 wdr->cmd_iohs[wd_status], 0); 772 } 773 ata_channel_unlock(chp); 774 return (ret_value); 775 } 776 777 void 778 wdcattach(struct ata_channel *chp) 779 { 780 struct atac_softc *atac = chp->ch_atac; 781 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 782 783 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 784 785 /* default data transfer methods */ 786 if (wdc->datain_pio == NULL) 787 wdc->datain_pio = wdc_datain_pio; 788 if (wdc->dataout_pio == NULL) 789 wdc->dataout_pio = wdc_dataout_pio; 790 /* default reset method */ 791 if (wdc->reset == NULL) 792 wdc->reset = wdc_do_reset; 793 794 /* initialise global data */ 795 if (atac->atac_bustype_ata == NULL) 796 atac->atac_bustype_ata = &wdc_ata_bustype; 797 if (atac->atac_probe == NULL) 798 atac->atac_probe = wdc_drvprobe; 799 #if NATAPIBUS > 0 800 if (atac->atac_atapibus_attach == NULL) 801 atac->atac_atapibus_attach = wdc_atapibus_attach; 802 #endif 803 804 ata_channel_attach(chp); 805 } 806 807 void 808 wdc_childdetached(device_t self, device_t child) 809 { 810 struct atac_softc *atac = device_private(self); 811 struct ata_channel *chp; 812 int i; 813 814 for (i = 0; i < atac->atac_nchannels; i++) { 815 chp = atac->atac_channels[i]; 816 if (child == chp->atabus) { 817 chp->atabus = NULL; 818 return; 819 } 820 } 821 } 822 823 int 824 wdcdetach(device_t self, int flags) 825 { 826 struct atac_softc *atac = device_private(self); 827 struct ata_channel *chp; 828 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 829 int i, error = 0; 830 831 for (i = 0; i < atac->atac_nchannels; i++) { 832 chp = atac->atac_channels[i]; 833 if (chp->atabus == NULL) 834 continue; 835 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 836 device_xname(atac->atac_dev), device_xname(chp->atabus)), 837 DEBUG_DETACH); 838 if ((error = config_detach(chp->atabus, flags)) != 0) 839 return error; 840 ata_channel_detach(chp); 841 } 842 if (adapt->adapt_refcnt != 0) 843 return EBUSY; 844 return 0; 845 } 846 847 /* restart an interrupted I/O */ 848 void 849 wdcrestart(void *v) 850 { 851 struct ata_channel *chp = v; 852 int s; 853 854 s = splbio(); 855 atastart(chp); 856 splx(s); 857 } 858 859 860 /* 861 * Interrupt routine for the controller. Acknowledge the interrupt, check for 862 * errors on the current operation, mark it done if necessary, and start the 863 * next request. Also check for a partially done transfer, and continue with 864 * the next chunk if so. 865 */ 866 int 867 wdcintr(void *arg) 868 { 869 struct ata_channel *chp = arg; 870 struct atac_softc *atac = chp->ch_atac; 871 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 872 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 873 struct ata_xfer *xfer; 874 int ret; 875 876 if (!device_is_active(atac->atac_dev)) { 877 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 878 DEBUG_INTR); 879 return (0); 880 } 881 882 xfer = ata_queue_get_active_xfer(chp); 883 if (xfer == NULL) { 884 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 885 /* try to clear the pending interrupt anyway */ 886 (void)bus_space_read_1(wdr->cmd_iot, 887 wdr->cmd_iohs[wd_status], 0); 888 return (0); 889 } 890 891 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 892 KASSERT(xfer != NULL); 893 894 #if NATA_DMA || NATA_PIOBM 895 if (chp->ch_flags & ATACH_DMA_WAIT) { 896 wdc->dma_status = 897 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 898 xfer->c_drive, WDC_DMAEND_END); 899 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 900 /* IRQ not for us, not detected by DMA engine */ 901 return 0; 902 } 903 chp->ch_flags &= ~ATACH_DMA_WAIT; 904 } 905 #endif 906 KASSERT(xfer->c_intr != NULL); 907 ret = xfer->c_intr(chp, xfer, 1); 908 return (ret); 909 } 910 911 /* Put all disk in RESET state */ 912 void 913 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 914 { 915 struct ata_channel *chp = drvp->chnl_softc; 916 917 KASSERT(sigp == NULL); 918 919 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 920 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 921 drvp->drive), DEBUG_FUNCS); 922 923 ata_reset_channel(chp, flags); 924 } 925 926 void 927 wdc_reset_channel(struct ata_channel *chp, int flags) 928 { 929 struct ata_xfer *xfer; 930 #if NATA_DMA || NATA_PIOBM 931 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 932 #endif 933 934 /* 935 * if the current command is on an ATAPI device, issue a 936 * ATAPI_SOFT_RESET 937 */ 938 xfer = ata_queue_get_active_xfer(chp); 939 940 ata_channel_lock(chp); 941 942 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 943 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 944 ata_delay(chp, 1000, "atardl", flags); 945 } 946 947 /* reset the channel */ 948 if (flags & AT_WAIT) 949 (void) wdcreset(chp, RESET_SLEEP); 950 else 951 (void) wdcreset(chp, RESET_POLL); 952 953 /* 954 * wait a bit after reset; in case the DMA engines needs some time 955 * to recover. 956 */ 957 ata_delay(chp, 1000, "atardl", flags); 958 959 /* 960 * Look for pending xfers. If we have a shared queue, we'll also reset 961 * the other channel if the current xfer is running on it. 962 * Then we'll kill the eventual active transfer explicitely, so that 963 * it is queued for retry immediatelly without waiting for I/O timeout. 964 */ 965 if (xfer) { 966 if (xfer->c_chp != chp) { 967 ata_channel_unlock(chp); 968 ata_reset_channel(xfer->c_chp, flags); 969 ata_channel_lock(chp); 970 } else { 971 #if NATA_DMA || NATA_PIOBM 972 /* 973 * If we're waiting for DMA, stop the 974 * DMA engine 975 */ 976 if (chp->ch_flags & ATACH_DMA_WAIT) { 977 (*wdc->dma_finish)(wdc->dma_arg, 978 chp->ch_channel, xfer->c_drive, 979 WDC_DMAEND_ABRT_QUIET); 980 chp->ch_flags &= ~ATACH_DMA_WAIT; 981 } 982 #endif 983 } 984 } 985 986 ata_kill_active(chp, KILL_RESET, flags); 987 988 ata_channel_unlock(chp); 989 } 990 991 static int 992 wdcreset(struct ata_channel *chp, int poll) 993 { 994 struct atac_softc *atac = chp->ch_atac; 995 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 996 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 997 int drv_mask1, drv_mask2; 998 999 ata_channel_lock_owned(chp); 1000 1001 #ifdef WDC_NO_IDS 1002 poll = RESET_POLL; 1003 #endif 1004 wdc->reset(chp, poll); 1005 1006 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1007 ? 0x01 : 0x00; 1008 if (chp->ch_ndrives > 1) 1009 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1010 ? 0x02 : 0x00; 1011 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1012 (poll == RESET_SLEEP) ? 0 : 1); 1013 if (drv_mask2 != drv_mask1) { 1014 aprint_error("%s channel %d: reset failed for", 1015 device_xname(atac->atac_dev), chp->ch_channel); 1016 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1017 aprint_normal(" drive 0"); 1018 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1019 aprint_normal(" drive 1"); 1020 aprint_normal("\n"); 1021 } 1022 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1023 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1024 WDCTL_4BIT); 1025 1026 return (drv_mask1 != drv_mask2) ? 1 : 0; 1027 } 1028 1029 void 1030 wdc_do_reset(struct ata_channel *chp, int poll) 1031 { 1032 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1033 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1034 int s = 0; 1035 1036 if (poll != RESET_SLEEP) 1037 s = splbio(); 1038 if (wdc->select) 1039 wdc->select(chp,0); 1040 /* master */ 1041 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1042 delay(10); /* 400ns delay */ 1043 /* assert SRST, wait for reset to complete */ 1044 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1045 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1046 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1047 delay(2000); 1048 } 1049 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1050 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1051 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1052 WDCTL_4BIT | WDCTL_IDS); 1053 delay(10); /* 400ns delay */ 1054 if (poll != RESET_SLEEP) { 1055 /* ACK interrupt in case there is one pending left */ 1056 if (wdc->irqack) 1057 wdc->irqack(chp); 1058 splx(s); 1059 } 1060 } 1061 1062 static int 1063 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1064 { 1065 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1066 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1067 int timeout, nloop; 1068 int wflags = poll ? AT_POLL : AT_WAIT; 1069 u_int8_t st0 = 0, st1 = 0; 1070 #ifdef ATADEBUG 1071 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1072 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1073 #endif 1074 if (poll) 1075 nloop = WDCNDELAY_RST; 1076 else 1077 nloop = WDC_RESET_WAIT * hz / 1000; 1078 /* wait for BSY to deassert */ 1079 for (timeout = 0; timeout < nloop; timeout++) { 1080 if ((drv_mask & 0x01) != 0) { 1081 if (wdc->select) 1082 wdc->select(chp,0); 1083 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1084 0, WDSD_IBM); /* master */ 1085 delay(10); 1086 st0 = bus_space_read_1(wdr->cmd_iot, 1087 wdr->cmd_iohs[wd_status], 0); 1088 #ifdef ATADEBUG 1089 sc0 = bus_space_read_1(wdr->cmd_iot, 1090 wdr->cmd_iohs[wd_seccnt], 0); 1091 sn0 = bus_space_read_1(wdr->cmd_iot, 1092 wdr->cmd_iohs[wd_sector], 0); 1093 cl0 = bus_space_read_1(wdr->cmd_iot, 1094 wdr->cmd_iohs[wd_cyl_lo], 0); 1095 ch0 = bus_space_read_1(wdr->cmd_iot, 1096 wdr->cmd_iohs[wd_cyl_hi], 0); 1097 #endif 1098 } 1099 if ((drv_mask & 0x02) != 0) { 1100 if (wdc->select) 1101 wdc->select(chp,1); 1102 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1103 0, WDSD_IBM | 0x10); /* slave */ 1104 delay(10); 1105 st1 = bus_space_read_1(wdr->cmd_iot, 1106 wdr->cmd_iohs[wd_status], 0); 1107 #ifdef ATADEBUG 1108 sc1 = bus_space_read_1(wdr->cmd_iot, 1109 wdr->cmd_iohs[wd_seccnt], 0); 1110 sn1 = bus_space_read_1(wdr->cmd_iot, 1111 wdr->cmd_iohs[wd_sector], 0); 1112 cl1 = bus_space_read_1(wdr->cmd_iot, 1113 wdr->cmd_iohs[wd_cyl_lo], 0); 1114 ch1 = bus_space_read_1(wdr->cmd_iot, 1115 wdr->cmd_iohs[wd_cyl_hi], 0); 1116 #endif 1117 } 1118 1119 if ((drv_mask & 0x01) == 0) { 1120 /* no master */ 1121 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1122 /* No master, slave is ready, it's done */ 1123 goto end; 1124 } 1125 if ((drv_mask & 0x02) == 0) { 1126 /* No master, no slave: it's done */ 1127 goto end; 1128 } 1129 } else if ((drv_mask & 0x02) == 0) { 1130 /* no slave */ 1131 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1132 /* No slave, master is ready, it's done */ 1133 goto end; 1134 } 1135 } else { 1136 /* Wait for both master and slave to be ready */ 1137 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1138 goto end; 1139 } 1140 } 1141 ata_delay(chp, WDCDELAY, "atarst", wflags); 1142 } 1143 /* Reset timed out. Maybe it's because drv_mask was not right */ 1144 if (st0 & WDCS_BSY) 1145 drv_mask &= ~0x01; 1146 if (st1 & WDCS_BSY) 1147 drv_mask &= ~0x02; 1148 end: 1149 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1150 "cl=0x%x ch=0x%x\n", 1151 device_xname(chp->ch_atac->atac_dev), 1152 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1153 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1154 "cl=0x%x ch=0x%x\n", 1155 device_xname(chp->ch_atac->atac_dev), 1156 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1157 1158 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1159 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1160 st0, st1), DEBUG_PROBE); 1161 1162 return drv_mask; 1163 } 1164 1165 /* 1166 * Wait for a drive to be !BSY, and have mask in its status register. 1167 * return -1 for a timeout after "timeout" ms. 1168 */ 1169 static int 1170 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1171 { 1172 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1173 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1174 u_char status, error = 0; 1175 int xtime = 0; 1176 int rv; 1177 1178 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1179 device_xname(chp->ch_atac->atac_dev), 1180 chp->ch_channel), DEBUG_STATUS); 1181 *tfd = 0; 1182 1183 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1184 1185 for (;;) { 1186 status = 1187 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1188 if ((status & (WDCS_BSY | mask)) == bits) 1189 break; 1190 if (++xtime > timeout) { 1191 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1192 "status %x error %x (mask 0x%x bits 0x%x)\n", 1193 xtime, status, 1194 bus_space_read_1(wdr->cmd_iot, 1195 wdr->cmd_iohs[wd_error], 0), mask, bits), 1196 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1197 rv = WDCWAIT_TOUT; 1198 goto out; 1199 } 1200 delay(WDCDELAY); 1201 } 1202 #ifdef ATADEBUG 1203 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1204 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1205 #endif 1206 if (status & WDCS_ERR) 1207 error = bus_space_read_1(wdr->cmd_iot, 1208 wdr->cmd_iohs[wd_error], 0); 1209 #ifdef WDCNDELAY_DEBUG 1210 /* After autoconfig, there should be no long delays. */ 1211 if (!cold && xtime > WDCNDELAY_DEBUG) { 1212 struct ata_xfer *xfer; 1213 1214 xfer = ata_queue_get_active_xfer(chp); 1215 if (xfer == NULL) 1216 printf("%s channel %d: warning: busy-wait took %dus\n", 1217 device_xname(chp->ch_atac->atac_dev), 1218 chp->ch_channel, WDCDELAY * xtime); 1219 else 1220 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1221 device_xname(chp->ch_atac->atac_dev), 1222 chp->ch_channel, xfer->c_drive, 1223 WDCDELAY * xtime); 1224 } 1225 #endif 1226 rv = WDCWAIT_OK; 1227 1228 out: 1229 *tfd = ATACH_ERR_ST(error, status); 1230 return rv; 1231 } 1232 1233 /* 1234 * Call __wdcwait(), polling using kpause() or waking up the kernel 1235 * thread if possible 1236 */ 1237 int 1238 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1239 int *tfd) 1240 { 1241 int error, i, timeout_hz = mstohz(timeout); 1242 1243 ata_channel_lock_owned(chp); 1244 1245 if (timeout_hz == 0 || 1246 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1247 error = __wdcwait(chp, mask, bits, timeout, tfd); 1248 else { 1249 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1250 if (error != 0) { 1251 if ((chp->ch_flags & ATACH_TH_RUN) || 1252 (flags & AT_WAIT)) { 1253 /* 1254 * we're running in the channel thread 1255 * or some userland thread context 1256 */ 1257 for (i = 0; i < timeout_hz; i++) { 1258 if (__wdcwait(chp, mask, bits, 1259 WDCDELAY_POLL, tfd) == 0) { 1260 error = 0; 1261 break; 1262 } 1263 kpause("atapoll", true, 1, 1264 &chp->ch_lock); 1265 } 1266 } else { 1267 /* 1268 * we're probably in interrupt context, 1269 * caller must ask the thread to come back here 1270 */ 1271 return(WDCWAIT_THR); 1272 } 1273 } 1274 } 1275 return (error); 1276 } 1277 1278 1279 #if NATA_DMA 1280 /* 1281 * Busy-wait for DMA to complete 1282 */ 1283 int 1284 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1285 { 1286 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1287 int xtime; 1288 1289 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1290 wdc->dma_status = 1291 (*wdc->dma_finish)(wdc->dma_arg, 1292 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1293 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1294 return 0; 1295 delay(WDCDELAY); 1296 } 1297 /* timeout, force a DMA halt */ 1298 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1299 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1300 return 1; 1301 } 1302 #endif 1303 1304 void 1305 wdctimeout(void *arg) 1306 { 1307 struct ata_xfer *xfer = arg; 1308 struct ata_channel *chp = xfer->c_chp; 1309 #if NATA_DMA || NATA_PIOBM 1310 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1311 #endif 1312 int s; 1313 1314 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1315 1316 s = splbio(); 1317 KASSERT(xfer != NULL); 1318 1319 if (ata_timo_xfer_check(xfer)) { 1320 /* Already logged */ 1321 goto out; 1322 } 1323 1324 __wdcerror(chp, "lost interrupt"); 1325 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1326 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1327 xfer->c_bcount, xfer->c_skip); 1328 #if NATA_DMA || NATA_PIOBM 1329 if (chp->ch_flags & ATACH_DMA_WAIT) { 1330 wdc->dma_status = 1331 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1332 xfer->c_drive, WDC_DMAEND_ABRT); 1333 chp->ch_flags &= ~ATACH_DMA_WAIT; 1334 } 1335 #endif 1336 /* 1337 * Call the interrupt routine. If we just missed an interrupt, 1338 * it will do what's needed. Else, it will take the needed 1339 * action (reset the device). 1340 * Before that we need to reinstall the timeout callback, 1341 * in case it will miss another irq while in this transfer 1342 * We arbitray chose it to be 1s 1343 */ 1344 callout_reset(&xfer->c_timo_callout, hz, wdctimeout, xfer); 1345 xfer->c_flags |= C_TIMEOU; 1346 KASSERT(xfer->c_intr != NULL); 1347 xfer->c_intr(chp, xfer, 1); 1348 1349 out: 1350 splx(s); 1351 } 1352 1353 int 1354 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1355 { 1356 struct ata_channel *chp = drvp->chnl_softc; 1357 struct ata_command *ata_c = &xfer->c_ata_c; 1358 int s, ret; 1359 1360 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1361 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1362 drvp->drive), DEBUG_FUNCS); 1363 1364 /* set up an xfer and queue. Wait for completion */ 1365 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1366 ata_c->flags |= AT_POLL; 1367 if (ata_c->flags & AT_POLL) 1368 xfer->c_flags |= C_POLL; 1369 if (ata_c->flags & AT_WAIT) 1370 xfer->c_flags |= C_WAIT; 1371 xfer->c_drive = drvp->drive; 1372 xfer->c_databuf = ata_c->data; 1373 xfer->c_bcount = ata_c->bcount; 1374 xfer->c_start = __wdccommand_start; 1375 xfer->c_poll = __wdccommand_poll; 1376 xfer->c_abort = __wdccommand_done; 1377 xfer->c_intr = __wdccommand_intr; 1378 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1379 1380 s = splbio(); 1381 ata_exec_xfer(chp, xfer); 1382 #ifdef DIAGNOSTIC 1383 if ((ata_c->flags & AT_POLL) != 0 && 1384 (ata_c->flags & AT_DONE) == 0) 1385 panic("wdc_exec_command: polled command not done"); 1386 #endif 1387 if (ata_c->flags & AT_DONE) { 1388 ret = ATACMD_COMPLETE; 1389 } else { 1390 if (ata_c->flags & AT_WAIT) { 1391 ata_channel_lock(chp); 1392 if ((ata_c->flags & AT_DONE) == 0) { 1393 ata_wait_xfer(chp, xfer); 1394 KASSERT((ata_c->flags & AT_DONE) != 0); 1395 } 1396 ata_channel_unlock(chp); 1397 ret = ATACMD_COMPLETE; 1398 } else { 1399 ret = ATACMD_QUEUED; 1400 } 1401 } 1402 splx(s); 1403 return ret; 1404 } 1405 1406 static int 1407 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1408 { 1409 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1410 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1411 int drive = xfer->c_drive; 1412 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1413 struct ata_command *ata_c = &xfer->c_ata_c; 1414 int tfd; 1415 1416 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1417 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1418 xfer->c_drive), DEBUG_FUNCS); 1419 1420 if (wdc->select) 1421 wdc->select(chp,drive); 1422 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1423 WDSD_IBM | (drive << 4)); 1424 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1425 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1426 case WDCWAIT_OK: 1427 break; 1428 case WDCWAIT_TOUT: 1429 ata_c->flags |= AT_TIMEOU; 1430 return ATASTART_ABORT; 1431 case WDCWAIT_THR: 1432 return ATASTART_TH; 1433 } 1434 if (ata_c->flags & AT_POLL) { 1435 /* polled command, disable interrupts */ 1436 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1437 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1438 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1439 } 1440 if ((ata_c->flags & AT_LBA48) != 0) { 1441 wdccommandext(chp, drive, ata_c->r_command, 1442 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1443 ata_c->r_device & ~0x10); 1444 } else { 1445 wdccommand(chp, drive, ata_c->r_command, 1446 (ata_c->r_lba >> 8) & 0xffff, 1447 WDSD_IBM | (drive << 4) | 1448 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1449 ((ata_c->r_lba >> 24) & 0x0f), 1450 ata_c->r_lba & 0xff, 1451 ata_c->r_count & 0xff, 1452 ata_c->r_features & 0xff); 1453 } 1454 1455 if ((ata_c->flags & AT_POLL) == 0) { 1456 callout_reset(&xfer->c_timo_callout, ata_c->timeout / 1000 * hz, 1457 wdctimeout, xfer); 1458 return ATASTART_STARTED; 1459 } 1460 1461 /* 1462 * Polled command. Wait for drive ready or drq. Done in intr(). 1463 * Wait for at last 400ns for status bit to be valid. 1464 */ 1465 delay(10); /* 400ns delay */ 1466 return ATASTART_POLL; 1467 } 1468 1469 static void 1470 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1471 { 1472 __wdccommand_intr(chp, xfer, 0); 1473 } 1474 1475 static int 1476 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1477 { 1478 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1479 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1480 struct ata_command *ata_c = &xfer->c_ata_c; 1481 int bcount = ata_c->bcount; 1482 char *data = ata_c->data; 1483 int wflags, tfd; 1484 int drive_flags; 1485 1486 if (ata_c->r_command == WDCC_IDENTIFY || 1487 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1488 /* 1489 * The IDENTIFY data has been designed as an array of 1490 * u_int16_t, so we can byteswap it on the fly. 1491 * Historically it's what we have always done so keeping it 1492 * here ensure binary backward compatibility. 1493 */ 1494 drive_flags = ATA_DRIVE_NOSTREAM | 1495 chp->ch_drive[xfer->c_drive].drive_flags; 1496 } else { 1497 /* 1498 * Other data structure are opaque and should be transfered 1499 * as is. 1500 */ 1501 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1502 } 1503 1504 #ifdef WDC_NO_IDS 1505 wflags = AT_POLL; 1506 #else 1507 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1508 /* both wait and poll, we can kpause here */ 1509 wflags = AT_WAIT | AT_POLL; 1510 } else { 1511 wflags = AT_POLL; 1512 } 1513 #endif 1514 1515 ata_channel_lock(chp); 1516 1517 again: 1518 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1519 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1520 xfer->c_drive), DEBUG_INTR); 1521 /* 1522 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1523 * Reselect again, it doesn't hurt for others commands, and the time 1524 * penalty for the extra register write is acceptable, 1525 * wdc_exec_command() isn't called often (mostly for autoconfig) 1526 */ 1527 if ((xfer->c_flags & C_ATAPI) != 0) { 1528 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1529 WDSD_IBM | (xfer->c_drive << 4)); 1530 } 1531 if ((ata_c->flags & AT_XFDONE) != 0) { 1532 /* 1533 * We have completed a data xfer. The drive should now be 1534 * in its initial state 1535 */ 1536 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1537 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1538 wflags, &tfd) == WDCWAIT_TOUT) { 1539 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1540 ata_channel_unlock(chp); 1541 return 0; /* IRQ was not for us */ 1542 } 1543 ata_c->flags |= AT_TIMEOU; 1544 } 1545 goto out; 1546 } 1547 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1548 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1549 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1550 ata_channel_unlock(chp); 1551 return 0; /* IRQ was not for us */ 1552 } 1553 ata_c->flags |= AT_TIMEOU; 1554 goto out; 1555 } 1556 if (wdc->irqack) 1557 wdc->irqack(chp); 1558 if (ata_c->flags & AT_READ) { 1559 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1560 ata_c->flags |= AT_TIMEOU; 1561 goto out; 1562 } 1563 wdc->datain_pio(chp, drive_flags, data, bcount); 1564 /* at this point the drive should be in its initial state */ 1565 ata_c->flags |= AT_XFDONE; 1566 /* 1567 * XXX checking the status register again here cause some 1568 * hardware to timeout. 1569 */ 1570 } else if (ata_c->flags & AT_WRITE) { 1571 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1572 ata_c->flags |= AT_TIMEOU; 1573 goto out; 1574 } 1575 wdc->dataout_pio(chp, drive_flags, data, bcount); 1576 ata_c->flags |= AT_XFDONE; 1577 if ((ata_c->flags & AT_POLL) == 0) { 1578 callout_reset(&xfer->c_timo_callout, 1579 mstohz(ata_c->timeout), wdctimeout, xfer); 1580 ata_channel_unlock(chp); 1581 return 1; 1582 } else { 1583 goto again; 1584 } 1585 } 1586 out: 1587 if (ATACH_ST(tfd) & WDCS_DWF) 1588 ata_c->flags |= AT_DF; 1589 if (ATACH_ST(tfd) & WDCS_ERR) { 1590 ata_c->flags |= AT_ERROR; 1591 ata_c->r_error = ATACH_ST(tfd); 1592 } 1593 1594 ata_channel_unlock(chp); 1595 1596 __wdccommand_done(chp, xfer); 1597 return 1; 1598 } 1599 1600 static void 1601 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1602 { 1603 struct atac_softc *atac = chp->ch_atac; 1604 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1605 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1606 struct ata_command *ata_c = &xfer->c_ata_c; 1607 bool start = true; 1608 1609 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1610 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1611 ata_c->flags), DEBUG_FUNCS); 1612 1613 if (ata_waitdrain_xfer_check(chp, xfer)) { 1614 start = false; 1615 goto out; 1616 } 1617 1618 if ((ata_c->flags & AT_READREG) != 0 && 1619 device_is_active(atac->atac_dev) && 1620 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1621 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1622 wdr->cmd_iohs[wd_status], 0); 1623 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1624 wdr->cmd_iohs[wd_error], 0); 1625 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1626 wdr->cmd_iohs[wd_seccnt], 0); 1627 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1628 wdr->cmd_iohs[wd_sector], 0) << 0; 1629 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1630 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1631 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1632 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1633 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1634 wdr->cmd_iohs[wd_sdh], 0); 1635 1636 if ((ata_c->flags & AT_LBA48) != 0) { 1637 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1638 if ((ata_c->flags & AT_POLL) != 0) 1639 bus_space_write_1(wdr->ctl_iot, 1640 wdr->ctl_ioh, wd_aux_ctlr, 1641 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1642 else 1643 bus_space_write_1(wdr->ctl_iot, 1644 wdr->ctl_ioh, wd_aux_ctlr, 1645 WDCTL_HOB|WDCTL_4BIT); 1646 } 1647 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1649 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_sector], 0) << 24; 1651 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1652 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1653 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1654 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1655 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1656 if ((ata_c->flags & AT_POLL) != 0) 1657 bus_space_write_1(wdr->ctl_iot, 1658 wdr->ctl_ioh, wd_aux_ctlr, 1659 WDCTL_4BIT|WDCTL_IDS); 1660 else 1661 bus_space_write_1(wdr->ctl_iot, 1662 wdr->ctl_ioh, wd_aux_ctlr, 1663 WDCTL_4BIT); 1664 } 1665 } else { 1666 ata_c->r_lba |= 1667 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1668 } 1669 ata_c->r_device &= 0xf0; 1670 } 1671 1672 ata_deactivate_xfer(chp, xfer); 1673 1674 __wdccommand_done_end(chp, xfer); 1675 1676 out: 1677 if (ata_c->flags & AT_POLL) { 1678 /* enable interrupts */ 1679 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1680 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1681 wd_aux_ctlr, WDCTL_4BIT); 1682 delay(10); /* some drives need a little delay here */ 1683 } 1684 1685 if (start) 1686 atastart(chp); 1687 } 1688 1689 static void 1690 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1691 { 1692 struct ata_command *ata_c = &xfer->c_ata_c; 1693 1694 ata_channel_lock(chp); 1695 ata_c->flags |= AT_DONE; 1696 if (ata_c->flags & AT_WAIT) 1697 ata_wake_xfer(chp, xfer); 1698 ata_channel_unlock(chp); 1699 } 1700 1701 static void 1702 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1703 int reason) 1704 { 1705 struct ata_command *ata_c = &xfer->c_ata_c; 1706 bool deactivate = true; 1707 1708 switch (reason) { 1709 case KILL_GONE_INACTIVE: 1710 deactivate = false; 1711 /* FALLTHROUGH */ 1712 case KILL_GONE: 1713 ata_c->flags |= AT_GONE; 1714 break; 1715 case KILL_RESET: 1716 ata_c->flags |= AT_RESET; 1717 break; 1718 default: 1719 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1720 reason); 1721 panic("__wdccommand_kill_xfer"); 1722 } 1723 1724 if (deactivate) 1725 ata_deactivate_xfer(chp, xfer); 1726 1727 __wdccommand_done_end(chp, xfer); 1728 } 1729 1730 /* 1731 * Send a command. The drive should be ready. 1732 * Assumes interrupts are blocked. 1733 */ 1734 void 1735 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1736 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1737 u_int8_t features) 1738 { 1739 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1740 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1741 1742 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1743 "sector=%d count=%d features=%d\n", 1744 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1745 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1746 1747 if (wdc->select) 1748 wdc->select(chp,drive); 1749 1750 /* Select drive, head, and addressing mode. */ 1751 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1752 WDSD_IBM | (drive << 4) | head); 1753 /* Load parameters into the wd_features register. */ 1754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1755 features); 1756 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1757 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1758 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1759 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1760 0, cylin >> 8); 1761 1762 /* Send command. */ 1763 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1764 return; 1765 } 1766 1767 /* 1768 * Send a 48-bit addressing command. The drive should be ready. 1769 * Assumes interrupts are blocked. 1770 */ 1771 void 1772 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1773 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1774 { 1775 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1776 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1777 1778 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1779 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1780 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1781 chp->ch_channel, drive, command, blkno, count, features, device), 1782 DEBUG_FUNCS); 1783 1784 KASSERT(drive < wdc->wdc_maxdrives); 1785 1786 if (wdc->select) 1787 wdc->select(chp,drive); 1788 1789 /* Select drive, head, and addressing mode. */ 1790 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1791 (drive << 4) | device); 1792 1793 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1794 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1795 0, features); 1796 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1797 0, count); 1798 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1799 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1800 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1801 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1802 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1803 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1804 } else { 1805 /* previous */ 1806 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1807 0, features >> 8); 1808 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1809 0, count >> 8); 1810 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1811 0, blkno >> 24); 1812 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1813 0, blkno >> 32); 1814 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1815 0, blkno >> 40); 1816 1817 /* current */ 1818 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1819 0, features); 1820 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1821 0, count); 1822 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1823 0, blkno); 1824 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1825 0, blkno >> 8); 1826 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1827 0, blkno >> 16); 1828 } 1829 1830 /* Send command. */ 1831 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1832 return; 1833 } 1834 1835 /* 1836 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1837 * tested by the caller. 1838 */ 1839 void 1840 wdccommandshort(struct ata_channel *chp, int drive, int command) 1841 { 1842 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1843 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1844 1845 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1846 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1847 command), DEBUG_FUNCS); 1848 1849 if (wdc->select) 1850 wdc->select(chp,drive); 1851 1852 /* Select drive. */ 1853 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1854 WDSD_IBM | (drive << 4)); 1855 1856 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1857 } 1858 1859 static void 1860 __wdcerror(struct ata_channel *chp, const char *msg) 1861 { 1862 struct atac_softc *atac = chp->ch_atac; 1863 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1864 1865 if (xfer == NULL) 1866 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1867 chp->ch_channel, msg); 1868 else 1869 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1870 chp->ch_channel, xfer->c_drive, msg); 1871 } 1872 1873 /* 1874 * the bit bucket 1875 */ 1876 void 1877 wdcbit_bucket(struct ata_channel *chp, int size) 1878 { 1879 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1880 1881 for (; size >= 2; size -= 2) 1882 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1883 if (size) 1884 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1885 } 1886 1887 static void 1888 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1889 { 1890 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1891 1892 #ifndef __NO_STRICT_ALIGNMENT 1893 if ((uintptr_t)bf & 1) 1894 goto unaligned; 1895 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1896 goto unaligned; 1897 #endif 1898 1899 if (flags & ATA_DRIVE_NOSTREAM) { 1900 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1901 bus_space_read_multi_4(wdr->data32iot, 1902 wdr->data32ioh, 0, bf, len >> 2); 1903 bf = (char *)bf + (len & ~3); 1904 len &= 3; 1905 } 1906 if (len > 1) { 1907 bus_space_read_multi_2(wdr->cmd_iot, 1908 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1909 bf = (char *)bf + (len & ~1); 1910 len &= 1; 1911 } 1912 } else { 1913 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1914 bus_space_read_multi_stream_4(wdr->data32iot, 1915 wdr->data32ioh, 0, bf, len >> 2); 1916 bf = (char *)bf + (len & ~3); 1917 len &= 3; 1918 } 1919 if (len > 1) { 1920 bus_space_read_multi_stream_2(wdr->cmd_iot, 1921 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1922 bf = (char *)bf + (len & ~1); 1923 len &= 1; 1924 } 1925 } 1926 if (len) 1927 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1928 wdr->cmd_iohs[wd_data], 0); 1929 return; 1930 1931 #ifndef __NO_STRICT_ALIGNMENT 1932 unaligned: 1933 if (flags & ATA_DRIVE_NOSTREAM) { 1934 if (flags & ATA_DRIVE_CAP32) { 1935 while (len > 3) { 1936 uint32_t val; 1937 1938 val = bus_space_read_4(wdr->data32iot, 1939 wdr->data32ioh, 0); 1940 memcpy(bf, &val, 4); 1941 bf = (char *)bf + 4; 1942 len -= 4; 1943 } 1944 } 1945 while (len > 1) { 1946 uint16_t val; 1947 1948 val = bus_space_read_2(wdr->cmd_iot, 1949 wdr->cmd_iohs[wd_data], 0); 1950 memcpy(bf, &val, 2); 1951 bf = (char *)bf + 2; 1952 len -= 2; 1953 } 1954 } else { 1955 if (flags & ATA_DRIVE_CAP32) { 1956 while (len > 3) { 1957 uint32_t val; 1958 1959 val = bus_space_read_stream_4(wdr->data32iot, 1960 wdr->data32ioh, 0); 1961 memcpy(bf, &val, 4); 1962 bf = (char *)bf + 4; 1963 len -= 4; 1964 } 1965 } 1966 while (len > 1) { 1967 uint16_t val; 1968 1969 val = bus_space_read_stream_2(wdr->cmd_iot, 1970 wdr->cmd_iohs[wd_data], 0); 1971 memcpy(bf, &val, 2); 1972 bf = (char *)bf + 2; 1973 len -= 2; 1974 } 1975 } 1976 #endif 1977 } 1978 1979 static void 1980 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1981 { 1982 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1983 1984 #ifndef __NO_STRICT_ALIGNMENT 1985 if ((uintptr_t)bf & 1) 1986 goto unaligned; 1987 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1988 goto unaligned; 1989 #endif 1990 1991 if (flags & ATA_DRIVE_NOSTREAM) { 1992 if (flags & ATA_DRIVE_CAP32) { 1993 bus_space_write_multi_4(wdr->data32iot, 1994 wdr->data32ioh, 0, bf, len >> 2); 1995 bf = (char *)bf + (len & ~3); 1996 len &= 3; 1997 } 1998 if (len) { 1999 bus_space_write_multi_2(wdr->cmd_iot, 2000 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2001 } 2002 } else { 2003 if (flags & ATA_DRIVE_CAP32) { 2004 bus_space_write_multi_stream_4(wdr->data32iot, 2005 wdr->data32ioh, 0, bf, len >> 2); 2006 bf = (char *)bf + (len & ~3); 2007 len &= 3; 2008 } 2009 if (len) { 2010 bus_space_write_multi_stream_2(wdr->cmd_iot, 2011 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2012 } 2013 } 2014 return; 2015 2016 #ifndef __NO_STRICT_ALIGNMENT 2017 unaligned: 2018 if (flags & ATA_DRIVE_NOSTREAM) { 2019 if (flags & ATA_DRIVE_CAP32) { 2020 while (len > 3) { 2021 uint32_t val; 2022 2023 memcpy(&val, bf, 4); 2024 bus_space_write_4(wdr->data32iot, 2025 wdr->data32ioh, 0, val); 2026 bf = (char *)bf + 4; 2027 len -= 4; 2028 } 2029 } 2030 while (len > 1) { 2031 uint16_t val; 2032 2033 memcpy(&val, bf, 2); 2034 bus_space_write_2(wdr->cmd_iot, 2035 wdr->cmd_iohs[wd_data], 0, val); 2036 bf = (char *)bf + 2; 2037 len -= 2; 2038 } 2039 } else { 2040 if (flags & ATA_DRIVE_CAP32) { 2041 while (len > 3) { 2042 uint32_t val; 2043 2044 memcpy(&val, bf, 4); 2045 bus_space_write_stream_4(wdr->data32iot, 2046 wdr->data32ioh, 0, val); 2047 bf = (char *)bf + 4; 2048 len -= 4; 2049 } 2050 } 2051 while (len > 1) { 2052 uint16_t val; 2053 2054 memcpy(&val, bf, 2); 2055 bus_space_write_stream_2(wdr->cmd_iot, 2056 wdr->cmd_iohs[wd_data], 0, val); 2057 bf = (char *)bf + 2; 2058 len -= 2; 2059 } 2060 } 2061 #endif 2062 } 2063
Indexes created Wed Sep 24 15:09:51 GMT 2025