wdc.c revision 1.293
1 /* $NetBSD: wdc.c,v 1.293 2019/10/22 12:09:11 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.293 2019/10/22 12:09:11 martin Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then kpause for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 .bustype_type = SCSIPI_BUSTYPE_ATA, 130 .ata_bio = NULL, 131 .ata_reset_drive = NULL, 132 .ata_reset_channel = wdc_reset_channel, 133 .ata_exec_command = wdc_exec_command, 134 .ata_get_params = NULL, 135 .ata_addref = NULL, 136 .ata_delref = NULL, 137 .ata_killpending = NULL, 138 .ata_recovery = NULL, 139 }; 140 #endif 141 142 /* Flags to wdcreset(). */ 143 #define RESET_POLL 1 144 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 145 146 static int wdcprobe1(struct ata_channel *, int); 147 static int wdcreset(struct ata_channel *, int); 148 static void __wdcerror(struct ata_channel *, const char *); 149 static int __wdcwait_reset(struct ata_channel *, int, int); 150 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_kill_xfer(struct ata_channel *, 154 struct ata_xfer *, int); 155 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 156 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 157 static int __wdcwait(struct ata_channel *, int, int, int, int *); 158 159 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 160 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 161 #define DEBUG_INTR 0x01 162 #define DEBUG_XFERS 0x02 163 #define DEBUG_STATUS 0x04 164 #define DEBUG_FUNCS 0x08 165 #define DEBUG_PROBE 0x10 166 #define DEBUG_DETACH 0x20 167 #define DEBUG_DELAY 0x40 168 #ifdef ATADEBUG 169 extern int atadebug_mask; /* init'ed in ata.c */ 170 int wdc_nxfer = 0; 171 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 172 #else 173 #define ATADEBUG_PRINT(args, level) 174 #endif 175 176 /* 177 * Initialize the "shadow register" handles for a standard wdc controller. 178 */ 179 void 180 wdc_init_shadow_regs(struct wdc_regs *wdr) 181 { 182 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 183 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 184 } 185 186 /* 187 * Allocate a wdc_regs array, based on the number of channels. 188 */ 189 void 190 wdc_allocate_regs(struct wdc_softc *wdc) 191 { 192 193 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 194 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 195 } 196 197 #if NSATA > 0 198 /* 199 * probe drives on SATA controllers with standard SATA registers: 200 * bring the PHYs online, read the drive signature and set drive flags 201 * appropriately. 202 */ 203 void 204 wdc_sataprobe(struct ata_channel *chp) 205 { 206 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 207 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 208 int i; 209 210 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 211 212 /* do this before we take lock */ 213 214 ata_channel_lock(chp); 215 216 /* reset the PHY and bring online */ 217 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 218 wdr->sata_status, AT_WAIT)) { 219 case SStatus_DET_DEV: 220 /* wait 5s for BSY to clear */ 221 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 222 bus_space_write_1(wdr->cmd_iot, 223 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 224 delay(10); /* 400ns delay */ 225 st = bus_space_read_1(wdr->cmd_iot, 226 wdr->cmd_iohs[wd_status], 0); 227 if ((st & WDCS_BSY) == 0) 228 break; 229 ata_delay(chp, 1, "sataprb", AT_WAIT); 230 } 231 if (i == WDC_PROBE_WAIT * hz) 232 aprint_error_dev(chp->ch_atac->atac_dev, 233 "BSY never cleared, status 0x%02x\n", st); 234 sc = bus_space_read_1(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_seccnt], 0); 236 sn = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_sector], 0); 238 cl = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_cyl_lo], 0); 240 ch = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_hi], 0); 242 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 243 "cl=0x%x ch=0x%x\n", 244 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 245 sc, sn, cl, ch), DEBUG_PROBE); 246 if (atabus_alloc_drives(chp, 1) != 0) 247 return; 248 /* 249 * sc and sn are supposed to be 0x1 for ATAPI, but in some 250 * cases we get wrong values here, so ignore it. 251 */ 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 254 else 255 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 256 257 /* 258 * issue a reset in case only the interface part of the drive 259 * is up 260 */ 261 if (wdcreset(chp, RESET_SLEEP) != 0) 262 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 263 break; 264 265 default: 266 break; 267 } 268 269 ata_channel_unlock(chp); 270 } 271 #endif /* NSATA > 0 */ 272 273 274 /* Test to see controller with at last one attached drive is there. 275 * Returns a bit for each possible drive found (0x01 for drive 0, 276 * 0x02 for drive 1). 277 * Logic: 278 * - If a status register is at 0xff, assume there is no drive here 279 * (ISA has pull-up resistors). Similarly if the status register has 280 * the value we last wrote to the bus (for IDE interfaces without pullups). 281 * If no drive at all -> return. 282 * - reset the controller, wait for it to complete (may take up to 31s !). 283 * If timeout -> return. 284 * - test ATA/ATAPI signatures. If at last one drive found -> return. 285 * - try an ATA command on the master. 286 */ 287 288 void 289 wdc_drvprobe(struct ata_channel *chp) 290 { 291 struct ataparams params; /* XXX: large struct */ 292 struct atac_softc *atac = chp->ch_atac; 293 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 294 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 295 u_int8_t st0 = 0, st1 = 0; 296 int i, j, error, tfd; 297 298 ata_channel_lock(chp); 299 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 300 return; 301 if (wdcprobe1(chp, 0) == 0) { 302 /* No drives, abort the attach here. */ 303 atabus_free_drives(chp); 304 ata_channel_unlock(chp); 305 return; 306 } 307 308 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 309 for (i = 0; i < mstohz(3000); i++) { 310 /* 311 * select drive 1 first, so that master is selected on 312 * exit from the loop 313 */ 314 if (chp->ch_ndrives > 1 && 315 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 316 if (wdc->select) 317 wdc->select(chp,1); 318 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 319 0, WDSD_IBM | 0x10); 320 delay(10); /* 400ns delay */ 321 st1 = bus_space_read_1(wdr->cmd_iot, 322 wdr->cmd_iohs[wd_status], 0); 323 } 324 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 325 if (wdc->select) 326 wdc->select(chp,0); 327 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 328 0, WDSD_IBM); 329 delay(10); /* 400ns delay */ 330 st0 = bus_space_read_1(wdr->cmd_iot, 331 wdr->cmd_iohs[wd_status], 0); 332 } 333 334 335 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 336 (st0 & WDCS_DRDY)) && 337 (chp->ch_ndrives < 2 || 338 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 339 (st1 & WDCS_DRDY))) 340 break; 341 #ifdef WDC_NO_IDS 342 /* cannot kpause here (can't enable IPL_BIO interrups), 343 * delay instead 344 */ 345 delay(1000000 / hz); 346 #else 347 ata_delay(chp, 1, "atadrdy", AT_WAIT); 348 #endif 349 } 350 if ((st0 & WDCS_DRDY) == 0 && 351 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 352 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 353 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 354 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 355 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 356 ata_channel_unlock(chp); 357 358 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 359 device_xname(atac->atac_dev), 360 chp->ch_channel, st0, st1), DEBUG_PROBE); 361 362 /* Wait a bit, some devices are weird just after a reset. */ 363 delay(5000); 364 365 for (i = 0; i < chp->ch_ndrives; i++) { 366 #if NATA_DMA 367 /* 368 * Init error counter so that an error within the first xfers 369 * will trigger a downgrade 370 */ 371 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 372 #endif 373 374 /* If controller can't do 16bit flag the drives as 32bit */ 375 if ((atac->atac_cap & 376 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 377 ata_channel_lock(chp); 378 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 379 ata_channel_unlock(chp); 380 } 381 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 382 continue; 383 384 /* Shortcut in case we've been shutdown */ 385 if (chp->ch_flags & ATACH_SHUTDOWN) 386 return; 387 388 /* 389 * Issue an identify, to try to detect ghosts. 390 * Note that we can't use interrupts here, because if there 391 * is no devices, we will get a command aborted without 392 * interrupts. 393 */ 394 error = ata_get_params(&chp->ch_drive[i], 395 AT_WAIT | AT_POLL, ¶ms); 396 if (error != CMD_OK) { 397 ata_channel_lock(chp); 398 ata_delay(chp, 1000, "atacnf", AT_WAIT); 399 ata_channel_unlock(chp); 400 401 /* Shortcut in case we've been shutdown */ 402 if (chp->ch_flags & ATACH_SHUTDOWN) 403 return; 404 405 error = ata_get_params(&chp->ch_drive[i], 406 AT_WAIT | AT_POLL, ¶ms); 407 } 408 if (error != CMD_OK) { 409 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 410 device_xname(atac->atac_dev), 411 chp->ch_channel, i, error), DEBUG_PROBE); 412 ata_channel_lock(chp); 413 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 414 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 415 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 416 ata_channel_unlock(chp); 417 continue; 418 } 419 /* 420 * Pre-ATA drive ? 421 * Test registers writability (Error register not 422 * writable, but cyllo is), then try an ATA command. 423 */ 424 if (wdc->select) 425 wdc->select(chp,i); 426 bus_space_write_1(wdr->cmd_iot, 427 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 428 delay(10); /* 400ns delay */ 429 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 430 0, 0x58); 431 bus_space_write_1(wdr->cmd_iot, 432 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 433 if (bus_space_read_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_error], 0) == 0x58 || 435 bus_space_read_1(wdr->cmd_iot, 436 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 437 ATADEBUG_PRINT(("%s:%d:%d: register " 438 "writability failed\n", 439 device_xname(atac->atac_dev), 440 chp->ch_channel, i), DEBUG_PROBE); 441 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 442 ata_channel_unlock(chp); 443 continue; 444 } 445 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 446 WDCWAIT_TOUT) { 447 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 448 device_xname(atac->atac_dev), 449 chp->ch_channel, i), DEBUG_PROBE); 450 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 451 ata_channel_unlock(chp); 452 continue; 453 } 454 bus_space_write_1(wdr->cmd_iot, 455 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 456 delay(10); /* 400ns delay */ 457 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 458 WDCWAIT_TOUT) { 459 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 460 device_xname(atac->atac_dev), 461 chp->ch_channel, i), DEBUG_PROBE); 462 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 463 ata_channel_unlock(chp); 464 } else { 465 for (j = 0; j < chp->ch_ndrives; j++) { 466 if (chp->ch_drive[i].drive_type != 467 ATA_DRIVET_NONE) { 468 chp->ch_drive[j].drive_type = 469 ATA_DRIVET_OLD; 470 } 471 } 472 ata_channel_unlock(chp); 473 } 474 } 475 } 476 } 477 478 int 479 wdcprobe(struct wdc_regs *wdr) 480 { 481 482 return wdcprobe_with_reset(wdr, NULL); 483 } 484 485 int 486 wdcprobe_with_reset(struct wdc_regs *wdr, 487 void (*do_reset)(struct ata_channel *, int)) 488 { 489 struct wdc_softc wdc; 490 struct ata_channel ch; 491 int rv; 492 493 memset(&wdc, 0, sizeof(wdc)); 494 memset(&ch, 0, sizeof(ch)); 495 ata_channel_init(&ch); 496 ch.ch_atac = &wdc.sc_atac; 497 wdc.regs = wdr; 498 499 /* check the MD reset method */ 500 wdc.reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 501 502 ata_channel_lock(&ch); 503 rv = wdcprobe1(&ch, 1); 504 ata_channel_unlock(&ch); 505 506 ata_channel_destroy(&ch); 507 508 return rv; 509 } 510 511 static int 512 wdcprobe1(struct ata_channel *chp, int poll) 513 { 514 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 515 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 516 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 517 u_int8_t ret_value = 0x03; 518 u_int8_t drive; 519 /* XXX if poll, wdc_probe_count is 0. */ 520 int wdc_probe_count = 521 poll ? (WDC_PROBE_WAIT / WDCDELAY) 522 : (WDC_PROBE_WAIT * hz); 523 524 /* 525 * Sanity check to see if the wdc channel responds at all. 526 */ 527 528 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 529 while (wdc_probe_count-- > 0) { 530 if (wdc->select) 531 wdc->select(chp,0); 532 533 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 534 0, WDSD_IBM); 535 delay(10); /* 400ns delay */ 536 st0 = bus_space_read_1(wdr->cmd_iot, 537 wdr->cmd_iohs[wd_status], 0); 538 539 if (wdc->select) 540 wdc->select(chp,1); 541 542 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 543 0, WDSD_IBM | 0x10); 544 delay(10); /* 400ns delay */ 545 st1 = bus_space_read_1(wdr->cmd_iot, 546 wdr->cmd_iohs[wd_status], 0); 547 if ((st0 & WDCS_BSY) == 0) 548 break; 549 } 550 551 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 552 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 553 554 if (st0 == 0xff || st0 == WDSD_IBM) 555 ret_value &= ~0x01; 556 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 557 ret_value &= ~0x02; 558 /* Register writability test, drive 0. */ 559 if (ret_value & 0x01) { 560 if (wdc->select) 561 wdc->select(chp,0); 562 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 563 0, WDSD_IBM); 564 bus_space_write_1(wdr->cmd_iot, 565 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 566 cl = bus_space_read_1(wdr->cmd_iot, 567 wdr->cmd_iohs[wd_cyl_lo], 0); 568 if (cl != 0x02) { 569 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 570 "got 0x%x != 0x02\n", 571 __func__, chp->ch_channel, cl), 572 DEBUG_PROBE); 573 ret_value &= ~0x01; 574 } 575 bus_space_write_1(wdr->cmd_iot, 576 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 577 cl = bus_space_read_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_cyl_lo], 0); 579 if (cl != 0x01) { 580 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 581 "got 0x%x != 0x01\n", 582 __func__, chp->ch_channel, cl), 583 DEBUG_PROBE); 584 ret_value &= ~0x01; 585 } 586 bus_space_write_1(wdr->cmd_iot, 587 wdr->cmd_iohs[wd_sector], 0, 0x01); 588 cl = bus_space_read_1(wdr->cmd_iot, 589 wdr->cmd_iohs[wd_sector], 0); 590 if (cl != 0x01) { 591 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 592 "got 0x%x != 0x01\n", 593 __func__, chp->ch_channel, cl), 594 DEBUG_PROBE); 595 ret_value &= ~0x01; 596 } 597 bus_space_write_1(wdr->cmd_iot, 598 wdr->cmd_iohs[wd_sector], 0, 0x02); 599 cl = bus_space_read_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_sector], 0); 601 if (cl != 0x02) { 602 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 603 "got 0x%x != 0x02\n", 604 __func__, chp->ch_channel, cl), 605 DEBUG_PROBE); 606 ret_value &= ~0x01; 607 } 608 cl = bus_space_read_1(wdr->cmd_iot, 609 wdr->cmd_iohs[wd_cyl_lo], 0); 610 if (cl != 0x01) { 611 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 612 "got 0x%x != 0x01\n", 613 __func__, chp->ch_channel, cl), 614 DEBUG_PROBE); 615 ret_value &= ~0x01; 616 } 617 } 618 /* Register writability test, drive 1. */ 619 if (ret_value & 0x02) { 620 if (wdc->select) 621 wdc->select(chp,1); 622 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 623 0, WDSD_IBM | 0x10); 624 bus_space_write_1(wdr->cmd_iot, 625 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 626 cl = bus_space_read_1(wdr->cmd_iot, 627 wdr->cmd_iohs[wd_cyl_lo], 0); 628 if (cl != 0x02) { 629 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 630 "got 0x%x != 0x02\n", 631 __func__, chp->ch_channel, cl), 632 DEBUG_PROBE); 633 ret_value &= ~0x02; 634 } 635 bus_space_write_1(wdr->cmd_iot, 636 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 637 cl = bus_space_read_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_cyl_lo], 0); 639 if (cl != 0x01) { 640 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 641 "got 0x%x != 0x01\n", 642 __func__, chp->ch_channel, cl), 643 DEBUG_PROBE); 644 ret_value &= ~0x02; 645 } 646 bus_space_write_1(wdr->cmd_iot, 647 wdr->cmd_iohs[wd_sector], 0, 0x01); 648 cl = bus_space_read_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0); 650 if (cl != 0x01) { 651 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 652 "got 0x%x != 0x01\n", 653 __func__, chp->ch_channel, cl), 654 DEBUG_PROBE); 655 ret_value &= ~0x02; 656 } 657 bus_space_write_1(wdr->cmd_iot, 658 wdr->cmd_iohs[wd_sector], 0, 0x02); 659 cl = bus_space_read_1(wdr->cmd_iot, 660 wdr->cmd_iohs[wd_sector], 0); 661 if (cl != 0x02) { 662 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 663 "got 0x%x != 0x02\n", 664 __func__, chp->ch_channel, cl), 665 DEBUG_PROBE); 666 ret_value &= ~0x02; 667 } 668 cl = bus_space_read_1(wdr->cmd_iot, 669 wdr->cmd_iohs[wd_cyl_lo], 0); 670 if (cl != 0x01) { 671 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 672 "got 0x%x != 0x01\n", 673 __func__, chp->ch_channel, cl), 674 DEBUG_PROBE); 675 ret_value &= ~0x02; 676 } 677 } 678 679 if (ret_value == 0) { 680 return 0; 681 } 682 } 683 684 #if 0 /* XXX this break some ATA or ATAPI devices */ 685 /* 686 * reset bus. Also send an ATAPI_RESET to devices, in case there are 687 * ATAPI device out there which don't react to the bus reset 688 */ 689 if (ret_value & 0x01) { 690 if (wdc->select) 691 wdc->select(chp,0); 692 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 693 0, WDSD_IBM); 694 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 695 ATAPI_SOFT_RESET); 696 } 697 if (ret_value & 0x02) { 698 if (wdc->select) 699 wdc->select(chp,0); 700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 701 0, WDSD_IBM | 0x10); 702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 703 ATAPI_SOFT_RESET); 704 } 705 706 delay(5000); 707 #endif 708 709 wdc->reset(chp, RESET_POLL); 710 DELAY(2000); 711 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 712 713 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 714 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 715 WDCTL_4BIT); 716 717 #ifdef WDC_NO_IDS 718 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 719 #else 720 ret_value = __wdcwait_reset(chp, ret_value, poll); 721 #endif 722 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 723 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 724 725 /* if reset failed, there's nothing here */ 726 if (ret_value == 0) { 727 return 0; 728 } 729 730 /* 731 * Test presence of drives. First test register signatures looking 732 * for ATAPI devices. If it's not an ATAPI and reset said there may 733 * be something here assume it's ATA or OLD. Ghost will be killed 734 * later in attach routine. 735 */ 736 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 737 if ((ret_value & (0x01 << drive)) == 0) 738 continue; 739 if (wdc->select) 740 wdc->select(chp,drive); 741 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 742 WDSD_IBM | (drive << 4)); 743 delay(10); /* 400ns delay */ 744 /* Save registers contents */ 745 sc = bus_space_read_1(wdr->cmd_iot, 746 wdr->cmd_iohs[wd_seccnt], 0); 747 sn = bus_space_read_1(wdr->cmd_iot, 748 wdr->cmd_iohs[wd_sector], 0); 749 cl = bus_space_read_1(wdr->cmd_iot, 750 wdr->cmd_iohs[wd_cyl_lo], 0); 751 ch = bus_space_read_1(wdr->cmd_iot, 752 wdr->cmd_iohs[wd_cyl_hi], 0); 753 754 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 755 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 756 sn, cl, ch), DEBUG_PROBE); 757 /* 758 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 759 * we get wrong values here, so ignore it. 760 */ 761 if (chp->ch_drive != NULL) { 762 if (cl == 0x14 && ch == 0xeb) { 763 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 764 } else { 765 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 766 } 767 } 768 } 769 /* 770 * Select an existing drive before lowering spl, some WDC_NO_IDS 771 * devices incorrectly assert IRQ on nonexistent slave 772 */ 773 if (ret_value & 0x01) { 774 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 775 WDSD_IBM); 776 (void)bus_space_read_1(wdr->cmd_iot, 777 wdr->cmd_iohs[wd_status], 0); 778 } 779 return (ret_value); 780 } 781 782 void 783 wdcattach(struct ata_channel *chp) 784 { 785 struct atac_softc *atac = chp->ch_atac; 786 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 787 788 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 789 790 /* default data transfer methods */ 791 if (wdc->datain_pio == NULL) 792 wdc->datain_pio = wdc_datain_pio; 793 if (wdc->dataout_pio == NULL) 794 wdc->dataout_pio = wdc_dataout_pio; 795 /* default reset method */ 796 if (wdc->reset == NULL) 797 wdc->reset = wdc_do_reset; 798 799 /* initialise global data */ 800 if (atac->atac_bustype_ata == NULL) 801 atac->atac_bustype_ata = &wdc_ata_bustype; 802 if (atac->atac_probe == NULL) 803 atac->atac_probe = wdc_drvprobe; 804 #if NATAPIBUS > 0 805 if (atac->atac_atapibus_attach == NULL) 806 atac->atac_atapibus_attach = wdc_atapibus_attach; 807 #endif 808 809 ata_channel_attach(chp); 810 } 811 812 void 813 wdc_childdetached(device_t self, device_t child) 814 { 815 struct atac_softc *atac = device_private(self); 816 struct ata_channel *chp; 817 int i; 818 819 for (i = 0; i < atac->atac_nchannels; i++) { 820 chp = atac->atac_channels[i]; 821 if (child == chp->atabus) { 822 chp->atabus = NULL; 823 return; 824 } 825 } 826 } 827 828 int 829 wdcdetach(device_t self, int flags) 830 { 831 struct atac_softc *atac = device_private(self); 832 struct ata_channel *chp; 833 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 834 int i, error = 0; 835 836 for (i = 0; i < atac->atac_nchannels; i++) { 837 chp = atac->atac_channels[i]; 838 if (chp->atabus == NULL) 839 continue; 840 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 841 device_xname(atac->atac_dev), device_xname(chp->atabus)), 842 DEBUG_DETACH); 843 if ((error = config_detach(chp->atabus, flags)) != 0) 844 return error; 845 ata_channel_detach(chp); 846 } 847 if (adapt->adapt_refcnt != 0) 848 return EBUSY; 849 return 0; 850 } 851 852 /* restart an interrupted I/O */ 853 void 854 wdcrestart(void *v) 855 { 856 struct ata_channel *chp = v; 857 int s; 858 859 s = splbio(); 860 atastart(chp); 861 splx(s); 862 } 863 864 865 /* 866 * Interrupt routine for the controller. Acknowledge the interrupt, check for 867 * errors on the current operation, mark it done if necessary, and start the 868 * next request. Also check for a partially done transfer, and continue with 869 * the next chunk if so. 870 */ 871 int 872 wdcintr(void *arg) 873 { 874 struct ata_channel *chp = arg; 875 struct atac_softc *atac = chp->ch_atac; 876 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 877 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 878 struct ata_xfer *xfer; 879 int ret; 880 881 if (!device_is_active(atac->atac_dev)) { 882 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 883 DEBUG_INTR); 884 return (0); 885 } 886 887 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 888 ATADEBUG_PRINT(("wdcintr: irq not expected\n"), DEBUG_INTR); 889 goto ignore; 890 } 891 892 xfer = ata_queue_get_active_xfer(chp); 893 if (xfer == NULL) { 894 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 895 ignore: 896 /* try to clear the pending interrupt anyway */ 897 (void)bus_space_read_1(wdr->cmd_iot, 898 wdr->cmd_iohs[wd_status], 0); 899 return (0); 900 } 901 902 /* 903 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 904 * actually has no effect, and interrupt is triggered regardless. 905 * Ignore polled commands here, they are processed separately. 906 */ 907 if (ISSET(xfer->c_flags, C_POLL)) { 908 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 909 DEBUG_INTR); 910 goto ignore; 911 } 912 913 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 914 KASSERT(xfer != NULL); 915 916 #if NATA_DMA || NATA_PIOBM 917 if (chp->ch_flags & ATACH_DMA_WAIT) { 918 wdc->dma_status = 919 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 920 xfer->c_drive, WDC_DMAEND_END); 921 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 922 /* IRQ not for us, not detected by DMA engine */ 923 return 0; 924 } 925 chp->ch_flags &= ~ATACH_DMA_WAIT; 926 } 927 #endif 928 chp->ch_flags &= ~ATACH_IRQ_WAIT; 929 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 930 ret = xfer->ops->c_intr(chp, xfer, 1); 931 if (ret == 0) /* irq was not for us, still waiting for irq */ 932 chp->ch_flags |= ATACH_IRQ_WAIT; 933 return (ret); 934 } 935 936 /* Put all disk in RESET state */ 937 void 938 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 939 { 940 struct ata_channel *chp = drvp->chnl_softc; 941 942 ata_channel_lock_owned(chp); 943 944 KASSERT(sigp == NULL); 945 946 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 947 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 948 drvp->drive), DEBUG_FUNCS); 949 950 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 951 } 952 953 void 954 wdc_reset_channel(struct ata_channel *chp, int flags) 955 { 956 struct ata_xfer *xfer; 957 958 ata_channel_lock_owned(chp); 959 960 #if NATA_DMA || NATA_PIOBM 961 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 962 #endif 963 964 chp->ch_flags &= ~ATACH_IRQ_WAIT; 965 966 /* 967 * if the current command is on an ATAPI device, issue a 968 * ATAPI_SOFT_RESET 969 */ 970 xfer = ata_queue_get_active_xfer_locked(chp); 971 972 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 973 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 974 ata_delay(chp, 1000, "atardl", flags); 975 } 976 977 /* reset the channel */ 978 if (flags & AT_WAIT) 979 (void) wdcreset(chp, RESET_SLEEP); 980 else 981 (void) wdcreset(chp, RESET_POLL); 982 983 /* 984 * wait a bit after reset; in case the DMA engines needs some time 985 * to recover. 986 */ 987 ata_delay(chp, 1000, "atardl", flags); 988 989 /* 990 * Look for pending xfers. If we have a shared queue, we'll also reset 991 * the other channel if the current xfer is running on it. 992 * Then we'll kill the eventual active transfer explicitely, so that 993 * it is queued for retry immediatelly without waiting for I/O timeout. 994 */ 995 if (xfer) { 996 if (xfer->c_chp != chp) { 997 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 998 ATACH_NODRIVE); 999 } else { 1000 #if NATA_DMA || NATA_PIOBM 1001 /* 1002 * If we're waiting for DMA, stop the 1003 * DMA engine 1004 */ 1005 if (chp->ch_flags & ATACH_DMA_WAIT) { 1006 (*wdc->dma_finish)(wdc->dma_arg, 1007 chp->ch_channel, xfer->c_drive, 1008 WDC_DMAEND_ABRT_QUIET); 1009 chp->ch_flags &= ~ATACH_DMA_WAIT; 1010 } 1011 #endif 1012 } 1013 } 1014 1015 ata_kill_active(chp, KILL_RESET, flags); 1016 } 1017 1018 static int 1019 wdcreset(struct ata_channel *chp, int poll) 1020 { 1021 struct atac_softc *atac = chp->ch_atac; 1022 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1023 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1024 int drv_mask1, drv_mask2; 1025 1026 ata_channel_lock_owned(chp); 1027 1028 #ifdef WDC_NO_IDS 1029 poll = RESET_POLL; 1030 #endif 1031 wdc->reset(chp, poll); 1032 1033 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1034 ? 0x01 : 0x00; 1035 if (chp->ch_ndrives > 1) 1036 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1037 ? 0x02 : 0x00; 1038 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1039 (poll == RESET_SLEEP) ? 0 : 1); 1040 if (drv_mask2 != drv_mask1) { 1041 aprint_error("%s channel %d: reset failed for", 1042 device_xname(atac->atac_dev), chp->ch_channel); 1043 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1044 aprint_normal(" drive 0"); 1045 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1046 aprint_normal(" drive 1"); 1047 aprint_normal("\n"); 1048 } 1049 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1050 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1051 WDCTL_4BIT); 1052 1053 return (drv_mask1 != drv_mask2) ? 1 : 0; 1054 } 1055 1056 void 1057 wdc_do_reset(struct ata_channel *chp, int poll) 1058 { 1059 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1060 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1061 int s = 0; 1062 1063 if (poll != RESET_SLEEP) 1064 s = splbio(); 1065 if (wdc->select) 1066 wdc->select(chp,0); 1067 /* master */ 1068 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1069 delay(10); /* 400ns delay */ 1070 /* assert SRST, wait for reset to complete */ 1071 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1072 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1073 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1074 delay(2000); 1075 } 1076 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1077 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1078 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1079 WDCTL_4BIT | WDCTL_IDS); 1080 delay(10); /* 400ns delay */ 1081 if (poll != RESET_SLEEP) { 1082 /* ACK interrupt in case there is one pending left */ 1083 if (wdc->irqack) 1084 wdc->irqack(chp); 1085 splx(s); 1086 } 1087 } 1088 1089 static int 1090 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1091 { 1092 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1093 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1094 int timeout, nloop; 1095 int wflags = poll ? AT_POLL : AT_WAIT; 1096 u_int8_t st0 = 0, st1 = 0; 1097 #ifdef ATADEBUG 1098 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1099 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1100 #endif 1101 if (poll) 1102 nloop = WDCNDELAY_RST; 1103 else 1104 nloop = WDC_RESET_WAIT * hz / 1000; 1105 /* wait for BSY to deassert */ 1106 for (timeout = 0; timeout < nloop; timeout++) { 1107 if ((drv_mask & 0x01) != 0) { 1108 if (wdc->select) 1109 wdc->select(chp,0); 1110 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1111 0, WDSD_IBM); /* master */ 1112 delay(10); 1113 st0 = bus_space_read_1(wdr->cmd_iot, 1114 wdr->cmd_iohs[wd_status], 0); 1115 #ifdef ATADEBUG 1116 sc0 = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_seccnt], 0); 1118 sn0 = bus_space_read_1(wdr->cmd_iot, 1119 wdr->cmd_iohs[wd_sector], 0); 1120 cl0 = bus_space_read_1(wdr->cmd_iot, 1121 wdr->cmd_iohs[wd_cyl_lo], 0); 1122 ch0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_cyl_hi], 0); 1124 #endif 1125 } 1126 if ((drv_mask & 0x02) != 0) { 1127 if (wdc->select) 1128 wdc->select(chp,1); 1129 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1130 0, WDSD_IBM | 0x10); /* slave */ 1131 delay(10); 1132 st1 = bus_space_read_1(wdr->cmd_iot, 1133 wdr->cmd_iohs[wd_status], 0); 1134 #ifdef ATADEBUG 1135 sc1 = bus_space_read_1(wdr->cmd_iot, 1136 wdr->cmd_iohs[wd_seccnt], 0); 1137 sn1 = bus_space_read_1(wdr->cmd_iot, 1138 wdr->cmd_iohs[wd_sector], 0); 1139 cl1 = bus_space_read_1(wdr->cmd_iot, 1140 wdr->cmd_iohs[wd_cyl_lo], 0); 1141 ch1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_cyl_hi], 0); 1143 #endif 1144 } 1145 1146 if ((drv_mask & 0x01) == 0) { 1147 /* no master */ 1148 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1149 /* No master, slave is ready, it's done */ 1150 goto end; 1151 } 1152 if ((drv_mask & 0x02) == 0) { 1153 /* No master, no slave: it's done */ 1154 goto end; 1155 } 1156 } else if ((drv_mask & 0x02) == 0) { 1157 /* no slave */ 1158 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1159 /* No slave, master is ready, it's done */ 1160 goto end; 1161 } 1162 } else { 1163 /* Wait for both master and slave to be ready */ 1164 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1165 goto end; 1166 } 1167 } 1168 ata_delay(chp, WDCDELAY, "atarst", wflags); 1169 } 1170 /* Reset timed out. Maybe it's because drv_mask was not right */ 1171 if (st0 & WDCS_BSY) 1172 drv_mask &= ~0x01; 1173 if (st1 & WDCS_BSY) 1174 drv_mask &= ~0x02; 1175 end: 1176 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1177 "cl=0x%x ch=0x%x\n", 1178 device_xname(chp->ch_atac->atac_dev), 1179 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1180 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1181 "cl=0x%x ch=0x%x\n", 1182 device_xname(chp->ch_atac->atac_dev), 1183 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1184 1185 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1186 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1187 st0, st1), DEBUG_PROBE); 1188 1189 return drv_mask; 1190 } 1191 1192 /* 1193 * Wait for a drive to be !BSY, and have mask in its status register. 1194 * return -1 for a timeout after "timeout" ms. 1195 */ 1196 static int 1197 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1198 { 1199 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1200 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1201 u_char status, error = 0; 1202 int xtime = 0; 1203 int rv; 1204 1205 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1206 device_xname(chp->ch_atac->atac_dev), 1207 chp->ch_channel), DEBUG_STATUS); 1208 *tfd = 0; 1209 1210 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1211 1212 for (;;) { 1213 status = 1214 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1215 if ((status & (WDCS_BSY | mask)) == bits) 1216 break; 1217 if (++xtime > timeout) { 1218 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1219 "status %x error %x (mask 0x%x bits 0x%x)\n", 1220 xtime, status, 1221 bus_space_read_1(wdr->cmd_iot, 1222 wdr->cmd_iohs[wd_error], 0), mask, bits), 1223 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1224 rv = WDCWAIT_TOUT; 1225 goto out; 1226 } 1227 delay(WDCDELAY); 1228 } 1229 #ifdef ATADEBUG 1230 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1231 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1232 #endif 1233 if (status & WDCS_ERR) 1234 error = bus_space_read_1(wdr->cmd_iot, 1235 wdr->cmd_iohs[wd_error], 0); 1236 #ifdef WDCNDELAY_DEBUG 1237 /* After autoconfig, there should be no long delays. */ 1238 if (!cold && xtime > WDCNDELAY_DEBUG) { 1239 struct ata_xfer *xfer; 1240 1241 xfer = ata_queue_get_active_xfer(chp); 1242 if (xfer == NULL) 1243 printf("%s channel %d: warning: busy-wait took %dus\n", 1244 device_xname(chp->ch_atac->atac_dev), 1245 chp->ch_channel, WDCDELAY * xtime); 1246 else 1247 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1248 device_xname(chp->ch_atac->atac_dev), 1249 chp->ch_channel, xfer->c_drive, 1250 WDCDELAY * xtime); 1251 } 1252 #endif 1253 rv = WDCWAIT_OK; 1254 1255 out: 1256 *tfd = ATACH_ERR_ST(error, status); 1257 return rv; 1258 } 1259 1260 /* 1261 * Call __wdcwait(), polling using kpause() or waking up the kernel 1262 * thread if possible 1263 */ 1264 int 1265 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1266 int *tfd) 1267 { 1268 int error, i, timeout_hz = mstohz(timeout); 1269 1270 ata_channel_lock_owned(chp); 1271 1272 if (timeout_hz == 0 || 1273 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1274 error = __wdcwait(chp, mask, bits, timeout, tfd); 1275 else { 1276 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1277 if (error != 0) { 1278 if ((chp->ch_flags & ATACH_TH_RUN) || 1279 (flags & AT_WAIT)) { 1280 /* 1281 * we're running in the channel thread 1282 * or some userland thread context 1283 */ 1284 for (i = 0; i < timeout_hz; i++) { 1285 if (__wdcwait(chp, mask, bits, 1286 WDCDELAY_POLL, tfd) == 0) { 1287 error = 0; 1288 break; 1289 } 1290 kpause("atapoll", true, 1, 1291 &chp->ch_lock); 1292 } 1293 } else { 1294 /* 1295 * we're probably in interrupt context, 1296 * caller must ask the thread to come back here 1297 */ 1298 return(WDCWAIT_THR); 1299 } 1300 } 1301 } 1302 return (error); 1303 } 1304 1305 1306 #if NATA_DMA 1307 /* 1308 * Busy-wait for DMA to complete 1309 */ 1310 int 1311 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1312 { 1313 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1314 int xtime; 1315 1316 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1317 wdc->dma_status = 1318 (*wdc->dma_finish)(wdc->dma_arg, 1319 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1320 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1321 return 0; 1322 delay(WDCDELAY); 1323 } 1324 /* timeout, force a DMA halt */ 1325 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1326 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1327 return 1; 1328 } 1329 #endif 1330 1331 void 1332 wdctimeout(void *arg) 1333 { 1334 struct ata_xfer *xfer; 1335 struct ata_channel *chp = arg; 1336 #if NATA_DMA || NATA_PIOBM 1337 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1338 #endif 1339 int s; 1340 1341 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1342 1343 s = splbio(); 1344 1345 callout_ack(&chp->c_timo_callout); 1346 1347 xfer = ata_queue_get_active_xfer(chp); 1348 KASSERT(xfer != NULL); 1349 1350 if (ata_timo_xfer_check(xfer)) { 1351 /* Already logged */ 1352 goto out; 1353 } 1354 1355 __wdcerror(chp, "lost interrupt"); 1356 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1357 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1358 xfer->c_bcount, xfer->c_skip); 1359 #if NATA_DMA || NATA_PIOBM 1360 if (chp->ch_flags & ATACH_DMA_WAIT) { 1361 wdc->dma_status = 1362 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1363 xfer->c_drive, WDC_DMAEND_ABRT); 1364 chp->ch_flags &= ~ATACH_DMA_WAIT; 1365 } 1366 #endif 1367 /* 1368 * Call the interrupt routine. If we just missed an interrupt, 1369 * it will do what's needed. Else, it will take the needed 1370 * action (reset the device). 1371 * Before that we need to reinstall the timeout callback, 1372 * in case it will miss another irq while in this transfer 1373 * We arbitray chose it to be 1s 1374 */ 1375 callout_reset(&chp->c_timo_callout, hz, wdctimeout, chp); 1376 xfer->c_flags |= C_TIMEOU; 1377 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1378 xfer->ops->c_intr(chp, xfer, 1); 1379 1380 out: 1381 splx(s); 1382 } 1383 1384 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1385 .c_start = __wdccommand_start, 1386 .c_poll = __wdccommand_poll, 1387 .c_abort = __wdccommand_done, 1388 .c_intr = __wdccommand_intr, 1389 .c_kill_xfer = __wdccommand_kill_xfer, 1390 }; 1391 1392 int 1393 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1394 { 1395 struct ata_channel *chp = drvp->chnl_softc; 1396 struct ata_command *ata_c = &xfer->c_ata_c; 1397 int s, ret; 1398 1399 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1400 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1401 drvp->drive), DEBUG_FUNCS); 1402 1403 /* set up an xfer and queue. Wait for completion */ 1404 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1405 ata_c->flags |= AT_POLL; 1406 if (ata_c->flags & AT_POLL) 1407 xfer->c_flags |= C_POLL; 1408 if (ata_c->flags & AT_WAIT) 1409 xfer->c_flags |= C_WAIT; 1410 xfer->c_drive = drvp->drive; 1411 xfer->c_databuf = ata_c->data; 1412 xfer->c_bcount = ata_c->bcount; 1413 xfer->ops = &wdc_cmd_xfer_ops; 1414 1415 s = splbio(); 1416 ata_exec_xfer(chp, xfer); 1417 #ifdef DIAGNOSTIC 1418 if ((ata_c->flags & AT_POLL) != 0 && 1419 (ata_c->flags & AT_DONE) == 0) 1420 panic("wdc_exec_command: polled command not done"); 1421 #endif 1422 if (ata_c->flags & AT_DONE) { 1423 ret = ATACMD_COMPLETE; 1424 } else { 1425 if (ata_c->flags & AT_WAIT) { 1426 ata_wait_cmd(chp, xfer); 1427 ret = ATACMD_COMPLETE; 1428 } else { 1429 ret = ATACMD_QUEUED; 1430 } 1431 } 1432 splx(s); 1433 return ret; 1434 } 1435 1436 static int 1437 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1438 { 1439 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1440 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1441 int drive = xfer->c_drive; 1442 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1443 struct ata_command *ata_c = &xfer->c_ata_c; 1444 int tfd; 1445 1446 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1447 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1448 xfer->c_drive), DEBUG_FUNCS); 1449 1450 if (wdc->select) 1451 wdc->select(chp,drive); 1452 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1453 WDSD_IBM | (drive << 4)); 1454 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1455 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1456 case WDCWAIT_OK: 1457 break; 1458 case WDCWAIT_TOUT: 1459 ata_c->flags |= AT_TIMEOU; 1460 return ATASTART_ABORT; 1461 case WDCWAIT_THR: 1462 return ATASTART_TH; 1463 } 1464 if (ata_c->flags & AT_POLL) { 1465 /* polled command, disable interrupts */ 1466 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1467 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1468 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1469 } 1470 if ((ata_c->flags & AT_LBA48) != 0) { 1471 wdccommandext(chp, drive, ata_c->r_command, 1472 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1473 ata_c->r_device & ~0x10); 1474 } else { 1475 wdccommand(chp, drive, ata_c->r_command, 1476 (ata_c->r_lba >> 8) & 0xffff, 1477 WDSD_IBM | (drive << 4) | 1478 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1479 ((ata_c->r_lba >> 24) & 0x0f), 1480 ata_c->r_lba & 0xff, 1481 ata_c->r_count & 0xff, 1482 ata_c->r_features & 0xff); 1483 } 1484 1485 if ((ata_c->flags & AT_POLL) == 0) { 1486 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1487 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1488 wdctimeout, chp); 1489 return ATASTART_STARTED; 1490 } 1491 1492 /* 1493 * Polled command. Wait for drive ready or drq. Done in intr(). 1494 * Wait for at last 400ns for status bit to be valid. 1495 */ 1496 delay(10); /* 400ns delay */ 1497 return ATASTART_POLL; 1498 } 1499 1500 static void 1501 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1502 { 1503 __wdccommand_intr(chp, xfer, 0); 1504 } 1505 1506 static int 1507 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1508 { 1509 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1510 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1511 struct ata_command *ata_c = &xfer->c_ata_c; 1512 int bcount = ata_c->bcount; 1513 char *data = ata_c->data; 1514 int wflags, tfd; 1515 int drive_flags; 1516 1517 if (ata_c->r_command == WDCC_IDENTIFY || 1518 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1519 /* 1520 * The IDENTIFY data has been designed as an array of 1521 * u_int16_t, so we can byteswap it on the fly. 1522 * Historically it's what we have always done so keeping it 1523 * here ensure binary backward compatibility. 1524 */ 1525 drive_flags = ATA_DRIVE_NOSTREAM | 1526 chp->ch_drive[xfer->c_drive].drive_flags; 1527 } else { 1528 /* 1529 * Other data structure are opaque and should be transfered 1530 * as is. 1531 */ 1532 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1533 } 1534 1535 #ifdef WDC_NO_IDS 1536 wflags = AT_POLL; 1537 #else 1538 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1539 /* both wait and poll, we can kpause here */ 1540 wflags = AT_WAIT | AT_POLL; 1541 } else { 1542 wflags = AT_POLL; 1543 } 1544 #endif 1545 1546 ata_channel_lock(chp); 1547 1548 again: 1549 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1550 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1551 xfer->c_drive), DEBUG_INTR); 1552 /* 1553 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1554 * Reselect again, it doesn't hurt for others commands, and the time 1555 * penalty for the extra register write is acceptable, 1556 * wdc_exec_command() isn't called often (mostly for autoconfig) 1557 */ 1558 if ((xfer->c_flags & C_ATAPI) != 0) { 1559 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1560 WDSD_IBM | (xfer->c_drive << 4)); 1561 } 1562 if ((ata_c->flags & AT_XFDONE) != 0) { 1563 /* 1564 * We have completed a data xfer. The drive should now be 1565 * in its initial state 1566 */ 1567 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1568 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1569 wflags, &tfd) == WDCWAIT_TOUT) { 1570 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1571 ata_channel_unlock(chp); 1572 return 0; /* IRQ was not for us */ 1573 } 1574 ata_c->flags |= AT_TIMEOU; 1575 } 1576 goto out; 1577 } 1578 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1579 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1580 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1581 ata_channel_unlock(chp); 1582 return 0; /* IRQ was not for us */ 1583 } 1584 ata_c->flags |= AT_TIMEOU; 1585 goto out; 1586 } 1587 if (wdc->irqack) 1588 wdc->irqack(chp); 1589 if (ata_c->flags & AT_READ) { 1590 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1591 ata_c->flags |= AT_TIMEOU; 1592 goto out; 1593 } 1594 wdc->datain_pio(chp, drive_flags, data, bcount); 1595 /* at this point the drive should be in its initial state */ 1596 ata_c->flags |= AT_XFDONE; 1597 /* 1598 * XXX checking the status register again here cause some 1599 * hardware to timeout. 1600 */ 1601 } else if (ata_c->flags & AT_WRITE) { 1602 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1603 ata_c->flags |= AT_TIMEOU; 1604 goto out; 1605 } 1606 wdc->dataout_pio(chp, drive_flags, data, bcount); 1607 ata_c->flags |= AT_XFDONE; 1608 if ((ata_c->flags & AT_POLL) == 0) { 1609 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1610 callout_reset(&chp->c_timo_callout, 1611 mstohz(ata_c->timeout), wdctimeout, chp); 1612 ata_channel_unlock(chp); 1613 return 1; 1614 } else { 1615 goto again; 1616 } 1617 } 1618 out: 1619 if (ATACH_ST(tfd) & WDCS_DWF) 1620 ata_c->flags |= AT_DF; 1621 if (ATACH_ST(tfd) & WDCS_ERR) { 1622 ata_c->flags |= AT_ERROR; 1623 ata_c->r_error = ATACH_ST(tfd); 1624 } 1625 1626 ata_channel_unlock(chp); 1627 1628 __wdccommand_done(chp, xfer); 1629 return 1; 1630 } 1631 1632 static void 1633 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1634 { 1635 struct atac_softc *atac = chp->ch_atac; 1636 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1637 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1638 struct ata_command *ata_c = &xfer->c_ata_c; 1639 bool start = true; 1640 1641 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1642 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1643 ata_c->flags), DEBUG_FUNCS); 1644 1645 if (ata_waitdrain_xfer_check(chp, xfer)) { 1646 start = false; 1647 goto out; 1648 } 1649 1650 if ((ata_c->flags & AT_READREG) != 0 && 1651 device_is_active(atac->atac_dev) && 1652 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1653 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1654 wdr->cmd_iohs[wd_status], 0); 1655 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1656 wdr->cmd_iohs[wd_error], 0); 1657 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1658 wdr->cmd_iohs[wd_seccnt], 0); 1659 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1660 wdr->cmd_iohs[wd_sector], 0) << 0; 1661 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1662 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1663 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1664 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1665 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1666 wdr->cmd_iohs[wd_sdh], 0); 1667 1668 if ((ata_c->flags & AT_LBA48) != 0) { 1669 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1670 if ((ata_c->flags & AT_POLL) != 0) 1671 bus_space_write_1(wdr->ctl_iot, 1672 wdr->ctl_ioh, wd_aux_ctlr, 1673 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1674 else 1675 bus_space_write_1(wdr->ctl_iot, 1676 wdr->ctl_ioh, wd_aux_ctlr, 1677 WDCTL_HOB|WDCTL_4BIT); 1678 } 1679 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1680 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1681 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1682 wdr->cmd_iohs[wd_sector], 0) << 24; 1683 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1684 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1685 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1686 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1687 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1688 if ((ata_c->flags & AT_POLL) != 0) 1689 bus_space_write_1(wdr->ctl_iot, 1690 wdr->ctl_ioh, wd_aux_ctlr, 1691 WDCTL_4BIT|WDCTL_IDS); 1692 else 1693 bus_space_write_1(wdr->ctl_iot, 1694 wdr->ctl_ioh, wd_aux_ctlr, 1695 WDCTL_4BIT); 1696 } 1697 } else { 1698 ata_c->r_lba |= 1699 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1700 } 1701 ata_c->r_device &= 0xf0; 1702 } 1703 1704 __wdccommand_done_end(chp, xfer); 1705 1706 ata_deactivate_xfer(chp, xfer); 1707 1708 out: 1709 if (ata_c->flags & AT_POLL) { 1710 /* enable interrupts */ 1711 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1712 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1713 wd_aux_ctlr, WDCTL_4BIT); 1714 delay(10); /* some drives need a little delay here */ 1715 } 1716 1717 if (start) 1718 atastart(chp); 1719 } 1720 1721 static void 1722 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1723 { 1724 struct ata_command *ata_c = &xfer->c_ata_c; 1725 1726 ata_c->flags |= AT_DONE; 1727 } 1728 1729 static void 1730 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1731 int reason) 1732 { 1733 struct ata_command *ata_c = &xfer->c_ata_c; 1734 bool deactivate = true; 1735 1736 switch (reason) { 1737 case KILL_GONE_INACTIVE: 1738 deactivate = false; 1739 /* FALLTHROUGH */ 1740 case KILL_GONE: 1741 ata_c->flags |= AT_GONE; 1742 break; 1743 case KILL_RESET: 1744 ata_c->flags |= AT_RESET; 1745 break; 1746 default: 1747 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1748 reason); 1749 panic("__wdccommand_kill_xfer"); 1750 } 1751 1752 __wdccommand_done_end(chp, xfer); 1753 1754 if (deactivate) 1755 ata_deactivate_xfer(chp, xfer); 1756 } 1757 1758 /* 1759 * Send a command. The drive should be ready. 1760 * Assumes interrupts are blocked. 1761 */ 1762 void 1763 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1764 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1765 u_int8_t features) 1766 { 1767 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1768 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1769 1770 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1771 "sector=%d count=%d features=%d\n", 1772 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1773 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1774 1775 if (wdc->select) 1776 wdc->select(chp,drive); 1777 1778 /* Select drive, head, and addressing mode. */ 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1780 WDSD_IBM | (drive << 4) | head); 1781 /* Load parameters into the wd_features register. */ 1782 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1783 features); 1784 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1785 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1786 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1787 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1788 0, cylin >> 8); 1789 1790 /* Send command. */ 1791 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1792 return; 1793 } 1794 1795 /* 1796 * Send a 48-bit addressing command. The drive should be ready. 1797 * Assumes interrupts are blocked. 1798 */ 1799 void 1800 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1801 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1802 { 1803 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1804 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1805 1806 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1807 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1808 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1809 chp->ch_channel, drive, command, blkno, count, features, device), 1810 DEBUG_FUNCS); 1811 1812 KASSERT(drive < wdc->wdc_maxdrives); 1813 1814 if (wdc->select) 1815 wdc->select(chp,drive); 1816 1817 /* Select drive, head, and addressing mode. */ 1818 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1819 (drive << 4) | device); 1820 1821 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1822 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1823 0, features); 1824 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1825 0, count); 1826 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1827 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1828 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1829 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1830 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1831 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1832 } else { 1833 /* previous */ 1834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1835 0, features >> 8); 1836 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1837 0, count >> 8); 1838 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1839 0, blkno >> 24); 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1841 0, blkno >> 32); 1842 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1843 0, blkno >> 40); 1844 1845 /* current */ 1846 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1847 0, features); 1848 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1849 0, count); 1850 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1851 0, blkno); 1852 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1853 0, blkno >> 8); 1854 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1855 0, blkno >> 16); 1856 } 1857 1858 /* Send command. */ 1859 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1860 return; 1861 } 1862 1863 /* 1864 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1865 * tested by the caller. 1866 */ 1867 void 1868 wdccommandshort(struct ata_channel *chp, int drive, int command) 1869 { 1870 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1871 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1872 1873 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1874 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1875 command), DEBUG_FUNCS); 1876 1877 if (wdc->select) 1878 wdc->select(chp,drive); 1879 1880 /* Select drive. */ 1881 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1882 WDSD_IBM | (drive << 4)); 1883 1884 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1885 } 1886 1887 static void 1888 __wdcerror(struct ata_channel *chp, const char *msg) 1889 { 1890 struct atac_softc *atac = chp->ch_atac; 1891 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1892 1893 if (xfer == NULL) 1894 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1895 chp->ch_channel, msg); 1896 else 1897 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1898 chp->ch_channel, xfer->c_drive, msg); 1899 } 1900 1901 /* 1902 * the bit bucket 1903 */ 1904 void 1905 wdcbit_bucket(struct ata_channel *chp, int size) 1906 { 1907 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1908 1909 for (; size >= 2; size -= 2) 1910 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1911 if (size) 1912 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1913 } 1914 1915 static void 1916 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1917 { 1918 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1919 1920 #ifndef __NO_STRICT_ALIGNMENT 1921 if ((uintptr_t)bf & 1) 1922 goto unaligned; 1923 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1924 goto unaligned; 1925 #endif 1926 1927 if (flags & ATA_DRIVE_NOSTREAM) { 1928 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1929 bus_space_read_multi_4(wdr->data32iot, 1930 wdr->data32ioh, 0, bf, len >> 2); 1931 bf = (char *)bf + (len & ~3); 1932 len &= 3; 1933 } 1934 if (len > 1) { 1935 bus_space_read_multi_2(wdr->cmd_iot, 1936 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1937 bf = (char *)bf + (len & ~1); 1938 len &= 1; 1939 } 1940 } else { 1941 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1942 bus_space_read_multi_stream_4(wdr->data32iot, 1943 wdr->data32ioh, 0, bf, len >> 2); 1944 bf = (char *)bf + (len & ~3); 1945 len &= 3; 1946 } 1947 if (len > 1) { 1948 bus_space_read_multi_stream_2(wdr->cmd_iot, 1949 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1950 bf = (char *)bf + (len & ~1); 1951 len &= 1; 1952 } 1953 } 1954 if (len) 1955 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1956 wdr->cmd_iohs[wd_data], 0); 1957 return; 1958 1959 #ifndef __NO_STRICT_ALIGNMENT 1960 unaligned: 1961 if (flags & ATA_DRIVE_NOSTREAM) { 1962 if (flags & ATA_DRIVE_CAP32) { 1963 while (len > 3) { 1964 uint32_t val; 1965 1966 val = bus_space_read_4(wdr->data32iot, 1967 wdr->data32ioh, 0); 1968 memcpy(bf, &val, 4); 1969 bf = (char *)bf + 4; 1970 len -= 4; 1971 } 1972 } 1973 while (len > 1) { 1974 uint16_t val; 1975 1976 val = bus_space_read_2(wdr->cmd_iot, 1977 wdr->cmd_iohs[wd_data], 0); 1978 memcpy(bf, &val, 2); 1979 bf = (char *)bf + 2; 1980 len -= 2; 1981 } 1982 } else { 1983 if (flags & ATA_DRIVE_CAP32) { 1984 while (len > 3) { 1985 uint32_t val; 1986 1987 val = bus_space_read_stream_4(wdr->data32iot, 1988 wdr->data32ioh, 0); 1989 memcpy(bf, &val, 4); 1990 bf = (char *)bf + 4; 1991 len -= 4; 1992 } 1993 } 1994 while (len > 1) { 1995 uint16_t val; 1996 1997 val = bus_space_read_stream_2(wdr->cmd_iot, 1998 wdr->cmd_iohs[wd_data], 0); 1999 memcpy(bf, &val, 2); 2000 bf = (char *)bf + 2; 2001 len -= 2; 2002 } 2003 } 2004 #endif 2005 } 2006 2007 static void 2008 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2009 { 2010 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2011 2012 #ifndef __NO_STRICT_ALIGNMENT 2013 if ((uintptr_t)bf & 1) 2014 goto unaligned; 2015 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2016 goto unaligned; 2017 #endif 2018 2019 if (flags & ATA_DRIVE_NOSTREAM) { 2020 if (flags & ATA_DRIVE_CAP32) { 2021 bus_space_write_multi_4(wdr->data32iot, 2022 wdr->data32ioh, 0, bf, len >> 2); 2023 bf = (char *)bf + (len & ~3); 2024 len &= 3; 2025 } 2026 if (len) { 2027 bus_space_write_multi_2(wdr->cmd_iot, 2028 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2029 } 2030 } else { 2031 if (flags & ATA_DRIVE_CAP32) { 2032 bus_space_write_multi_stream_4(wdr->data32iot, 2033 wdr->data32ioh, 0, bf, len >> 2); 2034 bf = (char *)bf + (len & ~3); 2035 len &= 3; 2036 } 2037 if (len) { 2038 bus_space_write_multi_stream_2(wdr->cmd_iot, 2039 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2040 } 2041 } 2042 return; 2043 2044 #ifndef __NO_STRICT_ALIGNMENT 2045 unaligned: 2046 if (flags & ATA_DRIVE_NOSTREAM) { 2047 if (flags & ATA_DRIVE_CAP32) { 2048 while (len > 3) { 2049 uint32_t val; 2050 2051 memcpy(&val, bf, 4); 2052 bus_space_write_4(wdr->data32iot, 2053 wdr->data32ioh, 0, val); 2054 bf = (char *)bf + 4; 2055 len -= 4; 2056 } 2057 } 2058 while (len > 1) { 2059 uint16_t val; 2060 2061 memcpy(&val, bf, 2); 2062 bus_space_write_2(wdr->cmd_iot, 2063 wdr->cmd_iohs[wd_data], 0, val); 2064 bf = (char *)bf + 2; 2065 len -= 2; 2066 } 2067 } else { 2068 if (flags & ATA_DRIVE_CAP32) { 2069 while (len > 3) { 2070 uint32_t val; 2071 2072 memcpy(&val, bf, 4); 2073 bus_space_write_stream_4(wdr->data32iot, 2074 wdr->data32ioh, 0, val); 2075 bf = (char *)bf + 4; 2076 len -= 4; 2077 } 2078 } 2079 while (len > 1) { 2080 uint16_t val; 2081 2082 memcpy(&val, bf, 2); 2083 bus_space_write_stream_2(wdr->cmd_iot, 2084 wdr->cmd_iohs[wd_data], 0, val); 2085 bf = (char *)bf + 2; 2086 len -= 2; 2087 } 2088 } 2089 #endif 2090 } 2091
Indexes created Fri Sep 26 20:09:58 GMT 2025