wdc.c revision 1.296
1 /* $NetBSD: wdc.c,v 1.296 2019/12/27 09:41:50 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.296 2019/12/27 09:41:50 msaitoh Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then kpause for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 .bustype_type = SCSIPI_BUSTYPE_ATA, 130 .ata_bio = NULL, 131 .ata_reset_drive = NULL, 132 .ata_reset_channel = wdc_reset_channel, 133 .ata_exec_command = wdc_exec_command, 134 .ata_get_params = NULL, 135 .ata_addref = NULL, 136 .ata_delref = NULL, 137 .ata_killpending = NULL, 138 .ata_recovery = NULL, 139 }; 140 #endif 141 142 /* Flags to wdcreset(). */ 143 #define RESET_POLL 1 144 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 145 146 static int wdcprobe1(struct ata_channel *, int); 147 static int wdcreset(struct ata_channel *, int); 148 static void __wdcerror(struct ata_channel *, const char *); 149 static int __wdcwait_reset(struct ata_channel *, int, int); 150 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_kill_xfer(struct ata_channel *, 154 struct ata_xfer *, int); 155 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 156 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 157 static int __wdcwait(struct ata_channel *, int, int, int, int *); 158 159 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 160 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 161 #define DEBUG_INTR 0x01 162 #define DEBUG_XFERS 0x02 163 #define DEBUG_STATUS 0x04 164 #define DEBUG_FUNCS 0x08 165 #define DEBUG_PROBE 0x10 166 #define DEBUG_DETACH 0x20 167 #define DEBUG_DELAY 0x40 168 #ifdef ATADEBUG 169 extern int atadebug_mask; /* init'ed in ata.c */ 170 int wdc_nxfer = 0; 171 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 172 #else 173 #define ATADEBUG_PRINT(args, level) 174 #endif 175 176 /* 177 * Initialize the "shadow register" handles for a standard wdc controller. 178 */ 179 void 180 wdc_init_shadow_regs(struct wdc_regs *wdr) 181 { 182 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 183 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 184 } 185 186 /* 187 * Allocate a wdc_regs array, based on the number of channels. 188 */ 189 void 190 wdc_allocate_regs(struct wdc_softc *wdc) 191 { 192 193 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 194 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 195 } 196 197 #if NSATA > 0 198 /* 199 * probe drives on SATA controllers with standard SATA registers: 200 * bring the PHYs online, read the drive signature and set drive flags 201 * appropriately. 202 */ 203 void 204 wdc_sataprobe(struct ata_channel *chp) 205 { 206 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 207 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 208 int i; 209 210 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 211 212 /* do this before we take lock */ 213 214 ata_channel_lock(chp); 215 216 /* reset the PHY and bring online */ 217 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 218 wdr->sata_status, AT_WAIT)) { 219 case SStatus_DET_DEV: 220 /* wait 5s for BSY to clear */ 221 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 222 bus_space_write_1(wdr->cmd_iot, 223 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 224 delay(10); /* 400ns delay */ 225 st = bus_space_read_1(wdr->cmd_iot, 226 wdr->cmd_iohs[wd_status], 0); 227 if ((st & WDCS_BSY) == 0) 228 break; 229 ata_delay(chp, 1, "sataprb", AT_WAIT); 230 } 231 if (i == WDC_PROBE_WAIT * hz) 232 aprint_error_dev(chp->ch_atac->atac_dev, 233 "BSY never cleared, status 0x%02x\n", st); 234 sc = bus_space_read_1(wdr->cmd_iot, 235 wdr->cmd_iohs[wd_seccnt], 0); 236 sn = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_sector], 0); 238 cl = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_cyl_lo], 0); 240 ch = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_hi], 0); 242 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 243 "cl=0x%x ch=0x%x\n", 244 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 245 sc, sn, cl, ch), DEBUG_PROBE); 246 if (atabus_alloc_drives(chp, 1) != 0) 247 return; 248 /* 249 * sc and sn are supposed to be 0x1 for ATAPI, but in some 250 * cases we get wrong values here, so ignore it. 251 */ 252 if (cl == 0x14 && ch == 0xeb) 253 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 254 else 255 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 256 257 /* 258 * issue a reset in case only the interface part of the drive 259 * is up 260 */ 261 if (wdcreset(chp, RESET_SLEEP) != 0) 262 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 263 break; 264 265 default: 266 break; 267 } 268 269 ata_channel_unlock(chp); 270 } 271 #endif /* NSATA > 0 */ 272 273 274 /* Test to see controller with at last one attached drive is there. 275 * Returns a bit for each possible drive found (0x01 for drive 0, 276 * 0x02 for drive 1). 277 * Logic: 278 * - If a status register is at 0xff, assume there is no drive here 279 * (ISA has pull-up resistors). Similarly if the status register has 280 * the value we last wrote to the bus (for IDE interfaces without pullups). 281 * If no drive at all -> return. 282 * - reset the controller, wait for it to complete (may take up to 31s !). 283 * If timeout -> return. 284 * - test ATA/ATAPI signatures. If at last one drive found -> return. 285 * - try an ATA command on the master. 286 */ 287 288 void 289 wdc_drvprobe(struct ata_channel *chp) 290 { 291 struct ataparams params; /* XXX: large struct */ 292 struct atac_softc *atac = chp->ch_atac; 293 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 294 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 295 u_int8_t st0 = 0, st1 = 0; 296 int i, j, error, tfd; 297 298 ata_channel_lock(chp); 299 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 300 ata_channel_unlock(chp); 301 return; 302 } 303 if (wdcprobe1(chp, 0) == 0) { 304 /* No drives, abort the attach here. */ 305 atabus_free_drives(chp); 306 ata_channel_unlock(chp); 307 return; 308 } 309 310 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 311 for (i = 0; i < mstohz(3000); i++) { 312 /* 313 * select drive 1 first, so that master is selected on 314 * exit from the loop 315 */ 316 if (chp->ch_ndrives > 1 && 317 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 318 if (wdc->select) 319 wdc->select(chp,1); 320 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 321 0, WDSD_IBM | 0x10); 322 delay(10); /* 400ns delay */ 323 st1 = bus_space_read_1(wdr->cmd_iot, 324 wdr->cmd_iohs[wd_status], 0); 325 } 326 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 327 if (wdc->select) 328 wdc->select(chp,0); 329 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 330 0, WDSD_IBM); 331 delay(10); /* 400ns delay */ 332 st0 = bus_space_read_1(wdr->cmd_iot, 333 wdr->cmd_iohs[wd_status], 0); 334 } 335 336 337 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 338 (st0 & WDCS_DRDY)) && 339 (chp->ch_ndrives < 2 || 340 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 341 (st1 & WDCS_DRDY))) 342 break; 343 #ifdef WDC_NO_IDS 344 /* cannot kpause here (can't enable IPL_BIO interrups), 345 * delay instead 346 */ 347 delay(1000000 / hz); 348 #else 349 ata_delay(chp, 1, "atadrdy", AT_WAIT); 350 #endif 351 } 352 if ((st0 & WDCS_DRDY) == 0 && 353 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 354 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 355 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 356 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 357 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 358 ata_channel_unlock(chp); 359 360 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 361 device_xname(atac->atac_dev), 362 chp->ch_channel, st0, st1), DEBUG_PROBE); 363 364 /* Wait a bit, some devices are weird just after a reset. */ 365 delay(5000); 366 367 for (i = 0; i < chp->ch_ndrives; i++) { 368 #if NATA_DMA 369 /* 370 * Init error counter so that an error within the first xfers 371 * will trigger a downgrade 372 */ 373 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 374 #endif 375 376 /* If controller can't do 16bit flag the drives as 32bit */ 377 if ((atac->atac_cap & 378 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 379 ata_channel_lock(chp); 380 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 381 ata_channel_unlock(chp); 382 } 383 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 384 continue; 385 386 /* Shortcut in case we've been shutdown */ 387 if (chp->ch_flags & ATACH_SHUTDOWN) 388 return; 389 390 /* 391 * Issue an identify, to try to detect ghosts. 392 * Note that we can't use interrupts here, because if there 393 * is no devices, we will get a command aborted without 394 * interrupts. 395 */ 396 error = ata_get_params(&chp->ch_drive[i], 397 AT_WAIT | AT_POLL, ¶ms); 398 if (error != CMD_OK) { 399 ata_channel_lock(chp); 400 ata_delay(chp, 1000, "atacnf", AT_WAIT); 401 ata_channel_unlock(chp); 402 403 /* Shortcut in case we've been shutdown */ 404 if (chp->ch_flags & ATACH_SHUTDOWN) 405 return; 406 407 error = ata_get_params(&chp->ch_drive[i], 408 AT_WAIT | AT_POLL, ¶ms); 409 } 410 if (error != CMD_OK) { 411 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 412 device_xname(atac->atac_dev), 413 chp->ch_channel, i, error), DEBUG_PROBE); 414 ata_channel_lock(chp); 415 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 416 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 417 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 418 ata_channel_unlock(chp); 419 continue; 420 } 421 /* 422 * Pre-ATA drive ? 423 * Test registers writability (Error register not 424 * writable, but cyllo is), then try an ATA command. 425 */ 426 if (wdc->select) 427 wdc->select(chp,i); 428 bus_space_write_1(wdr->cmd_iot, 429 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 430 delay(10); /* 400ns delay */ 431 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 432 0, 0x58); 433 bus_space_write_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 435 if (bus_space_read_1(wdr->cmd_iot, 436 wdr->cmd_iohs[wd_error], 0) == 0x58 || 437 bus_space_read_1(wdr->cmd_iot, 438 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 439 ATADEBUG_PRINT(("%s:%d:%d: register " 440 "writability failed\n", 441 device_xname(atac->atac_dev), 442 chp->ch_channel, i), DEBUG_PROBE); 443 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 444 ata_channel_unlock(chp); 445 continue; 446 } 447 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 448 WDCWAIT_TOUT) { 449 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 450 device_xname(atac->atac_dev), 451 chp->ch_channel, i), DEBUG_PROBE); 452 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 453 ata_channel_unlock(chp); 454 continue; 455 } 456 bus_space_write_1(wdr->cmd_iot, 457 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 458 delay(10); /* 400ns delay */ 459 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 460 WDCWAIT_TOUT) { 461 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 462 device_xname(atac->atac_dev), 463 chp->ch_channel, i), DEBUG_PROBE); 464 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 465 ata_channel_unlock(chp); 466 } else { 467 for (j = 0; j < chp->ch_ndrives; j++) { 468 if (chp->ch_drive[i].drive_type != 469 ATA_DRIVET_NONE) { 470 chp->ch_drive[j].drive_type = 471 ATA_DRIVET_OLD; 472 } 473 } 474 ata_channel_unlock(chp); 475 } 476 } 477 } 478 } 479 480 int 481 wdcprobe(struct wdc_regs *wdr) 482 { 483 484 return wdcprobe_with_reset(wdr, NULL); 485 } 486 487 int 488 wdcprobe_with_reset(struct wdc_regs *wdr, 489 void (*do_reset)(struct ata_channel *, int)) 490 { 491 struct wdc_softc wdc; 492 struct ata_channel ch; 493 int rv; 494 495 memset(&wdc, 0, sizeof(wdc)); 496 memset(&ch, 0, sizeof(ch)); 497 ata_channel_init(&ch); 498 ch.ch_atac = &wdc.sc_atac; 499 wdc.regs = wdr; 500 501 /* check the MD reset method */ 502 wdc.reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 503 504 ata_channel_lock(&ch); 505 rv = wdcprobe1(&ch, 1); 506 ata_channel_unlock(&ch); 507 508 ata_channel_destroy(&ch); 509 510 return rv; 511 } 512 513 static int 514 wdcprobe1(struct ata_channel *chp, int poll) 515 { 516 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 517 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 518 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 519 u_int8_t ret_value = 0x03; 520 u_int8_t drive; 521 /* XXX if poll, wdc_probe_count is 0. */ 522 int wdc_probe_count = 523 poll ? (WDC_PROBE_WAIT / WDCDELAY) 524 : (WDC_PROBE_WAIT * hz); 525 526 /* 527 * Sanity check to see if the wdc channel responds at all. 528 */ 529 530 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 531 while (wdc_probe_count-- > 0) { 532 if (wdc->select) 533 wdc->select(chp,0); 534 535 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 536 0, WDSD_IBM); 537 delay(10); /* 400ns delay */ 538 st0 = bus_space_read_1(wdr->cmd_iot, 539 wdr->cmd_iohs[wd_status], 0); 540 541 if (wdc->select) 542 wdc->select(chp,1); 543 544 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 545 0, WDSD_IBM | 0x10); 546 delay(10); /* 400ns delay */ 547 st1 = bus_space_read_1(wdr->cmd_iot, 548 wdr->cmd_iohs[wd_status], 0); 549 if ((st0 & WDCS_BSY) == 0) 550 break; 551 } 552 553 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 554 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 555 556 if (st0 == 0xff || st0 == WDSD_IBM) 557 ret_value &= ~0x01; 558 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 559 ret_value &= ~0x02; 560 /* Register writability test, drive 0. */ 561 if (ret_value & 0x01) { 562 if (wdc->select) 563 wdc->select(chp,0); 564 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 565 0, WDSD_IBM); 566 bus_space_write_1(wdr->cmd_iot, 567 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 568 cl = bus_space_read_1(wdr->cmd_iot, 569 wdr->cmd_iohs[wd_cyl_lo], 0); 570 if (cl != 0x02) { 571 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 572 "got 0x%x != 0x02\n", 573 __func__, chp->ch_channel, cl), 574 DEBUG_PROBE); 575 ret_value &= ~0x01; 576 } 577 bus_space_write_1(wdr->cmd_iot, 578 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 579 cl = bus_space_read_1(wdr->cmd_iot, 580 wdr->cmd_iohs[wd_cyl_lo], 0); 581 if (cl != 0x01) { 582 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 583 "got 0x%x != 0x01\n", 584 __func__, chp->ch_channel, cl), 585 DEBUG_PROBE); 586 ret_value &= ~0x01; 587 } 588 bus_space_write_1(wdr->cmd_iot, 589 wdr->cmd_iohs[wd_sector], 0, 0x01); 590 cl = bus_space_read_1(wdr->cmd_iot, 591 wdr->cmd_iohs[wd_sector], 0); 592 if (cl != 0x01) { 593 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 594 "got 0x%x != 0x01\n", 595 __func__, chp->ch_channel, cl), 596 DEBUG_PROBE); 597 ret_value &= ~0x01; 598 } 599 bus_space_write_1(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_sector], 0, 0x02); 601 cl = bus_space_read_1(wdr->cmd_iot, 602 wdr->cmd_iohs[wd_sector], 0); 603 if (cl != 0x02) { 604 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 605 "got 0x%x != 0x02\n", 606 __func__, chp->ch_channel, cl), 607 DEBUG_PROBE); 608 ret_value &= ~0x01; 609 } 610 cl = bus_space_read_1(wdr->cmd_iot, 611 wdr->cmd_iohs[wd_cyl_lo], 0); 612 if (cl != 0x01) { 613 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 614 "got 0x%x != 0x01\n", 615 __func__, chp->ch_channel, cl), 616 DEBUG_PROBE); 617 ret_value &= ~0x01; 618 } 619 } 620 /* Register writability test, drive 1. */ 621 if (ret_value & 0x02) { 622 if (wdc->select) 623 wdc->select(chp,1); 624 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 625 0, WDSD_IBM | 0x10); 626 bus_space_write_1(wdr->cmd_iot, 627 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 628 cl = bus_space_read_1(wdr->cmd_iot, 629 wdr->cmd_iohs[wd_cyl_lo], 0); 630 if (cl != 0x02) { 631 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 632 "got 0x%x != 0x02\n", 633 __func__, chp->ch_channel, cl), 634 DEBUG_PROBE); 635 ret_value &= ~0x02; 636 } 637 bus_space_write_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 639 cl = bus_space_read_1(wdr->cmd_iot, 640 wdr->cmd_iohs[wd_cyl_lo], 0); 641 if (cl != 0x01) { 642 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 643 "got 0x%x != 0x01\n", 644 __func__, chp->ch_channel, cl), 645 DEBUG_PROBE); 646 ret_value &= ~0x02; 647 } 648 bus_space_write_1(wdr->cmd_iot, 649 wdr->cmd_iohs[wd_sector], 0, 0x01); 650 cl = bus_space_read_1(wdr->cmd_iot, 651 wdr->cmd_iohs[wd_sector], 0); 652 if (cl != 0x01) { 653 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 654 "got 0x%x != 0x01\n", 655 __func__, chp->ch_channel, cl), 656 DEBUG_PROBE); 657 ret_value &= ~0x02; 658 } 659 bus_space_write_1(wdr->cmd_iot, 660 wdr->cmd_iohs[wd_sector], 0, 0x02); 661 cl = bus_space_read_1(wdr->cmd_iot, 662 wdr->cmd_iohs[wd_sector], 0); 663 if (cl != 0x02) { 664 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 665 "got 0x%x != 0x02\n", 666 __func__, chp->ch_channel, cl), 667 DEBUG_PROBE); 668 ret_value &= ~0x02; 669 } 670 cl = bus_space_read_1(wdr->cmd_iot, 671 wdr->cmd_iohs[wd_cyl_lo], 0); 672 if (cl != 0x01) { 673 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 674 "got 0x%x != 0x01\n", 675 __func__, chp->ch_channel, cl), 676 DEBUG_PROBE); 677 ret_value &= ~0x02; 678 } 679 } 680 681 if (ret_value == 0) { 682 return 0; 683 } 684 } 685 686 #if 0 /* XXX this break some ATA or ATAPI devices */ 687 /* 688 * reset bus. Also send an ATAPI_RESET to devices, in case there are 689 * ATAPI device out there which don't react to the bus reset 690 */ 691 if (ret_value & 0x01) { 692 if (wdc->select) 693 wdc->select(chp,0); 694 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 695 0, WDSD_IBM); 696 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 697 ATAPI_SOFT_RESET); 698 } 699 if (ret_value & 0x02) { 700 if (wdc->select) 701 wdc->select(chp,0); 702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 703 0, WDSD_IBM | 0x10); 704 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 705 ATAPI_SOFT_RESET); 706 } 707 708 delay(5000); 709 #endif 710 711 wdc->reset(chp, RESET_POLL); 712 DELAY(2000); 713 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 714 715 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 716 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 717 WDCTL_4BIT); 718 719 #ifdef WDC_NO_IDS 720 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 721 #else 722 ret_value = __wdcwait_reset(chp, ret_value, poll); 723 #endif 724 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 725 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 726 727 /* if reset failed, there's nothing here */ 728 if (ret_value == 0) { 729 return 0; 730 } 731 732 /* 733 * Test presence of drives. First test register signatures looking 734 * for ATAPI devices. If it's not an ATAPI and reset said there may 735 * be something here assume it's ATA or OLD. Ghost will be killed 736 * later in attach routine. 737 */ 738 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 739 if ((ret_value & (0x01 << drive)) == 0) 740 continue; 741 if (wdc->select) 742 wdc->select(chp,drive); 743 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 744 WDSD_IBM | (drive << 4)); 745 delay(10); /* 400ns delay */ 746 /* Save registers contents */ 747 sc = bus_space_read_1(wdr->cmd_iot, 748 wdr->cmd_iohs[wd_seccnt], 0); 749 sn = bus_space_read_1(wdr->cmd_iot, 750 wdr->cmd_iohs[wd_sector], 0); 751 cl = bus_space_read_1(wdr->cmd_iot, 752 wdr->cmd_iohs[wd_cyl_lo], 0); 753 ch = bus_space_read_1(wdr->cmd_iot, 754 wdr->cmd_iohs[wd_cyl_hi], 0); 755 756 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 757 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 758 sn, cl, ch), DEBUG_PROBE); 759 /* 760 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 761 * we get wrong values here, so ignore it. 762 */ 763 if (chp->ch_drive != NULL) { 764 if (cl == 0x14 && ch == 0xeb) { 765 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 766 } else { 767 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 768 } 769 } 770 } 771 /* 772 * Select an existing drive before lowering spl, some WDC_NO_IDS 773 * devices incorrectly assert IRQ on nonexistent slave 774 */ 775 if (ret_value & 0x01) { 776 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 777 WDSD_IBM); 778 (void)bus_space_read_1(wdr->cmd_iot, 779 wdr->cmd_iohs[wd_status], 0); 780 } 781 return (ret_value); 782 } 783 784 void 785 wdcattach(struct ata_channel *chp) 786 { 787 struct atac_softc *atac = chp->ch_atac; 788 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 789 790 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 791 792 /* default data transfer methods */ 793 if (wdc->datain_pio == NULL) 794 wdc->datain_pio = wdc_datain_pio; 795 if (wdc->dataout_pio == NULL) 796 wdc->dataout_pio = wdc_dataout_pio; 797 /* default reset method */ 798 if (wdc->reset == NULL) 799 wdc->reset = wdc_do_reset; 800 801 /* initialise global data */ 802 if (atac->atac_bustype_ata == NULL) 803 atac->atac_bustype_ata = &wdc_ata_bustype; 804 if (atac->atac_probe == NULL) 805 atac->atac_probe = wdc_drvprobe; 806 #if NATAPIBUS > 0 807 if (atac->atac_atapibus_attach == NULL) 808 atac->atac_atapibus_attach = wdc_atapibus_attach; 809 #endif 810 811 ata_channel_attach(chp); 812 } 813 814 void 815 wdc_childdetached(device_t self, device_t child) 816 { 817 struct atac_softc *atac = device_private(self); 818 struct ata_channel *chp; 819 int i; 820 821 for (i = 0; i < atac->atac_nchannels; i++) { 822 chp = atac->atac_channels[i]; 823 if (child == chp->atabus) { 824 chp->atabus = NULL; 825 return; 826 } 827 } 828 } 829 830 int 831 wdcdetach(device_t self, int flags) 832 { 833 struct atac_softc *atac = device_private(self); 834 struct ata_channel *chp; 835 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 836 int i, error = 0; 837 838 for (i = 0; i < atac->atac_nchannels; i++) { 839 chp = atac->atac_channels[i]; 840 if (chp->atabus == NULL) 841 continue; 842 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 843 device_xname(atac->atac_dev), device_xname(chp->atabus)), 844 DEBUG_DETACH); 845 if ((error = config_detach(chp->atabus, flags)) != 0) 846 return error; 847 ata_channel_detach(chp); 848 } 849 if (adapt->adapt_refcnt != 0) 850 return EBUSY; 851 return 0; 852 } 853 854 /* restart an interrupted I/O */ 855 void 856 wdcrestart(void *v) 857 { 858 struct ata_channel *chp = v; 859 int s; 860 861 s = splbio(); 862 atastart(chp); 863 splx(s); 864 } 865 866 867 /* 868 * Interrupt routine for the controller. Acknowledge the interrupt, check for 869 * errors on the current operation, mark it done if necessary, and start the 870 * next request. Also check for a partially done transfer, and continue with 871 * the next chunk if so. 872 */ 873 int 874 wdcintr(void *arg) 875 { 876 struct ata_channel *chp = arg; 877 struct atac_softc *atac = chp->ch_atac; 878 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 879 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 880 struct ata_xfer *xfer; 881 int ret; 882 883 if (!device_is_active(atac->atac_dev)) { 884 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 885 DEBUG_INTR); 886 return (0); 887 } 888 889 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 890 ATADEBUG_PRINT(("wdcintr: irq not expected\n"), DEBUG_INTR); 891 goto ignore; 892 } 893 894 xfer = ata_queue_get_active_xfer(chp); 895 if (xfer == NULL) { 896 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 897 ignore: 898 /* try to clear the pending interrupt anyway */ 899 (void)bus_space_read_1(wdr->cmd_iot, 900 wdr->cmd_iohs[wd_status], 0); 901 return (0); 902 } 903 904 /* 905 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 906 * actually has no effect, and interrupt is triggered regardless. 907 * Ignore polled commands here, they are processed separately. 908 */ 909 if (ISSET(xfer->c_flags, C_POLL)) { 910 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 911 DEBUG_INTR); 912 goto ignore; 913 } 914 915 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 916 KASSERT(xfer != NULL); 917 918 #if NATA_DMA || NATA_PIOBM 919 if (chp->ch_flags & ATACH_DMA_WAIT) { 920 wdc->dma_status = 921 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 922 xfer->c_drive, WDC_DMAEND_END); 923 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 924 /* IRQ not for us, not detected by DMA engine */ 925 return 0; 926 } 927 chp->ch_flags &= ~ATACH_DMA_WAIT; 928 } 929 #endif 930 chp->ch_flags &= ~ATACH_IRQ_WAIT; 931 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 932 ret = xfer->ops->c_intr(chp, xfer, 1); 933 if (ret == 0) /* irq was not for us, still waiting for irq */ 934 chp->ch_flags |= ATACH_IRQ_WAIT; 935 return (ret); 936 } 937 938 /* Put all disk in RESET state */ 939 void 940 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 941 { 942 struct ata_channel *chp = drvp->chnl_softc; 943 944 ata_channel_lock_owned(chp); 945 946 KASSERT(sigp == NULL); 947 948 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 949 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 950 drvp->drive), DEBUG_FUNCS); 951 952 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 953 } 954 955 void 956 wdc_reset_channel(struct ata_channel *chp, int flags) 957 { 958 struct ata_xfer *xfer; 959 960 ata_channel_lock_owned(chp); 961 962 #if NATA_DMA || NATA_PIOBM 963 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 964 #endif 965 966 chp->ch_flags &= ~ATACH_IRQ_WAIT; 967 968 /* 969 * if the current command is on an ATAPI device, issue a 970 * ATAPI_SOFT_RESET 971 */ 972 xfer = ata_queue_get_active_xfer_locked(chp); 973 974 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 975 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 976 ata_delay(chp, 1000, "atardl", flags); 977 } 978 979 /* reset the channel */ 980 if (flags & AT_WAIT) 981 (void) wdcreset(chp, RESET_SLEEP); 982 else 983 (void) wdcreset(chp, RESET_POLL); 984 985 /* 986 * wait a bit after reset; in case the DMA engines needs some time 987 * to recover. 988 */ 989 ata_delay(chp, 1000, "atardl", flags); 990 991 /* 992 * Look for pending xfers. If we have a shared queue, we'll also reset 993 * the other channel if the current xfer is running on it. 994 * Then we'll kill the eventual active transfer explicitely, so that 995 * it is queued for retry immediatelly without waiting for I/O timeout. 996 */ 997 if (xfer) { 998 if (xfer->c_chp != chp) { 999 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 1000 ATACH_NODRIVE); 1001 } else { 1002 #if NATA_DMA || NATA_PIOBM 1003 /* 1004 * If we're waiting for DMA, stop the 1005 * DMA engine 1006 */ 1007 if (chp->ch_flags & ATACH_DMA_WAIT) { 1008 (*wdc->dma_finish)(wdc->dma_arg, 1009 chp->ch_channel, xfer->c_drive, 1010 WDC_DMAEND_ABRT_QUIET); 1011 chp->ch_flags &= ~ATACH_DMA_WAIT; 1012 } 1013 #endif 1014 } 1015 } 1016 1017 ata_kill_active(chp, KILL_RESET, flags); 1018 } 1019 1020 static int 1021 wdcreset(struct ata_channel *chp, int poll) 1022 { 1023 struct atac_softc *atac = chp->ch_atac; 1024 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1025 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1026 int drv_mask1, drv_mask2; 1027 1028 ata_channel_lock_owned(chp); 1029 1030 #ifdef WDC_NO_IDS 1031 poll = RESET_POLL; 1032 #endif 1033 wdc->reset(chp, poll); 1034 1035 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1036 ? 0x01 : 0x00; 1037 if (chp->ch_ndrives > 1) 1038 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1039 ? 0x02 : 0x00; 1040 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1041 (poll == RESET_SLEEP) ? 0 : 1); 1042 if (drv_mask2 != drv_mask1) { 1043 aprint_error("%s channel %d: reset failed for", 1044 device_xname(atac->atac_dev), chp->ch_channel); 1045 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1046 aprint_normal(" drive 0"); 1047 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1048 aprint_normal(" drive 1"); 1049 aprint_normal("\n"); 1050 } 1051 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1052 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1053 WDCTL_4BIT); 1054 1055 return (drv_mask1 != drv_mask2) ? 1 : 0; 1056 } 1057 1058 void 1059 wdc_do_reset(struct ata_channel *chp, int poll) 1060 { 1061 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1062 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1063 int s = 0; 1064 1065 if (poll != RESET_SLEEP) 1066 s = splbio(); 1067 if (wdc->select) 1068 wdc->select(chp,0); 1069 /* master */ 1070 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1071 delay(10); /* 400ns delay */ 1072 /* assert SRST, wait for reset to complete */ 1073 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1074 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1075 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1076 delay(2000); 1077 } 1078 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1079 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1080 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1081 WDCTL_4BIT | WDCTL_IDS); 1082 delay(10); /* 400ns delay */ 1083 if (poll != RESET_SLEEP) { 1084 /* ACK interrupt in case there is one pending left */ 1085 if (wdc->irqack) 1086 wdc->irqack(chp); 1087 splx(s); 1088 } 1089 } 1090 1091 static int 1092 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1093 { 1094 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1095 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1096 int timeout, nloop; 1097 int wflags = poll ? AT_POLL : AT_WAIT; 1098 u_int8_t st0 = 0, st1 = 0; 1099 #ifdef ATADEBUG 1100 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1101 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1102 #endif 1103 if (poll) 1104 nloop = WDCNDELAY_RST; 1105 else 1106 nloop = WDC_RESET_WAIT * hz / 1000; 1107 /* wait for BSY to deassert */ 1108 for (timeout = 0; timeout < nloop; timeout++) { 1109 if ((drv_mask & 0x01) != 0) { 1110 if (wdc->select) 1111 wdc->select(chp,0); 1112 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1113 0, WDSD_IBM); /* master */ 1114 delay(10); 1115 st0 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_status], 0); 1117 #ifdef ATADEBUG 1118 sc0 = bus_space_read_1(wdr->cmd_iot, 1119 wdr->cmd_iohs[wd_seccnt], 0); 1120 sn0 = bus_space_read_1(wdr->cmd_iot, 1121 wdr->cmd_iohs[wd_sector], 0); 1122 cl0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_cyl_lo], 0); 1124 ch0 = bus_space_read_1(wdr->cmd_iot, 1125 wdr->cmd_iohs[wd_cyl_hi], 0); 1126 #endif 1127 } 1128 if ((drv_mask & 0x02) != 0) { 1129 if (wdc->select) 1130 wdc->select(chp,1); 1131 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1132 0, WDSD_IBM | 0x10); /* slave */ 1133 delay(10); 1134 st1 = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_status], 0); 1136 #ifdef ATADEBUG 1137 sc1 = bus_space_read_1(wdr->cmd_iot, 1138 wdr->cmd_iohs[wd_seccnt], 0); 1139 sn1 = bus_space_read_1(wdr->cmd_iot, 1140 wdr->cmd_iohs[wd_sector], 0); 1141 cl1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_cyl_lo], 0); 1143 ch1 = bus_space_read_1(wdr->cmd_iot, 1144 wdr->cmd_iohs[wd_cyl_hi], 0); 1145 #endif 1146 } 1147 1148 if ((drv_mask & 0x01) == 0) { 1149 /* no master */ 1150 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1151 /* No master, slave is ready, it's done */ 1152 goto end; 1153 } 1154 if ((drv_mask & 0x02) == 0) { 1155 /* No master, no slave: it's done */ 1156 goto end; 1157 } 1158 } else if ((drv_mask & 0x02) == 0) { 1159 /* no slave */ 1160 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1161 /* No slave, master is ready, it's done */ 1162 goto end; 1163 } 1164 } else { 1165 /* Wait for both master and slave to be ready */ 1166 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1167 goto end; 1168 } 1169 } 1170 ata_delay(chp, WDCDELAY, "atarst", wflags); 1171 } 1172 /* Reset timed out. Maybe it's because drv_mask was not right */ 1173 if (st0 & WDCS_BSY) 1174 drv_mask &= ~0x01; 1175 if (st1 & WDCS_BSY) 1176 drv_mask &= ~0x02; 1177 end: 1178 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1179 "cl=0x%x ch=0x%x\n", 1180 device_xname(chp->ch_atac->atac_dev), 1181 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1182 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1183 "cl=0x%x ch=0x%x\n", 1184 device_xname(chp->ch_atac->atac_dev), 1185 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1186 1187 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1188 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1189 st0, st1), DEBUG_PROBE); 1190 1191 return drv_mask; 1192 } 1193 1194 /* 1195 * Wait for a drive to be !BSY, and have mask in its status register. 1196 * return -1 for a timeout after "timeout" ms. 1197 */ 1198 static int 1199 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1200 { 1201 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1202 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1203 u_char status, error = 0; 1204 int xtime = 0; 1205 int rv; 1206 1207 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1208 device_xname(chp->ch_atac->atac_dev), 1209 chp->ch_channel), DEBUG_STATUS); 1210 *tfd = 0; 1211 1212 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1213 1214 for (;;) { 1215 status = 1216 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1217 if ((status & (WDCS_BSY | mask)) == bits) 1218 break; 1219 if (++xtime > timeout) { 1220 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1221 "status %x error %x (mask 0x%x bits 0x%x)\n", 1222 xtime, status, 1223 bus_space_read_1(wdr->cmd_iot, 1224 wdr->cmd_iohs[wd_error], 0), mask, bits), 1225 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1226 rv = WDCWAIT_TOUT; 1227 goto out; 1228 } 1229 delay(WDCDELAY); 1230 } 1231 #ifdef ATADEBUG 1232 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1233 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1234 #endif 1235 if (status & WDCS_ERR) 1236 error = bus_space_read_1(wdr->cmd_iot, 1237 wdr->cmd_iohs[wd_error], 0); 1238 #ifdef WDCNDELAY_DEBUG 1239 /* After autoconfig, there should be no long delays. */ 1240 if (!cold && xtime > WDCNDELAY_DEBUG) { 1241 struct ata_xfer *xfer; 1242 1243 xfer = ata_queue_get_active_xfer_locked(chp); 1244 if (xfer == NULL) 1245 printf("%s channel %d: warning: busy-wait took %dus\n", 1246 device_xname(chp->ch_atac->atac_dev), 1247 chp->ch_channel, WDCDELAY * xtime); 1248 else 1249 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1250 device_xname(chp->ch_atac->atac_dev), 1251 chp->ch_channel, xfer->c_drive, 1252 WDCDELAY * xtime); 1253 } 1254 #endif 1255 rv = WDCWAIT_OK; 1256 1257 out: 1258 *tfd = ATACH_ERR_ST(error, status); 1259 return rv; 1260 } 1261 1262 /* 1263 * Call __wdcwait(), polling using kpause() or waking up the kernel 1264 * thread if possible 1265 */ 1266 int 1267 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1268 int *tfd) 1269 { 1270 int error, i, timeout_hz = mstohz(timeout); 1271 1272 ata_channel_lock_owned(chp); 1273 1274 if (timeout_hz == 0 || 1275 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1276 error = __wdcwait(chp, mask, bits, timeout, tfd); 1277 else { 1278 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1279 if (error != 0) { 1280 if ((chp->ch_flags & ATACH_TH_RUN) || 1281 (flags & AT_WAIT)) { 1282 /* 1283 * we're running in the channel thread 1284 * or some userland thread context 1285 */ 1286 for (i = 0; i < timeout_hz; i++) { 1287 if (__wdcwait(chp, mask, bits, 1288 WDCDELAY_POLL, tfd) == 0) { 1289 error = 0; 1290 break; 1291 } 1292 kpause("atapoll", true, 1, 1293 &chp->ch_lock); 1294 } 1295 } else { 1296 /* 1297 * we're probably in interrupt context, 1298 * caller must ask the thread to come back here 1299 */ 1300 return(WDCWAIT_THR); 1301 } 1302 } 1303 } 1304 return (error); 1305 } 1306 1307 1308 #if NATA_DMA 1309 /* 1310 * Busy-wait for DMA to complete 1311 */ 1312 int 1313 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1314 { 1315 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1316 int xtime; 1317 1318 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1319 wdc->dma_status = 1320 (*wdc->dma_finish)(wdc->dma_arg, 1321 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1322 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1323 return 0; 1324 delay(WDCDELAY); 1325 } 1326 /* timeout, force a DMA halt */ 1327 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1328 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1329 return 1; 1330 } 1331 #endif 1332 1333 void 1334 wdctimeout(void *arg) 1335 { 1336 struct ata_xfer *xfer; 1337 struct ata_channel *chp = arg; 1338 #if NATA_DMA || NATA_PIOBM 1339 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1340 #endif 1341 int s; 1342 1343 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1344 1345 s = splbio(); 1346 1347 callout_ack(&chp->c_timo_callout); 1348 1349 xfer = ata_queue_get_active_xfer(chp); 1350 KASSERT(xfer != NULL); 1351 1352 if (ata_timo_xfer_check(xfer)) { 1353 /* Already logged */ 1354 goto out; 1355 } 1356 1357 __wdcerror(chp, "lost interrupt"); 1358 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1359 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1360 xfer->c_bcount, xfer->c_skip); 1361 #if NATA_DMA || NATA_PIOBM 1362 if (chp->ch_flags & ATACH_DMA_WAIT) { 1363 wdc->dma_status = 1364 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1365 xfer->c_drive, WDC_DMAEND_ABRT); 1366 chp->ch_flags &= ~ATACH_DMA_WAIT; 1367 } 1368 #endif 1369 /* 1370 * Call the interrupt routine. If we just missed an interrupt, 1371 * it will do what's needed. Else, it will take the needed 1372 * action (reset the device). 1373 * Before that we need to reinstall the timeout callback, 1374 * in case it will miss another irq while in this transfer 1375 * We arbitray chose it to be 1s 1376 */ 1377 callout_reset(&chp->c_timo_callout, hz, wdctimeout, chp); 1378 xfer->c_flags |= C_TIMEOU; 1379 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1380 xfer->ops->c_intr(chp, xfer, 1); 1381 1382 out: 1383 splx(s); 1384 } 1385 1386 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1387 .c_start = __wdccommand_start, 1388 .c_poll = __wdccommand_poll, 1389 .c_abort = __wdccommand_done, 1390 .c_intr = __wdccommand_intr, 1391 .c_kill_xfer = __wdccommand_kill_xfer, 1392 }; 1393 1394 int 1395 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1396 { 1397 struct ata_channel *chp = drvp->chnl_softc; 1398 struct ata_command *ata_c = &xfer->c_ata_c; 1399 int s, ret; 1400 1401 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1402 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1403 drvp->drive), DEBUG_FUNCS); 1404 1405 /* set up an xfer and queue. Wait for completion */ 1406 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1407 ata_c->flags |= AT_POLL; 1408 if (ata_c->flags & AT_POLL) 1409 xfer->c_flags |= C_POLL; 1410 if (ata_c->flags & AT_WAIT) 1411 xfer->c_flags |= C_WAIT; 1412 xfer->c_drive = drvp->drive; 1413 xfer->c_databuf = ata_c->data; 1414 xfer->c_bcount = ata_c->bcount; 1415 xfer->ops = &wdc_cmd_xfer_ops; 1416 1417 s = splbio(); 1418 ata_exec_xfer(chp, xfer); 1419 #ifdef DIAGNOSTIC 1420 if ((ata_c->flags & AT_POLL) != 0 && 1421 (ata_c->flags & AT_DONE) == 0) 1422 panic("wdc_exec_command: polled command not done"); 1423 #endif 1424 if (ata_c->flags & AT_DONE) { 1425 ret = ATACMD_COMPLETE; 1426 } else { 1427 if (ata_c->flags & AT_WAIT) { 1428 ata_wait_cmd(chp, xfer); 1429 ret = ATACMD_COMPLETE; 1430 } else { 1431 ret = ATACMD_QUEUED; 1432 } 1433 } 1434 splx(s); 1435 return ret; 1436 } 1437 1438 static int 1439 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1440 { 1441 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1442 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1443 int drive = xfer->c_drive; 1444 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1445 struct ata_command *ata_c = &xfer->c_ata_c; 1446 int tfd; 1447 1448 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1449 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1450 xfer->c_drive), DEBUG_FUNCS); 1451 1452 if (wdc->select) 1453 wdc->select(chp,drive); 1454 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1455 WDSD_IBM | (drive << 4)); 1456 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1457 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1458 case WDCWAIT_OK: 1459 break; 1460 case WDCWAIT_TOUT: 1461 ata_c->flags |= AT_TIMEOU; 1462 return ATASTART_ABORT; 1463 case WDCWAIT_THR: 1464 return ATASTART_TH; 1465 } 1466 if (ata_c->flags & AT_POLL) { 1467 /* polled command, disable interrupts */ 1468 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1469 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1470 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1471 } 1472 if ((ata_c->flags & AT_LBA48) != 0) { 1473 wdccommandext(chp, drive, ata_c->r_command, 1474 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1475 ata_c->r_device & ~0x10); 1476 } else { 1477 wdccommand(chp, drive, ata_c->r_command, 1478 (ata_c->r_lba >> 8) & 0xffff, 1479 WDSD_IBM | (drive << 4) | 1480 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1481 ((ata_c->r_lba >> 24) & 0x0f), 1482 ata_c->r_lba & 0xff, 1483 ata_c->r_count & 0xff, 1484 ata_c->r_features & 0xff); 1485 } 1486 1487 if ((ata_c->flags & AT_POLL) == 0) { 1488 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1489 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1490 wdctimeout, chp); 1491 return ATASTART_STARTED; 1492 } 1493 1494 /* 1495 * Polled command. Wait for drive ready or drq. Done in intr(). 1496 * Wait for at last 400ns for status bit to be valid. 1497 */ 1498 delay(10); /* 400ns delay */ 1499 return ATASTART_POLL; 1500 } 1501 1502 static void 1503 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1504 { 1505 __wdccommand_intr(chp, xfer, 0); 1506 } 1507 1508 static int 1509 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1510 { 1511 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1512 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1513 struct ata_command *ata_c = &xfer->c_ata_c; 1514 int bcount = ata_c->bcount; 1515 char *data = ata_c->data; 1516 int wflags, tfd; 1517 int drive_flags; 1518 1519 if (ata_c->r_command == WDCC_IDENTIFY || 1520 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1521 /* 1522 * The IDENTIFY data has been designed as an array of 1523 * u_int16_t, so we can byteswap it on the fly. 1524 * Historically it's what we have always done so keeping it 1525 * here ensure binary backward compatibility. 1526 */ 1527 drive_flags = ATA_DRIVE_NOSTREAM | 1528 chp->ch_drive[xfer->c_drive].drive_flags; 1529 } else { 1530 /* 1531 * Other data structure are opaque and should be transferred 1532 * as is. 1533 */ 1534 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1535 } 1536 1537 #ifdef WDC_NO_IDS 1538 wflags = AT_POLL; 1539 #else 1540 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1541 /* both wait and poll, we can kpause here */ 1542 wflags = AT_WAIT | AT_POLL; 1543 } else { 1544 wflags = AT_POLL; 1545 } 1546 #endif 1547 1548 ata_channel_lock(chp); 1549 1550 again: 1551 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1552 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1553 xfer->c_drive), DEBUG_INTR); 1554 /* 1555 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1556 * Reselect again, it doesn't hurt for others commands, and the time 1557 * penalty for the extra register write is acceptable, 1558 * wdc_exec_command() isn't called often (mostly for autoconfig) 1559 */ 1560 if ((xfer->c_flags & C_ATAPI) != 0) { 1561 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1562 WDSD_IBM | (xfer->c_drive << 4)); 1563 } 1564 if ((ata_c->flags & AT_XFDONE) != 0) { 1565 /* 1566 * We have completed a data xfer. The drive should now be 1567 * in its initial state 1568 */ 1569 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1570 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1571 wflags, &tfd) == WDCWAIT_TOUT) { 1572 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1573 ata_channel_unlock(chp); 1574 return 0; /* IRQ was not for us */ 1575 } 1576 ata_c->flags |= AT_TIMEOU; 1577 } 1578 goto out; 1579 } 1580 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1581 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1582 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1583 ata_channel_unlock(chp); 1584 return 0; /* IRQ was not for us */ 1585 } 1586 ata_c->flags |= AT_TIMEOU; 1587 goto out; 1588 } 1589 if (wdc->irqack) 1590 wdc->irqack(chp); 1591 if (ata_c->flags & AT_READ) { 1592 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1593 ata_c->flags |= AT_TIMEOU; 1594 goto out; 1595 } 1596 wdc->datain_pio(chp, drive_flags, data, bcount); 1597 /* at this point the drive should be in its initial state */ 1598 ata_c->flags |= AT_XFDONE; 1599 /* 1600 * XXX checking the status register again here cause some 1601 * hardware to timeout. 1602 */ 1603 } else if (ata_c->flags & AT_WRITE) { 1604 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1605 ata_c->flags |= AT_TIMEOU; 1606 goto out; 1607 } 1608 wdc->dataout_pio(chp, drive_flags, data, bcount); 1609 ata_c->flags |= AT_XFDONE; 1610 if ((ata_c->flags & AT_POLL) == 0) { 1611 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1612 callout_reset(&chp->c_timo_callout, 1613 mstohz(ata_c->timeout), wdctimeout, chp); 1614 ata_channel_unlock(chp); 1615 return 1; 1616 } else { 1617 goto again; 1618 } 1619 } 1620 out: 1621 if (ATACH_ST(tfd) & WDCS_DWF) 1622 ata_c->flags |= AT_DF; 1623 if (ATACH_ST(tfd) & WDCS_ERR) { 1624 ata_c->flags |= AT_ERROR; 1625 ata_c->r_error = ATACH_ST(tfd); 1626 } 1627 1628 ata_channel_unlock(chp); 1629 1630 __wdccommand_done(chp, xfer); 1631 return 1; 1632 } 1633 1634 static void 1635 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1636 { 1637 struct atac_softc *atac = chp->ch_atac; 1638 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1639 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1640 struct ata_command *ata_c = &xfer->c_ata_c; 1641 bool start = true; 1642 1643 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1644 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1645 ata_c->flags), DEBUG_FUNCS); 1646 1647 if (ata_waitdrain_xfer_check(chp, xfer)) { 1648 start = false; 1649 goto out; 1650 } 1651 1652 if ((ata_c->flags & AT_READREG) != 0 && 1653 device_is_active(atac->atac_dev) && 1654 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1655 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1656 wdr->cmd_iohs[wd_status], 0); 1657 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1658 wdr->cmd_iohs[wd_error], 0); 1659 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1660 wdr->cmd_iohs[wd_seccnt], 0); 1661 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1662 wdr->cmd_iohs[wd_sector], 0) << 0; 1663 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1664 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1665 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1666 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1667 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1668 wdr->cmd_iohs[wd_sdh], 0); 1669 1670 if ((ata_c->flags & AT_LBA48) != 0) { 1671 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1672 if ((ata_c->flags & AT_POLL) != 0) 1673 bus_space_write_1(wdr->ctl_iot, 1674 wdr->ctl_ioh, wd_aux_ctlr, 1675 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1676 else 1677 bus_space_write_1(wdr->ctl_iot, 1678 wdr->ctl_ioh, wd_aux_ctlr, 1679 WDCTL_HOB|WDCTL_4BIT); 1680 } 1681 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1682 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1683 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1684 wdr->cmd_iohs[wd_sector], 0) << 24; 1685 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1686 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1687 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1688 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1689 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1690 if ((ata_c->flags & AT_POLL) != 0) 1691 bus_space_write_1(wdr->ctl_iot, 1692 wdr->ctl_ioh, wd_aux_ctlr, 1693 WDCTL_4BIT|WDCTL_IDS); 1694 else 1695 bus_space_write_1(wdr->ctl_iot, 1696 wdr->ctl_ioh, wd_aux_ctlr, 1697 WDCTL_4BIT); 1698 } 1699 } else { 1700 ata_c->r_lba |= 1701 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1702 } 1703 ata_c->r_device &= 0xf0; 1704 } 1705 1706 __wdccommand_done_end(chp, xfer); 1707 1708 ata_deactivate_xfer(chp, xfer); 1709 1710 out: 1711 if (ata_c->flags & AT_POLL) { 1712 /* enable interrupts */ 1713 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1714 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1715 wd_aux_ctlr, WDCTL_4BIT); 1716 delay(10); /* some drives need a little delay here */ 1717 } 1718 1719 if (start) 1720 atastart(chp); 1721 } 1722 1723 static void 1724 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1725 { 1726 struct ata_command *ata_c = &xfer->c_ata_c; 1727 1728 ata_c->flags |= AT_DONE; 1729 } 1730 1731 static void 1732 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1733 int reason) 1734 { 1735 struct ata_command *ata_c = &xfer->c_ata_c; 1736 bool deactivate = true; 1737 1738 switch (reason) { 1739 case KILL_GONE_INACTIVE: 1740 deactivate = false; 1741 /* FALLTHROUGH */ 1742 case KILL_GONE: 1743 ata_c->flags |= AT_GONE; 1744 break; 1745 case KILL_RESET: 1746 ata_c->flags |= AT_RESET; 1747 break; 1748 default: 1749 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1750 reason); 1751 panic("__wdccommand_kill_xfer"); 1752 } 1753 1754 __wdccommand_done_end(chp, xfer); 1755 1756 if (deactivate) 1757 ata_deactivate_xfer(chp, xfer); 1758 } 1759 1760 /* 1761 * Send a command. The drive should be ready. 1762 * Assumes interrupts are blocked. 1763 */ 1764 void 1765 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1766 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1767 u_int8_t features) 1768 { 1769 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1770 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1771 1772 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1773 "sector=%d count=%d features=%d\n", 1774 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1775 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1776 1777 if (wdc->select) 1778 wdc->select(chp,drive); 1779 1780 /* Select drive, head, and addressing mode. */ 1781 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1782 WDSD_IBM | (drive << 4) | head); 1783 /* Load parameters into the wd_features register. */ 1784 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1785 features); 1786 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1787 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1788 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1789 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1790 0, cylin >> 8); 1791 1792 /* Send command. */ 1793 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1794 return; 1795 } 1796 1797 /* 1798 * Send a 48-bit addressing command. The drive should be ready. 1799 * Assumes interrupts are blocked. 1800 */ 1801 void 1802 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1803 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1804 { 1805 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1806 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1807 1808 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1809 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1810 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1811 chp->ch_channel, drive, command, blkno, count, features, device), 1812 DEBUG_FUNCS); 1813 1814 KASSERT(drive < wdc->wdc_maxdrives); 1815 1816 if (wdc->select) 1817 wdc->select(chp,drive); 1818 1819 /* Select drive, head, and addressing mode. */ 1820 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1821 (drive << 4) | device); 1822 1823 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1824 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1825 0, features); 1826 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1827 0, count); 1828 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1829 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1830 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1831 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1832 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1833 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1834 } else { 1835 /* previous */ 1836 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1837 0, features >> 8); 1838 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1839 0, count >> 8); 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1841 0, blkno >> 24); 1842 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1843 0, blkno >> 32); 1844 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1845 0, blkno >> 40); 1846 1847 /* current */ 1848 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1849 0, features); 1850 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1851 0, count); 1852 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1853 0, blkno); 1854 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1855 0, blkno >> 8); 1856 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1857 0, blkno >> 16); 1858 } 1859 1860 /* Send command. */ 1861 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1862 return; 1863 } 1864 1865 /* 1866 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1867 * tested by the caller. 1868 */ 1869 void 1870 wdccommandshort(struct ata_channel *chp, int drive, int command) 1871 { 1872 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1873 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1874 1875 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1876 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1877 command), DEBUG_FUNCS); 1878 1879 if (wdc->select) 1880 wdc->select(chp,drive); 1881 1882 /* Select drive. */ 1883 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1884 WDSD_IBM | (drive << 4)); 1885 1886 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1887 } 1888 1889 static void 1890 __wdcerror(struct ata_channel *chp, const char *msg) 1891 { 1892 struct atac_softc *atac = chp->ch_atac; 1893 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1894 1895 if (xfer == NULL) 1896 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1897 chp->ch_channel, msg); 1898 else 1899 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1900 chp->ch_channel, xfer->c_drive, msg); 1901 } 1902 1903 /* 1904 * the bit bucket 1905 */ 1906 void 1907 wdcbit_bucket(struct ata_channel *chp, int size) 1908 { 1909 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1910 1911 for (; size >= 2; size -= 2) 1912 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1913 if (size) 1914 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1915 } 1916 1917 static void 1918 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1919 { 1920 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1921 1922 #ifndef __NO_STRICT_ALIGNMENT 1923 if ((uintptr_t)bf & 1) 1924 goto unaligned; 1925 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1926 goto unaligned; 1927 #endif 1928 1929 if (flags & ATA_DRIVE_NOSTREAM) { 1930 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1931 bus_space_read_multi_4(wdr->data32iot, 1932 wdr->data32ioh, 0, bf, len >> 2); 1933 bf = (char *)bf + (len & ~3); 1934 len &= 3; 1935 } 1936 if (len > 1) { 1937 bus_space_read_multi_2(wdr->cmd_iot, 1938 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1939 bf = (char *)bf + (len & ~1); 1940 len &= 1; 1941 } 1942 } else { 1943 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1944 bus_space_read_multi_stream_4(wdr->data32iot, 1945 wdr->data32ioh, 0, bf, len >> 2); 1946 bf = (char *)bf + (len & ~3); 1947 len &= 3; 1948 } 1949 if (len > 1) { 1950 bus_space_read_multi_stream_2(wdr->cmd_iot, 1951 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1952 bf = (char *)bf + (len & ~1); 1953 len &= 1; 1954 } 1955 } 1956 if (len) 1957 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1958 wdr->cmd_iohs[wd_data], 0); 1959 return; 1960 1961 #ifndef __NO_STRICT_ALIGNMENT 1962 unaligned: 1963 if (flags & ATA_DRIVE_NOSTREAM) { 1964 if (flags & ATA_DRIVE_CAP32) { 1965 while (len > 3) { 1966 uint32_t val; 1967 1968 val = bus_space_read_4(wdr->data32iot, 1969 wdr->data32ioh, 0); 1970 memcpy(bf, &val, 4); 1971 bf = (char *)bf + 4; 1972 len -= 4; 1973 } 1974 } 1975 while (len > 1) { 1976 uint16_t val; 1977 1978 val = bus_space_read_2(wdr->cmd_iot, 1979 wdr->cmd_iohs[wd_data], 0); 1980 memcpy(bf, &val, 2); 1981 bf = (char *)bf + 2; 1982 len -= 2; 1983 } 1984 } else { 1985 if (flags & ATA_DRIVE_CAP32) { 1986 while (len > 3) { 1987 uint32_t val; 1988 1989 val = bus_space_read_stream_4(wdr->data32iot, 1990 wdr->data32ioh, 0); 1991 memcpy(bf, &val, 4); 1992 bf = (char *)bf + 4; 1993 len -= 4; 1994 } 1995 } 1996 while (len > 1) { 1997 uint16_t val; 1998 1999 val = bus_space_read_stream_2(wdr->cmd_iot, 2000 wdr->cmd_iohs[wd_data], 0); 2001 memcpy(bf, &val, 2); 2002 bf = (char *)bf + 2; 2003 len -= 2; 2004 } 2005 } 2006 #endif 2007 } 2008 2009 static void 2010 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2011 { 2012 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2013 2014 #ifndef __NO_STRICT_ALIGNMENT 2015 if ((uintptr_t)bf & 1) 2016 goto unaligned; 2017 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2018 goto unaligned; 2019 #endif 2020 2021 if (flags & ATA_DRIVE_NOSTREAM) { 2022 if (flags & ATA_DRIVE_CAP32) { 2023 bus_space_write_multi_4(wdr->data32iot, 2024 wdr->data32ioh, 0, bf, len >> 2); 2025 bf = (char *)bf + (len & ~3); 2026 len &= 3; 2027 } 2028 if (len) { 2029 bus_space_write_multi_2(wdr->cmd_iot, 2030 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2031 } 2032 } else { 2033 if (flags & ATA_DRIVE_CAP32) { 2034 bus_space_write_multi_stream_4(wdr->data32iot, 2035 wdr->data32ioh, 0, bf, len >> 2); 2036 bf = (char *)bf + (len & ~3); 2037 len &= 3; 2038 } 2039 if (len) { 2040 bus_space_write_multi_stream_2(wdr->cmd_iot, 2041 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2042 } 2043 } 2044 return; 2045 2046 #ifndef __NO_STRICT_ALIGNMENT 2047 unaligned: 2048 if (flags & ATA_DRIVE_NOSTREAM) { 2049 if (flags & ATA_DRIVE_CAP32) { 2050 while (len > 3) { 2051 uint32_t val; 2052 2053 memcpy(&val, bf, 4); 2054 bus_space_write_4(wdr->data32iot, 2055 wdr->data32ioh, 0, val); 2056 bf = (char *)bf + 4; 2057 len -= 4; 2058 } 2059 } 2060 while (len > 1) { 2061 uint16_t val; 2062 2063 memcpy(&val, bf, 2); 2064 bus_space_write_2(wdr->cmd_iot, 2065 wdr->cmd_iohs[wd_data], 0, val); 2066 bf = (char *)bf + 2; 2067 len -= 2; 2068 } 2069 } else { 2070 if (flags & ATA_DRIVE_CAP32) { 2071 while (len > 3) { 2072 uint32_t val; 2073 2074 memcpy(&val, bf, 4); 2075 bus_space_write_stream_4(wdr->data32iot, 2076 wdr->data32ioh, 0, val); 2077 bf = (char *)bf + 4; 2078 len -= 4; 2079 } 2080 } 2081 while (len > 1) { 2082 uint16_t val; 2083 2084 memcpy(&val, bf, 2); 2085 bus_space_write_stream_2(wdr->cmd_iot, 2086 wdr->cmd_iohs[wd_data], 0, val); 2087 bf = (char *)bf + 2; 2088 len -= 2; 2089 } 2090 } 2091 #endif 2092 } 2093
Indexes created Wed Sep 24 15:09:51 GMT 2025