wdc.c revision 1.300
1 /* $NetBSD: wdc.c,v 1.300 2020/05/19 08:21:29 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.300 2020/05/19 08:21:29 jdolecek Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then kpause for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 .bustype_type = SCSIPI_BUSTYPE_ATA, 130 .ata_bio = NULL, 131 .ata_reset_drive = NULL, 132 .ata_reset_channel = wdc_reset_channel, 133 .ata_exec_command = wdc_exec_command, 134 .ata_get_params = NULL, 135 .ata_addref = NULL, 136 .ata_delref = NULL, 137 .ata_killpending = NULL, 138 .ata_recovery = NULL, 139 }; 140 #endif 141 142 /* Flags to wdcreset(). */ 143 #define RESET_POLL 1 144 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 145 146 static int wdcprobe1(struct ata_channel *, int); 147 static int wdcreset(struct ata_channel *, int); 148 static void __wdcerror(struct ata_channel *, const char *); 149 static int __wdcwait_reset(struct ata_channel *, int, int); 150 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_kill_xfer(struct ata_channel *, 154 struct ata_xfer *, int); 155 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 156 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 157 static int __wdcwait(struct ata_channel *, int, int, int, int *); 158 159 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 160 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 161 #define DEBUG_INTR 0x01 162 #define DEBUG_XFERS 0x02 163 #define DEBUG_STATUS 0x04 164 #define DEBUG_FUNCS 0x08 165 #define DEBUG_PROBE 0x10 166 #define DEBUG_DETACH 0x20 167 #define DEBUG_DELAY 0x40 168 #ifdef ATADEBUG 169 extern int atadebug_mask; /* init'ed in ata.c */ 170 int wdc_nxfer = 0; 171 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 172 #else 173 #define ATADEBUG_PRINT(args, level) 174 #endif 175 176 /* 177 * Initialize the "shadow register" handles for a standard wdc controller. 178 */ 179 void 180 wdc_init_shadow_regs(struct wdc_regs *wdr) 181 { 182 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 183 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 184 } 185 186 /* 187 * Allocate a wdc_regs array, based on the number of channels. 188 */ 189 void 190 wdc_allocate_regs(struct wdc_softc *wdc) 191 { 192 193 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 194 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 195 } 196 197 #if NSATA > 0 198 /* 199 * probe drives on SATA controllers with standard SATA registers: 200 * bring the PHYs online, read the drive signature and set drive flags 201 * appropriately. 202 */ 203 void 204 wdc_sataprobe(struct ata_channel *chp) 205 { 206 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 207 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 208 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 209 int i; 210 211 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 212 213 /* do this before we take lock */ 214 215 ata_channel_lock(chp); 216 217 /* reset the PHY and bring online */ 218 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 219 wdr->sata_status, AT_WAIT)) { 220 case SStatus_DET_DEV: 221 /* wait 5s for BSY to clear */ 222 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 223 bus_space_write_1(wdr->cmd_iot, 224 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 225 delay(10); /* 400ns delay */ 226 st = bus_space_read_1(wdr->cmd_iot, 227 wdr->cmd_iohs[wd_status], 0); 228 if ((st & WDCS_BSY) == 0) 229 break; 230 ata_delay(chp, 1, "sataprb", AT_WAIT); 231 } 232 if (i == WDC_PROBE_WAIT * hz) 233 aprint_error_dev(chp->ch_atac->atac_dev, 234 "BSY never cleared, status 0x%02x\n", st); 235 sc = bus_space_read_1(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_seccnt], 0); 237 sn = bus_space_read_1(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_sector], 0); 239 cl = bus_space_read_1(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_lo], 0); 241 ch = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_cyl_hi], 0); 243 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 244 "cl=0x%x ch=0x%x\n", 245 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 246 sc, sn, cl, ch), DEBUG_PROBE); 247 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 248 return; 249 /* 250 * sc and sn are supposed to be 0x1 for ATAPI, but in some 251 * cases we get wrong values here, so ignore it. 252 */ 253 if (cl == 0x14 && ch == 0xeb) 254 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 255 else 256 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 257 258 /* 259 * issue a reset in case only the interface part of the drive 260 * is up 261 */ 262 if (wdcreset(chp, RESET_SLEEP) != 0) 263 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 264 break; 265 266 default: 267 break; 268 } 269 270 ata_channel_unlock(chp); 271 } 272 #endif /* NSATA > 0 */ 273 274 275 /* Test to see controller with at last one attached drive is there. 276 * Returns a bit for each possible drive found (0x01 for drive 0, 277 * 0x02 for drive 1). 278 * Logic: 279 * - If a status register is at 0xff, assume there is no drive here 280 * (ISA has pull-up resistors). Similarly if the status register has 281 * the value we last wrote to the bus (for IDE interfaces without pullups). 282 * If no drive at all -> return. 283 * - reset the controller, wait for it to complete (may take up to 31s !). 284 * If timeout -> return. 285 * - test ATA/ATAPI signatures. If at last one drive found -> return. 286 * - try an ATA command on the master. 287 */ 288 289 void 290 wdc_drvprobe(struct ata_channel *chp) 291 { 292 struct ataparams params; /* XXX: large struct */ 293 struct atac_softc *atac = chp->ch_atac; 294 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 295 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 296 u_int8_t st0 = 0, st1 = 0; 297 int i, j, error, tfd; 298 299 ata_channel_lock(chp); 300 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 301 ata_channel_unlock(chp); 302 return; 303 } 304 if (wdcprobe1(chp, 0) == 0) { 305 /* No drives, abort the attach here. */ 306 atabus_free_drives(chp); 307 ata_channel_unlock(chp); 308 return; 309 } 310 311 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 312 for (i = 0; i < mstohz(3000); i++) { 313 /* 314 * select drive 1 first, so that master is selected on 315 * exit from the loop 316 */ 317 if (chp->ch_ndrives > 1 && 318 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 319 if (wdc->select) 320 wdc->select(chp,1); 321 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 322 0, WDSD_IBM | 0x10); 323 delay(10); /* 400ns delay */ 324 st1 = bus_space_read_1(wdr->cmd_iot, 325 wdr->cmd_iohs[wd_status], 0); 326 } 327 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 328 if (wdc->select) 329 wdc->select(chp,0); 330 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 331 0, WDSD_IBM); 332 delay(10); /* 400ns delay */ 333 st0 = bus_space_read_1(wdr->cmd_iot, 334 wdr->cmd_iohs[wd_status], 0); 335 } 336 337 338 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 339 (st0 & WDCS_DRDY)) && 340 (chp->ch_ndrives < 2 || 341 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 342 (st1 & WDCS_DRDY))) 343 break; 344 #ifdef WDC_NO_IDS 345 /* cannot kpause here (can't enable IPL_BIO interrups), 346 * delay instead 347 */ 348 delay(1000000 / hz); 349 #else 350 ata_delay(chp, 1, "atadrdy", AT_WAIT); 351 #endif 352 } 353 if ((st0 & WDCS_DRDY) == 0 && 354 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 355 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 356 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 357 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 358 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 359 ata_channel_unlock(chp); 360 361 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 362 device_xname(atac->atac_dev), 363 chp->ch_channel, st0, st1), DEBUG_PROBE); 364 365 /* Wait a bit, some devices are weird just after a reset. */ 366 delay(5000); 367 368 for (i = 0; i < chp->ch_ndrives; i++) { 369 #if NATA_DMA 370 /* 371 * Init error counter so that an error within the first xfers 372 * will trigger a downgrade 373 */ 374 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 375 #endif 376 377 /* If controller can't do 16bit flag the drives as 32bit */ 378 if ((atac->atac_cap & 379 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 380 ata_channel_lock(chp); 381 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 382 ata_channel_unlock(chp); 383 } 384 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 385 continue; 386 387 /* Shortcut in case we've been shutdown */ 388 if (chp->ch_flags & ATACH_SHUTDOWN) 389 return; 390 391 /* 392 * Issue an identify, to try to detect ghosts. 393 * Note that we can't use interrupts here, because if there 394 * is no devices, we will get a command aborted without 395 * interrupts. 396 */ 397 error = ata_get_params(&chp->ch_drive[i], 398 AT_WAIT | AT_POLL, ¶ms); 399 if (error != CMD_OK) { 400 ata_channel_lock(chp); 401 ata_delay(chp, 1000, "atacnf", AT_WAIT); 402 ata_channel_unlock(chp); 403 404 /* Shortcut in case we've been shutdown */ 405 if (chp->ch_flags & ATACH_SHUTDOWN) 406 return; 407 408 error = ata_get_params(&chp->ch_drive[i], 409 AT_WAIT | AT_POLL, ¶ms); 410 } 411 if (error != CMD_OK) { 412 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 413 device_xname(atac->atac_dev), 414 chp->ch_channel, i, error), DEBUG_PROBE); 415 ata_channel_lock(chp); 416 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 417 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 418 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 419 ata_channel_unlock(chp); 420 continue; 421 } 422 /* 423 * Pre-ATA drive ? 424 * Test registers writability (Error register not 425 * writable, but cyllo is), then try an ATA command. 426 */ 427 if (wdc->select) 428 wdc->select(chp,i); 429 bus_space_write_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 431 delay(10); /* 400ns delay */ 432 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 433 0, 0x58); 434 bus_space_write_1(wdr->cmd_iot, 435 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 436 if (bus_space_read_1(wdr->cmd_iot, 437 wdr->cmd_iohs[wd_error], 0) == 0x58 || 438 bus_space_read_1(wdr->cmd_iot, 439 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 440 ATADEBUG_PRINT(("%s:%d:%d: register " 441 "writability failed\n", 442 device_xname(atac->atac_dev), 443 chp->ch_channel, i), DEBUG_PROBE); 444 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 445 ata_channel_unlock(chp); 446 continue; 447 } 448 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 449 WDCWAIT_TOUT) { 450 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 451 device_xname(atac->atac_dev), 452 chp->ch_channel, i), DEBUG_PROBE); 453 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 454 ata_channel_unlock(chp); 455 continue; 456 } 457 bus_space_write_1(wdr->cmd_iot, 458 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 459 delay(10); /* 400ns delay */ 460 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 461 WDCWAIT_TOUT) { 462 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 463 device_xname(atac->atac_dev), 464 chp->ch_channel, i), DEBUG_PROBE); 465 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 466 ata_channel_unlock(chp); 467 } else { 468 for (j = 0; j < chp->ch_ndrives; j++) { 469 if (chp->ch_drive[i].drive_type != 470 ATA_DRIVET_NONE) { 471 chp->ch_drive[j].drive_type = 472 ATA_DRIVET_OLD; 473 } 474 } 475 ata_channel_unlock(chp); 476 } 477 } 478 } 479 } 480 481 int 482 wdcprobe(struct wdc_regs *wdr) 483 { 484 485 return wdcprobe_with_reset(wdr, NULL); 486 } 487 488 int 489 wdcprobe_with_reset(struct wdc_regs *wdr, 490 void (*do_reset)(struct ata_channel *, int)) 491 { 492 struct wdc_softc wdc; 493 struct ata_channel ch; 494 int rv; 495 496 memset(&wdc, 0, sizeof(wdc)); 497 memset(&ch, 0, sizeof(ch)); 498 ata_channel_init(&ch); 499 ch.ch_atac = &wdc.sc_atac; 500 wdc.regs = wdr; 501 502 /* check the MD reset method */ 503 wdc.reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 504 505 ata_channel_lock(&ch); 506 rv = wdcprobe1(&ch, 1); 507 ata_channel_unlock(&ch); 508 509 ata_channel_destroy(&ch); 510 511 return rv; 512 } 513 514 static int 515 wdcprobe1(struct ata_channel *chp, int poll) 516 { 517 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 518 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 519 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 520 u_int8_t ret_value = 0x03; 521 u_int8_t drive; 522 /* XXX if poll, wdc_probe_count is 0. */ 523 int wdc_probe_count = 524 poll ? (WDC_PROBE_WAIT / WDCDELAY) 525 : (WDC_PROBE_WAIT * hz); 526 527 /* 528 * Sanity check to see if the wdc channel responds at all. 529 */ 530 531 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 532 while (wdc_probe_count-- > 0) { 533 if (wdc->select) 534 wdc->select(chp,0); 535 536 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 537 0, WDSD_IBM); 538 delay(10); /* 400ns delay */ 539 st0 = bus_space_read_1(wdr->cmd_iot, 540 wdr->cmd_iohs[wd_status], 0); 541 542 if (wdc->select) 543 wdc->select(chp,1); 544 545 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 546 0, WDSD_IBM | 0x10); 547 delay(10); /* 400ns delay */ 548 st1 = bus_space_read_1(wdr->cmd_iot, 549 wdr->cmd_iohs[wd_status], 0); 550 if ((st0 & WDCS_BSY) == 0) 551 break; 552 } 553 554 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 555 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 556 557 if (st0 == 0xff || st0 == WDSD_IBM) 558 ret_value &= ~0x01; 559 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 560 ret_value &= ~0x02; 561 /* Register writability test, drive 0. */ 562 if (ret_value & 0x01) { 563 if (wdc->select) 564 wdc->select(chp,0); 565 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 566 0, WDSD_IBM); 567 bus_space_write_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 569 cl = bus_space_read_1(wdr->cmd_iot, 570 wdr->cmd_iohs[wd_cyl_lo], 0); 571 if (cl != 0x02) { 572 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 573 "got 0x%x != 0x02\n", 574 __func__, chp->ch_channel, cl), 575 DEBUG_PROBE); 576 ret_value &= ~0x01; 577 } 578 bus_space_write_1(wdr->cmd_iot, 579 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 580 cl = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_cyl_lo], 0); 582 if (cl != 0x01) { 583 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 584 "got 0x%x != 0x01\n", 585 __func__, chp->ch_channel, cl), 586 DEBUG_PROBE); 587 ret_value &= ~0x01; 588 } 589 bus_space_write_1(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_sector], 0, 0x01); 591 cl = bus_space_read_1(wdr->cmd_iot, 592 wdr->cmd_iohs[wd_sector], 0); 593 if (cl != 0x01) { 594 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 595 "got 0x%x != 0x01\n", 596 __func__, chp->ch_channel, cl), 597 DEBUG_PROBE); 598 ret_value &= ~0x01; 599 } 600 bus_space_write_1(wdr->cmd_iot, 601 wdr->cmd_iohs[wd_sector], 0, 0x02); 602 cl = bus_space_read_1(wdr->cmd_iot, 603 wdr->cmd_iohs[wd_sector], 0); 604 if (cl != 0x02) { 605 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 606 "got 0x%x != 0x02\n", 607 __func__, chp->ch_channel, cl), 608 DEBUG_PROBE); 609 ret_value &= ~0x01; 610 } 611 cl = bus_space_read_1(wdr->cmd_iot, 612 wdr->cmd_iohs[wd_cyl_lo], 0); 613 if (cl != 0x01) { 614 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 615 "got 0x%x != 0x01\n", 616 __func__, chp->ch_channel, cl), 617 DEBUG_PROBE); 618 ret_value &= ~0x01; 619 } 620 } 621 /* Register writability test, drive 1. */ 622 if (ret_value & 0x02) { 623 if (wdc->select) 624 wdc->select(chp,1); 625 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 626 0, WDSD_IBM | 0x10); 627 bus_space_write_1(wdr->cmd_iot, 628 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 629 cl = bus_space_read_1(wdr->cmd_iot, 630 wdr->cmd_iohs[wd_cyl_lo], 0); 631 if (cl != 0x02) { 632 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 633 "got 0x%x != 0x02\n", 634 __func__, chp->ch_channel, cl), 635 DEBUG_PROBE); 636 ret_value &= ~0x02; 637 } 638 bus_space_write_1(wdr->cmd_iot, 639 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 640 cl = bus_space_read_1(wdr->cmd_iot, 641 wdr->cmd_iohs[wd_cyl_lo], 0); 642 if (cl != 0x01) { 643 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 644 "got 0x%x != 0x01\n", 645 __func__, chp->ch_channel, cl), 646 DEBUG_PROBE); 647 ret_value &= ~0x02; 648 } 649 bus_space_write_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_sector], 0, 0x01); 651 cl = bus_space_read_1(wdr->cmd_iot, 652 wdr->cmd_iohs[wd_sector], 0); 653 if (cl != 0x01) { 654 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 655 "got 0x%x != 0x01\n", 656 __func__, chp->ch_channel, cl), 657 DEBUG_PROBE); 658 ret_value &= ~0x02; 659 } 660 bus_space_write_1(wdr->cmd_iot, 661 wdr->cmd_iohs[wd_sector], 0, 0x02); 662 cl = bus_space_read_1(wdr->cmd_iot, 663 wdr->cmd_iohs[wd_sector], 0); 664 if (cl != 0x02) { 665 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 666 "got 0x%x != 0x02\n", 667 __func__, chp->ch_channel, cl), 668 DEBUG_PROBE); 669 ret_value &= ~0x02; 670 } 671 cl = bus_space_read_1(wdr->cmd_iot, 672 wdr->cmd_iohs[wd_cyl_lo], 0); 673 if (cl != 0x01) { 674 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 675 "got 0x%x != 0x01\n", 676 __func__, chp->ch_channel, cl), 677 DEBUG_PROBE); 678 ret_value &= ~0x02; 679 } 680 } 681 682 if (ret_value == 0) { 683 return 0; 684 } 685 } 686 687 #if 0 /* XXX this break some ATA or ATAPI devices */ 688 /* 689 * reset bus. Also send an ATAPI_RESET to devices, in case there are 690 * ATAPI device out there which don't react to the bus reset 691 */ 692 if (ret_value & 0x01) { 693 if (wdc->select) 694 wdc->select(chp,0); 695 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 696 0, WDSD_IBM); 697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 698 ATAPI_SOFT_RESET); 699 } 700 if (ret_value & 0x02) { 701 if (wdc->select) 702 wdc->select(chp,0); 703 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 704 0, WDSD_IBM | 0x10); 705 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 706 ATAPI_SOFT_RESET); 707 } 708 709 delay(5000); 710 #endif 711 712 wdc->reset(chp, RESET_POLL); 713 DELAY(2000); 714 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 715 716 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 717 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 718 WDCTL_4BIT); 719 720 #ifdef WDC_NO_IDS 721 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 722 #else 723 ret_value = __wdcwait_reset(chp, ret_value, poll); 724 #endif 725 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 726 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 727 728 /* if reset failed, there's nothing here */ 729 if (ret_value == 0) { 730 return 0; 731 } 732 733 /* 734 * Test presence of drives. First test register signatures looking 735 * for ATAPI devices. If it's not an ATAPI and reset said there may 736 * be something here assume it's ATA or OLD. Ghost will be killed 737 * later in attach routine. 738 */ 739 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 740 if ((ret_value & (0x01 << drive)) == 0) 741 continue; 742 if (wdc->select) 743 wdc->select(chp,drive); 744 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 745 WDSD_IBM | (drive << 4)); 746 delay(10); /* 400ns delay */ 747 /* Save registers contents */ 748 sc = bus_space_read_1(wdr->cmd_iot, 749 wdr->cmd_iohs[wd_seccnt], 0); 750 sn = bus_space_read_1(wdr->cmd_iot, 751 wdr->cmd_iohs[wd_sector], 0); 752 cl = bus_space_read_1(wdr->cmd_iot, 753 wdr->cmd_iohs[wd_cyl_lo], 0); 754 ch = bus_space_read_1(wdr->cmd_iot, 755 wdr->cmd_iohs[wd_cyl_hi], 0); 756 757 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 758 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 759 sn, cl, ch), DEBUG_PROBE); 760 /* 761 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 762 * we get wrong values here, so ignore it. 763 */ 764 if (chp->ch_drive != NULL) { 765 if (cl == 0x14 && ch == 0xeb) { 766 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 767 } else { 768 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 769 } 770 } 771 } 772 /* 773 * Select an existing drive before lowering spl, some WDC_NO_IDS 774 * devices incorrectly assert IRQ on nonexistent slave 775 */ 776 if (ret_value & 0x01) { 777 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 778 WDSD_IBM); 779 (void)bus_space_read_1(wdr->cmd_iot, 780 wdr->cmd_iohs[wd_status], 0); 781 } 782 return (ret_value); 783 } 784 785 void 786 wdcattach(struct ata_channel *chp) 787 { 788 struct atac_softc *atac = chp->ch_atac; 789 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 790 791 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 792 793 /* default data transfer methods */ 794 if (wdc->datain_pio == NULL) 795 wdc->datain_pio = wdc_datain_pio; 796 if (wdc->dataout_pio == NULL) 797 wdc->dataout_pio = wdc_dataout_pio; 798 /* default reset method */ 799 if (wdc->reset == NULL) 800 wdc->reset = wdc_do_reset; 801 802 /* initialise global data */ 803 if (atac->atac_bustype_ata == NULL) 804 atac->atac_bustype_ata = &wdc_ata_bustype; 805 if (atac->atac_probe == NULL) 806 atac->atac_probe = wdc_drvprobe; 807 #if NATAPIBUS > 0 808 if (atac->atac_atapibus_attach == NULL) 809 atac->atac_atapibus_attach = wdc_atapibus_attach; 810 #endif 811 812 ata_channel_attach(chp); 813 } 814 815 void 816 wdc_childdetached(device_t self, device_t child) 817 { 818 struct atac_softc *atac = device_private(self); 819 struct ata_channel *chp; 820 int i; 821 822 for (i = 0; i < atac->atac_nchannels; i++) { 823 chp = atac->atac_channels[i]; 824 if (child == chp->atabus) { 825 chp->atabus = NULL; 826 return; 827 } 828 } 829 } 830 831 int 832 wdcdetach(device_t self, int flags) 833 { 834 struct atac_softc *atac = device_private(self); 835 struct ata_channel *chp; 836 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 837 int i, error = 0; 838 839 for (i = 0; i < atac->atac_nchannels; i++) { 840 chp = atac->atac_channels[i]; 841 if (chp->atabus == NULL) 842 continue; 843 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 844 device_xname(atac->atac_dev), device_xname(chp->atabus)), 845 DEBUG_DETACH); 846 if ((error = config_detach(chp->atabus, flags)) != 0) 847 return error; 848 ata_channel_detach(chp); 849 } 850 if (adapt->adapt_refcnt != 0) 851 return EBUSY; 852 return 0; 853 } 854 855 /* restart an interrupted I/O */ 856 void 857 wdcrestart(void *v) 858 { 859 struct ata_channel *chp = v; 860 int s; 861 862 s = splbio(); 863 atastart(chp); 864 splx(s); 865 } 866 867 868 /* 869 * Interrupt routine for the controller. Acknowledge the interrupt, check for 870 * errors on the current operation, mark it done if necessary, and start the 871 * next request. Also check for a partially done transfer, and continue with 872 * the next chunk if so. 873 */ 874 int 875 wdcintr(void *arg) 876 { 877 struct ata_channel *chp = arg; 878 struct atac_softc *atac = chp->ch_atac; 879 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 880 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 881 struct ata_xfer *xfer; 882 int ret; 883 884 if (!device_is_active(atac->atac_dev)) { 885 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 886 DEBUG_INTR); 887 return (0); 888 } 889 890 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 891 __wdcerror(chp, "irq not expected"); 892 goto ignore; 893 } 894 895 xfer = ata_queue_get_active_xfer(chp); 896 if (xfer == NULL) { 897 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 898 ignore: 899 /* try to clear the pending interrupt anyway */ 900 (void)bus_space_read_1(wdr->cmd_iot, 901 wdr->cmd_iohs[wd_status], 0); 902 return (0); 903 } 904 905 /* 906 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 907 * actually has no effect, and interrupt is triggered regardless. 908 * Ignore polled commands here, they are processed separately. 909 */ 910 if (ISSET(xfer->c_flags, C_POLL)) { 911 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 912 DEBUG_INTR); 913 goto ignore; 914 } 915 916 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 917 KASSERT(xfer != NULL); 918 919 #if NATA_DMA || NATA_PIOBM 920 if (chp->ch_flags & ATACH_DMA_WAIT) { 921 wdc->dma_status = 922 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 923 xfer->c_drive, WDC_DMAEND_END); 924 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 925 /* IRQ not for us, not detected by DMA engine */ 926 return 0; 927 } 928 chp->ch_flags &= ~ATACH_DMA_WAIT; 929 } 930 #endif 931 chp->ch_flags &= ~ATACH_IRQ_WAIT; 932 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 933 ret = xfer->ops->c_intr(chp, xfer, 1); 934 if (ret == 0) /* irq was not for us, still waiting for irq */ 935 chp->ch_flags |= ATACH_IRQ_WAIT; 936 return (ret); 937 } 938 939 /* Put all disk in RESET state */ 940 void 941 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 942 { 943 struct ata_channel *chp = drvp->chnl_softc; 944 945 ata_channel_lock_owned(chp); 946 947 KASSERT(sigp == NULL); 948 949 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 950 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 951 drvp->drive), DEBUG_FUNCS); 952 953 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 954 } 955 956 void 957 wdc_reset_channel(struct ata_channel *chp, int flags) 958 { 959 struct ata_xfer *xfer; 960 961 ata_channel_lock_owned(chp); 962 963 #if NATA_DMA || NATA_PIOBM 964 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 965 #endif 966 967 chp->ch_flags &= ~ATACH_IRQ_WAIT; 968 969 /* 970 * if the current command is on an ATAPI device, issue a 971 * ATAPI_SOFT_RESET 972 */ 973 xfer = ata_queue_get_active_xfer_locked(chp); 974 975 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 976 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 977 ata_delay(chp, 1000, "atardl", flags); 978 } 979 980 /* reset the channel */ 981 if (flags & AT_WAIT) 982 (void) wdcreset(chp, RESET_SLEEP); 983 else 984 (void) wdcreset(chp, RESET_POLL); 985 986 /* 987 * wait a bit after reset; in case the DMA engines needs some time 988 * to recover. 989 */ 990 ata_delay(chp, 1000, "atardl", flags); 991 992 /* 993 * Look for pending xfers. If we have a shared queue, we'll also reset 994 * the other channel if the current xfer is running on it. 995 * Then we'll kill the eventual active transfer explicitely, so that 996 * it is queued for retry immediatelly without waiting for I/O timeout. 997 */ 998 if (xfer) { 999 if (xfer->c_chp != chp) { 1000 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 1001 ATACH_NODRIVE); 1002 } else { 1003 #if NATA_DMA || NATA_PIOBM 1004 /* 1005 * If we're waiting for DMA, stop the 1006 * DMA engine 1007 */ 1008 if (chp->ch_flags & ATACH_DMA_WAIT) { 1009 (*wdc->dma_finish)(wdc->dma_arg, 1010 chp->ch_channel, xfer->c_drive, 1011 WDC_DMAEND_ABRT_QUIET); 1012 chp->ch_flags &= ~ATACH_DMA_WAIT; 1013 } 1014 #endif 1015 } 1016 } 1017 1018 ata_kill_active(chp, KILL_RESET, flags); 1019 } 1020 1021 static int 1022 wdcreset(struct ata_channel *chp, int poll) 1023 { 1024 struct atac_softc *atac = chp->ch_atac; 1025 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1026 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1027 int drv_mask1, drv_mask2; 1028 1029 ata_channel_lock_owned(chp); 1030 1031 #ifdef WDC_NO_IDS 1032 poll = RESET_POLL; 1033 #endif 1034 wdc->reset(chp, poll); 1035 1036 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1037 ? 0x01 : 0x00; 1038 if (chp->ch_ndrives > 1) 1039 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1040 ? 0x02 : 0x00; 1041 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1042 (poll == RESET_SLEEP) ? 0 : 1); 1043 if (drv_mask2 != drv_mask1) { 1044 aprint_error("%s channel %d: reset failed for", 1045 device_xname(atac->atac_dev), chp->ch_channel); 1046 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1047 aprint_normal(" drive 0"); 1048 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1049 aprint_normal(" drive 1"); 1050 aprint_normal("\n"); 1051 } 1052 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1053 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1054 WDCTL_4BIT); 1055 1056 return (drv_mask1 != drv_mask2) ? 1 : 0; 1057 } 1058 1059 void 1060 wdc_do_reset(struct ata_channel *chp, int poll) 1061 { 1062 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1063 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1064 int s = 0; 1065 1066 if (poll != RESET_SLEEP) 1067 s = splbio(); 1068 if (wdc->select) 1069 wdc->select(chp,0); 1070 /* master */ 1071 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1072 delay(10); /* 400ns delay */ 1073 /* assert SRST, wait for reset to complete */ 1074 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1075 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1076 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1077 delay(2000); 1078 } 1079 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1080 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1081 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1082 WDCTL_4BIT | WDCTL_IDS); 1083 delay(10); /* 400ns delay */ 1084 if (poll != RESET_SLEEP) { 1085 /* ACK interrupt in case there is one pending left */ 1086 if (wdc->irqack) 1087 wdc->irqack(chp); 1088 splx(s); 1089 } 1090 } 1091 1092 static int 1093 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1094 { 1095 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1096 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1097 int timeout, nloop; 1098 int wflags = poll ? AT_POLL : AT_WAIT; 1099 u_int8_t st0 = 0, st1 = 0; 1100 #ifdef ATADEBUG 1101 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1102 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1103 #endif 1104 if (poll) 1105 nloop = WDCNDELAY_RST; 1106 else 1107 nloop = WDC_RESET_WAIT * hz / 1000; 1108 /* wait for BSY to deassert */ 1109 for (timeout = 0; timeout < nloop; timeout++) { 1110 if ((drv_mask & 0x01) != 0) { 1111 if (wdc->select) 1112 wdc->select(chp,0); 1113 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1114 0, WDSD_IBM); /* master */ 1115 delay(10); 1116 st0 = bus_space_read_1(wdr->cmd_iot, 1117 wdr->cmd_iohs[wd_status], 0); 1118 #ifdef ATADEBUG 1119 sc0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_seccnt], 0); 1121 sn0 = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_sector], 0); 1123 cl0 = bus_space_read_1(wdr->cmd_iot, 1124 wdr->cmd_iohs[wd_cyl_lo], 0); 1125 ch0 = bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_cyl_hi], 0); 1127 #endif 1128 } 1129 if ((drv_mask & 0x02) != 0) { 1130 if (wdc->select) 1131 wdc->select(chp,1); 1132 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1133 0, WDSD_IBM | 0x10); /* slave */ 1134 delay(10); 1135 st1 = bus_space_read_1(wdr->cmd_iot, 1136 wdr->cmd_iohs[wd_status], 0); 1137 #ifdef ATADEBUG 1138 sc1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_seccnt], 0); 1140 sn1 = bus_space_read_1(wdr->cmd_iot, 1141 wdr->cmd_iohs[wd_sector], 0); 1142 cl1 = bus_space_read_1(wdr->cmd_iot, 1143 wdr->cmd_iohs[wd_cyl_lo], 0); 1144 ch1 = bus_space_read_1(wdr->cmd_iot, 1145 wdr->cmd_iohs[wd_cyl_hi], 0); 1146 #endif 1147 } 1148 1149 if ((drv_mask & 0x01) == 0) { 1150 /* no master */ 1151 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1152 /* No master, slave is ready, it's done */ 1153 goto end; 1154 } 1155 if ((drv_mask & 0x02) == 0) { 1156 /* No master, no slave: it's done */ 1157 goto end; 1158 } 1159 } else if ((drv_mask & 0x02) == 0) { 1160 /* no slave */ 1161 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1162 /* No slave, master is ready, it's done */ 1163 goto end; 1164 } 1165 } else { 1166 /* Wait for both master and slave to be ready */ 1167 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1168 goto end; 1169 } 1170 } 1171 ata_delay(chp, WDCDELAY, "atarst", wflags); 1172 } 1173 /* Reset timed out. Maybe it's because drv_mask was not right */ 1174 if (st0 & WDCS_BSY) 1175 drv_mask &= ~0x01; 1176 if (st1 & WDCS_BSY) 1177 drv_mask &= ~0x02; 1178 end: 1179 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1180 "cl=0x%x ch=0x%x\n", 1181 device_xname(chp->ch_atac->atac_dev), 1182 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1183 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1184 "cl=0x%x ch=0x%x\n", 1185 device_xname(chp->ch_atac->atac_dev), 1186 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1187 1188 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1189 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1190 st0, st1), DEBUG_PROBE); 1191 1192 return drv_mask; 1193 } 1194 1195 /* 1196 * Wait for a drive to be !BSY, and have mask in its status register. 1197 * return -1 for a timeout after "timeout" ms. 1198 */ 1199 static int 1200 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1201 { 1202 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1203 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1204 u_char status, error = 0; 1205 int xtime = 0; 1206 int rv; 1207 1208 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1209 device_xname(chp->ch_atac->atac_dev), 1210 chp->ch_channel), DEBUG_STATUS); 1211 *tfd = 0; 1212 1213 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1214 1215 for (;;) { 1216 status = 1217 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1218 if ((status & (WDCS_BSY | mask)) == bits) 1219 break; 1220 if (++xtime > timeout) { 1221 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1222 "status %x error %x (mask 0x%x bits 0x%x)\n", 1223 xtime, status, 1224 bus_space_read_1(wdr->cmd_iot, 1225 wdr->cmd_iohs[wd_error], 0), mask, bits), 1226 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1227 rv = WDCWAIT_TOUT; 1228 goto out; 1229 } 1230 delay(WDCDELAY); 1231 } 1232 #ifdef ATADEBUG 1233 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1234 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1235 #endif 1236 if (status & WDCS_ERR) 1237 error = bus_space_read_1(wdr->cmd_iot, 1238 wdr->cmd_iohs[wd_error], 0); 1239 #ifdef WDCNDELAY_DEBUG 1240 /* After autoconfig, there should be no long delays. */ 1241 if (!cold && xtime > WDCNDELAY_DEBUG) { 1242 struct ata_xfer *xfer; 1243 1244 xfer = ata_queue_get_active_xfer_locked(chp); 1245 if (xfer == NULL) 1246 printf("%s channel %d: warning: busy-wait took %dus\n", 1247 device_xname(chp->ch_atac->atac_dev), 1248 chp->ch_channel, WDCDELAY * xtime); 1249 else 1250 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1251 device_xname(chp->ch_atac->atac_dev), 1252 chp->ch_channel, xfer->c_drive, 1253 WDCDELAY * xtime); 1254 } 1255 #endif 1256 rv = WDCWAIT_OK; 1257 1258 out: 1259 *tfd = ATACH_ERR_ST(error, status); 1260 return rv; 1261 } 1262 1263 /* 1264 * Call __wdcwait(), polling using kpause() or waking up the kernel 1265 * thread if possible 1266 */ 1267 int 1268 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1269 int *tfd) 1270 { 1271 int error, i, timeout_hz = mstohz(timeout); 1272 1273 ata_channel_lock_owned(chp); 1274 1275 if (timeout_hz == 0 || 1276 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1277 error = __wdcwait(chp, mask, bits, timeout, tfd); 1278 else { 1279 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1280 if (error != 0) { 1281 if (ata_is_thread_run(chp) || (flags & AT_WAIT)) { 1282 /* 1283 * we're running in the channel thread 1284 * or some userland thread context 1285 */ 1286 for (i = 0; i < timeout_hz; i++) { 1287 if (__wdcwait(chp, mask, bits, 1288 WDCDELAY_POLL, tfd) == 0) { 1289 error = 0; 1290 break; 1291 } 1292 kpause("atapoll", true, 1, 1293 &chp->ch_lock); 1294 } 1295 } else { 1296 /* 1297 * we're probably in interrupt context, 1298 * caller must ask the thread to come back here 1299 */ 1300 return(WDCWAIT_THR); 1301 } 1302 } 1303 } 1304 return (error); 1305 } 1306 1307 1308 #if NATA_DMA 1309 /* 1310 * Busy-wait for DMA to complete 1311 */ 1312 int 1313 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1314 { 1315 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1316 int xtime; 1317 1318 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1319 wdc->dma_status = 1320 (*wdc->dma_finish)(wdc->dma_arg, 1321 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1322 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1323 return 0; 1324 delay(WDCDELAY); 1325 } 1326 /* timeout, force a DMA halt */ 1327 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1328 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1329 return 1; 1330 } 1331 #endif 1332 1333 void 1334 wdctimeout(void *arg) 1335 { 1336 struct ata_xfer *xfer; 1337 struct ata_channel *chp = arg; 1338 #if NATA_DMA || NATA_PIOBM 1339 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1340 #endif 1341 int s; 1342 1343 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1344 1345 s = splbio(); 1346 1347 callout_ack(&chp->c_timo_callout); 1348 1349 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 1350 __wdcerror(chp, "timeout not expected without pending irq"); 1351 goto out; 1352 } 1353 1354 xfer = ata_queue_get_active_xfer(chp); 1355 KASSERT(xfer != NULL); 1356 1357 if (ata_timo_xfer_check(xfer)) { 1358 /* Already logged */ 1359 goto out; 1360 } 1361 1362 __wdcerror(chp, "lost interrupt"); 1363 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1364 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1365 xfer->c_bcount, xfer->c_skip); 1366 #if NATA_DMA || NATA_PIOBM 1367 if (chp->ch_flags & ATACH_DMA_WAIT) { 1368 wdc->dma_status = 1369 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1370 xfer->c_drive, WDC_DMAEND_ABRT); 1371 chp->ch_flags &= ~ATACH_DMA_WAIT; 1372 } 1373 #endif 1374 /* 1375 * Call the interrupt routine. If we just missed an interrupt, 1376 * it will do what's needed. Else, it will take the needed 1377 * action (reset the device). 1378 * Before that we need to reinstall the timeout callback, 1379 * in case it will miss another irq while in this transfer 1380 * We arbitray chose it to be 1s 1381 */ 1382 callout_reset(&chp->c_timo_callout, hz, wdctimeout, chp); 1383 xfer->c_flags |= C_TIMEOU; 1384 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1385 xfer->ops->c_intr(chp, xfer, 1); 1386 1387 out: 1388 splx(s); 1389 } 1390 1391 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1392 .c_start = __wdccommand_start, 1393 .c_poll = __wdccommand_poll, 1394 .c_abort = __wdccommand_done, 1395 .c_intr = __wdccommand_intr, 1396 .c_kill_xfer = __wdccommand_kill_xfer, 1397 }; 1398 1399 void 1400 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1401 { 1402 struct ata_channel *chp = drvp->chnl_softc; 1403 struct ata_command *ata_c = &xfer->c_ata_c; 1404 1405 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1406 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1407 drvp->drive), DEBUG_FUNCS); 1408 1409 /* set up an xfer and queue. Wait for completion */ 1410 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1411 ata_c->flags |= AT_POLL; 1412 if (ata_c->flags & AT_POLL) 1413 xfer->c_flags |= C_POLL; 1414 if (ata_c->flags & AT_WAIT) 1415 xfer->c_flags |= C_WAIT; 1416 xfer->c_drive = drvp->drive; 1417 xfer->c_databuf = ata_c->data; 1418 xfer->c_bcount = ata_c->bcount; 1419 xfer->ops = &wdc_cmd_xfer_ops; 1420 1421 ata_exec_xfer(chp, xfer); 1422 } 1423 1424 static int 1425 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1426 { 1427 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1428 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1429 int drive = xfer->c_drive; 1430 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1431 struct ata_command *ata_c = &xfer->c_ata_c; 1432 int tfd; 1433 1434 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1435 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1436 xfer->c_drive), DEBUG_FUNCS); 1437 1438 if (wdc->select) 1439 wdc->select(chp,drive); 1440 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1441 WDSD_IBM | (drive << 4)); 1442 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1443 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1444 case WDCWAIT_OK: 1445 break; 1446 case WDCWAIT_TOUT: 1447 ata_c->flags |= AT_TIMEOU; 1448 return ATASTART_ABORT; 1449 case WDCWAIT_THR: 1450 return ATASTART_TH; 1451 } 1452 if (ata_c->flags & AT_POLL) { 1453 /* polled command, disable interrupts */ 1454 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1455 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1456 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1457 } 1458 if ((ata_c->flags & AT_LBA48) != 0) { 1459 wdccommandext(chp, drive, ata_c->r_command, 1460 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1461 ata_c->r_device & ~0x10); 1462 } else { 1463 wdccommand(chp, drive, ata_c->r_command, 1464 (ata_c->r_lba >> 8) & 0xffff, 1465 WDSD_IBM | (drive << 4) | 1466 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1467 ((ata_c->r_lba >> 24) & 0x0f), 1468 ata_c->r_lba & 0xff, 1469 ata_c->r_count & 0xff, 1470 ata_c->r_features & 0xff); 1471 } 1472 1473 if ((ata_c->flags & AT_POLL) == 0) { 1474 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1475 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1476 wdctimeout, chp); 1477 return ATASTART_STARTED; 1478 } 1479 1480 /* 1481 * Polled command. Wait for drive ready or drq. Done in intr(). 1482 * Wait for at last 400ns for status bit to be valid. 1483 */ 1484 delay(10); /* 400ns delay */ 1485 return ATASTART_POLL; 1486 } 1487 1488 static void 1489 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1490 { 1491 __wdccommand_intr(chp, xfer, 0); 1492 } 1493 1494 static int 1495 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1496 { 1497 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1498 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1499 struct ata_command *ata_c = &xfer->c_ata_c; 1500 int bcount = ata_c->bcount; 1501 char *data = ata_c->data; 1502 int wflags, tfd; 1503 int drive_flags; 1504 1505 if (ata_c->r_command == WDCC_IDENTIFY || 1506 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1507 /* 1508 * The IDENTIFY data has been designed as an array of 1509 * u_int16_t, so we can byteswap it on the fly. 1510 * Historically it's what we have always done so keeping it 1511 * here ensure binary backward compatibility. 1512 */ 1513 drive_flags = ATA_DRIVE_NOSTREAM | 1514 chp->ch_drive[xfer->c_drive].drive_flags; 1515 } else { 1516 /* 1517 * Other data structure are opaque and should be transferred 1518 * as is. 1519 */ 1520 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1521 } 1522 1523 #ifdef WDC_NO_IDS 1524 wflags = AT_POLL; 1525 #else 1526 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1527 /* both wait and poll, we can kpause here */ 1528 wflags = AT_WAIT | AT_POLL; 1529 } else { 1530 wflags = AT_POLL; 1531 } 1532 #endif 1533 1534 ata_channel_lock(chp); 1535 1536 again: 1537 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1538 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1539 xfer->c_drive), DEBUG_INTR); 1540 /* 1541 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1542 * Reselect again, it doesn't hurt for others commands, and the time 1543 * penalty for the extra register write is acceptable, 1544 * wdc_exec_command() isn't called often (mostly for autoconfig) 1545 */ 1546 if ((xfer->c_flags & C_ATAPI) != 0) { 1547 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1548 WDSD_IBM | (xfer->c_drive << 4)); 1549 } 1550 if ((ata_c->flags & AT_XFDONE) != 0) { 1551 /* 1552 * We have completed a data xfer. The drive should now be 1553 * in its initial state 1554 */ 1555 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1556 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1557 wflags, &tfd) == WDCWAIT_TOUT) { 1558 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1559 ata_channel_unlock(chp); 1560 return 0; /* IRQ was not for us */ 1561 } 1562 ata_c->flags |= AT_TIMEOU; 1563 } 1564 goto out; 1565 } 1566 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1567 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1568 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1569 ata_channel_unlock(chp); 1570 return 0; /* IRQ was not for us */ 1571 } 1572 ata_c->flags |= AT_TIMEOU; 1573 goto out; 1574 } 1575 if (wdc->irqack) 1576 wdc->irqack(chp); 1577 if (ata_c->flags & AT_READ) { 1578 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1579 ata_c->flags |= AT_TIMEOU; 1580 goto out; 1581 } 1582 wdc->datain_pio(chp, drive_flags, data, bcount); 1583 /* at this point the drive should be in its initial state */ 1584 ata_c->flags |= AT_XFDONE; 1585 /* 1586 * XXX checking the status register again here cause some 1587 * hardware to timeout. 1588 */ 1589 } else if (ata_c->flags & AT_WRITE) { 1590 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1591 ata_c->flags |= AT_TIMEOU; 1592 goto out; 1593 } 1594 wdc->dataout_pio(chp, drive_flags, data, bcount); 1595 ata_c->flags |= AT_XFDONE; 1596 if ((ata_c->flags & AT_POLL) == 0) { 1597 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1598 callout_reset(&chp->c_timo_callout, 1599 mstohz(ata_c->timeout), wdctimeout, chp); 1600 ata_channel_unlock(chp); 1601 return 1; 1602 } else { 1603 goto again; 1604 } 1605 } 1606 out: 1607 if (ATACH_ST(tfd) & WDCS_DWF) 1608 ata_c->flags |= AT_DF; 1609 if (ATACH_ST(tfd) & WDCS_ERR) { 1610 ata_c->flags |= AT_ERROR; 1611 ata_c->r_error = ATACH_ST(tfd); 1612 } 1613 1614 ata_channel_unlock(chp); 1615 1616 __wdccommand_done(chp, xfer); 1617 return 1; 1618 } 1619 1620 static void 1621 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1622 { 1623 struct atac_softc *atac = chp->ch_atac; 1624 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1625 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1626 struct ata_command *ata_c = &xfer->c_ata_c; 1627 bool start = true; 1628 1629 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1630 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1631 ata_c->flags), DEBUG_FUNCS); 1632 1633 if (ata_waitdrain_xfer_check(chp, xfer)) { 1634 start = false; 1635 goto out; 1636 } 1637 1638 if ((ata_c->flags & AT_READREG) != 0 && 1639 device_is_active(atac->atac_dev) && 1640 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1641 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1642 wdr->cmd_iohs[wd_status], 0); 1643 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1644 wdr->cmd_iohs[wd_error], 0); 1645 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1646 wdr->cmd_iohs[wd_seccnt], 0); 1647 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_sector], 0) << 0; 1649 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1651 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1652 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1653 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1654 wdr->cmd_iohs[wd_sdh], 0); 1655 1656 if ((ata_c->flags & AT_LBA48) != 0) { 1657 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1658 if ((ata_c->flags & AT_POLL) != 0) 1659 bus_space_write_1(wdr->ctl_iot, 1660 wdr->ctl_ioh, wd_aux_ctlr, 1661 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1662 else 1663 bus_space_write_1(wdr->ctl_iot, 1664 wdr->ctl_ioh, wd_aux_ctlr, 1665 WDCTL_HOB|WDCTL_4BIT); 1666 } 1667 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1668 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1669 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1670 wdr->cmd_iohs[wd_sector], 0) << 24; 1671 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1672 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1673 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1674 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1675 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1676 if ((ata_c->flags & AT_POLL) != 0) 1677 bus_space_write_1(wdr->ctl_iot, 1678 wdr->ctl_ioh, wd_aux_ctlr, 1679 WDCTL_4BIT|WDCTL_IDS); 1680 else 1681 bus_space_write_1(wdr->ctl_iot, 1682 wdr->ctl_ioh, wd_aux_ctlr, 1683 WDCTL_4BIT); 1684 } 1685 } else { 1686 ata_c->r_lba |= 1687 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1688 } 1689 ata_c->r_device &= 0xf0; 1690 } 1691 1692 __wdccommand_done_end(chp, xfer); 1693 1694 ata_deactivate_xfer(chp, xfer); 1695 1696 out: 1697 if (ata_c->flags & AT_POLL) { 1698 /* enable interrupts */ 1699 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1700 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1701 wd_aux_ctlr, WDCTL_4BIT); 1702 delay(10); /* some drives need a little delay here */ 1703 } 1704 1705 if (start) 1706 atastart(chp); 1707 } 1708 1709 static void 1710 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1711 { 1712 struct ata_command *ata_c = &xfer->c_ata_c; 1713 1714 ata_c->flags |= AT_DONE; 1715 } 1716 1717 static void 1718 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1719 int reason) 1720 { 1721 struct ata_command *ata_c = &xfer->c_ata_c; 1722 bool deactivate = true; 1723 1724 switch (reason) { 1725 case KILL_GONE_INACTIVE: 1726 deactivate = false; 1727 /* FALLTHROUGH */ 1728 case KILL_GONE: 1729 ata_c->flags |= AT_GONE; 1730 break; 1731 case KILL_RESET: 1732 ata_c->flags |= AT_RESET; 1733 break; 1734 default: 1735 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1736 reason); 1737 panic("__wdccommand_kill_xfer"); 1738 } 1739 1740 __wdccommand_done_end(chp, xfer); 1741 1742 if (deactivate) 1743 ata_deactivate_xfer(chp, xfer); 1744 } 1745 1746 /* 1747 * Send a command. The drive should be ready. 1748 * Assumes interrupts are blocked. 1749 */ 1750 void 1751 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1752 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1753 u_int8_t features) 1754 { 1755 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1756 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1757 1758 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1759 "sector=%d count=%d features=%d\n", 1760 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1761 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1762 1763 if (wdc->select) 1764 wdc->select(chp,drive); 1765 1766 /* Select drive, head, and addressing mode. */ 1767 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1768 WDSD_IBM | (drive << 4) | head); 1769 /* Load parameters into the wd_features register. */ 1770 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1771 features); 1772 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1773 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1774 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1775 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1776 0, cylin >> 8); 1777 1778 /* Send command. */ 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1780 return; 1781 } 1782 1783 /* 1784 * Send a 48-bit addressing command. The drive should be ready. 1785 * Assumes interrupts are blocked. 1786 */ 1787 void 1788 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1789 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1790 { 1791 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1792 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1793 1794 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1795 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1796 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1797 chp->ch_channel, drive, command, blkno, count, features, device), 1798 DEBUG_FUNCS); 1799 1800 KASSERT(drive < wdc->wdc_maxdrives); 1801 1802 if (wdc->select) 1803 wdc->select(chp,drive); 1804 1805 /* Select drive, head, and addressing mode. */ 1806 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1807 (drive << 4) | device); 1808 1809 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1810 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1811 0, features); 1812 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1813 0, count); 1814 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1815 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1816 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1817 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1818 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1819 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1820 } else { 1821 /* previous */ 1822 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1823 0, features >> 8); 1824 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1825 0, count >> 8); 1826 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1827 0, blkno >> 24); 1828 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1829 0, blkno >> 32); 1830 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1831 0, blkno >> 40); 1832 1833 /* current */ 1834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1835 0, features); 1836 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1837 0, count); 1838 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1839 0, blkno); 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1841 0, blkno >> 8); 1842 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1843 0, blkno >> 16); 1844 } 1845 1846 /* Send command. */ 1847 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1848 return; 1849 } 1850 1851 /* 1852 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1853 * tested by the caller. 1854 */ 1855 void 1856 wdccommandshort(struct ata_channel *chp, int drive, int command) 1857 { 1858 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1859 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1860 1861 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1862 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1863 command), DEBUG_FUNCS); 1864 1865 if (wdc->select) 1866 wdc->select(chp,drive); 1867 1868 /* Select drive. */ 1869 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1870 WDSD_IBM | (drive << 4)); 1871 1872 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1873 } 1874 1875 static void 1876 __wdcerror(struct ata_channel *chp, const char *msg) 1877 { 1878 struct atac_softc *atac = chp->ch_atac; 1879 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1880 1881 if (xfer == NULL) 1882 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1883 chp->ch_channel, msg); 1884 else 1885 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1886 chp->ch_channel, xfer->c_drive, msg); 1887 } 1888 1889 /* 1890 * the bit bucket 1891 */ 1892 void 1893 wdcbit_bucket(struct ata_channel *chp, int size) 1894 { 1895 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1896 1897 for (; size >= 2; size -= 2) 1898 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1899 if (size) 1900 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1901 } 1902 1903 static void 1904 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1905 { 1906 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1907 1908 #ifndef __NO_STRICT_ALIGNMENT 1909 if ((uintptr_t)bf & 1) 1910 goto unaligned; 1911 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1912 goto unaligned; 1913 #endif 1914 1915 if (flags & ATA_DRIVE_NOSTREAM) { 1916 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1917 bus_space_read_multi_4(wdr->data32iot, 1918 wdr->data32ioh, 0, bf, len >> 2); 1919 bf = (char *)bf + (len & ~3); 1920 len &= 3; 1921 } 1922 if (len > 1) { 1923 bus_space_read_multi_2(wdr->cmd_iot, 1924 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1925 bf = (char *)bf + (len & ~1); 1926 len &= 1; 1927 } 1928 } else { 1929 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1930 bus_space_read_multi_stream_4(wdr->data32iot, 1931 wdr->data32ioh, 0, bf, len >> 2); 1932 bf = (char *)bf + (len & ~3); 1933 len &= 3; 1934 } 1935 if (len > 1) { 1936 bus_space_read_multi_stream_2(wdr->cmd_iot, 1937 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1938 bf = (char *)bf + (len & ~1); 1939 len &= 1; 1940 } 1941 } 1942 if (len) 1943 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1944 wdr->cmd_iohs[wd_data], 0); 1945 return; 1946 1947 #ifndef __NO_STRICT_ALIGNMENT 1948 unaligned: 1949 if (flags & ATA_DRIVE_NOSTREAM) { 1950 if (flags & ATA_DRIVE_CAP32) { 1951 while (len > 3) { 1952 uint32_t val; 1953 1954 val = bus_space_read_4(wdr->data32iot, 1955 wdr->data32ioh, 0); 1956 memcpy(bf, &val, 4); 1957 bf = (char *)bf + 4; 1958 len -= 4; 1959 } 1960 } 1961 while (len > 1) { 1962 uint16_t val; 1963 1964 val = bus_space_read_2(wdr->cmd_iot, 1965 wdr->cmd_iohs[wd_data], 0); 1966 memcpy(bf, &val, 2); 1967 bf = (char *)bf + 2; 1968 len -= 2; 1969 } 1970 } else { 1971 if (flags & ATA_DRIVE_CAP32) { 1972 while (len > 3) { 1973 uint32_t val; 1974 1975 val = bus_space_read_stream_4(wdr->data32iot, 1976 wdr->data32ioh, 0); 1977 memcpy(bf, &val, 4); 1978 bf = (char *)bf + 4; 1979 len -= 4; 1980 } 1981 } 1982 while (len > 1) { 1983 uint16_t val; 1984 1985 val = bus_space_read_stream_2(wdr->cmd_iot, 1986 wdr->cmd_iohs[wd_data], 0); 1987 memcpy(bf, &val, 2); 1988 bf = (char *)bf + 2; 1989 len -= 2; 1990 } 1991 } 1992 #endif 1993 } 1994 1995 static void 1996 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1997 { 1998 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1999 2000 #ifndef __NO_STRICT_ALIGNMENT 2001 if ((uintptr_t)bf & 1) 2002 goto unaligned; 2003 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2004 goto unaligned; 2005 #endif 2006 2007 if (flags & ATA_DRIVE_NOSTREAM) { 2008 if (flags & ATA_DRIVE_CAP32) { 2009 bus_space_write_multi_4(wdr->data32iot, 2010 wdr->data32ioh, 0, bf, len >> 2); 2011 bf = (char *)bf + (len & ~3); 2012 len &= 3; 2013 } 2014 if (len) { 2015 bus_space_write_multi_2(wdr->cmd_iot, 2016 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2017 } 2018 } else { 2019 if (flags & ATA_DRIVE_CAP32) { 2020 bus_space_write_multi_stream_4(wdr->data32iot, 2021 wdr->data32ioh, 0, bf, len >> 2); 2022 bf = (char *)bf + (len & ~3); 2023 len &= 3; 2024 } 2025 if (len) { 2026 bus_space_write_multi_stream_2(wdr->cmd_iot, 2027 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2028 } 2029 } 2030 return; 2031 2032 #ifndef __NO_STRICT_ALIGNMENT 2033 unaligned: 2034 if (flags & ATA_DRIVE_NOSTREAM) { 2035 if (flags & ATA_DRIVE_CAP32) { 2036 while (len > 3) { 2037 uint32_t val; 2038 2039 memcpy(&val, bf, 4); 2040 bus_space_write_4(wdr->data32iot, 2041 wdr->data32ioh, 0, val); 2042 bf = (char *)bf + 4; 2043 len -= 4; 2044 } 2045 } 2046 while (len > 1) { 2047 uint16_t val; 2048 2049 memcpy(&val, bf, 2); 2050 bus_space_write_2(wdr->cmd_iot, 2051 wdr->cmd_iohs[wd_data], 0, val); 2052 bf = (char *)bf + 2; 2053 len -= 2; 2054 } 2055 } else { 2056 if (flags & ATA_DRIVE_CAP32) { 2057 while (len > 3) { 2058 uint32_t val; 2059 2060 memcpy(&val, bf, 4); 2061 bus_space_write_stream_4(wdr->data32iot, 2062 wdr->data32ioh, 0, val); 2063 bf = (char *)bf + 4; 2064 len -= 4; 2065 } 2066 } 2067 while (len > 1) { 2068 uint16_t val; 2069 2070 memcpy(&val, bf, 2); 2071 bus_space_write_stream_2(wdr->cmd_iot, 2072 wdr->cmd_iohs[wd_data], 0, val); 2073 bf = (char *)bf + 2; 2074 len -= 2; 2075 } 2076 } 2077 #endif 2078 } 2079
Indexes created Tue Sep 23 14:10:03 GMT 2025