wdc.c revision 1.305
1 /* $NetBSD: wdc.c,v 1.305 2021/01/04 15:13:50 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.305 2021/01/04 15:13:50 skrll Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/kmem.h> 74 #include <sys/syslog.h> 75 #include <sys/proc.h> 76 77 #include <sys/intr.h> 78 #include <sys/bus.h> 79 80 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 81 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 82 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 83 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 84 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 85 #define bus_space_read_stream_2 bus_space_read_2 86 #define bus_space_read_stream_4 bus_space_read_4 87 #define bus_space_write_stream_2 bus_space_write_2 88 #define bus_space_write_stream_4 bus_space_write_4 89 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 90 91 #include <dev/ata/atavar.h> 92 #include <dev/ata/atareg.h> 93 #include <dev/ata/satareg.h> 94 #include <dev/ata/satavar.h> 95 #include <dev/ic/wdcreg.h> 96 #include <dev/ic/wdcvar.h> 97 98 #include "locators.h" 99 100 #include "atapibus.h" 101 #include "wd.h" 102 #include "sata.h" 103 104 #define WDCDELAY 100 /* 100 microseconds */ 105 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 106 #if 0 107 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 108 #define WDCNDELAY_DEBUG 50 109 #endif 110 111 /* When polling wait that much and then kpause for 1/hz seconds */ 112 #define WDCDELAY_POLL 1 /* ms */ 113 114 /* timeout for the control commands */ 115 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 116 117 /* 118 * timeout when waiting for BSY to deassert when probing. 119 * set to 5s. From the standards this could be up to 31, but we can't 120 * wait that much at boot time, and 5s seems to be enough. 121 */ 122 #define WDC_PROBE_WAIT 5 123 124 125 #if NWD > 0 126 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 127 #else 128 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 129 const struct ata_bustype wdc_ata_bustype = { 130 .bustype_type = SCSIPI_BUSTYPE_ATA, 131 .ata_bio = NULL, 132 .ata_reset_drive = NULL, 133 .ata_reset_channel = wdc_reset_channel, 134 .ata_exec_command = wdc_exec_command, 135 .ata_get_params = NULL, 136 .ata_addref = NULL, 137 .ata_delref = NULL, 138 .ata_killpending = NULL, 139 .ata_recovery = NULL, 140 }; 141 #endif 142 143 /* Flags to wdcreset(). */ 144 #define RESET_POLL 1 145 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 146 147 static int wdcprobe1(struct ata_channel *, int); 148 static int wdcreset(struct ata_channel *, int); 149 static void __wdcerror(struct ata_channel *, const char *); 150 static int __wdcwait_reset(struct ata_channel *, int, int); 151 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 154 static void __wdccommand_kill_xfer(struct ata_channel *, 155 struct ata_xfer *, int); 156 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 157 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 158 static int __wdcwait(struct ata_channel *, int, int, int, int *); 159 160 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 161 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 162 #define DEBUG_INTR 0x01 163 #define DEBUG_XFERS 0x02 164 #define DEBUG_STATUS 0x04 165 #define DEBUG_FUNCS 0x08 166 #define DEBUG_PROBE 0x10 167 #define DEBUG_DETACH 0x20 168 #define DEBUG_DELAY 0x40 169 #ifdef ATADEBUG 170 extern int atadebug_mask; /* init'ed in ata.c */ 171 int wdc_nxfer = 0; 172 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 173 #else 174 #define ATADEBUG_PRINT(args, level) 175 #endif 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct wdc_regs *wdr) 182 { 183 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 184 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 185 } 186 187 /* 188 * Allocate a wdc_regs array, based on the number of channels. 189 */ 190 void 191 wdc_allocate_regs(struct wdc_softc *wdc) 192 { 193 194 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 195 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 196 } 197 198 #if NSATA > 0 199 /* 200 * probe drives on SATA controllers with standard SATA registers: 201 * bring the PHYs online, read the drive signature and set drive flags 202 * appropriately. 203 */ 204 void 205 wdc_sataprobe(struct ata_channel *chp) 206 { 207 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 208 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 209 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 210 int i; 211 212 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 213 214 /* do this before we take lock */ 215 216 ata_channel_lock(chp); 217 218 /* reset the PHY and bring online */ 219 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 220 wdr->sata_status, AT_WAIT)) { 221 case SStatus_DET_DEV: 222 /* wait 5s for BSY to clear */ 223 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 224 bus_space_write_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 226 delay(10); /* 400ns delay */ 227 st = bus_space_read_1(wdr->cmd_iot, 228 wdr->cmd_iohs[wd_status], 0); 229 if ((st & WDCS_BSY) == 0) 230 break; 231 ata_delay(chp, 1, "sataprb", AT_WAIT); 232 } 233 if (i == WDC_PROBE_WAIT * hz) 234 aprint_error_dev(chp->ch_atac->atac_dev, 235 "BSY never cleared, status 0x%02x\n", st); 236 sc = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_seccnt], 0); 238 sn = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_sector], 0); 240 cl = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_lo], 0); 242 ch = bus_space_read_1(wdr->cmd_iot, 243 wdr->cmd_iohs[wd_cyl_hi], 0); 244 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 245 "cl=0x%x ch=0x%x\n", 246 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 247 sc, sn, cl, ch), DEBUG_PROBE); 248 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 249 return; 250 /* 251 * sc and sn are supposed to be 0x1 for ATAPI, but in some 252 * cases we get wrong values here, so ignore it. 253 */ 254 if (cl == 0x14 && ch == 0xeb) 255 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 256 else 257 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 258 259 /* 260 * issue a reset in case only the interface part of the drive 261 * is up 262 */ 263 if (wdcreset(chp, RESET_SLEEP) != 0) 264 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 265 break; 266 267 default: 268 break; 269 } 270 271 ata_channel_unlock(chp); 272 } 273 #endif /* NSATA > 0 */ 274 275 276 /* Test to see controller with at last one attached drive is there. 277 * Returns a bit for each possible drive found (0x01 for drive 0, 278 * 0x02 for drive 1). 279 * Logic: 280 * - If a status register is at 0xff, assume there is no drive here 281 * (ISA has pull-up resistors). Similarly if the status register has 282 * the value we last wrote to the bus (for IDE interfaces without pullups). 283 * If no drive at all -> return. 284 * - reset the controller, wait for it to complete (may take up to 31s !). 285 * If timeout -> return. 286 * - test ATA/ATAPI signatures. If at last one drive found -> return. 287 * - try an ATA command on the master. 288 */ 289 290 void 291 wdc_drvprobe(struct ata_channel *chp) 292 { 293 struct ataparams params; /* XXX: large struct */ 294 struct atac_softc *atac = chp->ch_atac; 295 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 296 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 297 u_int8_t st0 = 0, st1 = 0; 298 int i, j, error, tfd; 299 300 ata_channel_lock(chp); 301 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 302 ata_channel_unlock(chp); 303 return; 304 } 305 if (wdcprobe1(chp, 0) == 0) { 306 /* No drives, abort the attach here. */ 307 atabus_free_drives(chp); 308 ata_channel_unlock(chp); 309 return; 310 } 311 312 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 313 for (i = 0; i < mstohz(3000); i++) { 314 /* 315 * select drive 1 first, so that master is selected on 316 * exit from the loop 317 */ 318 if (chp->ch_ndrives > 1 && 319 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 320 if (wdc->select) 321 wdc->select(chp,1); 322 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 323 0, WDSD_IBM | 0x10); 324 delay(10); /* 400ns delay */ 325 st1 = bus_space_read_1(wdr->cmd_iot, 326 wdr->cmd_iohs[wd_status], 0); 327 } 328 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 329 if (wdc->select) 330 wdc->select(chp,0); 331 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 332 0, WDSD_IBM); 333 delay(10); /* 400ns delay */ 334 st0 = bus_space_read_1(wdr->cmd_iot, 335 wdr->cmd_iohs[wd_status], 0); 336 } 337 338 339 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 340 (st0 & WDCS_DRDY)) && 341 (chp->ch_ndrives < 2 || 342 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 343 (st1 & WDCS_DRDY))) 344 break; 345 #ifdef WDC_NO_IDS 346 /* cannot kpause here (can't enable IPL_BIO interrupts), 347 * delay instead 348 */ 349 delay(1000000 / hz); 350 #else 351 ata_delay(chp, 1, "atadrdy", AT_WAIT); 352 #endif 353 } 354 if ((st0 & WDCS_DRDY) == 0 && 355 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 356 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 357 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 358 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 359 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 360 ata_channel_unlock(chp); 361 362 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 363 device_xname(atac->atac_dev), 364 chp->ch_channel, st0, st1), DEBUG_PROBE); 365 366 /* Wait a bit, some devices are weird just after a reset. */ 367 delay(5000); 368 369 for (i = 0; i < chp->ch_ndrives; i++) { 370 #if NATA_DMA 371 /* 372 * Init error counter so that an error within the first xfers 373 * will trigger a downgrade 374 */ 375 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 376 #endif 377 378 /* If controller can't do 16bit flag the drives as 32bit */ 379 if ((atac->atac_cap & 380 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 381 ata_channel_lock(chp); 382 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 383 ata_channel_unlock(chp); 384 } 385 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 386 continue; 387 388 /* Shortcut in case we've been shutdown */ 389 if (chp->ch_flags & ATACH_SHUTDOWN) 390 return; 391 392 /* 393 * Issue an identify, to try to detect ghosts. 394 * Note that we can't use interrupts here, because if there 395 * is no devices, we will get a command aborted without 396 * interrupts. 397 */ 398 error = ata_get_params(&chp->ch_drive[i], 399 AT_WAIT | AT_POLL, ¶ms); 400 if (error != CMD_OK) { 401 ata_channel_lock(chp); 402 ata_delay(chp, 1000, "atacnf", AT_WAIT); 403 ata_channel_unlock(chp); 404 405 /* Shortcut in case we've been shutdown */ 406 if (chp->ch_flags & ATACH_SHUTDOWN) 407 return; 408 409 error = ata_get_params(&chp->ch_drive[i], 410 AT_WAIT | AT_POLL, ¶ms); 411 } 412 if (error != CMD_OK) { 413 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 414 device_xname(atac->atac_dev), 415 chp->ch_channel, i, error), DEBUG_PROBE); 416 ata_channel_lock(chp); 417 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 418 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 419 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 420 ata_channel_unlock(chp); 421 continue; 422 } 423 /* 424 * Pre-ATA drive ? 425 * Test registers writability (Error register not 426 * writable, but cyllo is), then try an ATA command. 427 */ 428 if (wdc->select) 429 wdc->select(chp,i); 430 bus_space_write_1(wdr->cmd_iot, 431 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 432 delay(10); /* 400ns delay */ 433 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 434 0, 0x58); 435 bus_space_write_1(wdr->cmd_iot, 436 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 437 if (bus_space_read_1(wdr->cmd_iot, 438 wdr->cmd_iohs[wd_error], 0) == 0x58 || 439 bus_space_read_1(wdr->cmd_iot, 440 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 441 ATADEBUG_PRINT(("%s:%d:%d: register " 442 "writability failed\n", 443 device_xname(atac->atac_dev), 444 chp->ch_channel, i), DEBUG_PROBE); 445 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 446 ata_channel_unlock(chp); 447 continue; 448 } 449 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 450 WDCWAIT_TOUT) { 451 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 452 device_xname(atac->atac_dev), 453 chp->ch_channel, i), DEBUG_PROBE); 454 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 455 ata_channel_unlock(chp); 456 continue; 457 } 458 bus_space_write_1(wdr->cmd_iot, 459 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 460 delay(10); /* 400ns delay */ 461 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 462 WDCWAIT_TOUT) { 463 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 464 device_xname(atac->atac_dev), 465 chp->ch_channel, i), DEBUG_PROBE); 466 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 467 ata_channel_unlock(chp); 468 } else { 469 for (j = 0; j < chp->ch_ndrives; j++) { 470 if (chp->ch_drive[i].drive_type != 471 ATA_DRIVET_NONE) { 472 chp->ch_drive[j].drive_type = 473 ATA_DRIVET_OLD; 474 } 475 } 476 ata_channel_unlock(chp); 477 } 478 } 479 } 480 } 481 482 int 483 wdcprobe(struct wdc_regs *wdr) 484 { 485 486 return wdcprobe_with_reset(wdr, NULL); 487 } 488 489 int 490 wdcprobe_with_reset(struct wdc_regs *wdr, 491 void (*do_reset)(struct ata_channel *, int)) 492 { 493 struct wdc_softc *wdc; 494 struct ata_channel *ch; 495 int rv; 496 497 wdc = kmem_zalloc(sizeof(*wdc), KM_SLEEP); 498 ch = kmem_zalloc(sizeof(*ch), KM_SLEEP); 499 500 ata_channel_init(ch); 501 ch->ch_atac = &wdc->sc_atac; 502 wdc->regs = wdr; 503 504 /* check the MD reset method */ 505 wdc->reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 506 507 ata_channel_lock(ch); 508 rv = wdcprobe1(ch, 1); 509 ata_channel_unlock(ch); 510 511 ata_channel_destroy(ch); 512 513 kmem_free(ch, sizeof(*ch)); 514 kmem_free(wdc, sizeof(*wdc)); 515 516 return rv; 517 } 518 519 static int 520 wdcprobe1(struct ata_channel *chp, int poll) 521 { 522 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 523 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 524 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 525 u_int8_t ret_value = 0x03; 526 u_int8_t drive; 527 /* XXX if poll, wdc_probe_count is 0. */ 528 int wdc_probe_count = 529 poll ? (WDC_PROBE_WAIT / WDCDELAY) 530 : (WDC_PROBE_WAIT * hz); 531 532 /* 533 * Sanity check to see if the wdc channel responds at all. 534 */ 535 536 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 537 while (wdc_probe_count-- > 0) { 538 if (wdc->select) 539 wdc->select(chp,0); 540 541 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 542 0, WDSD_IBM); 543 delay(10); /* 400ns delay */ 544 st0 = bus_space_read_1(wdr->cmd_iot, 545 wdr->cmd_iohs[wd_status], 0); 546 547 if (wdc->select) 548 wdc->select(chp,1); 549 550 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 551 0, WDSD_IBM | 0x10); 552 delay(10); /* 400ns delay */ 553 st1 = bus_space_read_1(wdr->cmd_iot, 554 wdr->cmd_iohs[wd_status], 0); 555 if ((st0 & WDCS_BSY) == 0) 556 break; 557 } 558 559 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 560 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 561 562 if (st0 == 0xff || st0 == WDSD_IBM) 563 ret_value &= ~0x01; 564 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 565 ret_value &= ~0x02; 566 /* Register writability test, drive 0. */ 567 if (ret_value & 0x01) { 568 if (wdc->select) 569 wdc->select(chp,0); 570 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 571 0, WDSD_IBM); 572 bus_space_write_1(wdr->cmd_iot, 573 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 574 cl = bus_space_read_1(wdr->cmd_iot, 575 wdr->cmd_iohs[wd_cyl_lo], 0); 576 if (cl != 0x02) { 577 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 578 "got 0x%x != 0x02\n", 579 __func__, chp->ch_channel, cl), 580 DEBUG_PROBE); 581 ret_value &= ~0x01; 582 } 583 bus_space_write_1(wdr->cmd_iot, 584 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 585 cl = bus_space_read_1(wdr->cmd_iot, 586 wdr->cmd_iohs[wd_cyl_lo], 0); 587 if (cl != 0x01) { 588 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 589 "got 0x%x != 0x01\n", 590 __func__, chp->ch_channel, cl), 591 DEBUG_PROBE); 592 ret_value &= ~0x01; 593 } 594 bus_space_write_1(wdr->cmd_iot, 595 wdr->cmd_iohs[wd_sector], 0, 0x01); 596 cl = bus_space_read_1(wdr->cmd_iot, 597 wdr->cmd_iohs[wd_sector], 0); 598 if (cl != 0x01) { 599 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 600 "got 0x%x != 0x01\n", 601 __func__, chp->ch_channel, cl), 602 DEBUG_PROBE); 603 ret_value &= ~0x01; 604 } 605 bus_space_write_1(wdr->cmd_iot, 606 wdr->cmd_iohs[wd_sector], 0, 0x02); 607 cl = bus_space_read_1(wdr->cmd_iot, 608 wdr->cmd_iohs[wd_sector], 0); 609 if (cl != 0x02) { 610 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 611 "got 0x%x != 0x02\n", 612 __func__, chp->ch_channel, cl), 613 DEBUG_PROBE); 614 ret_value &= ~0x01; 615 } 616 cl = bus_space_read_1(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_cyl_lo], 0); 618 if (cl != 0x01) { 619 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 620 "got 0x%x != 0x01\n", 621 __func__, chp->ch_channel, cl), 622 DEBUG_PROBE); 623 ret_value &= ~0x01; 624 } 625 } 626 /* Register writability test, drive 1. */ 627 if (ret_value & 0x02) { 628 if (wdc->select) 629 wdc->select(chp,1); 630 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 631 0, WDSD_IBM | 0x10); 632 bus_space_write_1(wdr->cmd_iot, 633 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 634 cl = bus_space_read_1(wdr->cmd_iot, 635 wdr->cmd_iohs[wd_cyl_lo], 0); 636 if (cl != 0x02) { 637 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 638 "got 0x%x != 0x02\n", 639 __func__, chp->ch_channel, cl), 640 DEBUG_PROBE); 641 ret_value &= ~0x02; 642 } 643 bus_space_write_1(wdr->cmd_iot, 644 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 645 cl = bus_space_read_1(wdr->cmd_iot, 646 wdr->cmd_iohs[wd_cyl_lo], 0); 647 if (cl != 0x01) { 648 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 649 "got 0x%x != 0x01\n", 650 __func__, chp->ch_channel, cl), 651 DEBUG_PROBE); 652 ret_value &= ~0x02; 653 } 654 bus_space_write_1(wdr->cmd_iot, 655 wdr->cmd_iohs[wd_sector], 0, 0x01); 656 cl = bus_space_read_1(wdr->cmd_iot, 657 wdr->cmd_iohs[wd_sector], 0); 658 if (cl != 0x01) { 659 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 660 "got 0x%x != 0x01\n", 661 __func__, chp->ch_channel, cl), 662 DEBUG_PROBE); 663 ret_value &= ~0x02; 664 } 665 bus_space_write_1(wdr->cmd_iot, 666 wdr->cmd_iohs[wd_sector], 0, 0x02); 667 cl = bus_space_read_1(wdr->cmd_iot, 668 wdr->cmd_iohs[wd_sector], 0); 669 if (cl != 0x02) { 670 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 671 "got 0x%x != 0x02\n", 672 __func__, chp->ch_channel, cl), 673 DEBUG_PROBE); 674 ret_value &= ~0x02; 675 } 676 cl = bus_space_read_1(wdr->cmd_iot, 677 wdr->cmd_iohs[wd_cyl_lo], 0); 678 if (cl != 0x01) { 679 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 680 "got 0x%x != 0x01\n", 681 __func__, chp->ch_channel, cl), 682 DEBUG_PROBE); 683 ret_value &= ~0x02; 684 } 685 } 686 687 if (ret_value == 0) { 688 return 0; 689 } 690 } 691 692 #if 0 /* XXX this break some ATA or ATAPI devices */ 693 /* 694 * reset bus. Also send an ATAPI_RESET to devices, in case there are 695 * ATAPI device out there which don't react to the bus reset 696 */ 697 if (ret_value & 0x01) { 698 if (wdc->select) 699 wdc->select(chp,0); 700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 701 0, WDSD_IBM); 702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 703 ATAPI_SOFT_RESET); 704 } 705 if (ret_value & 0x02) { 706 if (wdc->select) 707 wdc->select(chp,0); 708 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 709 0, WDSD_IBM | 0x10); 710 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 711 ATAPI_SOFT_RESET); 712 } 713 714 delay(5000); 715 #endif 716 717 wdc->reset(chp, RESET_POLL); 718 DELAY(2000); 719 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 720 721 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 722 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 723 WDCTL_4BIT); 724 725 #ifdef WDC_NO_IDS 726 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 727 #else 728 ret_value = __wdcwait_reset(chp, ret_value, poll); 729 #endif 730 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 731 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 732 733 /* if reset failed, there's nothing here */ 734 if (ret_value == 0) { 735 return 0; 736 } 737 738 /* 739 * Test presence of drives. First test register signatures looking 740 * for ATAPI devices. If it's not an ATAPI and reset said there may 741 * be something here assume it's ATA or OLD. Ghost will be killed 742 * later in attach routine. 743 */ 744 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 745 if ((ret_value & (0x01 << drive)) == 0) 746 continue; 747 if (wdc->select) 748 wdc->select(chp,drive); 749 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 750 WDSD_IBM | (drive << 4)); 751 delay(10); /* 400ns delay */ 752 /* Save registers contents */ 753 sc = bus_space_read_1(wdr->cmd_iot, 754 wdr->cmd_iohs[wd_seccnt], 0); 755 sn = bus_space_read_1(wdr->cmd_iot, 756 wdr->cmd_iohs[wd_sector], 0); 757 cl = bus_space_read_1(wdr->cmd_iot, 758 wdr->cmd_iohs[wd_cyl_lo], 0); 759 ch = bus_space_read_1(wdr->cmd_iot, 760 wdr->cmd_iohs[wd_cyl_hi], 0); 761 762 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 763 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 764 sn, cl, ch), DEBUG_PROBE); 765 /* 766 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 767 * we get wrong values here, so ignore it. 768 */ 769 if (chp->ch_drive != NULL) { 770 if (cl == 0x14 && ch == 0xeb) { 771 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 772 } else { 773 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 774 } 775 } 776 } 777 /* 778 * Select an existing drive before lowering spl, some WDC_NO_IDS 779 * devices incorrectly assert IRQ on nonexistent slave 780 */ 781 if (ret_value & 0x01) { 782 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 783 WDSD_IBM); 784 (void)bus_space_read_1(wdr->cmd_iot, 785 wdr->cmd_iohs[wd_status], 0); 786 } 787 return (ret_value); 788 } 789 790 void 791 wdcattach(struct ata_channel *chp) 792 { 793 struct atac_softc *atac = chp->ch_atac; 794 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 795 796 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 797 798 /* default data transfer methods */ 799 if (wdc->datain_pio == NULL) 800 wdc->datain_pio = wdc_datain_pio; 801 if (wdc->dataout_pio == NULL) 802 wdc->dataout_pio = wdc_dataout_pio; 803 /* default reset method */ 804 if (wdc->reset == NULL) 805 wdc->reset = wdc_do_reset; 806 807 /* initialise global data */ 808 if (atac->atac_bustype_ata == NULL) 809 atac->atac_bustype_ata = &wdc_ata_bustype; 810 if (atac->atac_probe == NULL) 811 atac->atac_probe = wdc_drvprobe; 812 #if NATAPIBUS > 0 813 if (atac->atac_atapibus_attach == NULL) 814 atac->atac_atapibus_attach = wdc_atapibus_attach; 815 #endif 816 817 ata_channel_attach(chp); 818 } 819 820 void 821 wdc_childdetached(device_t self, device_t child) 822 { 823 struct atac_softc *atac = device_private(self); 824 struct ata_channel *chp; 825 int i; 826 827 for (i = 0; i < atac->atac_nchannels; i++) { 828 chp = atac->atac_channels[i]; 829 if (child == chp->atabus) { 830 chp->atabus = NULL; 831 return; 832 } 833 } 834 } 835 836 int 837 wdcdetach(device_t self, int flags) 838 { 839 struct atac_softc *atac = device_private(self); 840 struct ata_channel *chp; 841 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 842 int i, error = 0; 843 844 for (i = 0; i < atac->atac_nchannels; i++) { 845 chp = atac->atac_channels[i]; 846 if (chp->atabus == NULL) 847 continue; 848 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 849 device_xname(atac->atac_dev), device_xname(chp->atabus)), 850 DEBUG_DETACH); 851 if ((error = config_detach(chp->atabus, flags)) != 0) 852 return error; 853 ata_channel_detach(chp); 854 } 855 if (adapt->adapt_refcnt != 0) 856 return EBUSY; 857 return 0; 858 } 859 860 /* restart an interrupted I/O */ 861 void 862 wdcrestart(void *v) 863 { 864 struct ata_channel *chp = v; 865 int s; 866 867 s = splbio(); 868 atastart(chp); 869 splx(s); 870 } 871 872 873 /* 874 * Interrupt routine for the controller. Acknowledge the interrupt, check for 875 * errors on the current operation, mark it done if necessary, and start the 876 * next request. Also check for a partially done transfer, and continue with 877 * the next chunk if so. 878 */ 879 int 880 wdcintr(void *arg) 881 { 882 struct ata_channel *chp = arg; 883 struct atac_softc *atac = chp->ch_atac; 884 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 885 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 886 struct ata_xfer *xfer; 887 int ret; 888 889 if (!device_is_active(atac->atac_dev)) { 890 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 891 DEBUG_INTR); 892 return (0); 893 } 894 895 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) 896 goto ignore; 897 898 xfer = ata_queue_get_active_xfer(chp); 899 if (xfer == NULL) { 900 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 901 ignore: 902 /* try to clear the pending interrupt anyway */ 903 (void)bus_space_read_1(wdr->cmd_iot, 904 wdr->cmd_iohs[wd_status], 0); 905 return (0); 906 } 907 908 /* 909 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 910 * actually has no effect, and interrupt is triggered regardless. 911 * Ignore polled commands here, they are processed separately. 912 */ 913 if (ISSET(xfer->c_flags, C_POLL)) { 914 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 915 DEBUG_INTR); 916 goto ignore; 917 } 918 919 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 920 KASSERT(xfer != NULL); 921 922 #if NATA_DMA || NATA_PIOBM 923 if (chp->ch_flags & ATACH_DMA_WAIT) { 924 wdc->dma_status = 925 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 926 xfer->c_drive, WDC_DMAEND_END); 927 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 928 /* IRQ not for us, not detected by DMA engine */ 929 return 0; 930 } 931 chp->ch_flags &= ~ATACH_DMA_WAIT; 932 } 933 #endif 934 chp->ch_flags &= ~ATACH_IRQ_WAIT; 935 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 936 ret = xfer->ops->c_intr(chp, xfer, 1); 937 if (ret == 0) /* irq was not for us, still waiting for irq */ 938 chp->ch_flags |= ATACH_IRQ_WAIT; 939 return (ret); 940 } 941 942 /* Put all disk in RESET state */ 943 void 944 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 945 { 946 struct ata_channel *chp = drvp->chnl_softc; 947 948 ata_channel_lock_owned(chp); 949 950 KASSERT(sigp == NULL); 951 952 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 953 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 954 drvp->drive), DEBUG_FUNCS); 955 956 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 957 } 958 959 void 960 wdc_reset_channel(struct ata_channel *chp, int flags) 961 { 962 struct ata_xfer *xfer; 963 964 ata_channel_lock_owned(chp); 965 966 #if NATA_DMA || NATA_PIOBM 967 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 968 #endif 969 970 chp->ch_flags &= ~ATACH_IRQ_WAIT; 971 972 /* 973 * if the current command is on an ATAPI device, issue a 974 * ATAPI_SOFT_RESET 975 */ 976 xfer = ata_queue_get_active_xfer_locked(chp); 977 978 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 979 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 980 ata_delay(chp, 1000, "atardl", flags); 981 } 982 983 /* reset the channel */ 984 if (flags & AT_WAIT) 985 (void) wdcreset(chp, RESET_SLEEP); 986 else 987 (void) wdcreset(chp, RESET_POLL); 988 989 /* 990 * wait a bit after reset; in case the DMA engines needs some time 991 * to recover. 992 */ 993 ata_delay(chp, 1000, "atardl", flags); 994 995 /* 996 * Look for pending xfers. If we have a shared queue, we'll also reset 997 * the other channel if the current xfer is running on it. 998 * Then we'll kill the eventual active transfer explicitely, so that 999 * it is queued for retry immediatelly without waiting for I/O timeout. 1000 */ 1001 if (xfer) { 1002 if (xfer->c_chp != chp) { 1003 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 1004 ATACH_NODRIVE); 1005 } else { 1006 #if NATA_DMA || NATA_PIOBM 1007 /* 1008 * If we're waiting for DMA, stop the 1009 * DMA engine 1010 */ 1011 if (chp->ch_flags & ATACH_DMA_WAIT) { 1012 (*wdc->dma_finish)(wdc->dma_arg, 1013 chp->ch_channel, xfer->c_drive, 1014 WDC_DMAEND_ABRT_QUIET); 1015 chp->ch_flags &= ~ATACH_DMA_WAIT; 1016 } 1017 #endif 1018 } 1019 } 1020 1021 ata_kill_active(chp, KILL_RESET, flags); 1022 } 1023 1024 static int 1025 wdcreset(struct ata_channel *chp, int poll) 1026 { 1027 struct atac_softc *atac = chp->ch_atac; 1028 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1029 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1030 int drv_mask1, drv_mask2; 1031 1032 ata_channel_lock_owned(chp); 1033 1034 #ifdef WDC_NO_IDS 1035 poll = RESET_POLL; 1036 #endif 1037 wdc->reset(chp, poll); 1038 1039 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1040 ? 0x01 : 0x00; 1041 if (chp->ch_ndrives > 1) 1042 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1043 ? 0x02 : 0x00; 1044 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1045 (poll == RESET_SLEEP) ? 0 : 1); 1046 if (drv_mask2 != drv_mask1) { 1047 aprint_error("%s channel %d: reset failed for", 1048 device_xname(atac->atac_dev), chp->ch_channel); 1049 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1050 aprint_normal(" drive 0"); 1051 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1052 aprint_normal(" drive 1"); 1053 aprint_normal("\n"); 1054 } 1055 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1056 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1057 WDCTL_4BIT); 1058 1059 return (drv_mask1 != drv_mask2) ? 1 : 0; 1060 } 1061 1062 void 1063 wdc_do_reset(struct ata_channel *chp, int poll) 1064 { 1065 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1066 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1067 int s = 0; 1068 1069 if (poll != RESET_SLEEP) 1070 s = splbio(); 1071 if (wdc->select) 1072 wdc->select(chp,0); 1073 /* master */ 1074 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1075 delay(10); /* 400ns delay */ 1076 /* assert SRST, wait for reset to complete */ 1077 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1078 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1079 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1080 delay(2000); 1081 } 1082 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1083 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1084 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1085 WDCTL_4BIT | WDCTL_IDS); 1086 delay(10); /* 400ns delay */ 1087 if (poll != RESET_SLEEP) { 1088 /* ACK interrupt in case there is one pending left */ 1089 if (wdc->irqack) 1090 wdc->irqack(chp); 1091 splx(s); 1092 } 1093 } 1094 1095 static int 1096 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1097 { 1098 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1099 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1100 int timeout, nloop; 1101 int wflags = poll ? AT_POLL : AT_WAIT; 1102 u_int8_t st0 = 0, st1 = 0; 1103 #ifdef ATADEBUG 1104 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1105 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1106 #endif 1107 if (poll) 1108 nloop = WDCNDELAY_RST; 1109 else 1110 nloop = WDC_RESET_WAIT * hz / 1000; 1111 /* wait for BSY to deassert */ 1112 for (timeout = 0; timeout < nloop; timeout++) { 1113 if ((drv_mask & 0x01) != 0) { 1114 if (wdc->select) 1115 wdc->select(chp,0); 1116 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1117 0, WDSD_IBM); /* master */ 1118 delay(10); 1119 st0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_status], 0); 1121 #ifdef ATADEBUG 1122 sc0 = bus_space_read_1(wdr->cmd_iot, 1123 wdr->cmd_iohs[wd_seccnt], 0); 1124 sn0 = bus_space_read_1(wdr->cmd_iot, 1125 wdr->cmd_iohs[wd_sector], 0); 1126 cl0 = bus_space_read_1(wdr->cmd_iot, 1127 wdr->cmd_iohs[wd_cyl_lo], 0); 1128 ch0 = bus_space_read_1(wdr->cmd_iot, 1129 wdr->cmd_iohs[wd_cyl_hi], 0); 1130 #endif 1131 } 1132 if ((drv_mask & 0x02) != 0) { 1133 if (wdc->select) 1134 wdc->select(chp,1); 1135 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1136 0, WDSD_IBM | 0x10); /* slave */ 1137 delay(10); 1138 st1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_status], 0); 1140 #ifdef ATADEBUG 1141 sc1 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_seccnt], 0); 1143 sn1 = bus_space_read_1(wdr->cmd_iot, 1144 wdr->cmd_iohs[wd_sector], 0); 1145 cl1 = bus_space_read_1(wdr->cmd_iot, 1146 wdr->cmd_iohs[wd_cyl_lo], 0); 1147 ch1 = bus_space_read_1(wdr->cmd_iot, 1148 wdr->cmd_iohs[wd_cyl_hi], 0); 1149 #endif 1150 } 1151 1152 if ((drv_mask & 0x01) == 0) { 1153 /* no master */ 1154 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1155 /* No master, slave is ready, it's done */ 1156 goto end; 1157 } 1158 if ((drv_mask & 0x02) == 0) { 1159 /* No master, no slave: it's done */ 1160 goto end; 1161 } 1162 } else if ((drv_mask & 0x02) == 0) { 1163 /* no slave */ 1164 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1165 /* No slave, master is ready, it's done */ 1166 goto end; 1167 } 1168 } else { 1169 /* Wait for both master and slave to be ready */ 1170 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1171 goto end; 1172 } 1173 } 1174 ata_delay(chp, WDCDELAY, "atarst", wflags); 1175 } 1176 /* Reset timed out. Maybe it's because drv_mask was not right */ 1177 if (st0 & WDCS_BSY) 1178 drv_mask &= ~0x01; 1179 if (st1 & WDCS_BSY) 1180 drv_mask &= ~0x02; 1181 end: 1182 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1183 "cl=0x%x ch=0x%x\n", 1184 device_xname(chp->ch_atac->atac_dev), 1185 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1186 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1187 "cl=0x%x ch=0x%x\n", 1188 device_xname(chp->ch_atac->atac_dev), 1189 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1190 1191 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1192 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1193 st0, st1), DEBUG_PROBE); 1194 1195 return drv_mask; 1196 } 1197 1198 /* 1199 * Wait for a drive to be !BSY, and have mask in its status register. 1200 * return -1 for a timeout after "timeout" ms. 1201 */ 1202 static int 1203 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1204 { 1205 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1206 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1207 u_char status, error = 0; 1208 int xtime = 0; 1209 int rv; 1210 1211 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1212 device_xname(chp->ch_atac->atac_dev), 1213 chp->ch_channel), DEBUG_STATUS); 1214 *tfd = 0; 1215 1216 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1217 1218 for (;;) { 1219 status = 1220 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1221 if ((status & (WDCS_BSY | mask)) == bits) 1222 break; 1223 if (++xtime > timeout) { 1224 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1225 "status %x error %x (mask 0x%x bits 0x%x)\n", 1226 xtime, status, 1227 bus_space_read_1(wdr->cmd_iot, 1228 wdr->cmd_iohs[wd_error], 0), mask, bits), 1229 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1230 rv = WDCWAIT_TOUT; 1231 goto out; 1232 } 1233 delay(WDCDELAY); 1234 } 1235 #ifdef ATADEBUG 1236 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1237 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1238 #endif 1239 if (status & WDCS_ERR) 1240 error = bus_space_read_1(wdr->cmd_iot, 1241 wdr->cmd_iohs[wd_error], 0); 1242 #ifdef WDCNDELAY_DEBUG 1243 /* After autoconfig, there should be no long delays. */ 1244 if (!cold && xtime > WDCNDELAY_DEBUG) { 1245 struct ata_xfer *xfer; 1246 1247 xfer = ata_queue_get_active_xfer_locked(chp); 1248 if (xfer == NULL) 1249 printf("%s channel %d: warning: busy-wait took %dus\n", 1250 device_xname(chp->ch_atac->atac_dev), 1251 chp->ch_channel, WDCDELAY * xtime); 1252 else 1253 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1254 device_xname(chp->ch_atac->atac_dev), 1255 chp->ch_channel, xfer->c_drive, 1256 WDCDELAY * xtime); 1257 } 1258 #endif 1259 rv = WDCWAIT_OK; 1260 1261 out: 1262 *tfd = ATACH_ERR_ST(error, status); 1263 return rv; 1264 } 1265 1266 /* 1267 * Call __wdcwait(), polling using kpause() or waking up the kernel 1268 * thread if possible 1269 */ 1270 int 1271 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1272 int *tfd) 1273 { 1274 int error, i, timeout_hz = mstohz(timeout); 1275 1276 ata_channel_lock_owned(chp); 1277 1278 if (timeout_hz == 0 || 1279 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1280 error = __wdcwait(chp, mask, bits, timeout, tfd); 1281 else { 1282 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1283 if (error != 0) { 1284 if (ata_is_thread_run(chp) || (flags & AT_WAIT)) { 1285 /* 1286 * we're running in the channel thread 1287 * or some userland thread context 1288 */ 1289 for (i = 0; i < timeout_hz; i++) { 1290 if (__wdcwait(chp, mask, bits, 1291 WDCDELAY_POLL, tfd) == 0) { 1292 error = 0; 1293 break; 1294 } 1295 kpause("atapoll", true, 1, 1296 &chp->ch_lock); 1297 } 1298 } else { 1299 /* 1300 * we're probably in interrupt context, 1301 * caller must ask the thread to come back here 1302 */ 1303 return(WDCWAIT_THR); 1304 } 1305 } 1306 } 1307 return (error); 1308 } 1309 1310 1311 #if NATA_DMA 1312 /* 1313 * Busy-wait for DMA to complete 1314 */ 1315 int 1316 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1317 { 1318 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1319 int xtime; 1320 1321 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1322 wdc->dma_status = 1323 (*wdc->dma_finish)(wdc->dma_arg, 1324 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1325 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1326 return 0; 1327 delay(WDCDELAY); 1328 } 1329 /* timeout, force a DMA halt */ 1330 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1331 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1332 return 1; 1333 } 1334 #endif 1335 1336 void 1337 wdctimeout(void *arg) 1338 { 1339 struct ata_xfer *xfer; 1340 struct ata_channel *chp = arg; 1341 #if NATA_DMA || NATA_PIOBM 1342 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1343 #endif 1344 int s; 1345 1346 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1347 1348 s = splbio(); 1349 1350 callout_ack(&chp->c_timo_callout); 1351 1352 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 1353 __wdcerror(chp, "timeout not expected without pending irq"); 1354 goto out; 1355 } 1356 1357 xfer = ata_queue_get_active_xfer(chp); 1358 KASSERT(xfer != NULL); 1359 1360 if (ata_timo_xfer_check(xfer)) { 1361 /* Already logged */ 1362 goto out; 1363 } 1364 1365 __wdcerror(chp, "lost interrupt"); 1366 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1367 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1368 xfer->c_bcount, xfer->c_skip); 1369 #if NATA_DMA || NATA_PIOBM 1370 if (chp->ch_flags & ATACH_DMA_WAIT) { 1371 wdc->dma_status = 1372 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1373 xfer->c_drive, WDC_DMAEND_ABRT); 1374 chp->ch_flags &= ~ATACH_DMA_WAIT; 1375 } 1376 #endif 1377 /* 1378 * Call the interrupt routine. If we just missed an interrupt, 1379 * it will do what's needed. Else, it will take the needed 1380 * action (reset the device). 1381 */ 1382 xfer->c_flags |= C_TIMEOU; 1383 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1384 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1385 xfer->ops->c_intr(chp, xfer, 1); 1386 1387 out: 1388 splx(s); 1389 } 1390 1391 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1392 .c_start = __wdccommand_start, 1393 .c_poll = __wdccommand_poll, 1394 .c_abort = __wdccommand_done, 1395 .c_intr = __wdccommand_intr, 1396 .c_kill_xfer = __wdccommand_kill_xfer, 1397 }; 1398 1399 void 1400 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1401 { 1402 struct ata_channel *chp = drvp->chnl_softc; 1403 struct ata_command *ata_c = &xfer->c_ata_c; 1404 1405 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1406 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1407 drvp->drive), DEBUG_FUNCS); 1408 1409 /* set up an xfer and queue. Wait for completion */ 1410 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1411 ata_c->flags |= AT_POLL; 1412 if (ata_c->flags & AT_POLL) 1413 xfer->c_flags |= C_POLL; 1414 if (ata_c->flags & AT_WAIT) 1415 xfer->c_flags |= C_WAIT; 1416 xfer->c_drive = drvp->drive; 1417 xfer->c_databuf = ata_c->data; 1418 xfer->c_bcount = ata_c->bcount; 1419 xfer->ops = &wdc_cmd_xfer_ops; 1420 1421 ata_exec_xfer(chp, xfer); 1422 } 1423 1424 static int 1425 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1426 { 1427 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1428 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1429 int drive = xfer->c_drive; 1430 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1431 struct ata_command *ata_c = &xfer->c_ata_c; 1432 int tfd; 1433 1434 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1435 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1436 xfer->c_drive), DEBUG_FUNCS); 1437 1438 if (wdc->select) 1439 wdc->select(chp,drive); 1440 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1441 WDSD_IBM | (drive << 4)); 1442 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1443 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1444 case WDCWAIT_OK: 1445 break; 1446 case WDCWAIT_TOUT: 1447 ata_c->flags |= AT_TIMEOU; 1448 return ATASTART_ABORT; 1449 case WDCWAIT_THR: 1450 return ATASTART_TH; 1451 } 1452 if (ata_c->flags & AT_POLL) { 1453 /* polled command, disable interrupts */ 1454 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1455 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1456 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1457 } 1458 if ((ata_c->flags & AT_LBA48) != 0) { 1459 wdccommandext(chp, drive, ata_c->r_command, 1460 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1461 ata_c->r_device & ~0x10); 1462 } else { 1463 wdccommand(chp, drive, ata_c->r_command, 1464 (ata_c->r_lba >> 8) & 0xffff, 1465 WDSD_IBM | (drive << 4) | 1466 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1467 ((ata_c->r_lba >> 24) & 0x0f), 1468 ata_c->r_lba & 0xff, 1469 ata_c->r_count & 0xff, 1470 ata_c->r_features & 0xff); 1471 } 1472 1473 if ((ata_c->flags & AT_POLL) == 0) { 1474 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1475 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1476 wdctimeout, chp); 1477 return ATASTART_STARTED; 1478 } 1479 1480 /* 1481 * Polled command. Wait for drive ready or drq. Done in intr(). 1482 * Wait for at last 400ns for status bit to be valid. 1483 */ 1484 delay(10); /* 400ns delay */ 1485 return ATASTART_POLL; 1486 } 1487 1488 static void 1489 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1490 { 1491 __wdccommand_intr(chp, xfer, 0); 1492 } 1493 1494 static int 1495 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1496 { 1497 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1498 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1499 struct ata_command *ata_c = &xfer->c_ata_c; 1500 int bcount = ata_c->bcount; 1501 char *data = ata_c->data; 1502 int wflags, tfd; 1503 int drive_flags; 1504 1505 if (ata_c->r_command == WDCC_IDENTIFY || 1506 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1507 /* 1508 * The IDENTIFY data has been designed as an array of 1509 * u_int16_t, so we can byteswap it on the fly. 1510 * Historically it's what we have always done so keeping it 1511 * here ensure binary backward compatibility. 1512 */ 1513 drive_flags = ATA_DRIVE_NOSTREAM | 1514 chp->ch_drive[xfer->c_drive].drive_flags; 1515 } else { 1516 /* 1517 * Other data structure are opaque and should be transferred 1518 * as is. 1519 */ 1520 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1521 } 1522 1523 #ifdef WDC_NO_IDS 1524 wflags = AT_POLL; 1525 #else 1526 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1527 /* both wait and poll, we can kpause here */ 1528 wflags = AT_WAIT | AT_POLL; 1529 } else { 1530 wflags = AT_POLL; 1531 } 1532 #endif 1533 1534 ata_channel_lock(chp); 1535 1536 again: 1537 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1538 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1539 xfer->c_drive), DEBUG_INTR); 1540 /* 1541 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1542 * Reselect again, it doesn't hurt for others commands, and the time 1543 * penalty for the extra register write is acceptable, 1544 * wdc_exec_command() isn't called often (mostly for autoconfig) 1545 */ 1546 if ((xfer->c_flags & C_ATAPI) != 0) { 1547 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1548 WDSD_IBM | (xfer->c_drive << 4)); 1549 } 1550 if ((ata_c->flags & AT_XFDONE) != 0) { 1551 /* 1552 * We have completed a data xfer. The drive should now be 1553 * in its initial state 1554 */ 1555 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1556 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1557 wflags, &tfd) == WDCWAIT_TOUT) { 1558 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1559 ata_channel_unlock(chp); 1560 return 0; /* IRQ was not for us */ 1561 } 1562 ata_c->flags |= AT_TIMEOU; 1563 } 1564 goto out; 1565 } 1566 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1567 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1568 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1569 ata_channel_unlock(chp); 1570 return 0; /* IRQ was not for us */ 1571 } 1572 ata_c->flags |= AT_TIMEOU; 1573 goto out; 1574 } 1575 if (wdc->irqack) 1576 wdc->irqack(chp); 1577 if (ata_c->flags & AT_READ) { 1578 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1579 ata_c->flags |= AT_TIMEOU; 1580 goto out; 1581 } 1582 wdc->datain_pio(chp, drive_flags, data, bcount); 1583 /* at this point the drive should be in its initial state */ 1584 ata_c->flags |= AT_XFDONE; 1585 /* 1586 * XXX checking the status register again here cause some 1587 * hardware to timeout. 1588 */ 1589 } else if (ata_c->flags & AT_WRITE) { 1590 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1591 ata_c->flags |= AT_TIMEOU; 1592 goto out; 1593 } 1594 wdc->dataout_pio(chp, drive_flags, data, bcount); 1595 ata_c->flags |= AT_XFDONE; 1596 if ((ata_c->flags & AT_POLL) == 0) { 1597 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1598 callout_reset(&chp->c_timo_callout, 1599 mstohz(ata_c->timeout), wdctimeout, chp); 1600 ata_channel_unlock(chp); 1601 return 1; 1602 } else { 1603 goto again; 1604 } 1605 } 1606 out: 1607 if (ATACH_ST(tfd) & WDCS_DWF) 1608 ata_c->flags |= AT_DF; 1609 if (ATACH_ST(tfd) & WDCS_ERR) { 1610 ata_c->flags |= AT_ERROR; 1611 ata_c->r_error = ATACH_ST(tfd); 1612 } 1613 1614 ata_channel_unlock(chp); 1615 1616 __wdccommand_done(chp, xfer); 1617 return 1; 1618 } 1619 1620 static void 1621 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1622 { 1623 struct atac_softc *atac = chp->ch_atac; 1624 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1625 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1626 struct ata_command *ata_c = &xfer->c_ata_c; 1627 bool start = true; 1628 1629 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1630 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1631 ata_c->flags), DEBUG_FUNCS); 1632 1633 if (ata_waitdrain_xfer_check(chp, xfer)) { 1634 start = false; 1635 goto out; 1636 } 1637 1638 if ((ata_c->flags & AT_READREG) != 0 && 1639 device_is_active(atac->atac_dev) && 1640 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1641 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1642 wdr->cmd_iohs[wd_status], 0); 1643 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1644 wdr->cmd_iohs[wd_error], 0); 1645 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1646 wdr->cmd_iohs[wd_seccnt], 0); 1647 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_sector], 0) << 0; 1649 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1651 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1652 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1653 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1654 wdr->cmd_iohs[wd_sdh], 0); 1655 1656 if ((ata_c->flags & AT_LBA48) != 0) { 1657 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1658 if ((ata_c->flags & AT_POLL) != 0) 1659 bus_space_write_1(wdr->ctl_iot, 1660 wdr->ctl_ioh, wd_aux_ctlr, 1661 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1662 else 1663 bus_space_write_1(wdr->ctl_iot, 1664 wdr->ctl_ioh, wd_aux_ctlr, 1665 WDCTL_HOB|WDCTL_4BIT); 1666 } 1667 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1668 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1669 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1670 wdr->cmd_iohs[wd_sector], 0) << 24; 1671 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1672 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1673 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1674 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1675 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1676 if ((ata_c->flags & AT_POLL) != 0) 1677 bus_space_write_1(wdr->ctl_iot, 1678 wdr->ctl_ioh, wd_aux_ctlr, 1679 WDCTL_4BIT|WDCTL_IDS); 1680 else 1681 bus_space_write_1(wdr->ctl_iot, 1682 wdr->ctl_ioh, wd_aux_ctlr, 1683 WDCTL_4BIT); 1684 } 1685 } else { 1686 ata_c->r_lba |= 1687 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1688 } 1689 ata_c->r_device &= 0xf0; 1690 } 1691 1692 __wdccommand_done_end(chp, xfer); 1693 1694 ata_deactivate_xfer(chp, xfer); 1695 1696 out: 1697 if (ata_c->flags & AT_POLL) { 1698 /* enable interrupts */ 1699 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1700 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1701 wd_aux_ctlr, WDCTL_4BIT); 1702 delay(10); /* some drives need a little delay here */ 1703 } 1704 1705 if (start) 1706 atastart(chp); 1707 } 1708 1709 static void 1710 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1711 { 1712 struct ata_command *ata_c = &xfer->c_ata_c; 1713 1714 ata_c->flags |= AT_DONE; 1715 } 1716 1717 static void 1718 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1719 int reason) 1720 { 1721 struct ata_command *ata_c = &xfer->c_ata_c; 1722 bool deactivate = true; 1723 1724 switch (reason) { 1725 case KILL_GONE_INACTIVE: 1726 deactivate = false; 1727 /* FALLTHROUGH */ 1728 case KILL_GONE: 1729 ata_c->flags |= AT_GONE; 1730 break; 1731 case KILL_RESET: 1732 ata_c->flags |= AT_RESET; 1733 break; 1734 default: 1735 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1736 reason); 1737 panic("__wdccommand_kill_xfer"); 1738 } 1739 1740 __wdccommand_done_end(chp, xfer); 1741 1742 if (deactivate) 1743 ata_deactivate_xfer(chp, xfer); 1744 } 1745 1746 /* 1747 * Send a command. The drive should be ready. 1748 * Assumes interrupts are blocked. 1749 */ 1750 void 1751 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1752 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1753 u_int8_t features) 1754 { 1755 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1756 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1757 1758 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1759 "sector=%d count=%d features=%d\n", 1760 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1761 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1762 1763 if (wdc->select) 1764 wdc->select(chp,drive); 1765 1766 /* Select drive, head, and addressing mode. */ 1767 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1768 WDSD_IBM | (drive << 4) | head); 1769 /* Load parameters into the wd_features register. */ 1770 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1771 features); 1772 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1773 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1774 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1775 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1776 0, cylin >> 8); 1777 1778 /* Send command. */ 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1780 return; 1781 } 1782 1783 /* 1784 * Send a 48-bit addressing command. The drive should be ready. 1785 * Assumes interrupts are blocked. 1786 */ 1787 void 1788 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1789 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1790 { 1791 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1792 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1793 1794 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1795 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1796 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1797 chp->ch_channel, drive, command, blkno, count, features, device), 1798 DEBUG_FUNCS); 1799 1800 KASSERT(drive < wdc->wdc_maxdrives); 1801 1802 if (wdc->select) 1803 wdc->select(chp,drive); 1804 1805 /* Select drive, head, and addressing mode. */ 1806 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1807 (drive << 4) | device); 1808 1809 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1810 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1811 0, features); 1812 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1813 0, count); 1814 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1815 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1816 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1817 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1818 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1819 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1820 } else { 1821 /* previous */ 1822 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1823 0, features >> 8); 1824 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1825 0, count >> 8); 1826 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1827 0, blkno >> 24); 1828 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1829 0, blkno >> 32); 1830 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1831 0, blkno >> 40); 1832 1833 /* current */ 1834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1835 0, features); 1836 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1837 0, count); 1838 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1839 0, blkno); 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1841 0, blkno >> 8); 1842 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1843 0, blkno >> 16); 1844 } 1845 1846 /* Send command. */ 1847 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1848 return; 1849 } 1850 1851 /* 1852 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1853 * tested by the caller. 1854 */ 1855 void 1856 wdccommandshort(struct ata_channel *chp, int drive, int command) 1857 { 1858 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1859 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1860 1861 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1862 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1863 command), DEBUG_FUNCS); 1864 1865 if (wdc->select) 1866 wdc->select(chp,drive); 1867 1868 /* Select drive. */ 1869 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1870 WDSD_IBM | (drive << 4)); 1871 1872 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1873 } 1874 1875 static void 1876 __wdcerror(struct ata_channel *chp, const char *msg) 1877 { 1878 struct atac_softc *atac = chp->ch_atac; 1879 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1880 1881 if (xfer == NULL) 1882 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1883 chp->ch_channel, msg); 1884 else 1885 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1886 chp->ch_channel, xfer->c_drive, msg); 1887 } 1888 1889 /* 1890 * the bit bucket 1891 */ 1892 void 1893 wdcbit_bucket(struct ata_channel *chp, int size) 1894 { 1895 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1896 1897 for (; size >= 2; size -= 2) 1898 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1899 if (size) 1900 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1901 } 1902 1903 static void 1904 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1905 { 1906 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1907 1908 #ifndef __NO_STRICT_ALIGNMENT 1909 if ((uintptr_t)bf & 1) 1910 goto unaligned; 1911 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1912 goto unaligned; 1913 #endif 1914 1915 if (flags & ATA_DRIVE_NOSTREAM) { 1916 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1917 bus_space_read_multi_4(wdr->data32iot, 1918 wdr->data32ioh, 0, bf, len >> 2); 1919 bf = (char *)bf + (len & ~3); 1920 len &= 3; 1921 } 1922 if (len > 1) { 1923 bus_space_read_multi_2(wdr->cmd_iot, 1924 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1925 bf = (char *)bf + (len & ~1); 1926 len &= 1; 1927 } 1928 } else { 1929 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1930 bus_space_read_multi_stream_4(wdr->data32iot, 1931 wdr->data32ioh, 0, bf, len >> 2); 1932 bf = (char *)bf + (len & ~3); 1933 len &= 3; 1934 } 1935 if (len > 1) { 1936 bus_space_read_multi_stream_2(wdr->cmd_iot, 1937 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1938 bf = (char *)bf + (len & ~1); 1939 len &= 1; 1940 } 1941 } 1942 if (len) 1943 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1944 wdr->cmd_iohs[wd_data], 0); 1945 return; 1946 1947 #ifndef __NO_STRICT_ALIGNMENT 1948 unaligned: 1949 if (flags & ATA_DRIVE_NOSTREAM) { 1950 if (flags & ATA_DRIVE_CAP32) { 1951 while (len > 3) { 1952 uint32_t val; 1953 1954 val = bus_space_read_4(wdr->data32iot, 1955 wdr->data32ioh, 0); 1956 memcpy(bf, &val, 4); 1957 bf = (char *)bf + 4; 1958 len -= 4; 1959 } 1960 } 1961 while (len > 1) { 1962 uint16_t val; 1963 1964 val = bus_space_read_2(wdr->cmd_iot, 1965 wdr->cmd_iohs[wd_data], 0); 1966 memcpy(bf, &val, 2); 1967 bf = (char *)bf + 2; 1968 len -= 2; 1969 } 1970 } else { 1971 if (flags & ATA_DRIVE_CAP32) { 1972 while (len > 3) { 1973 uint32_t val; 1974 1975 val = bus_space_read_stream_4(wdr->data32iot, 1976 wdr->data32ioh, 0); 1977 memcpy(bf, &val, 4); 1978 bf = (char *)bf + 4; 1979 len -= 4; 1980 } 1981 } 1982 while (len > 1) { 1983 uint16_t val; 1984 1985 val = bus_space_read_stream_2(wdr->cmd_iot, 1986 wdr->cmd_iohs[wd_data], 0); 1987 memcpy(bf, &val, 2); 1988 bf = (char *)bf + 2; 1989 len -= 2; 1990 } 1991 } 1992 #endif 1993 } 1994 1995 static void 1996 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1997 { 1998 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1999 2000 #ifndef __NO_STRICT_ALIGNMENT 2001 if ((uintptr_t)bf & 1) 2002 goto unaligned; 2003 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2004 goto unaligned; 2005 #endif 2006 2007 if (flags & ATA_DRIVE_NOSTREAM) { 2008 if (flags & ATA_DRIVE_CAP32) { 2009 bus_space_write_multi_4(wdr->data32iot, 2010 wdr->data32ioh, 0, bf, len >> 2); 2011 bf = (char *)bf + (len & ~3); 2012 len &= 3; 2013 } 2014 if (len) { 2015 bus_space_write_multi_2(wdr->cmd_iot, 2016 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2017 } 2018 } else { 2019 if (flags & ATA_DRIVE_CAP32) { 2020 bus_space_write_multi_stream_4(wdr->data32iot, 2021 wdr->data32ioh, 0, bf, len >> 2); 2022 bf = (char *)bf + (len & ~3); 2023 len &= 3; 2024 } 2025 if (len) { 2026 bus_space_write_multi_stream_2(wdr->cmd_iot, 2027 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2028 } 2029 } 2030 return; 2031 2032 #ifndef __NO_STRICT_ALIGNMENT 2033 unaligned: 2034 if (flags & ATA_DRIVE_NOSTREAM) { 2035 if (flags & ATA_DRIVE_CAP32) { 2036 while (len > 3) { 2037 uint32_t val; 2038 2039 memcpy(&val, bf, 4); 2040 bus_space_write_4(wdr->data32iot, 2041 wdr->data32ioh, 0, val); 2042 bf = (char *)bf + 4; 2043 len -= 4; 2044 } 2045 } 2046 while (len > 1) { 2047 uint16_t val; 2048 2049 memcpy(&val, bf, 2); 2050 bus_space_write_2(wdr->cmd_iot, 2051 wdr->cmd_iohs[wd_data], 0, val); 2052 bf = (char *)bf + 2; 2053 len -= 2; 2054 } 2055 } else { 2056 if (flags & ATA_DRIVE_CAP32) { 2057 while (len > 3) { 2058 uint32_t val; 2059 2060 memcpy(&val, bf, 4); 2061 bus_space_write_stream_4(wdr->data32iot, 2062 wdr->data32ioh, 0, val); 2063 bf = (char *)bf + 4; 2064 len -= 4; 2065 } 2066 } 2067 while (len > 1) { 2068 uint16_t val; 2069 2070 memcpy(&val, bf, 2); 2071 bus_space_write_stream_2(wdr->cmd_iot, 2072 wdr->cmd_iohs[wd_data], 0, val); 2073 bf = (char *)bf + 2; 2074 len -= 2; 2075 } 2076 } 2077 #endif 2078 } 2079
Indexes created Thu Sep 25 02:09:54 GMT 2025