wdc.c revision 1.31
1 /* $NetBSD: wdc.c,v 1.31 1998/10/12 16:09:18 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = DEBUG_PROBE; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 185 WDSD_IBM); 186 delay(1); 187 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM | 0x10); 190 delay(1); 191 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 193 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 194 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 195 st0, st1), DEBUG_PROBE); 196 197 if (st0 == 0xff) 198 ret_value &= ~0x01; 199 if (st1 == 0xff) 200 ret_value &= ~0x02; 201 if (ret_value == 0) 202 return 0; 203 204 /* assert SRST, wait for reset to complete */ 205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 206 WDSD_IBM); 207 delay(1); 208 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 209 WDCTL_RST | WDCTL_IDS); 210 DELAY(1000); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_IDS); 213 delay(1000); 214 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 216 delay(1); 217 218 ret_value = __wdcwait_reset(chp, ret_value); 219 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 221 ret_value), DEBUG_PROBE); 222 223 /* if reset failed, there's nothing here */ 224 if (ret_value == 0) 225 return 0; 226 227 /* 228 * Test presence of drives. First test register signatures looking for 229 * ATAPI devices , then rescan and try an ATA command, in case it's an 230 * old drive. 231 * Fill in drive_flags accordingly 232 */ 233 for (drive = 0; drive < 2; drive++) { 234 if ((ret_value & (0x01 << drive)) == 0) 235 continue; 236 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 237 WDSD_IBM | (drive << 4)); 238 delay(1); 239 /* Save registers contents */ 240 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 241 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 242 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 243 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 244 245 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 248 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 249 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 250 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 251 } 252 } 253 for (drive = 0; drive < 2; drive++) { 254 if ((ret_value & (0x01 << drive)) == 0 || 255 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 256 continue; 257 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 258 WDSD_IBM | (drive << 4)); 259 delay(1); 260 /* 261 * Maybe it's an old device, so don't rely on ATA sig. 262 * Test registers writability (Error register not writable, 263 * but cyllo is), then try an ATA command. 264 */ 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 268 0x58 || 269 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 270 0xa5) { 271 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 272 "failed\n", 273 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 274 chp->channel, drive), DEBUG_PROBE); 275 ret_value &= ~(0x01 << drive); 276 continue; 277 } 278 if (wait_for_ready(chp, 10000) != 0) { 279 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 280 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 281 chp->channel, drive), DEBUG_PROBE); 282 ret_value &= ~(0x01 << drive); 283 continue; 284 } 285 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 286 WDCC_DIAGNOSE); 287 if (wait_for_ready(chp, 10000) == 0) { 288 chp->ch_drive[drive].drive_flags |= 289 DRIVE_ATA; 290 } else { 291 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive), DEBUG_PROBE); 294 ret_value &= ~(0x01 << drive); 295 } 296 } 297 return (ret_value); 298 } 299 300 void 301 wdcattach(chp) 302 struct channel_softc *chp; 303 { 304 int channel_flags, ctrl_flags, i; 305 struct ata_atapi_attach aa_link; 306 307 LIST_INIT(&xfer_free_list); 308 for (i = 0; i < 2; i++) { 309 chp->ch_drive[i].chnl_softc = chp; 310 chp->ch_drive[i].drive = i; 311 /* If controller can't do 16bit flag the drives as 32bit */ 312 if ((chp->wdc->cap & 313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 314 WDC_CAPABILITY_DATA32) 315 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 316 } 317 318 if (wdcprobe(chp) == 0) 319 return; /* If no drives, abort attach here */ 320 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 323 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 324 325 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 326 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 327 DEBUG_PROBE); 328 329 /* 330 * Attach an ATAPI bus, if needed. 331 */ 332 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 333 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 334 #if NATAPIBUS > 0 335 wdc_atapibus_attach(chp); 336 #else 337 /* 338 * Fills in a fake aa_link and call config_found, so that 339 * the config machinery will print 340 * "atapibus at xxx not configured" 341 */ 342 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 343 aa_link.aa_type = T_ATAPI; 344 aa_link.aa_channel = chp->channel; 345 aa_link.aa_openings = 1; 346 aa_link.aa_drv_data = 0; 347 aa_link.aa_bus_private = NULL; 348 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 349 atapi_print); 350 #endif 351 } 352 353 for (i = 0; i < 2; i++) { 354 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 355 continue; 356 } 357 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 358 aa_link.aa_type = T_ATA; 359 aa_link.aa_channel = chp->channel; 360 aa_link.aa_openings = 1; 361 aa_link.aa_drv_data = &chp->ch_drive[i]; 362 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 363 wdc_probe_caps(&chp->ch_drive[i]); 364 } 365 366 /* 367 * Reset channel. The probe, with some combinations of ATA/ATAPI 368 * devices keep it in a mostly working, but strange state (with busy 369 * led on) 370 */ 371 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 372 wdcreset(chp, VERBOSE); 373 /* 374 * Read status registers to avoid spurious interrupts. 375 */ 376 for (i = 1; i >= 0; i--) { 377 if (chp->ch_drive[i].drive_flags & DRIVE) { 378 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 379 wd_sdh, WDSD_IBM | (i << 4)); 380 if (wait_for_unbusy(chp, 10000) < 0) 381 printf("%s:%d:%d: device busy\n", 382 chp->wdc->sc_dev.dv_xname, 383 chp->channel, i); 384 } 385 } 386 } 387 } 388 389 /* 390 * Start I/O on a controller, for the given channel. 391 * The first xfer may be not for our channel if the channel queues 392 * are shared. 393 */ 394 void 395 wdcstart(wdc, channel) 396 struct wdc_softc *wdc; 397 int channel; 398 { 399 struct wdc_xfer *xfer; 400 struct channel_softc *chp; 401 402 /* is there a xfer ? */ 403 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 404 return; 405 chp = &wdc->channels[xfer->channel]; 406 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 407 return; /* channel aleady active */ 408 } 409 #ifdef DIAGNOSTIC 410 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 411 panic("wdcstart: channel waiting for irq\n"); 412 #endif 413 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 414 if (!(*wdc->claim_hw)(chp, 0)) 415 return; 416 417 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 418 xfer->channel, xfer->drive), DEBUG_XFERS); 419 chp->ch_flags |= WDCF_ACTIVE; 420 xfer->c_start(chp, xfer); 421 } 422 423 /* restart an interrupted I/O */ 424 void 425 wdcrestart(v) 426 void *v; 427 { 428 struct channel_softc *chp = v; 429 int s; 430 431 s = splbio(); 432 wdcstart(chp->wdc, chp->channel); 433 splx(s); 434 } 435 436 437 /* 438 * Interrupt routine for the controller. Acknowledge the interrupt, check for 439 * errors on the current operation, mark it done if necessary, and start the 440 * next request. Also check for a partially done transfer, and continue with 441 * the next chunk if so. 442 */ 443 int 444 wdcintr(arg) 445 void *arg; 446 { 447 struct channel_softc *chp = arg; 448 struct wdc_xfer *xfer; 449 450 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 451 #if 0 452 /* Clear the pending interrupt and abort. */ 453 u_int8_t s = 454 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 455 #ifdef WDCDEBUG 456 u_int8_t e = 457 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 458 u_int8_t i = 459 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 460 #else 461 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 462 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 463 #endif 464 465 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 466 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 467 468 if (s & WDCS_DRQ) { 469 int len; 470 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 471 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 472 chp->cmd_ioh, wd_cyl_hi); 473 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 474 len), DEBUG_INTR); 475 wdcbit_bucket (chp, len); 476 } 477 #else 478 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 479 #endif 480 return 0; 481 } 482 483 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 484 untimeout(wdctimeout, chp); 485 chp->ch_flags &= ~WDCF_IRQ_WAIT; 486 xfer = chp->ch_queue->sc_xfer.tqh_first; 487 return xfer->c_intr(chp, xfer); 488 } 489 490 /* Put all disk in RESET state */ 491 void wdc_reset_channel(drvp) 492 struct ata_drive_datas *drvp; 493 { 494 struct channel_softc *chp = drvp->chnl_softc; 495 int drive; 496 WDCDEBUG_PRINT(("ata_reset_channel\n"), DEBUG_FUNCS); 497 (void) wdcreset(chp, VERBOSE); 498 for (drive = 0; drive < 2; drive++) { 499 chp->ch_drive[drive].state = 0; 500 } 501 } 502 503 int 504 wdcreset(chp, verb) 505 struct channel_softc *chp; 506 int verb; 507 { 508 int drv_mask1, drv_mask2; 509 510 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 511 WDSD_IBM); /* master */ 512 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 513 WDCTL_RST | WDCTL_IDS); 514 delay(1000); 515 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 516 WDCTL_IDS); 517 delay(1000); 518 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 519 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 520 WDCTL_4BIT); 521 522 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 523 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 524 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 525 if (verb && drv_mask2 != drv_mask1) { 526 printf("%s channel %d: reset failed for", 527 chp->wdc->sc_dev.dv_xname, chp->channel); 528 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 529 printf(" drive 0"); 530 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 531 printf(" drive 1"); 532 printf("\n"); 533 } 534 return (drv_mask1 != drv_mask2) ? 1 : 0; 535 } 536 537 static int 538 __wdcwait_reset(chp, drv_mask) 539 struct channel_softc *chp; 540 int drv_mask; 541 { 542 int timeout; 543 u_int8_t st0, st1; 544 /* wait for BSY to deassert */ 545 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 546 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 547 WDSD_IBM); /* master */ 548 delay(1); 549 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 550 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 551 WDSD_IBM | 0x10); /* slave */ 552 delay(1); 553 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 554 555 if ((drv_mask & 0x01) == 0) { 556 /* no master */ 557 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 558 /* No master, slave is ready, it's done */ 559 return drv_mask; 560 } 561 } else if ((drv_mask & 0x02) == 0) { 562 /* no slave */ 563 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 564 /* No slave, master is ready, it's done */ 565 return drv_mask; 566 } 567 } else { 568 /* Wait for both master and slave to be ready */ 569 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 570 return drv_mask; 571 } 572 } 573 delay(WDCDELAY); 574 } 575 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 576 if (st0 & WDCS_BSY) 577 drv_mask &= ~0x01; 578 if (st1 & WDCS_BSY) 579 drv_mask &= ~0x02; 580 return drv_mask; 581 } 582 583 /* 584 * Wait for a drive to be !BSY, and have mask in its status register. 585 * return -1 for a timeout after "timeout" ms. 586 */ 587 int 588 wdcwait(chp, mask, bits, timeout) 589 struct channel_softc *chp; 590 int mask, bits, timeout; 591 { 592 u_char status; 593 int time = 0; 594 #ifdef WDCNDELAY_DEBUG 595 extern int cold; 596 #endif 597 WDCDEBUG_PRINT(("wdcwait\n"), DEBUG_STATUS); 598 chp->ch_error = 0; 599 600 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 601 602 for (;;) { 603 chp->ch_status = status = 604 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 605 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 606 break; 607 if (++time > timeout) { 608 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 609 "error %x\n", status, 610 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 611 wd_error)), 612 DEBUG_STATUS); 613 return -1; 614 } 615 delay(WDCDELAY); 616 } 617 if (status & WDCS_ERR) 618 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 619 wd_error); 620 #ifdef WDCNDELAY_DEBUG 621 /* After autoconfig, there should be no long delays. */ 622 if (!cold && time > WDCNDELAY_DEBUG) { 623 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 624 if (xfer == NULL) 625 printf("%s channel %d: warning: busy-wait took %dus\n", 626 chp->wdc->sc_dev.dv_xname, chp->channel, 627 WDCDELAY * time); 628 else 629 printf("%s:%d:%d: warning: busy-wait took %dus\n", 630 chp->wdc->sc_dev.dv_xname, xfer->channel, 631 xfer->drive, 632 WDCDELAY * time); 633 } 634 #endif 635 return 0; 636 } 637 638 void 639 wdctimeout(arg) 640 void *arg; 641 { 642 struct channel_softc *chp = (struct channel_softc *)arg; 643 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 644 int s; 645 646 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 647 648 s = splbio(); 649 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 650 __wdcerror(chp, "lost interrupt"); 651 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 652 "atapi":"ata"); 653 printf("\tc_bcount: %d\n", xfer->c_bcount); 654 printf("\tc_skip: %d\n", xfer->c_skip); 655 /* 656 * Call the interrupt routine. If we just missed and interrupt, 657 * it will do what's needed. Else, it will take the needed 658 * action (reset the device). 659 */ 660 xfer->c_flags |= C_TIMEOU; 661 chp->ch_flags &= ~WDCF_IRQ_WAIT; 662 xfer->c_intr(chp, xfer); 663 } else 664 __wdcerror(chp, "missing untimeout"); 665 splx(s); 666 } 667 668 /* 669 * Probe drive's capabilites, for use by the controller later 670 * Assumes drvp points to an existing drive. 671 * XXX this should be a controller-indep function 672 */ 673 void 674 wdc_probe_caps(drvp) 675 struct ata_drive_datas *drvp; 676 { 677 struct ataparams params, params2; 678 struct channel_softc *chp = drvp->chnl_softc; 679 struct device *drv_dev = drvp->drv_softc; 680 struct wdc_softc *wdc = chp->wdc; 681 int i, printed; 682 char *sep = ""; 683 684 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 685 /* IDENTIFY failed. Can't tell more about the device */ 686 return; 687 } 688 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 689 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 690 /* 691 * Controller claims 16 and 32 bit transferts. 692 * Re-do an UDENTIFY with 32-bit transferts, 693 * and compare results. 694 */ 695 drvp->drive_flags |= DRIVE_CAP32; 696 ata_get_params(drvp, AT_POLL, ¶ms2); 697 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 698 /* Not good. fall back to 16bits */ 699 drvp->drive_flags &= ~DRIVE_CAP32; 700 } else { 701 printf("%s: using 32-bits pio transfers\n", 702 drv_dev->dv_xname); 703 } 704 } 705 706 /* An ATAPI device is at last PIO mode 3 */ 707 if (drvp->drive_flags & DRIVE_ATAPI) 708 drvp->PIO_mode = 3; 709 710 /* 711 * It's not in the specs, but it seems that some drive 712 * returns 0xffff in atap_extensions when this field is invalid 713 */ 714 if (params.atap_extensions != 0xffff && 715 (params.atap_extensions & WDC_EXT_MODES)) { 716 printed = 0; 717 /* 718 * XXX some drives report something wrong here (they claim to 719 * support PIO mode 8 !). As mode is coded on 3 bits in 720 * SET FEATURE, limit it to 7 (so limit i to 4). 721 */ 722 for (i = 4; i >= 0; i--) { 723 if ((params.atap_piomode_supp & (1 << i)) == 0) 724 continue; 725 /* 726 * See if mode is accepted. 727 * If the controller can't set its PIO mode, 728 * assume the defaults are good, so don't try 729 * to set it 730 */ 731 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 732 if (ata_set_mode(drvp, 0x08 | (i + 3), 733 AT_POLL) != CMD_OK) 734 continue; 735 if (!printed) { 736 printf("%s: PIO mode %d", drv_dev->dv_xname, 737 i + 3); 738 sep = ","; 739 printed = 1; 740 } 741 /* 742 * If controller's driver can't set its PIO mode, 743 * get the highter one for the drive. 744 */ 745 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 746 wdc->pio_mode >= i + 3) { 747 drvp->PIO_mode = i + 3; 748 break; 749 } 750 } 751 if (!printed) { 752 /* 753 * We didn't find a valid PIO mode. 754 * Assume the values returned for DMA are buggy too 755 */ 756 return; 757 } 758 printed = 0; 759 for (i = 7; i >= 0; i--) { 760 if ((params.atap_dmamode_supp & (1 << i)) == 0) 761 continue; 762 if ((wdc->cap & WDC_CAPABILITY_DMA) && 763 (wdc->cap & WDC_CAPABILITY_MODE)) 764 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 765 != CMD_OK) 766 continue; 767 if (!printed) { 768 printf("%s DMA mode %d", sep, i); 769 sep = ","; 770 printed = 1; 771 } 772 if (wdc->cap & WDC_CAPABILITY_DMA) { 773 if ((wdc->cap & WDC_CAPABILITY_MODE) && 774 wdc->dma_mode < i) 775 continue; 776 drvp->DMA_mode = i; 777 drvp->drive_flags |= DRIVE_DMA; 778 } 779 break; 780 } 781 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 782 for (i = 7; i >= 0; i--) { 783 if ((params.atap_udmamode_supp & (1 << i)) 784 == 0) 785 continue; 786 if ((wdc->cap & WDC_CAPABILITY_MODE) && 787 (wdc->cap & WDC_CAPABILITY_UDMA)) 788 if (ata_set_mode(drvp, 0x40 | i, 789 AT_POLL) != CMD_OK) 790 continue; 791 printf("%s UDMA mode %d", sep, i); 792 sep = ","; 793 /* 794 * ATA-4 specs says if a mode is supported, 795 * all lower modes shall be supported. 796 * No need to look further. 797 */ 798 if (wdc->cap & WDC_CAPABILITY_UDMA) { 799 drvp->UDMA_mode = i; 800 drvp->drive_flags |= DRIVE_UDMA; 801 } 802 break; 803 } 804 } 805 printf("\n"); 806 } 807 } 808 809 int 810 wdc_exec_command(drvp, wdc_c) 811 struct ata_drive_datas *drvp; 812 struct wdc_command *wdc_c; 813 { 814 struct channel_softc *chp = drvp->chnl_softc; 815 struct wdc_xfer *xfer; 816 int s, ret; 817 818 WDCDEBUG_PRINT(("wdc_exec_command\n"), DEBUG_FUNCS); 819 820 /* set up an xfer and queue. Wait for completion */ 821 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 822 WDC_NOSLEEP); 823 if (xfer == NULL) { 824 return WDC_TRY_AGAIN; 825 } 826 827 if (wdc_c->flags & AT_POLL) 828 xfer->c_flags |= C_POLL; 829 xfer->drive = drvp->drive; 830 xfer->databuf = wdc_c->data; 831 xfer->c_bcount = wdc_c->bcount; 832 xfer->cmd = wdc_c; 833 xfer->c_start = __wdccommand_start; 834 xfer->c_intr = __wdccommand_intr; 835 836 s = splbio(); 837 wdc_exec_xfer(chp, xfer); 838 #ifdef DIAGNOSTIC 839 if ((wdc_c->flags & AT_POLL) != 0 && 840 (wdc_c->flags & AT_DONE) == 0) 841 panic("wdc_exec_command: polled command not done\n"); 842 #endif 843 if (wdc_c->flags & AT_DONE) { 844 ret = WDC_COMPLETE; 845 } else { 846 if (wdc_c->flags & AT_WAIT) { 847 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 848 ret = WDC_COMPLETE; 849 } else { 850 ret = WDC_QUEUED; 851 } 852 } 853 splx(s); 854 return ret; 855 } 856 857 void 858 __wdccommand_start(chp, xfer) 859 struct channel_softc *chp; 860 struct wdc_xfer *xfer; 861 { 862 int drive = xfer->drive; 863 struct wdc_command *wdc_c = xfer->cmd; 864 865 WDCDEBUG_PRINT(("__wdccommand_start\n"), DEBUG_FUNCS); 866 867 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 868 WDSD_IBM | (drive << 4)); 869 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 870 wdc_c->timeout) != 0) { 871 wdc_c->flags |= AT_TIMEOU; 872 __wdccommand_done(chp, xfer); 873 } 874 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 875 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 876 if ((wdc_c->flags & AT_POLL) == 0) { 877 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 878 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 879 return; 880 } 881 /* 882 * Polled command. Wait for drive ready or drq. Done in intr(). 883 * Wait for at last 400ns for status bit to be valid. 884 */ 885 delay(10); 886 if (__wdccommand_intr(chp, xfer) == 0) { 887 wdc_c->flags |= AT_TIMEOU; 888 __wdccommand_done(chp, xfer); 889 } 890 } 891 892 int 893 __wdccommand_intr(chp, xfer) 894 struct channel_softc *chp; 895 struct wdc_xfer *xfer; 896 { 897 struct wdc_command *wdc_c = xfer->cmd; 898 int bcount = wdc_c->bcount; 899 char *data = wdc_c->data; 900 901 WDCDEBUG_PRINT(("__wdccommand_intr\n"), DEBUG_INTR); 902 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 903 wdc_c->timeout)) { 904 wdc_c->flags |= AT_ERROR; 905 __wdccommand_done(chp, xfer); 906 return 1; 907 } 908 if (wdc_c->flags & AT_READ) { 909 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 910 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 911 0, (u_int32_t*)data, bcount >> 2); 912 data += bcount & 0xfffffffc; 913 bcount = bcount & 0x03; 914 } 915 if (bcount > 0) 916 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 917 wd_data, (u_int16_t *)data, bcount >> 1); 918 } else if (wdc_c->flags & AT_WRITE) { 919 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 920 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 921 0, (u_int32_t*)data, bcount >> 2); 922 data += bcount & 0xfffffffc; 923 bcount = bcount & 0x03; 924 } 925 if (bcount > 0) 926 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 927 wd_data, (u_int16_t *)data, bcount >> 1); 928 } 929 __wdccommand_done(chp, xfer); 930 return 1; 931 } 932 933 void 934 __wdccommand_done(chp, xfer) 935 struct channel_softc *chp; 936 struct wdc_xfer *xfer; 937 { 938 int needdone = xfer->c_flags & C_NEEDDONE; 939 struct wdc_command *wdc_c = xfer->cmd; 940 941 WDCDEBUG_PRINT(("__wdccommand_done\n"), DEBUG_FUNCS); 942 if (chp->ch_status & WDCS_DWF) 943 wdc_c->flags |= AT_DF; 944 if (chp->ch_status & WDCS_ERR) { 945 wdc_c->flags |= AT_ERROR; 946 wdc_c->r_error = chp->ch_error; 947 } 948 wdc_c->flags |= AT_DONE; 949 wdc_free_xfer(chp, xfer); 950 if (needdone) { 951 if (wdc_c->flags & AT_WAIT) 952 wakeup(wdc_c); 953 else 954 wdc_c->callback(wdc_c->callback_arg); 955 } 956 return; 957 } 958 959 /* 960 * Send a command. The drive should be ready. 961 * Assumes interrupts are blocked. 962 */ 963 void 964 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 965 struct channel_softc *chp; 966 u_int8_t drive; 967 u_int8_t command; 968 u_int16_t cylin; 969 u_int8_t head, sector, count, precomp; 970 { 971 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 972 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 973 chp->channel, drive, command, cylin, head, sector, count, precomp), 974 DEBUG_FUNCS); 975 976 /* Select drive, head, and addressing mode. */ 977 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 978 WDSD_IBM | (drive << 4) | head); 979 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 980 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 981 precomp); 982 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 983 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 984 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 985 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 986 987 /* Send command. */ 988 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 989 return; 990 } 991 992 /* 993 * Simplified version of wdccommand(). Unbusy/ready/drq must be 994 * tested by the caller. 995 */ 996 void 997 wdccommandshort(chp, drive, command) 998 struct channel_softc *chp; 999 int drive; 1000 int command; 1001 { 1002 1003 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1004 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1005 DEBUG_FUNCS); 1006 1007 /* Select drive. */ 1008 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1009 WDSD_IBM | (drive << 4)); 1010 1011 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1012 } 1013 1014 /* Add a command to the queue and start controller. Must be called at splbio */ 1015 1016 void 1017 wdc_exec_xfer(chp, xfer) 1018 struct channel_softc *chp; 1019 struct wdc_xfer *xfer; 1020 { 1021 WDCDEBUG_PRINT(("wdc_exec_xfer %p\n", xfer), DEBUG_FUNCS); 1022 1023 /* complete xfer setup */ 1024 xfer->channel = chp->channel; 1025 1026 /* 1027 * If we are a polled command, and the list is not empty, 1028 * we are doing a dump. Drop the list to allow the polled command 1029 * to complete, we're going to reboot soon anyway. 1030 */ 1031 if ((xfer->c_flags & C_POLL) != 0 && 1032 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1033 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1034 } 1035 /* insert at the end of command list */ 1036 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1037 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1038 chp->ch_flags), DEBUG_FUNCS); 1039 wdcstart(chp->wdc, chp->channel); 1040 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1041 } 1042 1043 struct wdc_xfer * 1044 wdc_get_xfer(flags) 1045 int flags; 1046 { 1047 struct wdc_xfer *xfer; 1048 int s; 1049 1050 s = splbio(); 1051 if ((xfer = xfer_free_list.lh_first) != NULL) { 1052 LIST_REMOVE(xfer, free_list); 1053 splx(s); 1054 #ifdef DIAGNOSTIC 1055 if ((xfer->c_flags & C_INUSE) != 0) 1056 panic("wdc_get_xfer: xfer already in use\n"); 1057 #endif 1058 } else { 1059 splx(s); 1060 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1061 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1062 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1063 if (xfer == NULL) 1064 return 0; 1065 #ifdef DIAGNOSTIC 1066 xfer->c_flags &= ~C_INUSE; 1067 #endif 1068 #ifdef WDCDEBUG 1069 wdc_nxfer++; 1070 #endif 1071 } 1072 #ifdef DIAGNOSTIC 1073 if ((xfer->c_flags & C_INUSE) != 0) 1074 panic("wdc_get_xfer: xfer already in use\n"); 1075 #endif 1076 memset(xfer, 0, sizeof(struct wdc_xfer)); 1077 xfer->c_flags = C_INUSE; 1078 return xfer; 1079 } 1080 1081 void 1082 wdc_free_xfer(chp, xfer) 1083 struct channel_softc *chp; 1084 struct wdc_xfer *xfer; 1085 { 1086 struct wdc_softc *wdc = chp->wdc; 1087 int s; 1088 1089 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1090 (*wdc->free_hw)(chp); 1091 s = splbio(); 1092 chp->ch_flags &= ~WDCF_ACTIVE; 1093 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1094 xfer->c_flags &= ~C_INUSE; 1095 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1096 splx(s); 1097 } 1098 1099 static void 1100 __wdcerror(chp, msg) 1101 struct channel_softc *chp; 1102 char *msg; 1103 { 1104 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1105 if (xfer == NULL) 1106 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1107 msg); 1108 else 1109 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1110 xfer->channel, xfer->drive, msg); 1111 } 1112 1113 /* 1114 * the bit bucket 1115 */ 1116 void 1117 wdcbit_bucket(chp, size) 1118 struct channel_softc *chp; 1119 int size; 1120 { 1121 1122 for (; size >= 2; size -= 2) 1123 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1124 if (size) 1125 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1126 } 1127
Indexes created Thu Sep 25 16:09:42 GMT 2025