wdc.c revision 1.32
1 /* $NetBSD: wdc.c,v 1.32 1998/10/13 08:59:45 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 185 WDSD_IBM); 186 delay(1); 187 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM | 0x10); 190 delay(1); 191 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 193 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 194 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 195 st0, st1), DEBUG_PROBE); 196 197 if (st0 == 0xff) 198 ret_value &= ~0x01; 199 if (st1 == 0xff) 200 ret_value &= ~0x02; 201 if (ret_value == 0) 202 return 0; 203 204 /* assert SRST, wait for reset to complete */ 205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 206 WDSD_IBM); 207 delay(1); 208 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 209 WDCTL_RST | WDCTL_IDS); 210 DELAY(1000); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_IDS); 213 delay(1000); 214 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 216 delay(1); 217 218 ret_value = __wdcwait_reset(chp, ret_value); 219 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 221 ret_value), DEBUG_PROBE); 222 223 /* if reset failed, there's nothing here */ 224 if (ret_value == 0) 225 return 0; 226 227 /* 228 * Test presence of drives. First test register signatures looking for 229 * ATAPI devices , then rescan and try an ATA command, in case it's an 230 * old drive. 231 * Fill in drive_flags accordingly 232 */ 233 for (drive = 0; drive < 2; drive++) { 234 if ((ret_value & (0x01 << drive)) == 0) 235 continue; 236 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 237 WDSD_IBM | (drive << 4)); 238 delay(1); 239 /* Save registers contents */ 240 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 241 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 242 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 243 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 244 245 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 248 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 249 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 250 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 251 } 252 } 253 for (drive = 0; drive < 2; drive++) { 254 if ((ret_value & (0x01 << drive)) == 0 || 255 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 256 continue; 257 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 258 WDSD_IBM | (drive << 4)); 259 delay(1); 260 /* 261 * Maybe it's an old device, so don't rely on ATA sig. 262 * Test registers writability (Error register not writable, 263 * but cyllo is), then try an ATA command. 264 */ 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 268 0x58 || 269 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 270 0xa5) { 271 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 272 "failed\n", 273 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 274 chp->channel, drive), DEBUG_PROBE); 275 ret_value &= ~(0x01 << drive); 276 continue; 277 } 278 if (wait_for_ready(chp, 10000) != 0) { 279 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 280 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 281 chp->channel, drive), DEBUG_PROBE); 282 ret_value &= ~(0x01 << drive); 283 continue; 284 } 285 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 286 WDCC_DIAGNOSE); 287 if (wait_for_ready(chp, 10000) == 0) { 288 chp->ch_drive[drive].drive_flags |= 289 DRIVE_ATA; 290 } else { 291 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive), DEBUG_PROBE); 294 ret_value &= ~(0x01 << drive); 295 } 296 } 297 return (ret_value); 298 } 299 300 void 301 wdcattach(chp) 302 struct channel_softc *chp; 303 { 304 int channel_flags, ctrl_flags, i; 305 struct ata_atapi_attach aa_link; 306 307 LIST_INIT(&xfer_free_list); 308 for (i = 0; i < 2; i++) { 309 chp->ch_drive[i].chnl_softc = chp; 310 chp->ch_drive[i].drive = i; 311 /* If controller can't do 16bit flag the drives as 32bit */ 312 if ((chp->wdc->cap & 313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 314 WDC_CAPABILITY_DATA32) 315 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 316 } 317 318 if (wdcprobe(chp) == 0) 319 return; /* If no drives, abort attach here */ 320 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 323 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 324 325 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 326 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 327 DEBUG_PROBE); 328 329 /* 330 * Attach an ATAPI bus, if needed. 331 */ 332 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 333 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 334 #if NATAPIBUS > 0 335 wdc_atapibus_attach(chp); 336 #else 337 /* 338 * Fills in a fake aa_link and call config_found, so that 339 * the config machinery will print 340 * "atapibus at xxx not configured" 341 */ 342 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 343 aa_link.aa_type = T_ATAPI; 344 aa_link.aa_channel = chp->channel; 345 aa_link.aa_openings = 1; 346 aa_link.aa_drv_data = 0; 347 aa_link.aa_bus_private = NULL; 348 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 349 atapi_print); 350 #endif 351 } 352 353 for (i = 0; i < 2; i++) { 354 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 355 continue; 356 } 357 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 358 aa_link.aa_type = T_ATA; 359 aa_link.aa_channel = chp->channel; 360 aa_link.aa_openings = 1; 361 aa_link.aa_drv_data = &chp->ch_drive[i]; 362 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 363 wdc_probe_caps(&chp->ch_drive[i]); 364 } 365 366 /* 367 * reset drive_flags for unnatached devices, reset state for attached 368 * ones 369 */ 370 for (i = 0; i < 2; i++) { 371 if (chp->ch_drive[i].drv_softc == NULL) 372 chp->ch_drive[i].drive_flags = 0; 373 else 374 chp->ch_drive[i].state = 0; 375 } 376 377 /* 378 * Reset channel. The probe, with some combinations of ATA/ATAPI 379 * devices keep it in a mostly working, but strange state (with busy 380 * led on) 381 */ 382 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 383 wdcreset(chp, VERBOSE); 384 /* 385 * Read status registers to avoid spurious interrupts. 386 */ 387 for (i = 1; i >= 0; i--) { 388 if (chp->ch_drive[i].drive_flags & DRIVE) { 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_sdh, WDSD_IBM | (i << 4)); 391 if (wait_for_unbusy(chp, 10000) < 0) 392 printf("%s:%d:%d: device busy\n", 393 chp->wdc->sc_dev.dv_xname, 394 chp->channel, i); 395 } 396 } 397 } 398 } 399 400 /* 401 * Start I/O on a controller, for the given channel. 402 * The first xfer may be not for our channel if the channel queues 403 * are shared. 404 */ 405 void 406 wdcstart(wdc, channel) 407 struct wdc_softc *wdc; 408 int channel; 409 { 410 struct wdc_xfer *xfer; 411 struct channel_softc *chp; 412 413 /* is there a xfer ? */ 414 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 415 return; 416 chp = &wdc->channels[xfer->channel]; 417 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 418 return; /* channel aleady active */ 419 } 420 #ifdef DIAGNOSTIC 421 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 422 panic("wdcstart: channel waiting for irq\n"); 423 #endif 424 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 425 if (!(*wdc->claim_hw)(chp, 0)) 426 return; 427 428 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 429 xfer->channel, xfer->drive), DEBUG_XFERS); 430 chp->ch_flags |= WDCF_ACTIVE; 431 xfer->c_start(chp, xfer); 432 } 433 434 /* restart an interrupted I/O */ 435 void 436 wdcrestart(v) 437 void *v; 438 { 439 struct channel_softc *chp = v; 440 int s; 441 442 s = splbio(); 443 wdcstart(chp->wdc, chp->channel); 444 splx(s); 445 } 446 447 448 /* 449 * Interrupt routine for the controller. Acknowledge the interrupt, check for 450 * errors on the current operation, mark it done if necessary, and start the 451 * next request. Also check for a partially done transfer, and continue with 452 * the next chunk if so. 453 */ 454 int 455 wdcintr(arg) 456 void *arg; 457 { 458 struct channel_softc *chp = arg; 459 struct wdc_xfer *xfer; 460 461 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 462 #if 0 463 /* Clear the pending interrupt and abort. */ 464 u_int8_t s = 465 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 466 #ifdef WDCDEBUG 467 u_int8_t e = 468 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 469 u_int8_t i = 470 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 471 #else 472 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 473 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 474 #endif 475 476 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 477 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 478 479 if (s & WDCS_DRQ) { 480 int len; 481 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 482 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 483 chp->cmd_ioh, wd_cyl_hi); 484 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 485 len), DEBUG_INTR); 486 wdcbit_bucket (chp, len); 487 } 488 #else 489 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 490 #endif 491 return 0; 492 } 493 494 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 495 untimeout(wdctimeout, chp); 496 chp->ch_flags &= ~WDCF_IRQ_WAIT; 497 xfer = chp->ch_queue->sc_xfer.tqh_first; 498 return xfer->c_intr(chp, xfer); 499 } 500 501 /* Put all disk in RESET state */ 502 void wdc_reset_channel(drvp) 503 struct ata_drive_datas *drvp; 504 { 505 struct channel_softc *chp = drvp->chnl_softc; 506 int drive; 507 WDCDEBUG_PRINT(("ata_reset_channel\n"), DEBUG_FUNCS); 508 (void) wdcreset(chp, VERBOSE); 509 for (drive = 0; drive < 2; drive++) { 510 chp->ch_drive[drive].state = 0; 511 } 512 } 513 514 int 515 wdcreset(chp, verb) 516 struct channel_softc *chp; 517 int verb; 518 { 519 int drv_mask1, drv_mask2; 520 521 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 522 WDSD_IBM); /* master */ 523 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 524 WDCTL_RST | WDCTL_IDS); 525 delay(1000); 526 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 527 WDCTL_IDS); 528 delay(1000); 529 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 530 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 531 WDCTL_4BIT); 532 533 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 534 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 535 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 536 if (verb && drv_mask2 != drv_mask1) { 537 printf("%s channel %d: reset failed for", 538 chp->wdc->sc_dev.dv_xname, chp->channel); 539 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 540 printf(" drive 0"); 541 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 542 printf(" drive 1"); 543 printf("\n"); 544 } 545 return (drv_mask1 != drv_mask2) ? 1 : 0; 546 } 547 548 static int 549 __wdcwait_reset(chp, drv_mask) 550 struct channel_softc *chp; 551 int drv_mask; 552 { 553 int timeout; 554 u_int8_t st0, st1; 555 /* wait for BSY to deassert */ 556 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 557 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 558 WDSD_IBM); /* master */ 559 delay(1); 560 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 561 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 562 WDSD_IBM | 0x10); /* slave */ 563 delay(1); 564 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 565 566 if ((drv_mask & 0x01) == 0) { 567 /* no master */ 568 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 569 /* No master, slave is ready, it's done */ 570 return drv_mask; 571 } 572 } else if ((drv_mask & 0x02) == 0) { 573 /* no slave */ 574 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 575 /* No slave, master is ready, it's done */ 576 return drv_mask; 577 } 578 } else { 579 /* Wait for both master and slave to be ready */ 580 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 581 return drv_mask; 582 } 583 } 584 delay(WDCDELAY); 585 } 586 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 587 if (st0 & WDCS_BSY) 588 drv_mask &= ~0x01; 589 if (st1 & WDCS_BSY) 590 drv_mask &= ~0x02; 591 return drv_mask; 592 } 593 594 /* 595 * Wait for a drive to be !BSY, and have mask in its status register. 596 * return -1 for a timeout after "timeout" ms. 597 */ 598 int 599 wdcwait(chp, mask, bits, timeout) 600 struct channel_softc *chp; 601 int mask, bits, timeout; 602 { 603 u_char status; 604 int time = 0; 605 #ifdef WDCNDELAY_DEBUG 606 extern int cold; 607 #endif 608 WDCDEBUG_PRINT(("wdcwait\n"), DEBUG_STATUS); 609 chp->ch_error = 0; 610 611 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 612 613 for (;;) { 614 chp->ch_status = status = 615 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 616 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 617 break; 618 if (++time > timeout) { 619 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 620 "error %x\n", status, 621 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 622 wd_error)), 623 DEBUG_STATUS); 624 return -1; 625 } 626 delay(WDCDELAY); 627 } 628 if (status & WDCS_ERR) 629 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 630 wd_error); 631 #ifdef WDCNDELAY_DEBUG 632 /* After autoconfig, there should be no long delays. */ 633 if (!cold && time > WDCNDELAY_DEBUG) { 634 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 635 if (xfer == NULL) 636 printf("%s channel %d: warning: busy-wait took %dus\n", 637 chp->wdc->sc_dev.dv_xname, chp->channel, 638 WDCDELAY * time); 639 else 640 printf("%s:%d:%d: warning: busy-wait took %dus\n", 641 chp->wdc->sc_dev.dv_xname, xfer->channel, 642 xfer->drive, 643 WDCDELAY * time); 644 } 645 #endif 646 return 0; 647 } 648 649 void 650 wdctimeout(arg) 651 void *arg; 652 { 653 struct channel_softc *chp = (struct channel_softc *)arg; 654 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 655 int s; 656 657 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 658 659 s = splbio(); 660 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 661 __wdcerror(chp, "lost interrupt"); 662 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 663 "atapi":"ata"); 664 printf("\tc_bcount: %d\n", xfer->c_bcount); 665 printf("\tc_skip: %d\n", xfer->c_skip); 666 /* 667 * Call the interrupt routine. If we just missed and interrupt, 668 * it will do what's needed. Else, it will take the needed 669 * action (reset the device). 670 */ 671 xfer->c_flags |= C_TIMEOU; 672 chp->ch_flags &= ~WDCF_IRQ_WAIT; 673 xfer->c_intr(chp, xfer); 674 } else 675 __wdcerror(chp, "missing untimeout"); 676 splx(s); 677 } 678 679 /* 680 * Probe drive's capabilites, for use by the controller later 681 * Assumes drvp points to an existing drive. 682 * XXX this should be a controller-indep function 683 */ 684 void 685 wdc_probe_caps(drvp) 686 struct ata_drive_datas *drvp; 687 { 688 struct ataparams params, params2; 689 struct channel_softc *chp = drvp->chnl_softc; 690 struct device *drv_dev = drvp->drv_softc; 691 struct wdc_softc *wdc = chp->wdc; 692 int i, printed; 693 char *sep = ""; 694 695 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 696 /* IDENTIFY failed. Can't tell more about the device */ 697 return; 698 } 699 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 700 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 701 /* 702 * Controller claims 16 and 32 bit transferts. 703 * Re-do an UDENTIFY with 32-bit transferts, 704 * and compare results. 705 */ 706 drvp->drive_flags |= DRIVE_CAP32; 707 ata_get_params(drvp, AT_POLL, ¶ms2); 708 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 709 /* Not good. fall back to 16bits */ 710 drvp->drive_flags &= ~DRIVE_CAP32; 711 } else { 712 printf("%s: using 32-bits pio transfers\n", 713 drv_dev->dv_xname); 714 } 715 } 716 717 /* An ATAPI device is at last PIO mode 3 */ 718 if (drvp->drive_flags & DRIVE_ATAPI) 719 drvp->PIO_mode = 3; 720 721 /* 722 * It's not in the specs, but it seems that some drive 723 * returns 0xffff in atap_extensions when this field is invalid 724 */ 725 if (params.atap_extensions != 0xffff && 726 (params.atap_extensions & WDC_EXT_MODES)) { 727 printed = 0; 728 /* 729 * XXX some drives report something wrong here (they claim to 730 * support PIO mode 8 !). As mode is coded on 3 bits in 731 * SET FEATURE, limit it to 7 (so limit i to 4). 732 */ 733 for (i = 4; i >= 0; i--) { 734 if ((params.atap_piomode_supp & (1 << i)) == 0) 735 continue; 736 /* 737 * See if mode is accepted. 738 * If the controller can't set its PIO mode, 739 * assume the defaults are good, so don't try 740 * to set it 741 */ 742 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 743 if (ata_set_mode(drvp, 0x08 | (i + 3), 744 AT_POLL) != CMD_OK) 745 continue; 746 if (!printed) { 747 printf("%s: PIO mode %d", drv_dev->dv_xname, 748 i + 3); 749 sep = ","; 750 printed = 1; 751 } 752 /* 753 * If controller's driver can't set its PIO mode, 754 * get the highter one for the drive. 755 */ 756 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 757 wdc->pio_mode >= i + 3) { 758 drvp->PIO_mode = i + 3; 759 break; 760 } 761 } 762 if (!printed) { 763 /* 764 * We didn't find a valid PIO mode. 765 * Assume the values returned for DMA are buggy too 766 */ 767 return; 768 } 769 printed = 0; 770 for (i = 7; i >= 0; i--) { 771 if ((params.atap_dmamode_supp & (1 << i)) == 0) 772 continue; 773 if ((wdc->cap & WDC_CAPABILITY_DMA) && 774 (wdc->cap & WDC_CAPABILITY_MODE)) 775 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 776 != CMD_OK) 777 continue; 778 if (!printed) { 779 printf("%s DMA mode %d", sep, i); 780 sep = ","; 781 printed = 1; 782 } 783 if (wdc->cap & WDC_CAPABILITY_DMA) { 784 if ((wdc->cap & WDC_CAPABILITY_MODE) && 785 wdc->dma_mode < i) 786 continue; 787 drvp->DMA_mode = i; 788 drvp->drive_flags |= DRIVE_DMA; 789 } 790 break; 791 } 792 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 793 for (i = 7; i >= 0; i--) { 794 if ((params.atap_udmamode_supp & (1 << i)) 795 == 0) 796 continue; 797 if ((wdc->cap & WDC_CAPABILITY_MODE) && 798 (wdc->cap & WDC_CAPABILITY_UDMA)) 799 if (ata_set_mode(drvp, 0x40 | i, 800 AT_POLL) != CMD_OK) 801 continue; 802 printf("%s UDMA mode %d", sep, i); 803 sep = ","; 804 /* 805 * ATA-4 specs says if a mode is supported, 806 * all lower modes shall be supported. 807 * No need to look further. 808 */ 809 if (wdc->cap & WDC_CAPABILITY_UDMA) { 810 drvp->UDMA_mode = i; 811 drvp->drive_flags |= DRIVE_UDMA; 812 } 813 break; 814 } 815 } 816 printf("\n"); 817 } 818 } 819 820 int 821 wdc_exec_command(drvp, wdc_c) 822 struct ata_drive_datas *drvp; 823 struct wdc_command *wdc_c; 824 { 825 struct channel_softc *chp = drvp->chnl_softc; 826 struct wdc_xfer *xfer; 827 int s, ret; 828 829 WDCDEBUG_PRINT(("wdc_exec_command\n"), DEBUG_FUNCS); 830 831 /* set up an xfer and queue. Wait for completion */ 832 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 833 WDC_NOSLEEP); 834 if (xfer == NULL) { 835 return WDC_TRY_AGAIN; 836 } 837 838 if (wdc_c->flags & AT_POLL) 839 xfer->c_flags |= C_POLL; 840 xfer->drive = drvp->drive; 841 xfer->databuf = wdc_c->data; 842 xfer->c_bcount = wdc_c->bcount; 843 xfer->cmd = wdc_c; 844 xfer->c_start = __wdccommand_start; 845 xfer->c_intr = __wdccommand_intr; 846 847 s = splbio(); 848 wdc_exec_xfer(chp, xfer); 849 #ifdef DIAGNOSTIC 850 if ((wdc_c->flags & AT_POLL) != 0 && 851 (wdc_c->flags & AT_DONE) == 0) 852 panic("wdc_exec_command: polled command not done\n"); 853 #endif 854 if (wdc_c->flags & AT_DONE) { 855 ret = WDC_COMPLETE; 856 } else { 857 if (wdc_c->flags & AT_WAIT) { 858 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 859 ret = WDC_COMPLETE; 860 } else { 861 ret = WDC_QUEUED; 862 } 863 } 864 splx(s); 865 return ret; 866 } 867 868 void 869 __wdccommand_start(chp, xfer) 870 struct channel_softc *chp; 871 struct wdc_xfer *xfer; 872 { 873 int drive = xfer->drive; 874 struct wdc_command *wdc_c = xfer->cmd; 875 876 WDCDEBUG_PRINT(("__wdccommand_start\n"), DEBUG_FUNCS); 877 878 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 879 WDSD_IBM | (drive << 4)); 880 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 881 wdc_c->timeout) != 0) { 882 wdc_c->flags |= AT_TIMEOU; 883 __wdccommand_done(chp, xfer); 884 } 885 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 886 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 887 if ((wdc_c->flags & AT_POLL) == 0) { 888 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 889 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 890 return; 891 } 892 /* 893 * Polled command. Wait for drive ready or drq. Done in intr(). 894 * Wait for at last 400ns for status bit to be valid. 895 */ 896 delay(10); 897 if (__wdccommand_intr(chp, xfer) == 0) { 898 wdc_c->flags |= AT_TIMEOU; 899 __wdccommand_done(chp, xfer); 900 } 901 } 902 903 int 904 __wdccommand_intr(chp, xfer) 905 struct channel_softc *chp; 906 struct wdc_xfer *xfer; 907 { 908 struct wdc_command *wdc_c = xfer->cmd; 909 int bcount = wdc_c->bcount; 910 char *data = wdc_c->data; 911 912 WDCDEBUG_PRINT(("__wdccommand_intr\n"), DEBUG_INTR); 913 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 914 wdc_c->timeout)) { 915 wdc_c->flags |= AT_ERROR; 916 __wdccommand_done(chp, xfer); 917 return 1; 918 } 919 if (wdc_c->flags & AT_READ) { 920 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 921 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 922 0, (u_int32_t*)data, bcount >> 2); 923 data += bcount & 0xfffffffc; 924 bcount = bcount & 0x03; 925 } 926 if (bcount > 0) 927 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 928 wd_data, (u_int16_t *)data, bcount >> 1); 929 } else if (wdc_c->flags & AT_WRITE) { 930 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 931 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 932 0, (u_int32_t*)data, bcount >> 2); 933 data += bcount & 0xfffffffc; 934 bcount = bcount & 0x03; 935 } 936 if (bcount > 0) 937 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 938 wd_data, (u_int16_t *)data, bcount >> 1); 939 } 940 __wdccommand_done(chp, xfer); 941 return 1; 942 } 943 944 void 945 __wdccommand_done(chp, xfer) 946 struct channel_softc *chp; 947 struct wdc_xfer *xfer; 948 { 949 int needdone = xfer->c_flags & C_NEEDDONE; 950 struct wdc_command *wdc_c = xfer->cmd; 951 952 WDCDEBUG_PRINT(("__wdccommand_done\n"), DEBUG_FUNCS); 953 if (chp->ch_status & WDCS_DWF) 954 wdc_c->flags |= AT_DF; 955 if (chp->ch_status & WDCS_ERR) { 956 wdc_c->flags |= AT_ERROR; 957 wdc_c->r_error = chp->ch_error; 958 } 959 wdc_c->flags |= AT_DONE; 960 wdc_free_xfer(chp, xfer); 961 if (needdone) { 962 if (wdc_c->flags & AT_WAIT) 963 wakeup(wdc_c); 964 else 965 wdc_c->callback(wdc_c->callback_arg); 966 } 967 return; 968 } 969 970 /* 971 * Send a command. The drive should be ready. 972 * Assumes interrupts are blocked. 973 */ 974 void 975 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 976 struct channel_softc *chp; 977 u_int8_t drive; 978 u_int8_t command; 979 u_int16_t cylin; 980 u_int8_t head, sector, count, precomp; 981 { 982 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 983 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 984 chp->channel, drive, command, cylin, head, sector, count, precomp), 985 DEBUG_FUNCS); 986 987 /* Select drive, head, and addressing mode. */ 988 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 989 WDSD_IBM | (drive << 4) | head); 990 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 991 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 992 precomp); 993 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 994 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 995 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 996 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 997 998 /* Send command. */ 999 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1000 return; 1001 } 1002 1003 /* 1004 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1005 * tested by the caller. 1006 */ 1007 void 1008 wdccommandshort(chp, drive, command) 1009 struct channel_softc *chp; 1010 int drive; 1011 int command; 1012 { 1013 1014 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1015 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1016 DEBUG_FUNCS); 1017 1018 /* Select drive. */ 1019 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1020 WDSD_IBM | (drive << 4)); 1021 1022 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1023 } 1024 1025 /* Add a command to the queue and start controller. Must be called at splbio */ 1026 1027 void 1028 wdc_exec_xfer(chp, xfer) 1029 struct channel_softc *chp; 1030 struct wdc_xfer *xfer; 1031 { 1032 WDCDEBUG_PRINT(("wdc_exec_xfer %p\n", xfer), DEBUG_FUNCS); 1033 1034 /* complete xfer setup */ 1035 xfer->channel = chp->channel; 1036 1037 /* 1038 * If we are a polled command, and the list is not empty, 1039 * we are doing a dump. Drop the list to allow the polled command 1040 * to complete, we're going to reboot soon anyway. 1041 */ 1042 if ((xfer->c_flags & C_POLL) != 0 && 1043 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1044 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1045 } 1046 /* insert at the end of command list */ 1047 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1048 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1049 chp->ch_flags), DEBUG_FUNCS); 1050 wdcstart(chp->wdc, chp->channel); 1051 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1052 } 1053 1054 struct wdc_xfer * 1055 wdc_get_xfer(flags) 1056 int flags; 1057 { 1058 struct wdc_xfer *xfer; 1059 int s; 1060 1061 s = splbio(); 1062 if ((xfer = xfer_free_list.lh_first) != NULL) { 1063 LIST_REMOVE(xfer, free_list); 1064 splx(s); 1065 #ifdef DIAGNOSTIC 1066 if ((xfer->c_flags & C_INUSE) != 0) 1067 panic("wdc_get_xfer: xfer already in use\n"); 1068 #endif 1069 } else { 1070 splx(s); 1071 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1072 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1073 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1074 if (xfer == NULL) 1075 return 0; 1076 #ifdef DIAGNOSTIC 1077 xfer->c_flags &= ~C_INUSE; 1078 #endif 1079 #ifdef WDCDEBUG 1080 wdc_nxfer++; 1081 #endif 1082 } 1083 #ifdef DIAGNOSTIC 1084 if ((xfer->c_flags & C_INUSE) != 0) 1085 panic("wdc_get_xfer: xfer already in use\n"); 1086 #endif 1087 memset(xfer, 0, sizeof(struct wdc_xfer)); 1088 xfer->c_flags = C_INUSE; 1089 return xfer; 1090 } 1091 1092 void 1093 wdc_free_xfer(chp, xfer) 1094 struct channel_softc *chp; 1095 struct wdc_xfer *xfer; 1096 { 1097 struct wdc_softc *wdc = chp->wdc; 1098 int s; 1099 1100 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1101 (*wdc->free_hw)(chp); 1102 s = splbio(); 1103 chp->ch_flags &= ~WDCF_ACTIVE; 1104 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1105 xfer->c_flags &= ~C_INUSE; 1106 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1107 splx(s); 1108 } 1109 1110 static void 1111 __wdcerror(chp, msg) 1112 struct channel_softc *chp; 1113 char *msg; 1114 { 1115 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1116 if (xfer == NULL) 1117 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1118 msg); 1119 else 1120 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1121 xfer->channel, xfer->drive, msg); 1122 } 1123 1124 /* 1125 * the bit bucket 1126 */ 1127 void 1128 wdcbit_bucket(chp, size) 1129 struct channel_softc *chp; 1130 int size; 1131 { 1132 1133 for (; size >= 2; size -= 2) 1134 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1135 if (size) 1136 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1137 } 1138
Indexes created Mon Sep 22 10:09:38 GMT 2025