wdc.c revision 1.34
1 /* $NetBSD: wdc.c,v 1.34 1998/10/13 15:02:42 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 185 WDSD_IBM); 186 delay(1); 187 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM | 0x10); 190 delay(1); 191 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 193 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 194 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 195 st0, st1), DEBUG_PROBE); 196 197 if (st0 == 0xff) 198 ret_value &= ~0x01; 199 if (st1 == 0xff) 200 ret_value &= ~0x02; 201 if (ret_value == 0) 202 return 0; 203 204 /* assert SRST, wait for reset to complete */ 205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 206 WDSD_IBM); 207 delay(1); 208 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 209 WDCTL_RST | WDCTL_IDS); 210 DELAY(1000); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_IDS); 213 delay(1000); 214 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 216 delay(1); 217 218 ret_value = __wdcwait_reset(chp, ret_value); 219 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 221 ret_value), DEBUG_PROBE); 222 223 /* if reset failed, there's nothing here */ 224 if (ret_value == 0) 225 return 0; 226 227 /* 228 * Test presence of drives. First test register signatures looking for 229 * ATAPI devices , then rescan and try an ATA command, in case it's an 230 * old drive. 231 * Fill in drive_flags accordingly 232 */ 233 for (drive = 0; drive < 2; drive++) { 234 if ((ret_value & (0x01 << drive)) == 0) 235 continue; 236 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 237 WDSD_IBM | (drive << 4)); 238 delay(1); 239 /* Save registers contents */ 240 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 241 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 242 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 243 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 244 245 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 248 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 249 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 250 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 251 } 252 } 253 for (drive = 0; drive < 2; drive++) { 254 if ((ret_value & (0x01 << drive)) == 0 || 255 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 256 continue; 257 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 258 WDSD_IBM | (drive << 4)); 259 delay(1); 260 /* 261 * Maybe it's an old device, so don't rely on ATA sig. 262 * Test registers writability (Error register not writable, 263 * but cyllo is), then try an ATA command. 264 */ 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 268 0x58 || 269 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 270 0xa5) { 271 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 272 "failed\n", 273 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 274 chp->channel, drive), DEBUG_PROBE); 275 ret_value &= ~(0x01 << drive); 276 continue; 277 } 278 if (wait_for_ready(chp, 10000) != 0) { 279 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 280 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 281 chp->channel, drive), DEBUG_PROBE); 282 ret_value &= ~(0x01 << drive); 283 continue; 284 } 285 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 286 WDCC_DIAGNOSE); 287 if (wait_for_ready(chp, 10000) == 0) { 288 chp->ch_drive[drive].drive_flags |= 289 DRIVE_ATA; 290 } else { 291 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive), DEBUG_PROBE); 294 ret_value &= ~(0x01 << drive); 295 } 296 } 297 return (ret_value); 298 } 299 300 void 301 wdcattach(chp) 302 struct channel_softc *chp; 303 { 304 int channel_flags, ctrl_flags, i; 305 struct ata_atapi_attach aa_link; 306 307 LIST_INIT(&xfer_free_list); 308 for (i = 0; i < 2; i++) { 309 chp->ch_drive[i].chnl_softc = chp; 310 chp->ch_drive[i].drive = i; 311 /* If controller can't do 16bit flag the drives as 32bit */ 312 if ((chp->wdc->cap & 313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 314 WDC_CAPABILITY_DATA32) 315 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 316 } 317 318 if (wdcprobe(chp) == 0) 319 return; /* If no drives, abort attach here */ 320 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 323 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 324 325 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 326 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 327 DEBUG_PROBE); 328 329 /* 330 * Attach an ATAPI bus, if needed. 331 */ 332 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 333 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 334 #if NATAPIBUS > 0 335 wdc_atapibus_attach(chp); 336 #else 337 /* 338 * Fills in a fake aa_link and call config_found, so that 339 * the config machinery will print 340 * "atapibus at xxx not configured" 341 */ 342 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 343 aa_link.aa_type = T_ATAPI; 344 aa_link.aa_channel = chp->channel; 345 aa_link.aa_openings = 1; 346 aa_link.aa_drv_data = 0; 347 aa_link.aa_bus_private = NULL; 348 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 349 atapi_print); 350 #endif 351 } 352 353 for (i = 0; i < 2; i++) { 354 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 355 continue; 356 } 357 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 358 aa_link.aa_type = T_ATA; 359 aa_link.aa_channel = chp->channel; 360 aa_link.aa_openings = 1; 361 aa_link.aa_drv_data = &chp->ch_drive[i]; 362 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 363 wdc_probe_caps(&chp->ch_drive[i]); 364 } 365 366 /* 367 * reset drive_flags for unnatached devices, reset state for attached 368 * ones 369 */ 370 for (i = 0; i < 2; i++) { 371 if (chp->ch_drive[i].drv_softc == NULL) 372 chp->ch_drive[i].drive_flags = 0; 373 else 374 chp->ch_drive[i].state = 0; 375 } 376 377 /* 378 * Reset channel. The probe, with some combinations of ATA/ATAPI 379 * devices keep it in a mostly working, but strange state (with busy 380 * led on) 381 */ 382 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 383 wdcreset(chp, VERBOSE); 384 /* 385 * Read status registers to avoid spurious interrupts. 386 */ 387 for (i = 1; i >= 0; i--) { 388 if (chp->ch_drive[i].drive_flags & DRIVE) { 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_sdh, WDSD_IBM | (i << 4)); 391 if (wait_for_unbusy(chp, 10000) < 0) 392 printf("%s:%d:%d: device busy\n", 393 chp->wdc->sc_dev.dv_xname, 394 chp->channel, i); 395 } 396 } 397 } 398 } 399 400 /* 401 * Start I/O on a controller, for the given channel. 402 * The first xfer may be not for our channel if the channel queues 403 * are shared. 404 */ 405 void 406 wdcstart(wdc, channel) 407 struct wdc_softc *wdc; 408 int channel; 409 { 410 struct wdc_xfer *xfer; 411 struct channel_softc *chp; 412 413 /* is there a xfer ? */ 414 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 415 return; 416 chp = &wdc->channels[xfer->channel]; 417 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 418 return; /* channel aleady active */ 419 } 420 #ifdef DIAGNOSTIC 421 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 422 panic("wdcstart: channel waiting for irq\n"); 423 #endif 424 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 425 if (!(*wdc->claim_hw)(chp, 0)) 426 return; 427 428 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 429 xfer->channel, xfer->drive), DEBUG_XFERS); 430 chp->ch_flags |= WDCF_ACTIVE; 431 xfer->c_start(chp, xfer); 432 } 433 434 /* restart an interrupted I/O */ 435 void 436 wdcrestart(v) 437 void *v; 438 { 439 struct channel_softc *chp = v; 440 int s; 441 442 s = splbio(); 443 wdcstart(chp->wdc, chp->channel); 444 splx(s); 445 } 446 447 448 /* 449 * Interrupt routine for the controller. Acknowledge the interrupt, check for 450 * errors on the current operation, mark it done if necessary, and start the 451 * next request. Also check for a partially done transfer, and continue with 452 * the next chunk if so. 453 */ 454 int 455 wdcintr(arg) 456 void *arg; 457 { 458 struct channel_softc *chp = arg; 459 struct wdc_xfer *xfer; 460 461 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 462 #if 0 463 /* Clear the pending interrupt and abort. */ 464 u_int8_t s = 465 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 466 #ifdef WDCDEBUG 467 u_int8_t e = 468 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 469 u_int8_t i = 470 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 471 #else 472 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 473 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 474 #endif 475 476 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 477 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 478 479 if (s & WDCS_DRQ) { 480 int len; 481 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 482 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 483 chp->cmd_ioh, wd_cyl_hi); 484 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 485 len), DEBUG_INTR); 486 wdcbit_bucket (chp, len); 487 } 488 #else 489 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 490 #endif 491 return 0; 492 } 493 494 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 495 untimeout(wdctimeout, chp); 496 chp->ch_flags &= ~WDCF_IRQ_WAIT; 497 xfer = chp->ch_queue->sc_xfer.tqh_first; 498 return xfer->c_intr(chp, xfer); 499 } 500 501 /* Put all disk in RESET state */ 502 void wdc_reset_channel(drvp) 503 struct ata_drive_datas *drvp; 504 { 505 struct channel_softc *chp = drvp->chnl_softc; 506 int drive; 507 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 508 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 509 DEBUG_FUNCS); 510 (void) wdcreset(chp, VERBOSE); 511 for (drive = 0; drive < 2; drive++) { 512 chp->ch_drive[drive].state = 0; 513 } 514 } 515 516 int 517 wdcreset(chp, verb) 518 struct channel_softc *chp; 519 int verb; 520 { 521 int drv_mask1, drv_mask2; 522 523 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 524 WDSD_IBM); /* master */ 525 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 526 WDCTL_RST | WDCTL_IDS); 527 delay(1000); 528 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 529 WDCTL_IDS); 530 delay(1000); 531 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 532 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 533 WDCTL_4BIT); 534 535 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 536 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 537 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 538 if (verb && drv_mask2 != drv_mask1) { 539 printf("%s channel %d: reset failed for", 540 chp->wdc->sc_dev.dv_xname, chp->channel); 541 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 542 printf(" drive 0"); 543 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 544 printf(" drive 1"); 545 printf("\n"); 546 } 547 return (drv_mask1 != drv_mask2) ? 1 : 0; 548 } 549 550 static int 551 __wdcwait_reset(chp, drv_mask) 552 struct channel_softc *chp; 553 int drv_mask; 554 { 555 int timeout; 556 u_int8_t st0, st1; 557 /* wait for BSY to deassert */ 558 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 559 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 560 WDSD_IBM); /* master */ 561 delay(1); 562 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 563 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 564 WDSD_IBM | 0x10); /* slave */ 565 delay(1); 566 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 567 568 if ((drv_mask & 0x01) == 0) { 569 /* no master */ 570 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 571 /* No master, slave is ready, it's done */ 572 return drv_mask; 573 } 574 } else if ((drv_mask & 0x02) == 0) { 575 /* no slave */ 576 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 577 /* No slave, master is ready, it's done */ 578 return drv_mask; 579 } 580 } else { 581 /* Wait for both master and slave to be ready */ 582 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 583 return drv_mask; 584 } 585 } 586 delay(WDCDELAY); 587 } 588 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 589 if (st0 & WDCS_BSY) 590 drv_mask &= ~0x01; 591 if (st1 & WDCS_BSY) 592 drv_mask &= ~0x02; 593 return drv_mask; 594 } 595 596 /* 597 * Wait for a drive to be !BSY, and have mask in its status register. 598 * return -1 for a timeout after "timeout" ms. 599 */ 600 int 601 wdcwait(chp, mask, bits, timeout) 602 struct channel_softc *chp; 603 int mask, bits, timeout; 604 { 605 u_char status; 606 int time = 0; 607 #ifdef WDCNDELAY_DEBUG 608 extern int cold; 609 #endif 610 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 611 chp->channel), DEBUG_STATUS); 612 chp->ch_error = 0; 613 614 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 615 616 for (;;) { 617 chp->ch_status = status = 618 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 619 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 620 break; 621 if (++time > timeout) { 622 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 623 "error %x\n", status, 624 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 625 wd_error)), 626 DEBUG_STATUS); 627 return -1; 628 } 629 delay(WDCDELAY); 630 } 631 if (status & WDCS_ERR) 632 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 633 wd_error); 634 #ifdef WDCNDELAY_DEBUG 635 /* After autoconfig, there should be no long delays. */ 636 if (!cold && time > WDCNDELAY_DEBUG) { 637 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 638 if (xfer == NULL) 639 printf("%s channel %d: warning: busy-wait took %dus\n", 640 chp->wdc->sc_dev.dv_xname, chp->channel, 641 WDCDELAY * time); 642 else 643 printf("%s:%d:%d: warning: busy-wait took %dus\n", 644 chp->wdc->sc_dev.dv_xname, xfer->channel, 645 xfer->drive, 646 WDCDELAY * time); 647 } 648 #endif 649 return 0; 650 } 651 652 void 653 wdctimeout(arg) 654 void *arg; 655 { 656 struct channel_softc *chp = (struct channel_softc *)arg; 657 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 658 int s; 659 660 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 661 662 s = splbio(); 663 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 664 __wdcerror(chp, "lost interrupt"); 665 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 666 "atapi":"ata"); 667 printf("\tc_bcount: %d\n", xfer->c_bcount); 668 printf("\tc_skip: %d\n", xfer->c_skip); 669 /* 670 * Call the interrupt routine. If we just missed and interrupt, 671 * it will do what's needed. Else, it will take the needed 672 * action (reset the device). 673 */ 674 xfer->c_flags |= C_TIMEOU; 675 chp->ch_flags &= ~WDCF_IRQ_WAIT; 676 xfer->c_intr(chp, xfer); 677 } else 678 __wdcerror(chp, "missing untimeout"); 679 splx(s); 680 } 681 682 /* 683 * Probe drive's capabilites, for use by the controller later 684 * Assumes drvp points to an existing drive. 685 * XXX this should be a controller-indep function 686 */ 687 void 688 wdc_probe_caps(drvp) 689 struct ata_drive_datas *drvp; 690 { 691 struct ataparams params, params2; 692 struct channel_softc *chp = drvp->chnl_softc; 693 struct device *drv_dev = drvp->drv_softc; 694 struct wdc_softc *wdc = chp->wdc; 695 int i, printed; 696 char *sep = ""; 697 698 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 699 /* IDENTIFY failed. Can't tell more about the device */ 700 return; 701 } 702 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 703 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 704 /* 705 * Controller claims 16 and 32 bit transferts. 706 * Re-do an UDENTIFY with 32-bit transferts, 707 * and compare results. 708 */ 709 drvp->drive_flags |= DRIVE_CAP32; 710 ata_get_params(drvp, AT_POLL, ¶ms2); 711 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 712 /* Not good. fall back to 16bits */ 713 drvp->drive_flags &= ~DRIVE_CAP32; 714 } else { 715 printf("%s: using 32-bits pio transfers\n", 716 drv_dev->dv_xname); 717 } 718 } 719 720 /* An ATAPI device is at last PIO mode 3 */ 721 if (drvp->drive_flags & DRIVE_ATAPI) 722 drvp->PIO_mode = 3; 723 724 /* 725 * It's not in the specs, but it seems that some drive 726 * returns 0xffff in atap_extensions when this field is invalid 727 */ 728 if (params.atap_extensions != 0xffff && 729 (params.atap_extensions & WDC_EXT_MODES)) { 730 printed = 0; 731 /* 732 * XXX some drives report something wrong here (they claim to 733 * support PIO mode 8 !). As mode is coded on 3 bits in 734 * SET FEATURE, limit it to 7 (so limit i to 4). 735 */ 736 for (i = 4; i >= 0; i--) { 737 if ((params.atap_piomode_supp & (1 << i)) == 0) 738 continue; 739 /* 740 * See if mode is accepted. 741 * If the controller can't set its PIO mode, 742 * assume the defaults are good, so don't try 743 * to set it 744 */ 745 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 746 if (ata_set_mode(drvp, 0x08 | (i + 3), 747 AT_POLL) != CMD_OK) 748 continue; 749 if (!printed) { 750 printf("%s: PIO mode %d", drv_dev->dv_xname, 751 i + 3); 752 sep = ","; 753 printed = 1; 754 } 755 /* 756 * If controller's driver can't set its PIO mode, 757 * get the highter one for the drive. 758 */ 759 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 760 wdc->pio_mode >= i + 3) { 761 drvp->PIO_mode = i + 3; 762 break; 763 } 764 } 765 if (!printed) { 766 /* 767 * We didn't find a valid PIO mode. 768 * Assume the values returned for DMA are buggy too 769 */ 770 printf("\n"); 771 return; 772 } 773 printed = 0; 774 for (i = 7; i >= 0; i--) { 775 if ((params.atap_dmamode_supp & (1 << i)) == 0) 776 continue; 777 if ((wdc->cap & WDC_CAPABILITY_DMA) && 778 (wdc->cap & WDC_CAPABILITY_MODE)) 779 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 780 != CMD_OK) 781 continue; 782 if (!printed) { 783 printf("%s DMA mode %d", sep, i); 784 sep = ","; 785 printed = 1; 786 } 787 if (wdc->cap & WDC_CAPABILITY_DMA) { 788 if ((wdc->cap & WDC_CAPABILITY_MODE) && 789 wdc->dma_mode < i) 790 continue; 791 drvp->DMA_mode = i; 792 drvp->drive_flags |= DRIVE_DMA; 793 } 794 break; 795 } 796 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 797 for (i = 7; i >= 0; i--) { 798 if ((params.atap_udmamode_supp & (1 << i)) 799 == 0) 800 continue; 801 if ((wdc->cap & WDC_CAPABILITY_MODE) && 802 (wdc->cap & WDC_CAPABILITY_UDMA)) 803 if (ata_set_mode(drvp, 0x40 | i, 804 AT_POLL) != CMD_OK) 805 continue; 806 printf("%s UDMA mode %d", sep, i); 807 sep = ","; 808 /* 809 * ATA-4 specs says if a mode is supported, 810 * all lower modes shall be supported. 811 * No need to look further. 812 */ 813 if (wdc->cap & WDC_CAPABILITY_UDMA) { 814 drvp->UDMA_mode = i; 815 drvp->drive_flags |= DRIVE_UDMA; 816 } 817 break; 818 } 819 } 820 printf("\n"); 821 } 822 } 823 824 int 825 wdc_exec_command(drvp, wdc_c) 826 struct ata_drive_datas *drvp; 827 struct wdc_command *wdc_c; 828 { 829 struct channel_softc *chp = drvp->chnl_softc; 830 struct wdc_xfer *xfer; 831 int s, ret; 832 833 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 834 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 835 DEBUG_FUNCS); 836 837 /* set up an xfer and queue. Wait for completion */ 838 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 839 WDC_NOSLEEP); 840 if (xfer == NULL) { 841 return WDC_TRY_AGAIN; 842 } 843 844 if (wdc_c->flags & AT_POLL) 845 xfer->c_flags |= C_POLL; 846 xfer->drive = drvp->drive; 847 xfer->databuf = wdc_c->data; 848 xfer->c_bcount = wdc_c->bcount; 849 xfer->cmd = wdc_c; 850 xfer->c_start = __wdccommand_start; 851 xfer->c_intr = __wdccommand_intr; 852 853 s = splbio(); 854 wdc_exec_xfer(chp, xfer); 855 #ifdef DIAGNOSTIC 856 if ((wdc_c->flags & AT_POLL) != 0 && 857 (wdc_c->flags & AT_DONE) == 0) 858 panic("wdc_exec_command: polled command not done\n"); 859 #endif 860 if (wdc_c->flags & AT_DONE) { 861 ret = WDC_COMPLETE; 862 } else { 863 if (wdc_c->flags & AT_WAIT) { 864 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 865 ret = WDC_COMPLETE; 866 } else { 867 ret = WDC_QUEUED; 868 } 869 } 870 splx(s); 871 return ret; 872 } 873 874 void 875 __wdccommand_start(chp, xfer) 876 struct channel_softc *chp; 877 struct wdc_xfer *xfer; 878 { 879 int drive = xfer->drive; 880 struct wdc_command *wdc_c = xfer->cmd; 881 882 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 883 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 884 DEBUG_FUNCS); 885 886 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 887 WDSD_IBM | (drive << 4)); 888 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 889 wdc_c->timeout) != 0) { 890 wdc_c->flags |= AT_TIMEOU; 891 __wdccommand_done(chp, xfer); 892 } 893 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 894 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 895 if ((wdc_c->flags & AT_POLL) == 0) { 896 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 897 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 898 return; 899 } 900 /* 901 * Polled command. Wait for drive ready or drq. Done in intr(). 902 * Wait for at last 400ns for status bit to be valid. 903 */ 904 delay(10); 905 if (__wdccommand_intr(chp, xfer) == 0) { 906 wdc_c->flags |= AT_TIMEOU; 907 __wdccommand_done(chp, xfer); 908 } 909 } 910 911 int 912 __wdccommand_intr(chp, xfer) 913 struct channel_softc *chp; 914 struct wdc_xfer *xfer; 915 { 916 struct wdc_command *wdc_c = xfer->cmd; 917 int bcount = wdc_c->bcount; 918 char *data = wdc_c->data; 919 920 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 921 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 922 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 923 wdc_c->timeout)) { 924 wdc_c->flags |= AT_ERROR; 925 __wdccommand_done(chp, xfer); 926 return 1; 927 } 928 if (wdc_c->flags & AT_READ) { 929 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 930 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 931 0, (u_int32_t*)data, bcount >> 2); 932 data += bcount & 0xfffffffc; 933 bcount = bcount & 0x03; 934 } 935 if (bcount > 0) 936 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 937 wd_data, (u_int16_t *)data, bcount >> 1); 938 } else if (wdc_c->flags & AT_WRITE) { 939 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 940 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 941 0, (u_int32_t*)data, bcount >> 2); 942 data += bcount & 0xfffffffc; 943 bcount = bcount & 0x03; 944 } 945 if (bcount > 0) 946 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 947 wd_data, (u_int16_t *)data, bcount >> 1); 948 } 949 __wdccommand_done(chp, xfer); 950 return 1; 951 } 952 953 void 954 __wdccommand_done(chp, xfer) 955 struct channel_softc *chp; 956 struct wdc_xfer *xfer; 957 { 958 int needdone = xfer->c_flags & C_NEEDDONE; 959 struct wdc_command *wdc_c = xfer->cmd; 960 961 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 962 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 963 if (chp->ch_status & WDCS_DWF) 964 wdc_c->flags |= AT_DF; 965 if (chp->ch_status & WDCS_ERR) { 966 wdc_c->flags |= AT_ERROR; 967 wdc_c->r_error = chp->ch_error; 968 } 969 wdc_c->flags |= AT_DONE; 970 wdc_free_xfer(chp, xfer); 971 if (needdone) { 972 if (wdc_c->flags & AT_WAIT) 973 wakeup(wdc_c); 974 else 975 wdc_c->callback(wdc_c->callback_arg); 976 } 977 return; 978 } 979 980 /* 981 * Send a command. The drive should be ready. 982 * Assumes interrupts are blocked. 983 */ 984 void 985 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 986 struct channel_softc *chp; 987 u_int8_t drive; 988 u_int8_t command; 989 u_int16_t cylin; 990 u_int8_t head, sector, count, precomp; 991 { 992 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 993 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 994 chp->channel, drive, command, cylin, head, sector, count, precomp), 995 DEBUG_FUNCS); 996 997 /* Select drive, head, and addressing mode. */ 998 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 999 WDSD_IBM | (drive << 4) | head); 1000 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1001 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1002 precomp); 1003 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1004 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1005 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1006 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1007 1008 /* Send command. */ 1009 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1010 return; 1011 } 1012 1013 /* 1014 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1015 * tested by the caller. 1016 */ 1017 void 1018 wdccommandshort(chp, drive, command) 1019 struct channel_softc *chp; 1020 int drive; 1021 int command; 1022 { 1023 1024 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1025 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1026 DEBUG_FUNCS); 1027 1028 /* Select drive. */ 1029 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1030 WDSD_IBM | (drive << 4)); 1031 1032 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1033 } 1034 1035 /* Add a command to the queue and start controller. Must be called at splbio */ 1036 1037 void 1038 wdc_exec_xfer(chp, xfer) 1039 struct channel_softc *chp; 1040 struct wdc_xfer *xfer; 1041 { 1042 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1043 chp->channel, xfer->drive), DEBUG_XFERS); 1044 1045 /* complete xfer setup */ 1046 xfer->channel = chp->channel; 1047 1048 /* 1049 * If we are a polled command, and the list is not empty, 1050 * we are doing a dump. Drop the list to allow the polled command 1051 * to complete, we're going to reboot soon anyway. 1052 */ 1053 if ((xfer->c_flags & C_POLL) != 0 && 1054 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1055 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1056 } 1057 /* insert at the end of command list */ 1058 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1059 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1060 chp->ch_flags), DEBUG_XFERS); 1061 wdcstart(chp->wdc, chp->channel); 1062 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1063 } 1064 1065 struct wdc_xfer * 1066 wdc_get_xfer(flags) 1067 int flags; 1068 { 1069 struct wdc_xfer *xfer; 1070 int s; 1071 1072 s = splbio(); 1073 if ((xfer = xfer_free_list.lh_first) != NULL) { 1074 LIST_REMOVE(xfer, free_list); 1075 splx(s); 1076 #ifdef DIAGNOSTIC 1077 if ((xfer->c_flags & C_INUSE) != 0) 1078 panic("wdc_get_xfer: xfer already in use\n"); 1079 #endif 1080 } else { 1081 splx(s); 1082 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1083 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1084 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1085 if (xfer == NULL) 1086 return 0; 1087 #ifdef DIAGNOSTIC 1088 xfer->c_flags &= ~C_INUSE; 1089 #endif 1090 #ifdef WDCDEBUG 1091 wdc_nxfer++; 1092 #endif 1093 } 1094 #ifdef DIAGNOSTIC 1095 if ((xfer->c_flags & C_INUSE) != 0) 1096 panic("wdc_get_xfer: xfer already in use\n"); 1097 #endif 1098 memset(xfer, 0, sizeof(struct wdc_xfer)); 1099 xfer->c_flags = C_INUSE; 1100 return xfer; 1101 } 1102 1103 void 1104 wdc_free_xfer(chp, xfer) 1105 struct channel_softc *chp; 1106 struct wdc_xfer *xfer; 1107 { 1108 struct wdc_softc *wdc = chp->wdc; 1109 int s; 1110 1111 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1112 (*wdc->free_hw)(chp); 1113 s = splbio(); 1114 chp->ch_flags &= ~WDCF_ACTIVE; 1115 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1116 xfer->c_flags &= ~C_INUSE; 1117 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1118 splx(s); 1119 } 1120 1121 static void 1122 __wdcerror(chp, msg) 1123 struct channel_softc *chp; 1124 char *msg; 1125 { 1126 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1127 if (xfer == NULL) 1128 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1129 msg); 1130 else 1131 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1132 xfer->channel, xfer->drive, msg); 1133 } 1134 1135 /* 1136 * the bit bucket 1137 */ 1138 void 1139 wdcbit_bucket(chp, size) 1140 struct channel_softc *chp; 1141 int size; 1142 { 1143 1144 for (; size >= 2; size -= 2) 1145 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1146 if (size) 1147 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1148 } 1149
Indexes created Thu Sep 25 16:09:42 GMT 2025