wdc.c revision 1.37
1 /* $NetBSD: wdc.c,v 1.37 1998/10/20 17:00:26 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 185 WDSD_IBM); 186 delay(1); 187 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM | 0x10); 190 delay(1); 191 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 193 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 194 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 195 st0, st1), DEBUG_PROBE); 196 197 if (st0 == 0xff) 198 ret_value &= ~0x01; 199 if (st1 == 0xff) 200 ret_value &= ~0x02; 201 if (ret_value == 0) 202 return 0; 203 204 /* assert SRST, wait for reset to complete */ 205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 206 WDSD_IBM); 207 delay(1); 208 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 209 WDCTL_RST | WDCTL_IDS); 210 DELAY(1000); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_IDS); 213 delay(1000); 214 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 216 delay(1); 217 218 ret_value = __wdcwait_reset(chp, ret_value); 219 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 221 ret_value), DEBUG_PROBE); 222 223 /* if reset failed, there's nothing here */ 224 if (ret_value == 0) 225 return 0; 226 227 /* 228 * Test presence of drives. First test register signatures looking for 229 * ATAPI devices , then rescan and try an ATA command, in case it's an 230 * old drive. 231 * Fill in drive_flags accordingly 232 */ 233 for (drive = 0; drive < 2; drive++) { 234 if ((ret_value & (0x01 << drive)) == 0) 235 continue; 236 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 237 WDSD_IBM | (drive << 4)); 238 delay(1); 239 /* Save registers contents */ 240 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 241 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 242 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 243 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 244 245 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 248 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 249 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 250 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 251 } 252 } 253 for (drive = 0; drive < 2; drive++) { 254 if ((ret_value & (0x01 << drive)) == 0 || 255 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 256 continue; 257 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 258 WDSD_IBM | (drive << 4)); 259 delay(1); 260 /* 261 * Maybe it's an old device, so don't rely on ATA sig. 262 * Test registers writability (Error register not writable, 263 * but cyllo is), then try an ATA command. 264 */ 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 268 0x58 || 269 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 270 0xa5) { 271 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 272 "failed\n", 273 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 274 chp->channel, drive), DEBUG_PROBE); 275 ret_value &= ~(0x01 << drive); 276 continue; 277 } 278 if (wait_for_ready(chp, 10000) != 0) { 279 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 280 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 281 chp->channel, drive), DEBUG_PROBE); 282 ret_value &= ~(0x01 << drive); 283 continue; 284 } 285 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 286 WDCC_DIAGNOSE); 287 if (wait_for_ready(chp, 10000) == 0) { 288 chp->ch_drive[drive].drive_flags |= 289 DRIVE_ATA; 290 } else { 291 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive), DEBUG_PROBE); 294 ret_value &= ~(0x01 << drive); 295 } 296 } 297 return (ret_value); 298 } 299 300 void 301 wdcattach(chp) 302 struct channel_softc *chp; 303 { 304 int channel_flags, ctrl_flags, i; 305 struct ata_atapi_attach aa_link; 306 307 LIST_INIT(&xfer_free_list); 308 for (i = 0; i < 2; i++) { 309 chp->ch_drive[i].chnl_softc = chp; 310 chp->ch_drive[i].drive = i; 311 /* If controller can't do 16bit flag the drives as 32bit */ 312 if ((chp->wdc->cap & 313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 314 WDC_CAPABILITY_DATA32) 315 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 316 } 317 318 if (wdcprobe(chp) == 0) 319 return; /* If no drives, abort attach here */ 320 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 323 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 324 325 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 326 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 327 DEBUG_PROBE); 328 329 /* 330 * Attach an ATAPI bus, if needed. 331 */ 332 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 333 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 334 #if NATAPIBUS > 0 335 wdc_atapibus_attach(chp); 336 #else 337 /* 338 * Fills in a fake aa_link and call config_found, so that 339 * the config machinery will print 340 * "atapibus at xxx not configured" 341 */ 342 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 343 aa_link.aa_type = T_ATAPI; 344 aa_link.aa_channel = chp->channel; 345 aa_link.aa_openings = 1; 346 aa_link.aa_drv_data = 0; 347 aa_link.aa_bus_private = NULL; 348 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 349 atapi_print); 350 #endif 351 } 352 353 for (i = 0; i < 2; i++) { 354 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 355 continue; 356 } 357 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 358 aa_link.aa_type = T_ATA; 359 aa_link.aa_channel = chp->channel; 360 aa_link.aa_openings = 1; 361 aa_link.aa_drv_data = &chp->ch_drive[i]; 362 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 363 wdc_probe_caps(&chp->ch_drive[i]); 364 } 365 366 /* 367 * reset drive_flags for unnatached devices, reset state for attached 368 * ones 369 */ 370 for (i = 0; i < 2; i++) { 371 if (chp->ch_drive[i].drv_softc == NULL) 372 chp->ch_drive[i].drive_flags = 0; 373 else 374 chp->ch_drive[i].state = 0; 375 } 376 377 /* 378 * Reset channel. The probe, with some combinations of ATA/ATAPI 379 * devices keep it in a mostly working, but strange state (with busy 380 * led on) 381 */ 382 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 383 wdcreset(chp, VERBOSE); 384 /* 385 * Read status registers to avoid spurious interrupts. 386 */ 387 for (i = 1; i >= 0; i--) { 388 if (chp->ch_drive[i].drive_flags & DRIVE) { 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_sdh, WDSD_IBM | (i << 4)); 391 if (wait_for_unbusy(chp, 10000) < 0) 392 printf("%s:%d:%d: device busy\n", 393 chp->wdc->sc_dev.dv_xname, 394 chp->channel, i); 395 } 396 } 397 } 398 } 399 400 /* 401 * Start I/O on a controller, for the given channel. 402 * The first xfer may be not for our channel if the channel queues 403 * are shared. 404 */ 405 void 406 wdcstart(wdc, channel) 407 struct wdc_softc *wdc; 408 int channel; 409 { 410 struct wdc_xfer *xfer; 411 struct channel_softc *chp; 412 413 /* is there a xfer ? */ 414 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 415 return; 416 chp = &wdc->channels[xfer->channel]; 417 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 418 return; /* channel aleady active */ 419 } 420 #ifdef DIAGNOSTIC 421 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 422 panic("wdcstart: channel waiting for irq\n"); 423 #endif 424 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 425 if (!(*wdc->claim_hw)(chp, 0)) 426 return; 427 428 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 429 xfer->channel, xfer->drive), DEBUG_XFERS); 430 chp->ch_flags |= WDCF_ACTIVE; 431 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 432 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 433 chp->ch_drive[xfer->drive].state = 0; 434 } 435 xfer->c_start(chp, xfer); 436 } 437 438 /* restart an interrupted I/O */ 439 void 440 wdcrestart(v) 441 void *v; 442 { 443 struct channel_softc *chp = v; 444 int s; 445 446 s = splbio(); 447 wdcstart(chp->wdc, chp->channel); 448 splx(s); 449 } 450 451 452 /* 453 * Interrupt routine for the controller. Acknowledge the interrupt, check for 454 * errors on the current operation, mark it done if necessary, and start the 455 * next request. Also check for a partially done transfer, and continue with 456 * the next chunk if so. 457 */ 458 int 459 wdcintr(arg) 460 void *arg; 461 { 462 struct channel_softc *chp = arg; 463 struct wdc_xfer *xfer; 464 465 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 466 #if 0 467 /* Clear the pending interrupt and abort. */ 468 u_int8_t s = 469 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 470 #ifdef WDCDEBUG 471 u_int8_t e = 472 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 473 u_int8_t i = 474 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 475 #else 476 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 477 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 478 #endif 479 480 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 481 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 482 483 if (s & WDCS_DRQ) { 484 int len; 485 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 486 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 487 chp->cmd_ioh, wd_cyl_hi); 488 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 489 len), DEBUG_INTR); 490 wdcbit_bucket (chp, len); 491 } 492 #else 493 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 494 #endif 495 return 0; 496 } 497 498 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 499 untimeout(wdctimeout, chp); 500 chp->ch_flags &= ~WDCF_IRQ_WAIT; 501 xfer = chp->ch_queue->sc_xfer.tqh_first; 502 return xfer->c_intr(chp, xfer); 503 } 504 505 /* Put all disk in RESET state */ 506 void wdc_reset_channel(drvp) 507 struct ata_drive_datas *drvp; 508 { 509 struct channel_softc *chp = drvp->chnl_softc; 510 int drive; 511 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 512 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 513 DEBUG_FUNCS); 514 (void) wdcreset(chp, VERBOSE); 515 for (drive = 0; drive < 2; drive++) { 516 chp->ch_drive[drive].state = 0; 517 } 518 } 519 520 int 521 wdcreset(chp, verb) 522 struct channel_softc *chp; 523 int verb; 524 { 525 int drv_mask1, drv_mask2; 526 527 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 528 WDSD_IBM); /* master */ 529 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 530 WDCTL_RST | WDCTL_IDS); 531 delay(1000); 532 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 533 WDCTL_IDS); 534 delay(1000); 535 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 536 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 537 WDCTL_4BIT); 538 539 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 540 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 541 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 542 if (verb && drv_mask2 != drv_mask1) { 543 printf("%s channel %d: reset failed for", 544 chp->wdc->sc_dev.dv_xname, chp->channel); 545 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 546 printf(" drive 0"); 547 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 548 printf(" drive 1"); 549 printf("\n"); 550 } 551 return (drv_mask1 != drv_mask2) ? 1 : 0; 552 } 553 554 static int 555 __wdcwait_reset(chp, drv_mask) 556 struct channel_softc *chp; 557 int drv_mask; 558 { 559 int timeout; 560 u_int8_t st0, st1; 561 /* wait for BSY to deassert */ 562 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 563 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 564 WDSD_IBM); /* master */ 565 delay(1); 566 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 567 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 568 WDSD_IBM | 0x10); /* slave */ 569 delay(1); 570 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 571 572 if ((drv_mask & 0x01) == 0) { 573 /* no master */ 574 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 575 /* No master, slave is ready, it's done */ 576 return drv_mask; 577 } 578 } else if ((drv_mask & 0x02) == 0) { 579 /* no slave */ 580 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 581 /* No slave, master is ready, it's done */ 582 return drv_mask; 583 } 584 } else { 585 /* Wait for both master and slave to be ready */ 586 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 587 return drv_mask; 588 } 589 } 590 delay(WDCDELAY); 591 } 592 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 593 if (st0 & WDCS_BSY) 594 drv_mask &= ~0x01; 595 if (st1 & WDCS_BSY) 596 drv_mask &= ~0x02; 597 return drv_mask; 598 } 599 600 /* 601 * Wait for a drive to be !BSY, and have mask in its status register. 602 * return -1 for a timeout after "timeout" ms. 603 */ 604 int 605 wdcwait(chp, mask, bits, timeout) 606 struct channel_softc *chp; 607 int mask, bits, timeout; 608 { 609 u_char status; 610 int time = 0; 611 #ifdef WDCNDELAY_DEBUG 612 extern int cold; 613 #endif 614 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 615 chp->channel), DEBUG_STATUS); 616 chp->ch_error = 0; 617 618 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 619 620 for (;;) { 621 chp->ch_status = status = 622 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 623 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 624 break; 625 if (++time > timeout) { 626 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 627 "error %x\n", status, 628 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 629 wd_error)), 630 DEBUG_STATUS); 631 return -1; 632 } 633 delay(WDCDELAY); 634 } 635 if (status & WDCS_ERR) 636 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 637 wd_error); 638 #ifdef WDCNDELAY_DEBUG 639 /* After autoconfig, there should be no long delays. */ 640 if (!cold && time > WDCNDELAY_DEBUG) { 641 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 642 if (xfer == NULL) 643 printf("%s channel %d: warning: busy-wait took %dus\n", 644 chp->wdc->sc_dev.dv_xname, chp->channel, 645 WDCDELAY * time); 646 else 647 printf("%s:%d:%d: warning: busy-wait took %dus\n", 648 chp->wdc->sc_dev.dv_xname, xfer->channel, 649 xfer->drive, 650 WDCDELAY * time); 651 } 652 #endif 653 return 0; 654 } 655 656 void 657 wdctimeout(arg) 658 void *arg; 659 { 660 struct channel_softc *chp = (struct channel_softc *)arg; 661 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 662 int s; 663 664 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 665 666 s = splbio(); 667 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 668 __wdcerror(chp, "lost interrupt"); 669 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 670 "atapi":"ata"); 671 printf("\tc_bcount: %d\n", xfer->c_bcount); 672 printf("\tc_skip: %d\n", xfer->c_skip); 673 /* 674 * Call the interrupt routine. If we just missed and interrupt, 675 * it will do what's needed. Else, it will take the needed 676 * action (reset the device). 677 */ 678 xfer->c_flags |= C_TIMEOU; 679 chp->ch_flags &= ~WDCF_IRQ_WAIT; 680 xfer->c_intr(chp, xfer); 681 } else 682 __wdcerror(chp, "missing untimeout"); 683 splx(s); 684 } 685 686 /* 687 * Probe drive's capabilites, for use by the controller later 688 * Assumes drvp points to an existing drive. 689 * XXX this should be a controller-indep function 690 */ 691 void 692 wdc_probe_caps(drvp) 693 struct ata_drive_datas *drvp; 694 { 695 struct ataparams params, params2; 696 struct channel_softc *chp = drvp->chnl_softc; 697 struct device *drv_dev = drvp->drv_softc; 698 struct wdc_softc *wdc = chp->wdc; 699 int i, printed; 700 char *sep = ""; 701 702 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 703 /* IDENTIFY failed. Can't tell more about the device */ 704 return; 705 } 706 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 707 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 708 /* 709 * Controller claims 16 and 32 bit transferts. 710 * Re-do an UDENTIFY with 32-bit transferts, 711 * and compare results. 712 */ 713 drvp->drive_flags |= DRIVE_CAP32; 714 ata_get_params(drvp, AT_POLL, ¶ms2); 715 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 716 /* Not good. fall back to 16bits */ 717 drvp->drive_flags &= ~DRIVE_CAP32; 718 } else { 719 printf("%s: using 32-bits pio transfers\n", 720 drv_dev->dv_xname); 721 } 722 } 723 724 /* An ATAPI device is at last PIO mode 3 */ 725 if (drvp->drive_flags & DRIVE_ATAPI) 726 drvp->PIO_mode = 3; 727 728 /* 729 * It's not in the specs, but it seems that some drive 730 * returns 0xffff in atap_extensions when this field is invalid 731 */ 732 if (params.atap_extensions != 0xffff && 733 (params.atap_extensions & WDC_EXT_MODES)) { 734 printed = 0; 735 /* 736 * XXX some drives report something wrong here (they claim to 737 * support PIO mode 8 !). As mode is coded on 3 bits in 738 * SET FEATURE, limit it to 7 (so limit i to 4). 739 */ 740 for (i = 4; i >= 0; i--) { 741 if ((params.atap_piomode_supp & (1 << i)) == 0) 742 continue; 743 /* 744 * See if mode is accepted. 745 * If the controller can't set its PIO mode, 746 * assume the defaults are good, so don't try 747 * to set it 748 */ 749 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 750 if (ata_set_mode(drvp, 0x08 | (i + 3), 751 AT_POLL) != CMD_OK) 752 continue; 753 if (!printed) { 754 printf("%s: PIO mode %d", drv_dev->dv_xname, 755 i + 3); 756 sep = ","; 757 printed = 1; 758 } 759 /* 760 * If controller's driver can't set its PIO mode, 761 * get the highter one for the drive. 762 */ 763 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 764 wdc->pio_mode >= i + 3) { 765 drvp->PIO_mode = i + 3; 766 break; 767 } 768 } 769 if (!printed) { 770 /* 771 * We didn't find a valid PIO mode. 772 * Assume the values returned for DMA are buggy too 773 */ 774 return; 775 } 776 drvp->drive_flags |= DRIVE_MODE; 777 printed = 0; 778 for (i = 7; i >= 0; i--) { 779 if ((params.atap_dmamode_supp & (1 << i)) == 0) 780 continue; 781 if ((wdc->cap & WDC_CAPABILITY_DMA) && 782 (wdc->cap & WDC_CAPABILITY_MODE)) 783 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 784 != CMD_OK) 785 continue; 786 if (!printed) { 787 printf("%s DMA mode %d", sep, i); 788 sep = ","; 789 printed = 1; 790 } 791 if (wdc->cap & WDC_CAPABILITY_DMA) { 792 if ((wdc->cap & WDC_CAPABILITY_MODE) && 793 wdc->dma_mode < i) 794 continue; 795 drvp->DMA_mode = i; 796 drvp->drive_flags |= DRIVE_DMA; 797 } 798 break; 799 } 800 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 801 for (i = 7; i >= 0; i--) { 802 if ((params.atap_udmamode_supp & (1 << i)) 803 == 0) 804 continue; 805 if ((wdc->cap & WDC_CAPABILITY_MODE) && 806 (wdc->cap & WDC_CAPABILITY_UDMA)) 807 if (ata_set_mode(drvp, 0x40 | i, 808 AT_POLL) != CMD_OK) 809 continue; 810 printf("%s UDMA mode %d", sep, i); 811 sep = ","; 812 /* 813 * ATA-4 specs says if a mode is supported, 814 * all lower modes shall be supported. 815 * No need to look further. 816 */ 817 if (wdc->cap & WDC_CAPABILITY_UDMA) { 818 drvp->UDMA_mode = i; 819 drvp->drive_flags |= DRIVE_UDMA; 820 } 821 break; 822 } 823 } 824 printf("\n"); 825 } 826 } 827 828 int 829 wdc_exec_command(drvp, wdc_c) 830 struct ata_drive_datas *drvp; 831 struct wdc_command *wdc_c; 832 { 833 struct channel_softc *chp = drvp->chnl_softc; 834 struct wdc_xfer *xfer; 835 int s, ret; 836 837 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 838 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 839 DEBUG_FUNCS); 840 841 /* set up an xfer and queue. Wait for completion */ 842 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 843 WDC_NOSLEEP); 844 if (xfer == NULL) { 845 return WDC_TRY_AGAIN; 846 } 847 848 if (wdc_c->flags & AT_POLL) 849 xfer->c_flags |= C_POLL; 850 xfer->drive = drvp->drive; 851 xfer->databuf = wdc_c->data; 852 xfer->c_bcount = wdc_c->bcount; 853 xfer->cmd = wdc_c; 854 xfer->c_start = __wdccommand_start; 855 xfer->c_intr = __wdccommand_intr; 856 857 s = splbio(); 858 wdc_exec_xfer(chp, xfer); 859 #ifdef DIAGNOSTIC 860 if ((wdc_c->flags & AT_POLL) != 0 && 861 (wdc_c->flags & AT_DONE) == 0) 862 panic("wdc_exec_command: polled command not done\n"); 863 #endif 864 if (wdc_c->flags & AT_DONE) { 865 ret = WDC_COMPLETE; 866 } else { 867 if (wdc_c->flags & AT_WAIT) { 868 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 869 ret = WDC_COMPLETE; 870 } else { 871 ret = WDC_QUEUED; 872 } 873 } 874 splx(s); 875 return ret; 876 } 877 878 void 879 __wdccommand_start(chp, xfer) 880 struct channel_softc *chp; 881 struct wdc_xfer *xfer; 882 { 883 int drive = xfer->drive; 884 struct wdc_command *wdc_c = xfer->cmd; 885 886 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 887 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 888 DEBUG_FUNCS); 889 890 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 891 WDSD_IBM | (drive << 4)); 892 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 893 wdc_c->timeout) != 0) { 894 wdc_c->flags |= AT_TIMEOU; 895 __wdccommand_done(chp, xfer); 896 } 897 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 898 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 899 if ((wdc_c->flags & AT_POLL) == 0) { 900 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 901 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 902 return; 903 } 904 /* 905 * Polled command. Wait for drive ready or drq. Done in intr(). 906 * Wait for at last 400ns for status bit to be valid. 907 */ 908 delay(10); 909 if (__wdccommand_intr(chp, xfer) == 0) { 910 wdc_c->flags |= AT_TIMEOU; 911 __wdccommand_done(chp, xfer); 912 } 913 } 914 915 int 916 __wdccommand_intr(chp, xfer) 917 struct channel_softc *chp; 918 struct wdc_xfer *xfer; 919 { 920 struct wdc_command *wdc_c = xfer->cmd; 921 int bcount = wdc_c->bcount; 922 char *data = wdc_c->data; 923 924 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 925 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 926 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 927 wdc_c->timeout)) { 928 wdc_c->flags |= AT_ERROR; 929 __wdccommand_done(chp, xfer); 930 return 1; 931 } 932 if (wdc_c->flags & AT_READ) { 933 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 934 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 935 0, (u_int32_t*)data, bcount >> 2); 936 data += bcount & 0xfffffffc; 937 bcount = bcount & 0x03; 938 } 939 if (bcount > 0) 940 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 941 wd_data, (u_int16_t *)data, bcount >> 1); 942 } else if (wdc_c->flags & AT_WRITE) { 943 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 944 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 945 0, (u_int32_t*)data, bcount >> 2); 946 data += bcount & 0xfffffffc; 947 bcount = bcount & 0x03; 948 } 949 if (bcount > 0) 950 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 951 wd_data, (u_int16_t *)data, bcount >> 1); 952 } 953 __wdccommand_done(chp, xfer); 954 return 1; 955 } 956 957 void 958 __wdccommand_done(chp, xfer) 959 struct channel_softc *chp; 960 struct wdc_xfer *xfer; 961 { 962 int needdone = xfer->c_flags & C_NEEDDONE; 963 struct wdc_command *wdc_c = xfer->cmd; 964 965 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 966 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 967 if (chp->ch_status & WDCS_DWF) 968 wdc_c->flags |= AT_DF; 969 if (chp->ch_status & WDCS_ERR) { 970 wdc_c->flags |= AT_ERROR; 971 wdc_c->r_error = chp->ch_error; 972 } 973 wdc_c->flags |= AT_DONE; 974 wdc_free_xfer(chp, xfer); 975 if (needdone) { 976 if (wdc_c->flags & AT_WAIT) 977 wakeup(wdc_c); 978 else 979 wdc_c->callback(wdc_c->callback_arg); 980 } 981 return; 982 } 983 984 /* 985 * Send a command. The drive should be ready. 986 * Assumes interrupts are blocked. 987 */ 988 void 989 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 990 struct channel_softc *chp; 991 u_int8_t drive; 992 u_int8_t command; 993 u_int16_t cylin; 994 u_int8_t head, sector, count, precomp; 995 { 996 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 997 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 998 chp->channel, drive, command, cylin, head, sector, count, precomp), 999 DEBUG_FUNCS); 1000 1001 /* Select drive, head, and addressing mode. */ 1002 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1003 WDSD_IBM | (drive << 4) | head); 1004 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1005 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1006 precomp); 1007 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1008 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1009 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1010 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1011 1012 /* Send command. */ 1013 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1014 return; 1015 } 1016 1017 /* 1018 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1019 * tested by the caller. 1020 */ 1021 void 1022 wdccommandshort(chp, drive, command) 1023 struct channel_softc *chp; 1024 int drive; 1025 int command; 1026 { 1027 1028 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1029 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1030 DEBUG_FUNCS); 1031 1032 /* Select drive. */ 1033 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1034 WDSD_IBM | (drive << 4)); 1035 1036 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1037 } 1038 1039 /* Add a command to the queue and start controller. Must be called at splbio */ 1040 1041 void 1042 wdc_exec_xfer(chp, xfer) 1043 struct channel_softc *chp; 1044 struct wdc_xfer *xfer; 1045 { 1046 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1047 chp->channel, xfer->drive), DEBUG_XFERS); 1048 1049 /* complete xfer setup */ 1050 xfer->channel = chp->channel; 1051 1052 /* 1053 * If we are a polled command, and the list is not empty, 1054 * we are doing a dump. Drop the list to allow the polled command 1055 * to complete, we're going to reboot soon anyway. 1056 */ 1057 if ((xfer->c_flags & C_POLL) != 0 && 1058 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1059 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1060 } 1061 /* insert at the end of command list */ 1062 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1063 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1064 chp->ch_flags), DEBUG_XFERS); 1065 wdcstart(chp->wdc, chp->channel); 1066 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1067 } 1068 1069 struct wdc_xfer * 1070 wdc_get_xfer(flags) 1071 int flags; 1072 { 1073 struct wdc_xfer *xfer; 1074 int s; 1075 1076 s = splbio(); 1077 if ((xfer = xfer_free_list.lh_first) != NULL) { 1078 LIST_REMOVE(xfer, free_list); 1079 splx(s); 1080 #ifdef DIAGNOSTIC 1081 if ((xfer->c_flags & C_INUSE) != 0) 1082 panic("wdc_get_xfer: xfer already in use\n"); 1083 #endif 1084 } else { 1085 splx(s); 1086 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1087 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1088 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1089 if (xfer == NULL) 1090 return 0; 1091 #ifdef DIAGNOSTIC 1092 xfer->c_flags &= ~C_INUSE; 1093 #endif 1094 #ifdef WDCDEBUG 1095 wdc_nxfer++; 1096 #endif 1097 } 1098 #ifdef DIAGNOSTIC 1099 if ((xfer->c_flags & C_INUSE) != 0) 1100 panic("wdc_get_xfer: xfer already in use\n"); 1101 #endif 1102 memset(xfer, 0, sizeof(struct wdc_xfer)); 1103 xfer->c_flags = C_INUSE; 1104 return xfer; 1105 } 1106 1107 void 1108 wdc_free_xfer(chp, xfer) 1109 struct channel_softc *chp; 1110 struct wdc_xfer *xfer; 1111 { 1112 struct wdc_softc *wdc = chp->wdc; 1113 int s; 1114 1115 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1116 (*wdc->free_hw)(chp); 1117 s = splbio(); 1118 chp->ch_flags &= ~WDCF_ACTIVE; 1119 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1120 xfer->c_flags &= ~C_INUSE; 1121 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1122 splx(s); 1123 } 1124 1125 static void 1126 __wdcerror(chp, msg) 1127 struct channel_softc *chp; 1128 char *msg; 1129 { 1130 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1131 if (xfer == NULL) 1132 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1133 msg); 1134 else 1135 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1136 xfer->channel, xfer->drive, msg); 1137 } 1138 1139 /* 1140 * the bit bucket 1141 */ 1142 void 1143 wdcbit_bucket(chp, size) 1144 struct channel_softc *chp; 1145 int size; 1146 { 1147 1148 for (; size >= 2; size -= 2) 1149 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1150 if (size) 1151 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1152 } 1153
Indexes created Fri Sep 26 08:10:20 GMT 2025