wdc.c revision 1.38
1 /* $NetBSD: wdc.c,v 1.38 1998/10/21 09:12:46 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 185 WDSD_IBM); 186 delay(1); 187 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM | 0x10); 190 delay(1); 191 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 193 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 194 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 195 st0, st1), DEBUG_PROBE); 196 197 if (st0 == 0xff) 198 ret_value &= ~0x01; 199 if (st1 == 0xff) 200 ret_value &= ~0x02; 201 if (ret_value == 0) 202 return 0; 203 204 /* assert SRST, wait for reset to complete */ 205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 206 WDSD_IBM); 207 delay(1); 208 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 209 WDCTL_RST | WDCTL_IDS); 210 DELAY(1000); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_IDS); 213 delay(1000); 214 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 216 delay(1); 217 218 ret_value = __wdcwait_reset(chp, ret_value); 219 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 221 ret_value), DEBUG_PROBE); 222 223 /* if reset failed, there's nothing here */ 224 if (ret_value == 0) 225 return 0; 226 227 /* 228 * Test presence of drives. First test register signatures looking for 229 * ATAPI devices , then rescan and try an ATA command, in case it's an 230 * old drive. 231 * Fill in drive_flags accordingly 232 */ 233 for (drive = 0; drive < 2; drive++) { 234 if ((ret_value & (0x01 << drive)) == 0) 235 continue; 236 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 237 WDSD_IBM | (drive << 4)); 238 delay(1); 239 /* Save registers contents */ 240 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 241 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 242 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 243 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 244 245 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 248 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 249 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 250 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 251 } 252 } 253 for (drive = 0; drive < 2; drive++) { 254 if ((ret_value & (0x01 << drive)) == 0 || 255 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 256 continue; 257 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 258 WDSD_IBM | (drive << 4)); 259 delay(1); 260 /* 261 * Maybe it's an old device, so don't rely on ATA sig. 262 * Test registers writability (Error register not writable, 263 * but cyllo is), then try an ATA command. 264 */ 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 268 0x58 || 269 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 270 0xa5) { 271 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 272 "failed\n", 273 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 274 chp->channel, drive), DEBUG_PROBE); 275 ret_value &= ~(0x01 << drive); 276 continue; 277 } 278 if (wait_for_ready(chp, 10000) != 0) { 279 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 280 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 281 chp->channel, drive), DEBUG_PROBE); 282 ret_value &= ~(0x01 << drive); 283 continue; 284 } 285 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 286 WDCC_DIAGNOSE); 287 if (wait_for_ready(chp, 10000) == 0) { 288 chp->ch_drive[drive].drive_flags |= 289 DRIVE_ATA; 290 } else { 291 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive), DEBUG_PROBE); 294 ret_value &= ~(0x01 << drive); 295 } 296 } 297 return (ret_value); 298 } 299 300 void 301 wdcattach(chp) 302 struct channel_softc *chp; 303 { 304 int channel_flags, ctrl_flags, i; 305 struct ata_atapi_attach aa_link; 306 307 LIST_INIT(&xfer_free_list); 308 for (i = 0; i < 2; i++) { 309 chp->ch_drive[i].chnl_softc = chp; 310 chp->ch_drive[i].drive = i; 311 /* If controller can't do 16bit flag the drives as 32bit */ 312 if ((chp->wdc->cap & 313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 314 WDC_CAPABILITY_DATA32) 315 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 316 } 317 318 if (wdcprobe(chp) == 0) 319 return; /* If no drives, abort attach here */ 320 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 323 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 324 325 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 326 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 327 DEBUG_PROBE); 328 329 /* 330 * Attach an ATAPI bus, if needed. 331 */ 332 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 333 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 334 #if NATAPIBUS > 0 335 wdc_atapibus_attach(chp); 336 #else 337 /* 338 * Fills in a fake aa_link and call config_found, so that 339 * the config machinery will print 340 * "atapibus at xxx not configured" 341 */ 342 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 343 aa_link.aa_type = T_ATAPI; 344 aa_link.aa_channel = chp->channel; 345 aa_link.aa_openings = 1; 346 aa_link.aa_drv_data = 0; 347 aa_link.aa_bus_private = NULL; 348 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 349 atapi_print); 350 #endif 351 } 352 353 for (i = 0; i < 2; i++) { 354 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 355 continue; 356 } 357 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 358 aa_link.aa_type = T_ATA; 359 aa_link.aa_channel = chp->channel; 360 aa_link.aa_openings = 1; 361 aa_link.aa_drv_data = &chp->ch_drive[i]; 362 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 363 wdc_probe_caps(&chp->ch_drive[i]); 364 } 365 366 /* 367 * reset drive_flags for unnatached devices, reset state for attached 368 * ones 369 */ 370 for (i = 0; i < 2; i++) { 371 if (chp->ch_drive[i].drv_softc == NULL) 372 chp->ch_drive[i].drive_flags = 0; 373 else 374 chp->ch_drive[i].state = 0; 375 } 376 377 /* 378 * Reset channel. The probe, with some combinations of ATA/ATAPI 379 * devices keep it in a mostly working, but strange state (with busy 380 * led on) 381 */ 382 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 383 wdcreset(chp, VERBOSE); 384 /* 385 * Read status registers to avoid spurious interrupts. 386 */ 387 for (i = 1; i >= 0; i--) { 388 if (chp->ch_drive[i].drive_flags & DRIVE) { 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_sdh, WDSD_IBM | (i << 4)); 391 if (wait_for_unbusy(chp, 10000) < 0) 392 printf("%s:%d:%d: device busy\n", 393 chp->wdc->sc_dev.dv_xname, 394 chp->channel, i); 395 } 396 } 397 } 398 } 399 400 /* 401 * Start I/O on a controller, for the given channel. 402 * The first xfer may be not for our channel if the channel queues 403 * are shared. 404 */ 405 void 406 wdcstart(wdc, channel) 407 struct wdc_softc *wdc; 408 int channel; 409 { 410 struct wdc_xfer *xfer; 411 struct channel_softc *chp; 412 413 #ifdef WDC_DIAGNOSTIC 414 int spl1, spl2; 415 416 spl1 = splbio(); 417 spl2 = splbio(); 418 if (spl2 != spl1) { 419 printf("wdcstart: not at splbio()\n"); 420 panic("wdcstart"); 421 } 422 splx(spl2); 423 splx(spl1); 424 #endif /* WDC_DIAGNOSTIC */ 425 426 /* is there a xfer ? */ 427 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 428 return; 429 chp = &wdc->channels[xfer->channel]; 430 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 431 return; /* channel aleady active */ 432 } 433 #ifdef DIAGNOSTIC 434 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 435 panic("wdcstart: channel waiting for irq\n"); 436 #endif 437 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 438 if (!(*wdc->claim_hw)(chp, 0)) 439 return; 440 441 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 442 xfer->channel, xfer->drive), DEBUG_XFERS); 443 chp->ch_flags |= WDCF_ACTIVE; 444 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 445 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 446 chp->ch_drive[xfer->drive].state = 0; 447 } 448 xfer->c_start(chp, xfer); 449 } 450 451 /* restart an interrupted I/O */ 452 void 453 wdcrestart(v) 454 void *v; 455 { 456 struct channel_softc *chp = v; 457 int s; 458 459 s = splbio(); 460 wdcstart(chp->wdc, chp->channel); 461 splx(s); 462 } 463 464 465 /* 466 * Interrupt routine for the controller. Acknowledge the interrupt, check for 467 * errors on the current operation, mark it done if necessary, and start the 468 * next request. Also check for a partially done transfer, and continue with 469 * the next chunk if so. 470 */ 471 int 472 wdcintr(arg) 473 void *arg; 474 { 475 struct channel_softc *chp = arg; 476 struct wdc_xfer *xfer; 477 478 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 479 #if 0 480 /* Clear the pending interrupt and abort. */ 481 u_int8_t s = 482 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 483 #ifdef WDCDEBUG 484 u_int8_t e = 485 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 486 u_int8_t i = 487 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 488 #else 489 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 490 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 491 #endif 492 493 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 494 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 495 496 if (s & WDCS_DRQ) { 497 int len; 498 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 499 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 500 chp->cmd_ioh, wd_cyl_hi); 501 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 502 len), DEBUG_INTR); 503 wdcbit_bucket (chp, len); 504 } 505 #else 506 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 507 #endif 508 return 0; 509 } 510 511 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 512 untimeout(wdctimeout, chp); 513 chp->ch_flags &= ~WDCF_IRQ_WAIT; 514 xfer = chp->ch_queue->sc_xfer.tqh_first; 515 return xfer->c_intr(chp, xfer); 516 } 517 518 /* Put all disk in RESET state */ 519 void wdc_reset_channel(drvp) 520 struct ata_drive_datas *drvp; 521 { 522 struct channel_softc *chp = drvp->chnl_softc; 523 int drive; 524 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 525 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 526 DEBUG_FUNCS); 527 (void) wdcreset(chp, VERBOSE); 528 for (drive = 0; drive < 2; drive++) { 529 chp->ch_drive[drive].state = 0; 530 } 531 } 532 533 int 534 wdcreset(chp, verb) 535 struct channel_softc *chp; 536 int verb; 537 { 538 int drv_mask1, drv_mask2; 539 540 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 541 WDSD_IBM); /* master */ 542 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 543 WDCTL_RST | WDCTL_IDS); 544 delay(1000); 545 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 546 WDCTL_IDS); 547 delay(1000); 548 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 549 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 550 WDCTL_4BIT); 551 552 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 553 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 554 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 555 if (verb && drv_mask2 != drv_mask1) { 556 printf("%s channel %d: reset failed for", 557 chp->wdc->sc_dev.dv_xname, chp->channel); 558 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 559 printf(" drive 0"); 560 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 561 printf(" drive 1"); 562 printf("\n"); 563 } 564 return (drv_mask1 != drv_mask2) ? 1 : 0; 565 } 566 567 static int 568 __wdcwait_reset(chp, drv_mask) 569 struct channel_softc *chp; 570 int drv_mask; 571 { 572 int timeout; 573 u_int8_t st0, st1; 574 /* wait for BSY to deassert */ 575 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 576 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 577 WDSD_IBM); /* master */ 578 delay(1); 579 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 580 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 581 WDSD_IBM | 0x10); /* slave */ 582 delay(1); 583 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 584 585 if ((drv_mask & 0x01) == 0) { 586 /* no master */ 587 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 588 /* No master, slave is ready, it's done */ 589 return drv_mask; 590 } 591 } else if ((drv_mask & 0x02) == 0) { 592 /* no slave */ 593 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 594 /* No slave, master is ready, it's done */ 595 return drv_mask; 596 } 597 } else { 598 /* Wait for both master and slave to be ready */ 599 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 600 return drv_mask; 601 } 602 } 603 delay(WDCDELAY); 604 } 605 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 606 if (st0 & WDCS_BSY) 607 drv_mask &= ~0x01; 608 if (st1 & WDCS_BSY) 609 drv_mask &= ~0x02; 610 return drv_mask; 611 } 612 613 /* 614 * Wait for a drive to be !BSY, and have mask in its status register. 615 * return -1 for a timeout after "timeout" ms. 616 */ 617 int 618 wdcwait(chp, mask, bits, timeout) 619 struct channel_softc *chp; 620 int mask, bits, timeout; 621 { 622 u_char status; 623 int time = 0; 624 #ifdef WDCNDELAY_DEBUG 625 extern int cold; 626 #endif 627 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 628 chp->channel), DEBUG_STATUS); 629 chp->ch_error = 0; 630 631 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 632 633 for (;;) { 634 chp->ch_status = status = 635 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 636 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 637 break; 638 if (++time > timeout) { 639 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 640 "error %x\n", status, 641 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 642 wd_error)), 643 DEBUG_STATUS); 644 return -1; 645 } 646 delay(WDCDELAY); 647 } 648 if (status & WDCS_ERR) 649 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 650 wd_error); 651 #ifdef WDCNDELAY_DEBUG 652 /* After autoconfig, there should be no long delays. */ 653 if (!cold && time > WDCNDELAY_DEBUG) { 654 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 655 if (xfer == NULL) 656 printf("%s channel %d: warning: busy-wait took %dus\n", 657 chp->wdc->sc_dev.dv_xname, chp->channel, 658 WDCDELAY * time); 659 else 660 printf("%s:%d:%d: warning: busy-wait took %dus\n", 661 chp->wdc->sc_dev.dv_xname, xfer->channel, 662 xfer->drive, 663 WDCDELAY * time); 664 } 665 #endif 666 return 0; 667 } 668 669 void 670 wdctimeout(arg) 671 void *arg; 672 { 673 struct channel_softc *chp = (struct channel_softc *)arg; 674 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 675 int s; 676 677 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 678 679 s = splbio(); 680 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 681 __wdcerror(chp, "lost interrupt"); 682 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 683 "atapi":"ata"); 684 printf("\tc_bcount: %d\n", xfer->c_bcount); 685 printf("\tc_skip: %d\n", xfer->c_skip); 686 /* 687 * Call the interrupt routine. If we just missed and interrupt, 688 * it will do what's needed. Else, it will take the needed 689 * action (reset the device). 690 */ 691 xfer->c_flags |= C_TIMEOU; 692 chp->ch_flags &= ~WDCF_IRQ_WAIT; 693 xfer->c_intr(chp, xfer); 694 } else 695 __wdcerror(chp, "missing untimeout"); 696 splx(s); 697 } 698 699 /* 700 * Probe drive's capabilites, for use by the controller later 701 * Assumes drvp points to an existing drive. 702 * XXX this should be a controller-indep function 703 */ 704 void 705 wdc_probe_caps(drvp) 706 struct ata_drive_datas *drvp; 707 { 708 struct ataparams params, params2; 709 struct channel_softc *chp = drvp->chnl_softc; 710 struct device *drv_dev = drvp->drv_softc; 711 struct wdc_softc *wdc = chp->wdc; 712 int i, printed; 713 char *sep = ""; 714 715 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 716 /* IDENTIFY failed. Can't tell more about the device */ 717 return; 718 } 719 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 720 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 721 /* 722 * Controller claims 16 and 32 bit transferts. 723 * Re-do an UDENTIFY with 32-bit transferts, 724 * and compare results. 725 */ 726 drvp->drive_flags |= DRIVE_CAP32; 727 ata_get_params(drvp, AT_POLL, ¶ms2); 728 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 729 /* Not good. fall back to 16bits */ 730 drvp->drive_flags &= ~DRIVE_CAP32; 731 } else { 732 printf("%s: using 32-bits pio transfers\n", 733 drv_dev->dv_xname); 734 } 735 } 736 737 /* An ATAPI device is at last PIO mode 3 */ 738 if (drvp->drive_flags & DRIVE_ATAPI) 739 drvp->PIO_mode = 3; 740 741 /* 742 * It's not in the specs, but it seems that some drive 743 * returns 0xffff in atap_extensions when this field is invalid 744 */ 745 if (params.atap_extensions != 0xffff && 746 (params.atap_extensions & WDC_EXT_MODES)) { 747 printed = 0; 748 /* 749 * XXX some drives report something wrong here (they claim to 750 * support PIO mode 8 !). As mode is coded on 3 bits in 751 * SET FEATURE, limit it to 7 (so limit i to 4). 752 */ 753 for (i = 4; i >= 0; i--) { 754 if ((params.atap_piomode_supp & (1 << i)) == 0) 755 continue; 756 /* 757 * See if mode is accepted. 758 * If the controller can't set its PIO mode, 759 * assume the defaults are good, so don't try 760 * to set it 761 */ 762 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 763 if (ata_set_mode(drvp, 0x08 | (i + 3), 764 AT_POLL) != CMD_OK) 765 continue; 766 if (!printed) { 767 printf("%s: PIO mode %d", drv_dev->dv_xname, 768 i + 3); 769 sep = ","; 770 printed = 1; 771 } 772 /* 773 * If controller's driver can't set its PIO mode, 774 * get the highter one for the drive. 775 */ 776 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 777 wdc->pio_mode >= i + 3) { 778 drvp->PIO_mode = i + 3; 779 break; 780 } 781 } 782 if (!printed) { 783 /* 784 * We didn't find a valid PIO mode. 785 * Assume the values returned for DMA are buggy too 786 */ 787 return; 788 } 789 drvp->drive_flags |= DRIVE_MODE; 790 printed = 0; 791 for (i = 7; i >= 0; i--) { 792 if ((params.atap_dmamode_supp & (1 << i)) == 0) 793 continue; 794 if ((wdc->cap & WDC_CAPABILITY_DMA) && 795 (wdc->cap & WDC_CAPABILITY_MODE)) 796 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 797 != CMD_OK) 798 continue; 799 if (!printed) { 800 printf("%s DMA mode %d", sep, i); 801 sep = ","; 802 printed = 1; 803 } 804 if (wdc->cap & WDC_CAPABILITY_DMA) { 805 if ((wdc->cap & WDC_CAPABILITY_MODE) && 806 wdc->dma_mode < i) 807 continue; 808 drvp->DMA_mode = i; 809 drvp->drive_flags |= DRIVE_DMA; 810 } 811 break; 812 } 813 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 814 for (i = 7; i >= 0; i--) { 815 if ((params.atap_udmamode_supp & (1 << i)) 816 == 0) 817 continue; 818 if ((wdc->cap & WDC_CAPABILITY_MODE) && 819 (wdc->cap & WDC_CAPABILITY_UDMA)) 820 if (ata_set_mode(drvp, 0x40 | i, 821 AT_POLL) != CMD_OK) 822 continue; 823 printf("%s UDMA mode %d", sep, i); 824 sep = ","; 825 /* 826 * ATA-4 specs says if a mode is supported, 827 * all lower modes shall be supported. 828 * No need to look further. 829 */ 830 if (wdc->cap & WDC_CAPABILITY_UDMA) { 831 drvp->UDMA_mode = i; 832 drvp->drive_flags |= DRIVE_UDMA; 833 } 834 break; 835 } 836 } 837 printf("\n"); 838 } 839 } 840 841 int 842 wdc_exec_command(drvp, wdc_c) 843 struct ata_drive_datas *drvp; 844 struct wdc_command *wdc_c; 845 { 846 struct channel_softc *chp = drvp->chnl_softc; 847 struct wdc_xfer *xfer; 848 int s, ret; 849 850 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 851 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 852 DEBUG_FUNCS); 853 854 /* set up an xfer and queue. Wait for completion */ 855 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 856 WDC_NOSLEEP); 857 if (xfer == NULL) { 858 return WDC_TRY_AGAIN; 859 } 860 861 if (wdc_c->flags & AT_POLL) 862 xfer->c_flags |= C_POLL; 863 xfer->drive = drvp->drive; 864 xfer->databuf = wdc_c->data; 865 xfer->c_bcount = wdc_c->bcount; 866 xfer->cmd = wdc_c; 867 xfer->c_start = __wdccommand_start; 868 xfer->c_intr = __wdccommand_intr; 869 870 s = splbio(); 871 wdc_exec_xfer(chp, xfer); 872 #ifdef DIAGNOSTIC 873 if ((wdc_c->flags & AT_POLL) != 0 && 874 (wdc_c->flags & AT_DONE) == 0) 875 panic("wdc_exec_command: polled command not done\n"); 876 #endif 877 if (wdc_c->flags & AT_DONE) { 878 ret = WDC_COMPLETE; 879 } else { 880 if (wdc_c->flags & AT_WAIT) { 881 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 882 ret = WDC_COMPLETE; 883 } else { 884 ret = WDC_QUEUED; 885 } 886 } 887 splx(s); 888 return ret; 889 } 890 891 void 892 __wdccommand_start(chp, xfer) 893 struct channel_softc *chp; 894 struct wdc_xfer *xfer; 895 { 896 int drive = xfer->drive; 897 struct wdc_command *wdc_c = xfer->cmd; 898 899 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 900 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 901 DEBUG_FUNCS); 902 903 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 904 WDSD_IBM | (drive << 4)); 905 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 906 wdc_c->timeout) != 0) { 907 wdc_c->flags |= AT_TIMEOU; 908 __wdccommand_done(chp, xfer); 909 } 910 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 911 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 912 if ((wdc_c->flags & AT_POLL) == 0) { 913 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 914 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 915 return; 916 } 917 /* 918 * Polled command. Wait for drive ready or drq. Done in intr(). 919 * Wait for at last 400ns for status bit to be valid. 920 */ 921 delay(10); 922 if (__wdccommand_intr(chp, xfer) == 0) { 923 wdc_c->flags |= AT_TIMEOU; 924 __wdccommand_done(chp, xfer); 925 } 926 } 927 928 int 929 __wdccommand_intr(chp, xfer) 930 struct channel_softc *chp; 931 struct wdc_xfer *xfer; 932 { 933 struct wdc_command *wdc_c = xfer->cmd; 934 int bcount = wdc_c->bcount; 935 char *data = wdc_c->data; 936 937 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 938 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 939 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 940 wdc_c->timeout)) { 941 wdc_c->flags |= AT_ERROR; 942 __wdccommand_done(chp, xfer); 943 return 1; 944 } 945 if (wdc_c->flags & AT_READ) { 946 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 947 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 948 0, (u_int32_t*)data, bcount >> 2); 949 data += bcount & 0xfffffffc; 950 bcount = bcount & 0x03; 951 } 952 if (bcount > 0) 953 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 954 wd_data, (u_int16_t *)data, bcount >> 1); 955 } else if (wdc_c->flags & AT_WRITE) { 956 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 957 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 958 0, (u_int32_t*)data, bcount >> 2); 959 data += bcount & 0xfffffffc; 960 bcount = bcount & 0x03; 961 } 962 if (bcount > 0) 963 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 964 wd_data, (u_int16_t *)data, bcount >> 1); 965 } 966 __wdccommand_done(chp, xfer); 967 return 1; 968 } 969 970 void 971 __wdccommand_done(chp, xfer) 972 struct channel_softc *chp; 973 struct wdc_xfer *xfer; 974 { 975 int needdone = xfer->c_flags & C_NEEDDONE; 976 struct wdc_command *wdc_c = xfer->cmd; 977 978 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 979 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 980 if (chp->ch_status & WDCS_DWF) 981 wdc_c->flags |= AT_DF; 982 if (chp->ch_status & WDCS_ERR) { 983 wdc_c->flags |= AT_ERROR; 984 wdc_c->r_error = chp->ch_error; 985 } 986 wdc_c->flags |= AT_DONE; 987 wdc_free_xfer(chp, xfer); 988 if (needdone) { 989 if (wdc_c->flags & AT_WAIT) 990 wakeup(wdc_c); 991 else 992 wdc_c->callback(wdc_c->callback_arg); 993 } 994 return; 995 } 996 997 /* 998 * Send a command. The drive should be ready. 999 * Assumes interrupts are blocked. 1000 */ 1001 void 1002 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1003 struct channel_softc *chp; 1004 u_int8_t drive; 1005 u_int8_t command; 1006 u_int16_t cylin; 1007 u_int8_t head, sector, count, precomp; 1008 { 1009 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1010 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1011 chp->channel, drive, command, cylin, head, sector, count, precomp), 1012 DEBUG_FUNCS); 1013 1014 /* Select drive, head, and addressing mode. */ 1015 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1016 WDSD_IBM | (drive << 4) | head); 1017 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1018 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1019 precomp); 1020 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1021 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1022 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1023 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1024 1025 /* Send command. */ 1026 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1027 return; 1028 } 1029 1030 /* 1031 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1032 * tested by the caller. 1033 */ 1034 void 1035 wdccommandshort(chp, drive, command) 1036 struct channel_softc *chp; 1037 int drive; 1038 int command; 1039 { 1040 1041 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1042 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1043 DEBUG_FUNCS); 1044 1045 /* Select drive. */ 1046 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1047 WDSD_IBM | (drive << 4)); 1048 1049 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1050 } 1051 1052 /* Add a command to the queue and start controller. Must be called at splbio */ 1053 1054 void 1055 wdc_exec_xfer(chp, xfer) 1056 struct channel_softc *chp; 1057 struct wdc_xfer *xfer; 1058 { 1059 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1060 chp->channel, xfer->drive), DEBUG_XFERS); 1061 1062 /* complete xfer setup */ 1063 xfer->channel = chp->channel; 1064 1065 /* 1066 * If we are a polled command, and the list is not empty, 1067 * we are doing a dump. Drop the list to allow the polled command 1068 * to complete, we're going to reboot soon anyway. 1069 */ 1070 if ((xfer->c_flags & C_POLL) != 0 && 1071 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1072 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1073 } 1074 /* insert at the end of command list */ 1075 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1076 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1077 chp->ch_flags), DEBUG_XFERS); 1078 wdcstart(chp->wdc, chp->channel); 1079 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1080 } 1081 1082 struct wdc_xfer * 1083 wdc_get_xfer(flags) 1084 int flags; 1085 { 1086 struct wdc_xfer *xfer; 1087 int s; 1088 1089 s = splbio(); 1090 if ((xfer = xfer_free_list.lh_first) != NULL) { 1091 LIST_REMOVE(xfer, free_list); 1092 splx(s); 1093 #ifdef DIAGNOSTIC 1094 if ((xfer->c_flags & C_INUSE) != 0) 1095 panic("wdc_get_xfer: xfer already in use\n"); 1096 #endif 1097 } else { 1098 splx(s); 1099 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1100 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1101 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1102 if (xfer == NULL) 1103 return 0; 1104 #ifdef DIAGNOSTIC 1105 xfer->c_flags &= ~C_INUSE; 1106 #endif 1107 #ifdef WDCDEBUG 1108 wdc_nxfer++; 1109 #endif 1110 } 1111 #ifdef DIAGNOSTIC 1112 if ((xfer->c_flags & C_INUSE) != 0) 1113 panic("wdc_get_xfer: xfer already in use\n"); 1114 #endif 1115 memset(xfer, 0, sizeof(struct wdc_xfer)); 1116 xfer->c_flags = C_INUSE; 1117 return xfer; 1118 } 1119 1120 void 1121 wdc_free_xfer(chp, xfer) 1122 struct channel_softc *chp; 1123 struct wdc_xfer *xfer; 1124 { 1125 struct wdc_softc *wdc = chp->wdc; 1126 int s; 1127 1128 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1129 (*wdc->free_hw)(chp); 1130 s = splbio(); 1131 chp->ch_flags &= ~WDCF_ACTIVE; 1132 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1133 xfer->c_flags &= ~C_INUSE; 1134 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1135 splx(s); 1136 } 1137 1138 static void 1139 __wdcerror(chp, msg) 1140 struct channel_softc *chp; 1141 char *msg; 1142 { 1143 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1144 if (xfer == NULL) 1145 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1146 msg); 1147 else 1148 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1149 xfer->channel, xfer->drive, msg); 1150 } 1151 1152 /* 1153 * the bit bucket 1154 */ 1155 void 1156 wdcbit_bucket(chp, size) 1157 struct channel_softc *chp; 1158 int size; 1159 { 1160 1161 for (; size >= 2; size -= 2) 1162 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1163 if (size) 1164 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1165 } 1166
Indexes created Fri Sep 26 08:10:20 GMT 2025