wdc.c revision 1.39
1 /* $NetBSD: wdc.c,v 1.39 1998/11/11 19:38:27 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 185 WDSD_IBM); 186 delay(1); 187 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM | 0x10); 190 delay(1); 191 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 193 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 194 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 195 st0, st1), DEBUG_PROBE); 196 197 if (st0 == 0xff) 198 ret_value &= ~0x01; 199 if (st1 == 0xff) 200 ret_value &= ~0x02; 201 if (ret_value == 0) 202 return 0; 203 204 /* assert SRST, wait for reset to complete */ 205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 206 WDSD_IBM); 207 delay(1); 208 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 209 WDCTL_RST | WDCTL_IDS); 210 DELAY(1000); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_IDS); 213 delay(1000); 214 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 216 delay(1); 217 218 ret_value = __wdcwait_reset(chp, ret_value); 219 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 220 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 221 ret_value), DEBUG_PROBE); 222 223 /* if reset failed, there's nothing here */ 224 if (ret_value == 0) 225 return 0; 226 227 /* 228 * Test presence of drives. First test register signatures looking for 229 * ATAPI devices , then rescan and try an ATA command, in case it's an 230 * old drive. 231 * Fill in drive_flags accordingly 232 */ 233 for (drive = 0; drive < 2; drive++) { 234 if ((ret_value & (0x01 << drive)) == 0) 235 continue; 236 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 237 WDSD_IBM | (drive << 4)); 238 delay(1); 239 /* Save registers contents */ 240 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 241 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 242 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 243 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 244 245 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 246 "cl=0x%x ch=0x%x\n", 247 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 248 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 249 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 250 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 251 } 252 } 253 for (drive = 0; drive < 2; drive++) { 254 if ((ret_value & (0x01 << drive)) == 0 || 255 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 256 continue; 257 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 258 WDSD_IBM | (drive << 4)); 259 delay(1); 260 /* 261 * Maybe it's an old device, so don't rely on ATA sig. 262 * Test registers writability (Error register not writable, 263 * but cyllo is), then try an ATA command. 264 */ 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 267 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 268 0x58 || 269 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 270 0xa5) { 271 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 272 "failed\n", 273 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 274 chp->channel, drive), DEBUG_PROBE); 275 ret_value &= ~(0x01 << drive); 276 continue; 277 } 278 if (wait_for_ready(chp, 10000) != 0) { 279 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 280 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 281 chp->channel, drive), DEBUG_PROBE); 282 ret_value &= ~(0x01 << drive); 283 continue; 284 } 285 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 286 WDCC_DIAGNOSE); 287 if (wait_for_ready(chp, 10000) == 0) { 288 chp->ch_drive[drive].drive_flags |= 289 DRIVE_ATA; 290 } else { 291 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 292 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 293 chp->channel, drive), DEBUG_PROBE); 294 ret_value &= ~(0x01 << drive); 295 } 296 } 297 return (ret_value); 298 } 299 300 void 301 wdcattach(chp) 302 struct channel_softc *chp; 303 { 304 int channel_flags, ctrl_flags, i; 305 struct ata_atapi_attach aa_link; 306 307 LIST_INIT(&xfer_free_list); 308 for (i = 0; i < 2; i++) { 309 chp->ch_drive[i].chnl_softc = chp; 310 chp->ch_drive[i].drive = i; 311 /* If controller can't do 16bit flag the drives as 32bit */ 312 if ((chp->wdc->cap & 313 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 314 WDC_CAPABILITY_DATA32) 315 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 316 } 317 318 if (wdcprobe(chp) == 0) 319 return; /* If no drives, abort attach here */ 320 321 TAILQ_INIT(&chp->ch_queue->sc_xfer); 322 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 323 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 324 325 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 326 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 327 DEBUG_PROBE); 328 329 /* 330 * Attach an ATAPI bus, if needed. 331 */ 332 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 333 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 334 #if NATAPIBUS > 0 335 wdc_atapibus_attach(chp); 336 #else 337 /* 338 * Fills in a fake aa_link and call config_found, so that 339 * the config machinery will print 340 * "atapibus at xxx not configured" 341 */ 342 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 343 aa_link.aa_type = T_ATAPI; 344 aa_link.aa_channel = chp->channel; 345 aa_link.aa_openings = 1; 346 aa_link.aa_drv_data = 0; 347 aa_link.aa_bus_private = NULL; 348 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 349 atapi_print); 350 #endif 351 } 352 353 for (i = 0; i < 2; i++) { 354 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 355 continue; 356 } 357 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 358 aa_link.aa_type = T_ATA; 359 aa_link.aa_channel = chp->channel; 360 aa_link.aa_openings = 1; 361 aa_link.aa_drv_data = &chp->ch_drive[i]; 362 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 363 wdc_probe_caps(&chp->ch_drive[i]); 364 } 365 366 /* 367 * reset drive_flags for unnatached devices, reset state for attached 368 * ones 369 */ 370 for (i = 0; i < 2; i++) { 371 if (chp->ch_drive[i].drv_softc == NULL) 372 chp->ch_drive[i].drive_flags = 0; 373 else 374 chp->ch_drive[i].state = 0; 375 } 376 377 /* 378 * Reset channel. The probe, with some combinations of ATA/ATAPI 379 * devices keep it in a mostly working, but strange state (with busy 380 * led on) 381 */ 382 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 383 wdcreset(chp, VERBOSE); 384 /* 385 * Read status registers to avoid spurious interrupts. 386 */ 387 for (i = 1; i >= 0; i--) { 388 if (chp->ch_drive[i].drive_flags & DRIVE) { 389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 390 wd_sdh, WDSD_IBM | (i << 4)); 391 if (wait_for_unbusy(chp, 10000) < 0) 392 printf("%s:%d:%d: device busy\n", 393 chp->wdc->sc_dev.dv_xname, 394 chp->channel, i); 395 } 396 } 397 } 398 } 399 400 /* 401 * Start I/O on a controller, for the given channel. 402 * The first xfer may be not for our channel if the channel queues 403 * are shared. 404 */ 405 void 406 wdcstart(wdc, channel) 407 struct wdc_softc *wdc; 408 int channel; 409 { 410 struct wdc_xfer *xfer; 411 struct channel_softc *chp; 412 413 #ifdef WDC_DIAGNOSTIC 414 int spl1, spl2; 415 416 spl1 = splbio(); 417 spl2 = splbio(); 418 if (spl2 != spl1) { 419 printf("wdcstart: not at splbio()\n"); 420 panic("wdcstart"); 421 } 422 splx(spl2); 423 splx(spl1); 424 #endif /* WDC_DIAGNOSTIC */ 425 426 /* is there a xfer ? */ 427 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 428 return; 429 chp = &wdc->channels[xfer->channel]; 430 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 431 return; /* channel aleady active */ 432 } 433 #ifdef DIAGNOSTIC 434 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 435 panic("wdcstart: channel waiting for irq\n"); 436 #endif 437 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 438 if (!(*wdc->claim_hw)(chp, 0)) 439 return; 440 441 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 442 xfer->channel, xfer->drive), DEBUG_XFERS); 443 chp->ch_flags |= WDCF_ACTIVE; 444 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 445 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 446 chp->ch_drive[xfer->drive].state = 0; 447 } 448 xfer->c_start(chp, xfer); 449 } 450 451 /* restart an interrupted I/O */ 452 void 453 wdcrestart(v) 454 void *v; 455 { 456 struct channel_softc *chp = v; 457 int s; 458 459 s = splbio(); 460 wdcstart(chp->wdc, chp->channel); 461 splx(s); 462 } 463 464 465 /* 466 * Interrupt routine for the controller. Acknowledge the interrupt, check for 467 * errors on the current operation, mark it done if necessary, and start the 468 * next request. Also check for a partially done transfer, and continue with 469 * the next chunk if so. 470 */ 471 int 472 wdcintr(arg) 473 void *arg; 474 { 475 struct channel_softc *chp = arg; 476 struct wdc_xfer *xfer; 477 478 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 479 #if 0 480 /* Clear the pending interrupt and abort. */ 481 u_int8_t s = 482 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 483 #ifdef WDCDEBUG 484 u_int8_t e = 485 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 486 u_int8_t i = 487 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 488 #else 489 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 490 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 491 #endif 492 493 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 494 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 495 496 if (s & WDCS_DRQ) { 497 int len; 498 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 499 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 500 chp->cmd_ioh, wd_cyl_hi); 501 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 502 len), DEBUG_INTR); 503 wdcbit_bucket (chp, len); 504 } 505 #else 506 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 507 #endif 508 return 0; 509 } 510 511 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 512 untimeout(wdctimeout, chp); 513 chp->ch_flags &= ~WDCF_IRQ_WAIT; 514 xfer = chp->ch_queue->sc_xfer.tqh_first; 515 return xfer->c_intr(chp, xfer); 516 } 517 518 /* Put all disk in RESET state */ 519 void wdc_reset_channel(drvp) 520 struct ata_drive_datas *drvp; 521 { 522 struct channel_softc *chp = drvp->chnl_softc; 523 int drive; 524 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 525 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 526 DEBUG_FUNCS); 527 (void) wdcreset(chp, VERBOSE); 528 for (drive = 0; drive < 2; drive++) { 529 chp->ch_drive[drive].state = 0; 530 } 531 } 532 533 int 534 wdcreset(chp, verb) 535 struct channel_softc *chp; 536 int verb; 537 { 538 int drv_mask1, drv_mask2; 539 540 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 541 WDSD_IBM); /* master */ 542 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 543 WDCTL_RST | WDCTL_IDS); 544 delay(1000); 545 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 546 WDCTL_IDS); 547 delay(1000); 548 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 549 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 550 WDCTL_4BIT); 551 552 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 553 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 554 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 555 if (verb && drv_mask2 != drv_mask1) { 556 printf("%s channel %d: reset failed for", 557 chp->wdc->sc_dev.dv_xname, chp->channel); 558 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 559 printf(" drive 0"); 560 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 561 printf(" drive 1"); 562 printf("\n"); 563 } 564 return (drv_mask1 != drv_mask2) ? 1 : 0; 565 } 566 567 static int 568 __wdcwait_reset(chp, drv_mask) 569 struct channel_softc *chp; 570 int drv_mask; 571 { 572 int timeout; 573 u_int8_t st0, st1; 574 /* wait for BSY to deassert */ 575 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 576 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 577 WDSD_IBM); /* master */ 578 delay(1); 579 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 580 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 581 WDSD_IBM | 0x10); /* slave */ 582 delay(1); 583 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 584 585 if ((drv_mask & 0x01) == 0) { 586 /* no master */ 587 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 588 /* No master, slave is ready, it's done */ 589 return drv_mask; 590 } 591 } else if ((drv_mask & 0x02) == 0) { 592 /* no slave */ 593 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 594 /* No slave, master is ready, it's done */ 595 return drv_mask; 596 } 597 } else { 598 /* Wait for both master and slave to be ready */ 599 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 600 return drv_mask; 601 } 602 } 603 delay(WDCDELAY); 604 } 605 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 606 if (st0 & WDCS_BSY) 607 drv_mask &= ~0x01; 608 if (st1 & WDCS_BSY) 609 drv_mask &= ~0x02; 610 return drv_mask; 611 } 612 613 /* 614 * Wait for a drive to be !BSY, and have mask in its status register. 615 * return -1 for a timeout after "timeout" ms. 616 */ 617 int 618 wdcwait(chp, mask, bits, timeout) 619 struct channel_softc *chp; 620 int mask, bits, timeout; 621 { 622 u_char status; 623 int time = 0; 624 #ifdef WDCNDELAY_DEBUG 625 extern int cold; 626 #endif 627 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 628 chp->channel), DEBUG_STATUS); 629 chp->ch_error = 0; 630 631 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 632 633 for (;;) { 634 chp->ch_status = status = 635 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 636 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 637 break; 638 if (++time > timeout) { 639 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 640 "error %x\n", status, 641 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 642 wd_error)), 643 DEBUG_STATUS); 644 return -1; 645 } 646 delay(WDCDELAY); 647 } 648 if (status & WDCS_ERR) 649 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 650 wd_error); 651 #ifdef WDCNDELAY_DEBUG 652 /* After autoconfig, there should be no long delays. */ 653 if (!cold && time > WDCNDELAY_DEBUG) { 654 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 655 if (xfer == NULL) 656 printf("%s channel %d: warning: busy-wait took %dus\n", 657 chp->wdc->sc_dev.dv_xname, chp->channel, 658 WDCDELAY * time); 659 else 660 printf("%s:%d:%d: warning: busy-wait took %dus\n", 661 chp->wdc->sc_dev.dv_xname, xfer->channel, 662 xfer->drive, 663 WDCDELAY * time); 664 } 665 #endif 666 return 0; 667 } 668 669 void 670 wdctimeout(arg) 671 void *arg; 672 { 673 struct channel_softc *chp = (struct channel_softc *)arg; 674 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 675 int s; 676 677 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 678 679 s = splbio(); 680 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 681 __wdcerror(chp, "lost interrupt"); 682 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 683 "atapi":"ata"); 684 printf("\tc_bcount: %d\n", xfer->c_bcount); 685 printf("\tc_skip: %d\n", xfer->c_skip); 686 /* 687 * Call the interrupt routine. If we just missed and interrupt, 688 * it will do what's needed. Else, it will take the needed 689 * action (reset the device). 690 */ 691 xfer->c_flags |= C_TIMEOU; 692 chp->ch_flags &= ~WDCF_IRQ_WAIT; 693 xfer->c_intr(chp, xfer); 694 } else 695 __wdcerror(chp, "missing untimeout"); 696 splx(s); 697 } 698 699 /* 700 * Probe drive's capabilites, for use by the controller later 701 * Assumes drvp points to an existing drive. 702 * XXX this should be a controller-indep function 703 */ 704 void 705 wdc_probe_caps(drvp) 706 struct ata_drive_datas *drvp; 707 { 708 struct ataparams params, params2; 709 struct channel_softc *chp = drvp->chnl_softc; 710 struct device *drv_dev = drvp->drv_softc; 711 struct wdc_softc *wdc = chp->wdc; 712 int i, printed; 713 char *sep = ""; 714 715 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 716 /* IDENTIFY failed. Can't tell more about the device */ 717 return; 718 } 719 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 720 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 721 /* 722 * Controller claims 16 and 32 bit transfers. 723 * Re-do an IDENTIFY with 32-bit transfers, 724 * and compare results. 725 */ 726 drvp->drive_flags |= DRIVE_CAP32; 727 ata_get_params(drvp, AT_POLL, ¶ms2); 728 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 729 /* Not good. fall back to 16bits */ 730 drvp->drive_flags &= ~DRIVE_CAP32; 731 } else { 732 printf("%s: 32-bits data port\n", drv_dev->dv_xname); 733 } 734 } 735 736 /* An ATAPI device is at last PIO mode 3 */ 737 if (drvp->drive_flags & DRIVE_ATAPI) 738 drvp->PIO_mode = 3; 739 740 /* 741 * It's not in the specs, but it seems that some drive 742 * returns 0xffff in atap_extensions when this field is invalid 743 */ 744 if (params.atap_extensions != 0xffff && 745 (params.atap_extensions & WDC_EXT_MODES)) { 746 printed = 0; 747 /* 748 * XXX some drives report something wrong here (they claim to 749 * support PIO mode 8 !). As mode is coded on 3 bits in 750 * SET FEATURE, limit it to 7 (so limit i to 4). 751 * If higther mode than 7 is found, abort. 752 */ 753 for (i = 7; i >= 0; i--) { 754 if ((params.atap_piomode_supp & (1 << i)) == 0) 755 continue; 756 if (i > 4) 757 return; 758 /* 759 * See if mode is accepted. 760 * If the controller can't set its PIO mode, 761 * assume the defaults are good, so don't try 762 * to set it 763 */ 764 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 765 if (ata_set_mode(drvp, 0x08 | (i + 3), 766 AT_POLL) != CMD_OK) 767 continue; 768 if (!printed) { 769 printf("%s: drive supports PIO mode %d", 770 drv_dev->dv_xname, i + 3); 771 sep = ","; 772 printed = 1; 773 } 774 /* 775 * If controller's driver can't set its PIO mode, 776 * get the highter one for the drive. 777 */ 778 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 779 wdc->pio_mode >= i + 3) { 780 drvp->PIO_mode = i + 3; 781 break; 782 } 783 } 784 if (!printed) { 785 /* 786 * We didn't find a valid PIO mode. 787 * Assume the values returned for DMA are buggy too 788 */ 789 return; 790 } 791 drvp->drive_flags |= DRIVE_MODE; 792 printed = 0; 793 for (i = 7; i >= 0; i--) { 794 if ((params.atap_dmamode_supp & (1 << i)) == 0) 795 continue; 796 if ((wdc->cap & WDC_CAPABILITY_DMA) && 797 (wdc->cap & WDC_CAPABILITY_MODE)) 798 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 799 != CMD_OK) 800 continue; 801 if (!printed) { 802 printf("%s DMA mode %d", sep, i); 803 sep = ","; 804 printed = 1; 805 } 806 if (wdc->cap & WDC_CAPABILITY_DMA) { 807 if ((wdc->cap & WDC_CAPABILITY_MODE) && 808 wdc->dma_mode < i) 809 continue; 810 drvp->DMA_mode = i; 811 drvp->drive_flags |= DRIVE_DMA; 812 } 813 break; 814 } 815 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 816 for (i = 7; i >= 0; i--) { 817 if ((params.atap_udmamode_supp & (1 << i)) 818 == 0) 819 continue; 820 if ((wdc->cap & WDC_CAPABILITY_MODE) && 821 (wdc->cap & WDC_CAPABILITY_UDMA)) 822 if (ata_set_mode(drvp, 0x40 | i, 823 AT_POLL) != CMD_OK) 824 continue; 825 printf("%s UDMA mode %d", sep, i); 826 sep = ","; 827 /* 828 * ATA-4 specs says if a mode is supported, 829 * all lower modes shall be supported. 830 * No need to look further. 831 */ 832 if (wdc->cap & WDC_CAPABILITY_UDMA) { 833 drvp->UDMA_mode = i; 834 drvp->drive_flags |= DRIVE_UDMA; 835 } 836 break; 837 } 838 } 839 printf("\n"); 840 } 841 } 842 843 int 844 wdc_exec_command(drvp, wdc_c) 845 struct ata_drive_datas *drvp; 846 struct wdc_command *wdc_c; 847 { 848 struct channel_softc *chp = drvp->chnl_softc; 849 struct wdc_xfer *xfer; 850 int s, ret; 851 852 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 853 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 854 DEBUG_FUNCS); 855 856 /* set up an xfer and queue. Wait for completion */ 857 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 858 WDC_NOSLEEP); 859 if (xfer == NULL) { 860 return WDC_TRY_AGAIN; 861 } 862 863 if (wdc_c->flags & AT_POLL) 864 xfer->c_flags |= C_POLL; 865 xfer->drive = drvp->drive; 866 xfer->databuf = wdc_c->data; 867 xfer->c_bcount = wdc_c->bcount; 868 xfer->cmd = wdc_c; 869 xfer->c_start = __wdccommand_start; 870 xfer->c_intr = __wdccommand_intr; 871 872 s = splbio(); 873 wdc_exec_xfer(chp, xfer); 874 #ifdef DIAGNOSTIC 875 if ((wdc_c->flags & AT_POLL) != 0 && 876 (wdc_c->flags & AT_DONE) == 0) 877 panic("wdc_exec_command: polled command not done\n"); 878 #endif 879 if (wdc_c->flags & AT_DONE) { 880 ret = WDC_COMPLETE; 881 } else { 882 if (wdc_c->flags & AT_WAIT) { 883 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 884 ret = WDC_COMPLETE; 885 } else { 886 ret = WDC_QUEUED; 887 } 888 } 889 splx(s); 890 return ret; 891 } 892 893 void 894 __wdccommand_start(chp, xfer) 895 struct channel_softc *chp; 896 struct wdc_xfer *xfer; 897 { 898 int drive = xfer->drive; 899 struct wdc_command *wdc_c = xfer->cmd; 900 901 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 902 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 903 DEBUG_FUNCS); 904 905 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 906 WDSD_IBM | (drive << 4)); 907 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 908 wdc_c->timeout) != 0) { 909 wdc_c->flags |= AT_TIMEOU; 910 __wdccommand_done(chp, xfer); 911 } 912 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 913 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 914 if ((wdc_c->flags & AT_POLL) == 0) { 915 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 916 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 917 return; 918 } 919 /* 920 * Polled command. Wait for drive ready or drq. Done in intr(). 921 * Wait for at last 400ns for status bit to be valid. 922 */ 923 delay(10); 924 if (__wdccommand_intr(chp, xfer) == 0) { 925 wdc_c->flags |= AT_TIMEOU; 926 __wdccommand_done(chp, xfer); 927 } 928 } 929 930 int 931 __wdccommand_intr(chp, xfer) 932 struct channel_softc *chp; 933 struct wdc_xfer *xfer; 934 { 935 struct wdc_command *wdc_c = xfer->cmd; 936 int bcount = wdc_c->bcount; 937 char *data = wdc_c->data; 938 939 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 940 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 941 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 942 wdc_c->timeout)) { 943 wdc_c->flags |= AT_ERROR; 944 __wdccommand_done(chp, xfer); 945 return 1; 946 } 947 if (wdc_c->flags & AT_READ) { 948 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 949 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 950 0, (u_int32_t*)data, bcount >> 2); 951 data += bcount & 0xfffffffc; 952 bcount = bcount & 0x03; 953 } 954 if (bcount > 0) 955 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 956 wd_data, (u_int16_t *)data, bcount >> 1); 957 } else if (wdc_c->flags & AT_WRITE) { 958 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 959 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 960 0, (u_int32_t*)data, bcount >> 2); 961 data += bcount & 0xfffffffc; 962 bcount = bcount & 0x03; 963 } 964 if (bcount > 0) 965 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 966 wd_data, (u_int16_t *)data, bcount >> 1); 967 } 968 __wdccommand_done(chp, xfer); 969 return 1; 970 } 971 972 void 973 __wdccommand_done(chp, xfer) 974 struct channel_softc *chp; 975 struct wdc_xfer *xfer; 976 { 977 int needdone = xfer->c_flags & C_NEEDDONE; 978 struct wdc_command *wdc_c = xfer->cmd; 979 980 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 981 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 982 if (chp->ch_status & WDCS_DWF) 983 wdc_c->flags |= AT_DF; 984 if (chp->ch_status & WDCS_ERR) { 985 wdc_c->flags |= AT_ERROR; 986 wdc_c->r_error = chp->ch_error; 987 } 988 wdc_c->flags |= AT_DONE; 989 wdc_free_xfer(chp, xfer); 990 if (needdone) { 991 if (wdc_c->flags & AT_WAIT) 992 wakeup(wdc_c); 993 else 994 wdc_c->callback(wdc_c->callback_arg); 995 } 996 return; 997 } 998 999 /* 1000 * Send a command. The drive should be ready. 1001 * Assumes interrupts are blocked. 1002 */ 1003 void 1004 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1005 struct channel_softc *chp; 1006 u_int8_t drive; 1007 u_int8_t command; 1008 u_int16_t cylin; 1009 u_int8_t head, sector, count, precomp; 1010 { 1011 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1012 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1013 chp->channel, drive, command, cylin, head, sector, count, precomp), 1014 DEBUG_FUNCS); 1015 1016 /* Select drive, head, and addressing mode. */ 1017 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1018 WDSD_IBM | (drive << 4) | head); 1019 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1020 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1021 precomp); 1022 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1023 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1024 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1025 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1026 1027 /* Send command. */ 1028 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1029 return; 1030 } 1031 1032 /* 1033 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1034 * tested by the caller. 1035 */ 1036 void 1037 wdccommandshort(chp, drive, command) 1038 struct channel_softc *chp; 1039 int drive; 1040 int command; 1041 { 1042 1043 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1044 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1045 DEBUG_FUNCS); 1046 1047 /* Select drive. */ 1048 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1049 WDSD_IBM | (drive << 4)); 1050 1051 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1052 } 1053 1054 /* Add a command to the queue and start controller. Must be called at splbio */ 1055 1056 void 1057 wdc_exec_xfer(chp, xfer) 1058 struct channel_softc *chp; 1059 struct wdc_xfer *xfer; 1060 { 1061 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1062 chp->channel, xfer->drive), DEBUG_XFERS); 1063 1064 /* complete xfer setup */ 1065 xfer->channel = chp->channel; 1066 1067 /* 1068 * If we are a polled command, and the list is not empty, 1069 * we are doing a dump. Drop the list to allow the polled command 1070 * to complete, we're going to reboot soon anyway. 1071 */ 1072 if ((xfer->c_flags & C_POLL) != 0 && 1073 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1074 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1075 } 1076 /* insert at the end of command list */ 1077 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1078 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1079 chp->ch_flags), DEBUG_XFERS); 1080 wdcstart(chp->wdc, chp->channel); 1081 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1082 } 1083 1084 struct wdc_xfer * 1085 wdc_get_xfer(flags) 1086 int flags; 1087 { 1088 struct wdc_xfer *xfer; 1089 int s; 1090 1091 s = splbio(); 1092 if ((xfer = xfer_free_list.lh_first) != NULL) { 1093 LIST_REMOVE(xfer, free_list); 1094 splx(s); 1095 #ifdef DIAGNOSTIC 1096 if ((xfer->c_flags & C_INUSE) != 0) 1097 panic("wdc_get_xfer: xfer already in use\n"); 1098 #endif 1099 } else { 1100 splx(s); 1101 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1102 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1103 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1104 if (xfer == NULL) 1105 return 0; 1106 #ifdef DIAGNOSTIC 1107 xfer->c_flags &= ~C_INUSE; 1108 #endif 1109 #ifdef WDCDEBUG 1110 wdc_nxfer++; 1111 #endif 1112 } 1113 #ifdef DIAGNOSTIC 1114 if ((xfer->c_flags & C_INUSE) != 0) 1115 panic("wdc_get_xfer: xfer already in use\n"); 1116 #endif 1117 memset(xfer, 0, sizeof(struct wdc_xfer)); 1118 xfer->c_flags = C_INUSE; 1119 return xfer; 1120 } 1121 1122 void 1123 wdc_free_xfer(chp, xfer) 1124 struct channel_softc *chp; 1125 struct wdc_xfer *xfer; 1126 { 1127 struct wdc_softc *wdc = chp->wdc; 1128 int s; 1129 1130 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1131 (*wdc->free_hw)(chp); 1132 s = splbio(); 1133 chp->ch_flags &= ~WDCF_ACTIVE; 1134 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1135 xfer->c_flags &= ~C_INUSE; 1136 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1137 splx(s); 1138 } 1139 1140 static void 1141 __wdcerror(chp, msg) 1142 struct channel_softc *chp; 1143 char *msg; 1144 { 1145 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1146 if (xfer == NULL) 1147 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1148 msg); 1149 else 1150 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1151 xfer->channel, xfer->drive, msg); 1152 } 1153 1154 /* 1155 * the bit bucket 1156 */ 1157 void 1158 wdcbit_bucket(chp, size) 1159 struct channel_softc *chp; 1160 int size; 1161 { 1162 1163 for (; size >= 2; size -= 2) 1164 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1165 if (size) 1166 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1167 } 1168
Indexes created Fri Sep 26 20:09:58 GMT 2025