wdc.c revision 1.41
1 /* $NetBSD: wdc.c,v 1.41 1998/11/19 04:07:54 kenh Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 185 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 186 WDSD_IBM); 187 delay(1); 188 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 189 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 190 WDSD_IBM | 0x10); 191 delay(1); 192 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 193 194 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 195 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 196 st0, st1), DEBUG_PROBE); 197 198 if (st0 == 0xff) 199 ret_value &= ~0x01; 200 if (st1 == 0xff) 201 ret_value &= ~0x02; 202 if (ret_value == 0) 203 return 0; 204 } 205 /* assert SRST, wait for reset to complete */ 206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 207 WDSD_IBM); 208 delay(1); 209 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 210 WDCTL_RST | WDCTL_IDS); 211 DELAY(1000); 212 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 213 WDCTL_IDS); 214 delay(1000); 215 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 217 delay(1); 218 219 ret_value = __wdcwait_reset(chp, ret_value); 220 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 221 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 222 ret_value), DEBUG_PROBE); 223 224 /* if reset failed, there's nothing here */ 225 if (ret_value == 0) 226 return 0; 227 228 /* 229 * Test presence of drives. First test register signatures looking for 230 * ATAPI devices , then rescan and try an ATA command, in case it's an 231 * old drive. 232 * Fill in drive_flags accordingly 233 */ 234 for (drive = 0; drive < 2; drive++) { 235 if ((ret_value & (0x01 << drive)) == 0) 236 continue; 237 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 238 WDSD_IBM | (drive << 4)); 239 delay(1); 240 /* Save registers contents */ 241 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 242 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 243 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 244 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 245 246 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 247 "cl=0x%x ch=0x%x\n", 248 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 249 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 250 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 251 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 252 } 253 } 254 for (drive = 0; drive < 2; drive++) { 255 if ((ret_value & (0x01 << drive)) == 0 || 256 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 257 continue; 258 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 259 WDSD_IBM | (drive << 4)); 260 delay(1); 261 /* 262 * Maybe it's an old device, so don't rely on ATA sig. 263 * Test registers writability (Error register not writable, 264 * but cyllo is), then try an ATA command. 265 */ 266 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 267 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 268 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 269 0x58 || 270 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 271 0xa5) { 272 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 273 "failed\n", 274 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 275 chp->channel, drive), DEBUG_PROBE); 276 ret_value &= ~(0x01 << drive); 277 continue; 278 } 279 if (wait_for_ready(chp, 10000) != 0) { 280 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 281 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 282 chp->channel, drive), DEBUG_PROBE); 283 ret_value &= ~(0x01 << drive); 284 continue; 285 } 286 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 287 WDCC_DIAGNOSE); 288 if (wait_for_ready(chp, 10000) == 0) { 289 chp->ch_drive[drive].drive_flags |= 290 DRIVE_ATA; 291 } else { 292 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 293 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 294 chp->channel, drive), DEBUG_PROBE); 295 ret_value &= ~(0x01 << drive); 296 } 297 } 298 return (ret_value); 299 } 300 301 void 302 wdcattach(chp) 303 struct channel_softc *chp; 304 { 305 int channel_flags, ctrl_flags, i; 306 struct ata_atapi_attach aa_link; 307 308 LIST_INIT(&xfer_free_list); 309 for (i = 0; i < 2; i++) { 310 chp->ch_drive[i].chnl_softc = chp; 311 chp->ch_drive[i].drive = i; 312 /* If controller can't do 16bit flag the drives as 32bit */ 313 if ((chp->wdc->cap & 314 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 315 WDC_CAPABILITY_DATA32) 316 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 317 } 318 319 if (wdcprobe(chp) == 0) 320 return; /* If no drives, abort attach here */ 321 322 TAILQ_INIT(&chp->ch_queue->sc_xfer); 323 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 324 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 325 326 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 327 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 328 DEBUG_PROBE); 329 330 /* 331 * Attach an ATAPI bus, if needed. 332 */ 333 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 334 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 335 #if NATAPIBUS > 0 336 wdc_atapibus_attach(chp); 337 #else 338 /* 339 * Fills in a fake aa_link and call config_found, so that 340 * the config machinery will print 341 * "atapibus at xxx not configured" 342 */ 343 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 344 aa_link.aa_type = T_ATAPI; 345 aa_link.aa_channel = chp->channel; 346 aa_link.aa_openings = 1; 347 aa_link.aa_drv_data = 0; 348 aa_link.aa_bus_private = NULL; 349 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 350 atapi_print); 351 #endif 352 } 353 354 for (i = 0; i < 2; i++) { 355 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 356 continue; 357 } 358 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 359 aa_link.aa_type = T_ATA; 360 aa_link.aa_channel = chp->channel; 361 aa_link.aa_openings = 1; 362 aa_link.aa_drv_data = &chp->ch_drive[i]; 363 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 364 wdc_probe_caps(&chp->ch_drive[i]); 365 } 366 367 /* 368 * reset drive_flags for unnatached devices, reset state for attached 369 * ones 370 */ 371 for (i = 0; i < 2; i++) { 372 if (chp->ch_drive[i].drv_softc == NULL) 373 chp->ch_drive[i].drive_flags = 0; 374 else 375 chp->ch_drive[i].state = 0; 376 } 377 378 /* 379 * Reset channel. The probe, with some combinations of ATA/ATAPI 380 * devices keep it in a mostly working, but strange state (with busy 381 * led on) 382 */ 383 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 384 wdcreset(chp, VERBOSE); 385 /* 386 * Read status registers to avoid spurious interrupts. 387 */ 388 for (i = 1; i >= 0; i--) { 389 if (chp->ch_drive[i].drive_flags & DRIVE) { 390 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 391 wd_sdh, WDSD_IBM | (i << 4)); 392 if (wait_for_unbusy(chp, 10000) < 0) 393 printf("%s:%d:%d: device busy\n", 394 chp->wdc->sc_dev.dv_xname, 395 chp->channel, i); 396 } 397 } 398 } 399 } 400 401 /* 402 * Start I/O on a controller, for the given channel. 403 * The first xfer may be not for our channel if the channel queues 404 * are shared. 405 */ 406 void 407 wdcstart(wdc, channel) 408 struct wdc_softc *wdc; 409 int channel; 410 { 411 struct wdc_xfer *xfer; 412 struct channel_softc *chp; 413 414 #ifdef WDC_DIAGNOSTIC 415 int spl1, spl2; 416 417 spl1 = splbio(); 418 spl2 = splbio(); 419 if (spl2 != spl1) { 420 printf("wdcstart: not at splbio()\n"); 421 panic("wdcstart"); 422 } 423 splx(spl2); 424 splx(spl1); 425 #endif /* WDC_DIAGNOSTIC */ 426 427 /* is there a xfer ? */ 428 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 429 return; 430 chp = &wdc->channels[xfer->channel]; 431 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 432 return; /* channel aleady active */ 433 } 434 #ifdef DIAGNOSTIC 435 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 436 panic("wdcstart: channel waiting for irq\n"); 437 #endif 438 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 439 if (!(*wdc->claim_hw)(chp, 0)) 440 return; 441 442 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 443 xfer->channel, xfer->drive), DEBUG_XFERS); 444 chp->ch_flags |= WDCF_ACTIVE; 445 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 446 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 447 chp->ch_drive[xfer->drive].state = 0; 448 } 449 xfer->c_start(chp, xfer); 450 } 451 452 /* restart an interrupted I/O */ 453 void 454 wdcrestart(v) 455 void *v; 456 { 457 struct channel_softc *chp = v; 458 int s; 459 460 s = splbio(); 461 wdcstart(chp->wdc, chp->channel); 462 splx(s); 463 } 464 465 466 /* 467 * Interrupt routine for the controller. Acknowledge the interrupt, check for 468 * errors on the current operation, mark it done if necessary, and start the 469 * next request. Also check for a partially done transfer, and continue with 470 * the next chunk if so. 471 */ 472 int 473 wdcintr(arg) 474 void *arg; 475 { 476 struct channel_softc *chp = arg; 477 struct wdc_xfer *xfer; 478 479 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 480 #if 0 481 /* Clear the pending interrupt and abort. */ 482 u_int8_t s = 483 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 484 #ifdef WDCDEBUG 485 u_int8_t e = 486 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 487 u_int8_t i = 488 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 489 #else 490 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 491 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 492 #endif 493 494 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 495 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 496 497 if (s & WDCS_DRQ) { 498 int len; 499 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 500 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 501 chp->cmd_ioh, wd_cyl_hi); 502 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 503 len), DEBUG_INTR); 504 wdcbit_bucket (chp, len); 505 } 506 #else 507 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 508 #endif 509 return 0; 510 } 511 512 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 513 untimeout(wdctimeout, chp); 514 chp->ch_flags &= ~WDCF_IRQ_WAIT; 515 xfer = chp->ch_queue->sc_xfer.tqh_first; 516 return xfer->c_intr(chp, xfer); 517 } 518 519 /* Put all disk in RESET state */ 520 void wdc_reset_channel(drvp) 521 struct ata_drive_datas *drvp; 522 { 523 struct channel_softc *chp = drvp->chnl_softc; 524 int drive; 525 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 526 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 527 DEBUG_FUNCS); 528 (void) wdcreset(chp, VERBOSE); 529 for (drive = 0; drive < 2; drive++) { 530 chp->ch_drive[drive].state = 0; 531 } 532 } 533 534 int 535 wdcreset(chp, verb) 536 struct channel_softc *chp; 537 int verb; 538 { 539 int drv_mask1, drv_mask2; 540 541 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 542 WDSD_IBM); /* master */ 543 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 544 WDCTL_RST | WDCTL_IDS); 545 delay(1000); 546 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 547 WDCTL_IDS); 548 delay(1000); 549 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 550 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 551 WDCTL_4BIT); 552 553 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 554 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 555 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 556 if (verb && drv_mask2 != drv_mask1) { 557 printf("%s channel %d: reset failed for", 558 chp->wdc->sc_dev.dv_xname, chp->channel); 559 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 560 printf(" drive 0"); 561 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 562 printf(" drive 1"); 563 printf("\n"); 564 } 565 return (drv_mask1 != drv_mask2) ? 1 : 0; 566 } 567 568 static int 569 __wdcwait_reset(chp, drv_mask) 570 struct channel_softc *chp; 571 int drv_mask; 572 { 573 int timeout; 574 u_int8_t st0, st1; 575 /* wait for BSY to deassert */ 576 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 577 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 578 WDSD_IBM); /* master */ 579 delay(1); 580 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 581 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 582 WDSD_IBM | 0x10); /* slave */ 583 delay(1); 584 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 585 586 if ((drv_mask & 0x01) == 0) { 587 /* no master */ 588 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 589 /* No master, slave is ready, it's done */ 590 return drv_mask; 591 } 592 } else if ((drv_mask & 0x02) == 0) { 593 /* no slave */ 594 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 595 /* No slave, master is ready, it's done */ 596 return drv_mask; 597 } 598 } else { 599 /* Wait for both master and slave to be ready */ 600 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 601 return drv_mask; 602 } 603 } 604 delay(WDCDELAY); 605 } 606 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 607 if (st0 & WDCS_BSY) 608 drv_mask &= ~0x01; 609 if (st1 & WDCS_BSY) 610 drv_mask &= ~0x02; 611 return drv_mask; 612 } 613 614 /* 615 * Wait for a drive to be !BSY, and have mask in its status register. 616 * return -1 for a timeout after "timeout" ms. 617 */ 618 int 619 wdcwait(chp, mask, bits, timeout) 620 struct channel_softc *chp; 621 int mask, bits, timeout; 622 { 623 u_char status; 624 int time = 0; 625 #ifdef WDCNDELAY_DEBUG 626 extern int cold; 627 #endif 628 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 629 chp->channel), DEBUG_STATUS); 630 chp->ch_error = 0; 631 632 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 633 634 for (;;) { 635 chp->ch_status = status = 636 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 637 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 638 break; 639 if (++time > timeout) { 640 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 641 "error %x\n", status, 642 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 643 wd_error)), 644 DEBUG_STATUS); 645 return -1; 646 } 647 delay(WDCDELAY); 648 } 649 if (status & WDCS_ERR) 650 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 651 wd_error); 652 #ifdef WDCNDELAY_DEBUG 653 /* After autoconfig, there should be no long delays. */ 654 if (!cold && time > WDCNDELAY_DEBUG) { 655 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 656 if (xfer == NULL) 657 printf("%s channel %d: warning: busy-wait took %dus\n", 658 chp->wdc->sc_dev.dv_xname, chp->channel, 659 WDCDELAY * time); 660 else 661 printf("%s:%d:%d: warning: busy-wait took %dus\n", 662 chp->wdc->sc_dev.dv_xname, xfer->channel, 663 xfer->drive, 664 WDCDELAY * time); 665 } 666 #endif 667 return 0; 668 } 669 670 void 671 wdctimeout(arg) 672 void *arg; 673 { 674 struct channel_softc *chp = (struct channel_softc *)arg; 675 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 676 int s; 677 678 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 679 680 s = splbio(); 681 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 682 __wdcerror(chp, "lost interrupt"); 683 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 684 "atapi":"ata"); 685 printf("\tc_bcount: %d\n", xfer->c_bcount); 686 printf("\tc_skip: %d\n", xfer->c_skip); 687 /* 688 * Call the interrupt routine. If we just missed and interrupt, 689 * it will do what's needed. Else, it will take the needed 690 * action (reset the device). 691 */ 692 xfer->c_flags |= C_TIMEOU; 693 chp->ch_flags &= ~WDCF_IRQ_WAIT; 694 xfer->c_intr(chp, xfer); 695 } else 696 __wdcerror(chp, "missing untimeout"); 697 splx(s); 698 } 699 700 /* 701 * Probe drive's capabilites, for use by the controller later 702 * Assumes drvp points to an existing drive. 703 * XXX this should be a controller-indep function 704 */ 705 void 706 wdc_probe_caps(drvp) 707 struct ata_drive_datas *drvp; 708 { 709 struct ataparams params, params2; 710 struct channel_softc *chp = drvp->chnl_softc; 711 struct device *drv_dev = drvp->drv_softc; 712 struct wdc_softc *wdc = chp->wdc; 713 int i, printed; 714 char *sep = ""; 715 716 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 717 /* IDENTIFY failed. Can't tell more about the device */ 718 return; 719 } 720 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 721 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 722 /* 723 * Controller claims 16 and 32 bit transfers. 724 * Re-do an IDENTIFY with 32-bit transfers, 725 * and compare results. 726 */ 727 drvp->drive_flags |= DRIVE_CAP32; 728 ata_get_params(drvp, AT_POLL, ¶ms2); 729 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 730 /* Not good. fall back to 16bits */ 731 drvp->drive_flags &= ~DRIVE_CAP32; 732 } else { 733 printf("%s: 32-bits data port\n", drv_dev->dv_xname); 734 } 735 } 736 737 /* An ATAPI device is at last PIO mode 3 */ 738 if (drvp->drive_flags & DRIVE_ATAPI) 739 drvp->PIO_mode = 3; 740 741 /* 742 * It's not in the specs, but it seems that some drive 743 * returns 0xffff in atap_extensions when this field is invalid 744 */ 745 if (params.atap_extensions != 0xffff && 746 (params.atap_extensions & WDC_EXT_MODES)) { 747 printed = 0; 748 /* 749 * XXX some drives report something wrong here (they claim to 750 * support PIO mode 8 !). As mode is coded on 3 bits in 751 * SET FEATURE, limit it to 7 (so limit i to 4). 752 * If higther mode than 7 is found, abort. 753 */ 754 for (i = 7; i >= 0; i--) { 755 if ((params.atap_piomode_supp & (1 << i)) == 0) 756 continue; 757 if (i > 4) 758 return; 759 /* 760 * See if mode is accepted. 761 * If the controller can't set its PIO mode, 762 * assume the defaults are good, so don't try 763 * to set it 764 */ 765 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 766 if (ata_set_mode(drvp, 0x08 | (i + 3), 767 AT_POLL) != CMD_OK) 768 continue; 769 if (!printed) { 770 printf("%s: drive supports PIO mode %d", 771 drv_dev->dv_xname, i + 3); 772 sep = ","; 773 printed = 1; 774 } 775 /* 776 * If controller's driver can't set its PIO mode, 777 * get the highter one for the drive. 778 */ 779 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 780 wdc->pio_mode >= i + 3) { 781 drvp->PIO_mode = i + 3; 782 break; 783 } 784 } 785 if (!printed) { 786 /* 787 * We didn't find a valid PIO mode. 788 * Assume the values returned for DMA are buggy too 789 */ 790 return; 791 } 792 drvp->drive_flags |= DRIVE_MODE; 793 printed = 0; 794 for (i = 7; i >= 0; i--) { 795 if ((params.atap_dmamode_supp & (1 << i)) == 0) 796 continue; 797 if ((wdc->cap & WDC_CAPABILITY_DMA) && 798 (wdc->cap & WDC_CAPABILITY_MODE)) 799 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 800 != CMD_OK) 801 continue; 802 if (!printed) { 803 printf("%s DMA mode %d", sep, i); 804 sep = ","; 805 printed = 1; 806 } 807 if (wdc->cap & WDC_CAPABILITY_DMA) { 808 if ((wdc->cap & WDC_CAPABILITY_MODE) && 809 wdc->dma_mode < i) 810 continue; 811 drvp->DMA_mode = i; 812 drvp->drive_flags |= DRIVE_DMA; 813 } 814 break; 815 } 816 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 817 for (i = 7; i >= 0; i--) { 818 if ((params.atap_udmamode_supp & (1 << i)) 819 == 0) 820 continue; 821 if ((wdc->cap & WDC_CAPABILITY_MODE) && 822 (wdc->cap & WDC_CAPABILITY_UDMA)) 823 if (ata_set_mode(drvp, 0x40 | i, 824 AT_POLL) != CMD_OK) 825 continue; 826 printf("%s UDMA mode %d", sep, i); 827 sep = ","; 828 /* 829 * ATA-4 specs says if a mode is supported, 830 * all lower modes shall be supported. 831 * No need to look further. 832 */ 833 if (wdc->cap & WDC_CAPABILITY_UDMA) { 834 drvp->UDMA_mode = i; 835 drvp->drive_flags |= DRIVE_UDMA; 836 } 837 break; 838 } 839 } 840 printf("\n"); 841 } 842 } 843 844 int 845 wdc_exec_command(drvp, wdc_c) 846 struct ata_drive_datas *drvp; 847 struct wdc_command *wdc_c; 848 { 849 struct channel_softc *chp = drvp->chnl_softc; 850 struct wdc_xfer *xfer; 851 int s, ret; 852 853 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 854 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 855 DEBUG_FUNCS); 856 857 /* set up an xfer and queue. Wait for completion */ 858 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 859 WDC_NOSLEEP); 860 if (xfer == NULL) { 861 return WDC_TRY_AGAIN; 862 } 863 864 if (wdc_c->flags & AT_POLL) 865 xfer->c_flags |= C_POLL; 866 xfer->drive = drvp->drive; 867 xfer->databuf = wdc_c->data; 868 xfer->c_bcount = wdc_c->bcount; 869 xfer->cmd = wdc_c; 870 xfer->c_start = __wdccommand_start; 871 xfer->c_intr = __wdccommand_intr; 872 873 s = splbio(); 874 wdc_exec_xfer(chp, xfer); 875 #ifdef DIAGNOSTIC 876 if ((wdc_c->flags & AT_POLL) != 0 && 877 (wdc_c->flags & AT_DONE) == 0) 878 panic("wdc_exec_command: polled command not done\n"); 879 #endif 880 if (wdc_c->flags & AT_DONE) { 881 ret = WDC_COMPLETE; 882 } else { 883 if (wdc_c->flags & AT_WAIT) { 884 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 885 ret = WDC_COMPLETE; 886 } else { 887 ret = WDC_QUEUED; 888 } 889 } 890 splx(s); 891 return ret; 892 } 893 894 void 895 __wdccommand_start(chp, xfer) 896 struct channel_softc *chp; 897 struct wdc_xfer *xfer; 898 { 899 int drive = xfer->drive; 900 struct wdc_command *wdc_c = xfer->cmd; 901 902 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 903 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 904 DEBUG_FUNCS); 905 906 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 907 WDSD_IBM | (drive << 4)); 908 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 909 wdc_c->timeout) != 0) { 910 wdc_c->flags |= AT_TIMEOU; 911 __wdccommand_done(chp, xfer); 912 } 913 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 914 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 915 if ((wdc_c->flags & AT_POLL) == 0) { 916 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 917 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 918 return; 919 } 920 /* 921 * Polled command. Wait for drive ready or drq. Done in intr(). 922 * Wait for at last 400ns for status bit to be valid. 923 */ 924 delay(10); 925 if (__wdccommand_intr(chp, xfer) == 0) { 926 wdc_c->flags |= AT_TIMEOU; 927 __wdccommand_done(chp, xfer); 928 } 929 } 930 931 int 932 __wdccommand_intr(chp, xfer) 933 struct channel_softc *chp; 934 struct wdc_xfer *xfer; 935 { 936 struct wdc_command *wdc_c = xfer->cmd; 937 int bcount = wdc_c->bcount; 938 char *data = wdc_c->data; 939 940 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 941 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 942 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 943 wdc_c->timeout)) { 944 wdc_c->flags |= AT_ERROR; 945 __wdccommand_done(chp, xfer); 946 return 1; 947 } 948 if (wdc_c->flags & AT_READ) { 949 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 950 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 951 0, (u_int32_t*)data, bcount >> 2); 952 data += bcount & 0xfffffffc; 953 bcount = bcount & 0x03; 954 } 955 if (bcount > 0) 956 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 957 wd_data, (u_int16_t *)data, bcount >> 1); 958 } else if (wdc_c->flags & AT_WRITE) { 959 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 960 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 961 0, (u_int32_t*)data, bcount >> 2); 962 data += bcount & 0xfffffffc; 963 bcount = bcount & 0x03; 964 } 965 if (bcount > 0) 966 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 967 wd_data, (u_int16_t *)data, bcount >> 1); 968 } 969 __wdccommand_done(chp, xfer); 970 return 1; 971 } 972 973 void 974 __wdccommand_done(chp, xfer) 975 struct channel_softc *chp; 976 struct wdc_xfer *xfer; 977 { 978 int needdone = xfer->c_flags & C_NEEDDONE; 979 struct wdc_command *wdc_c = xfer->cmd; 980 981 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 982 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 983 if (chp->ch_status & WDCS_DWF) 984 wdc_c->flags |= AT_DF; 985 if (chp->ch_status & WDCS_ERR) { 986 wdc_c->flags |= AT_ERROR; 987 wdc_c->r_error = chp->ch_error; 988 } 989 wdc_c->flags |= AT_DONE; 990 wdc_free_xfer(chp, xfer); 991 if (needdone) { 992 if (wdc_c->flags & AT_WAIT) 993 wakeup(wdc_c); 994 else 995 wdc_c->callback(wdc_c->callback_arg); 996 } 997 wdcstart(chp->wdc, chp->channel); 998 return; 999 } 1000 1001 /* 1002 * Send a command. The drive should be ready. 1003 * Assumes interrupts are blocked. 1004 */ 1005 void 1006 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1007 struct channel_softc *chp; 1008 u_int8_t drive; 1009 u_int8_t command; 1010 u_int16_t cylin; 1011 u_int8_t head, sector, count, precomp; 1012 { 1013 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1014 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1015 chp->channel, drive, command, cylin, head, sector, count, precomp), 1016 DEBUG_FUNCS); 1017 1018 /* Select drive, head, and addressing mode. */ 1019 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1020 WDSD_IBM | (drive << 4) | head); 1021 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1022 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1023 precomp); 1024 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1025 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1026 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1027 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1028 1029 /* Send command. */ 1030 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1031 return; 1032 } 1033 1034 /* 1035 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1036 * tested by the caller. 1037 */ 1038 void 1039 wdccommandshort(chp, drive, command) 1040 struct channel_softc *chp; 1041 int drive; 1042 int command; 1043 { 1044 1045 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1046 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1047 DEBUG_FUNCS); 1048 1049 /* Select drive. */ 1050 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1051 WDSD_IBM | (drive << 4)); 1052 1053 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1054 } 1055 1056 /* Add a command to the queue and start controller. Must be called at splbio */ 1057 1058 void 1059 wdc_exec_xfer(chp, xfer) 1060 struct channel_softc *chp; 1061 struct wdc_xfer *xfer; 1062 { 1063 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1064 chp->channel, xfer->drive), DEBUG_XFERS); 1065 1066 /* complete xfer setup */ 1067 xfer->channel = chp->channel; 1068 1069 /* 1070 * If we are a polled command, and the list is not empty, 1071 * we are doing a dump. Drop the list to allow the polled command 1072 * to complete, we're going to reboot soon anyway. 1073 */ 1074 if ((xfer->c_flags & C_POLL) != 0 && 1075 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1076 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1077 } 1078 /* insert at the end of command list */ 1079 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1080 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1081 chp->ch_flags), DEBUG_XFERS); 1082 wdcstart(chp->wdc, chp->channel); 1083 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1084 } 1085 1086 struct wdc_xfer * 1087 wdc_get_xfer(flags) 1088 int flags; 1089 { 1090 struct wdc_xfer *xfer; 1091 int s; 1092 1093 s = splbio(); 1094 if ((xfer = xfer_free_list.lh_first) != NULL) { 1095 LIST_REMOVE(xfer, free_list); 1096 splx(s); 1097 #ifdef DIAGNOSTIC 1098 if ((xfer->c_flags & C_INUSE) != 0) 1099 panic("wdc_get_xfer: xfer already in use\n"); 1100 #endif 1101 } else { 1102 splx(s); 1103 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1104 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1105 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1106 if (xfer == NULL) 1107 return 0; 1108 #ifdef DIAGNOSTIC 1109 xfer->c_flags &= ~C_INUSE; 1110 #endif 1111 #ifdef WDCDEBUG 1112 wdc_nxfer++; 1113 #endif 1114 } 1115 #ifdef DIAGNOSTIC 1116 if ((xfer->c_flags & C_INUSE) != 0) 1117 panic("wdc_get_xfer: xfer already in use\n"); 1118 #endif 1119 memset(xfer, 0, sizeof(struct wdc_xfer)); 1120 xfer->c_flags = C_INUSE; 1121 return xfer; 1122 } 1123 1124 void 1125 wdc_free_xfer(chp, xfer) 1126 struct channel_softc *chp; 1127 struct wdc_xfer *xfer; 1128 { 1129 struct wdc_softc *wdc = chp->wdc; 1130 int s; 1131 1132 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1133 (*wdc->free_hw)(chp); 1134 s = splbio(); 1135 chp->ch_flags &= ~WDCF_ACTIVE; 1136 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1137 xfer->c_flags &= ~C_INUSE; 1138 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1139 splx(s); 1140 } 1141 1142 static void 1143 __wdcerror(chp, msg) 1144 struct channel_softc *chp; 1145 char *msg; 1146 { 1147 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1148 if (xfer == NULL) 1149 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1150 msg); 1151 else 1152 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1153 xfer->channel, xfer->drive, msg); 1154 } 1155 1156 /* 1157 * the bit bucket 1158 */ 1159 void 1160 wdcbit_bucket(chp, size) 1161 struct channel_softc *chp; 1162 int size; 1163 { 1164 1165 for (; size >= 2; size -= 2) 1166 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1167 if (size) 1168 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1169 } 1170
Indexes created Fri Sep 26 08:10:20 GMT 2025