wdc.c revision 1.43
1 /* $NetBSD: wdc.c,v 1.43 1998/11/19 22:50:21 kenh Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(1); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(1); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff) 200 ret_value &= ~0x01; 201 if (st1 == 0xff) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(1); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(1); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices , then rescan and try an ATA command, in case it's an 233 * old drive. 234 * Fill in drive_flags accordingly 235 */ 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 240 WDSD_IBM | (drive << 4)); 241 delay(1); 242 /* Save registers contents */ 243 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 244 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 245 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 246 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 247 248 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 249 "cl=0x%x ch=0x%x\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 251 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 252 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 253 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 254 } 255 } 256 for (drive = 0; drive < 2; drive++) { 257 if ((ret_value & (0x01 << drive)) == 0 || 258 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 259 continue; 260 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 261 WDSD_IBM | (drive << 4)); 262 delay(1); 263 /* 264 * Maybe it's an old device, so don't rely on ATA sig. 265 * Test registers writability (Error register not writable, 266 * but cyllo is), then try an ATA command. 267 */ 268 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 269 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 270 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 271 0x58 || 272 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 273 0xa5) { 274 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 275 "failed\n", 276 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 277 chp->channel, drive), DEBUG_PROBE); 278 ret_value &= ~(0x01 << drive); 279 continue; 280 } 281 if (wait_for_ready(chp, 10000) != 0) { 282 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 283 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 284 chp->channel, drive), DEBUG_PROBE); 285 ret_value &= ~(0x01 << drive); 286 continue; 287 } 288 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 289 WDCC_DIAGNOSE); 290 if (wait_for_ready(chp, 10000) == 0) { 291 chp->ch_drive[drive].drive_flags |= 292 DRIVE_ATA; 293 } else { 294 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 295 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 296 chp->channel, drive), DEBUG_PROBE); 297 ret_value &= ~(0x01 << drive); 298 } 299 } 300 return (ret_value); 301 } 302 303 void 304 wdcattach(chp) 305 struct channel_softc *chp; 306 { 307 int channel_flags, ctrl_flags, i; 308 struct ata_atapi_attach aa_link; 309 310 LIST_INIT(&xfer_free_list); 311 for (i = 0; i < 2; i++) { 312 chp->ch_drive[i].chnl_softc = chp; 313 chp->ch_drive[i].drive = i; 314 /* If controller can't do 16bit flag the drives as 32bit */ 315 if ((chp->wdc->cap & 316 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 317 WDC_CAPABILITY_DATA32) 318 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 319 } 320 321 if (wdcprobe(chp) == 0) 322 return; /* If no drives, abort attach here */ 323 324 TAILQ_INIT(&chp->ch_queue->sc_xfer); 325 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 326 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 327 328 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 329 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 330 DEBUG_PROBE); 331 332 /* 333 * Attach an ATAPI bus, if needed. 334 */ 335 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 336 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 337 #if NATAPIBUS > 0 338 wdc_atapibus_attach(chp); 339 #else 340 /* 341 * Fills in a fake aa_link and call config_found, so that 342 * the config machinery will print 343 * "atapibus at xxx not configured" 344 */ 345 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 346 aa_link.aa_type = T_ATAPI; 347 aa_link.aa_channel = chp->channel; 348 aa_link.aa_openings = 1; 349 aa_link.aa_drv_data = 0; 350 aa_link.aa_bus_private = NULL; 351 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 352 atapi_print); 353 #endif 354 } 355 356 for (i = 0; i < 2; i++) { 357 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 358 continue; 359 } 360 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 361 aa_link.aa_type = T_ATA; 362 aa_link.aa_channel = chp->channel; 363 aa_link.aa_openings = 1; 364 aa_link.aa_drv_data = &chp->ch_drive[i]; 365 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 366 wdc_probe_caps(&chp->ch_drive[i]); 367 } 368 369 /* 370 * reset drive_flags for unnatached devices, reset state for attached 371 * ones 372 */ 373 for (i = 0; i < 2; i++) { 374 if (chp->ch_drive[i].drv_softc == NULL) 375 chp->ch_drive[i].drive_flags = 0; 376 else 377 chp->ch_drive[i].state = 0; 378 } 379 380 /* 381 * Reset channel. The probe, with some combinations of ATA/ATAPI 382 * devices keep it in a mostly working, but strange state (with busy 383 * led on) 384 */ 385 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 386 wdcreset(chp, VERBOSE); 387 /* 388 * Read status registers to avoid spurious interrupts. 389 */ 390 for (i = 1; i >= 0; i--) { 391 if (chp->ch_drive[i].drive_flags & DRIVE) { 392 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 393 wd_sdh, WDSD_IBM | (i << 4)); 394 if (wait_for_unbusy(chp, 10000) < 0) 395 printf("%s:%d:%d: device busy\n", 396 chp->wdc->sc_dev.dv_xname, 397 chp->channel, i); 398 } 399 } 400 } 401 } 402 403 /* 404 * Start I/O on a controller, for the given channel. 405 * The first xfer may be not for our channel if the channel queues 406 * are shared. 407 */ 408 void 409 wdcstart(wdc, channel) 410 struct wdc_softc *wdc; 411 int channel; 412 { 413 struct wdc_xfer *xfer; 414 struct channel_softc *chp; 415 416 #ifdef WDC_DIAGNOSTIC 417 int spl1, spl2; 418 419 spl1 = splbio(); 420 spl2 = splbio(); 421 if (spl2 != spl1) { 422 printf("wdcstart: not at splbio()\n"); 423 panic("wdcstart"); 424 } 425 splx(spl2); 426 splx(spl1); 427 #endif /* WDC_DIAGNOSTIC */ 428 429 /* is there a xfer ? */ 430 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 431 return; 432 chp = &wdc->channels[xfer->channel]; 433 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 434 return; /* channel aleady active */ 435 } 436 #ifdef DIAGNOSTIC 437 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 438 panic("wdcstart: channel waiting for irq\n"); 439 #endif 440 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 441 if (!(*wdc->claim_hw)(chp, 0)) 442 return; 443 444 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 445 xfer->channel, xfer->drive), DEBUG_XFERS); 446 chp->ch_flags |= WDCF_ACTIVE; 447 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 448 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 449 chp->ch_drive[xfer->drive].state = 0; 450 } 451 xfer->c_start(chp, xfer); 452 } 453 454 /* restart an interrupted I/O */ 455 void 456 wdcrestart(v) 457 void *v; 458 { 459 struct channel_softc *chp = v; 460 int s; 461 462 s = splbio(); 463 wdcstart(chp->wdc, chp->channel); 464 splx(s); 465 } 466 467 468 /* 469 * Interrupt routine for the controller. Acknowledge the interrupt, check for 470 * errors on the current operation, mark it done if necessary, and start the 471 * next request. Also check for a partially done transfer, and continue with 472 * the next chunk if so. 473 */ 474 int 475 wdcintr(arg) 476 void *arg; 477 { 478 struct channel_softc *chp = arg; 479 struct wdc_xfer *xfer; 480 481 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 482 #if 0 483 /* Clear the pending interrupt and abort. */ 484 u_int8_t s = 485 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 486 #ifdef WDCDEBUG 487 u_int8_t e = 488 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 489 u_int8_t i = 490 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 491 #else 492 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 493 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 494 #endif 495 496 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 497 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 498 499 if (s & WDCS_DRQ) { 500 int len; 501 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 502 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 503 chp->cmd_ioh, wd_cyl_hi); 504 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 505 len), DEBUG_INTR); 506 wdcbit_bucket (chp, len); 507 } 508 #else 509 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 510 #endif 511 return 0; 512 } 513 514 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 515 untimeout(wdctimeout, chp); 516 chp->ch_flags &= ~WDCF_IRQ_WAIT; 517 xfer = chp->ch_queue->sc_xfer.tqh_first; 518 return xfer->c_intr(chp, xfer); 519 } 520 521 /* Put all disk in RESET state */ 522 void wdc_reset_channel(drvp) 523 struct ata_drive_datas *drvp; 524 { 525 struct channel_softc *chp = drvp->chnl_softc; 526 int drive; 527 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 528 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 529 DEBUG_FUNCS); 530 (void) wdcreset(chp, VERBOSE); 531 for (drive = 0; drive < 2; drive++) { 532 chp->ch_drive[drive].state = 0; 533 } 534 } 535 536 int 537 wdcreset(chp, verb) 538 struct channel_softc *chp; 539 int verb; 540 { 541 int drv_mask1, drv_mask2; 542 543 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 544 WDSD_IBM); /* master */ 545 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 546 WDCTL_RST | WDCTL_IDS); 547 delay(1000); 548 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 549 WDCTL_IDS); 550 delay(1000); 551 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 552 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 553 WDCTL_4BIT); 554 555 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 556 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 557 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 558 if (verb && drv_mask2 != drv_mask1) { 559 printf("%s channel %d: reset failed for", 560 chp->wdc->sc_dev.dv_xname, chp->channel); 561 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 562 printf(" drive 0"); 563 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 564 printf(" drive 1"); 565 printf("\n"); 566 } 567 return (drv_mask1 != drv_mask2) ? 1 : 0; 568 } 569 570 static int 571 __wdcwait_reset(chp, drv_mask) 572 struct channel_softc *chp; 573 int drv_mask; 574 { 575 int timeout; 576 u_int8_t st0, st1; 577 /* wait for BSY to deassert */ 578 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 579 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 580 WDSD_IBM); /* master */ 581 delay(1); 582 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 583 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 584 WDSD_IBM | 0x10); /* slave */ 585 delay(1); 586 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 587 588 if ((drv_mask & 0x01) == 0) { 589 /* no master */ 590 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 591 /* No master, slave is ready, it's done */ 592 return drv_mask; 593 } 594 } else if ((drv_mask & 0x02) == 0) { 595 /* no slave */ 596 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 597 /* No slave, master is ready, it's done */ 598 return drv_mask; 599 } 600 } else { 601 /* Wait for both master and slave to be ready */ 602 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 603 return drv_mask; 604 } 605 } 606 delay(WDCDELAY); 607 } 608 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 609 if (st0 & WDCS_BSY) 610 drv_mask &= ~0x01; 611 if (st1 & WDCS_BSY) 612 drv_mask &= ~0x02; 613 return drv_mask; 614 } 615 616 /* 617 * Wait for a drive to be !BSY, and have mask in its status register. 618 * return -1 for a timeout after "timeout" ms. 619 */ 620 int 621 wdcwait(chp, mask, bits, timeout) 622 struct channel_softc *chp; 623 int mask, bits, timeout; 624 { 625 u_char status; 626 int time = 0; 627 #ifdef WDCNDELAY_DEBUG 628 extern int cold; 629 #endif 630 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 631 chp->channel), DEBUG_STATUS); 632 chp->ch_error = 0; 633 634 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 635 636 for (;;) { 637 chp->ch_status = status = 638 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 639 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 640 break; 641 if (++time > timeout) { 642 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 643 "error %x\n", status, 644 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 645 wd_error)), 646 DEBUG_STATUS); 647 return -1; 648 } 649 delay(WDCDELAY); 650 } 651 if (status & WDCS_ERR) 652 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 653 wd_error); 654 #ifdef WDCNDELAY_DEBUG 655 /* After autoconfig, there should be no long delays. */ 656 if (!cold && time > WDCNDELAY_DEBUG) { 657 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 658 if (xfer == NULL) 659 printf("%s channel %d: warning: busy-wait took %dus\n", 660 chp->wdc->sc_dev.dv_xname, chp->channel, 661 WDCDELAY * time); 662 else 663 printf("%s:%d:%d: warning: busy-wait took %dus\n", 664 chp->wdc->sc_dev.dv_xname, xfer->channel, 665 xfer->drive, 666 WDCDELAY * time); 667 } 668 #endif 669 return 0; 670 } 671 672 void 673 wdctimeout(arg) 674 void *arg; 675 { 676 struct channel_softc *chp = (struct channel_softc *)arg; 677 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 678 int s; 679 680 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 681 682 s = splbio(); 683 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 684 __wdcerror(chp, "lost interrupt"); 685 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 686 "atapi":"ata"); 687 printf("\tc_bcount: %d\n", xfer->c_bcount); 688 printf("\tc_skip: %d\n", xfer->c_skip); 689 /* 690 * Call the interrupt routine. If we just missed and interrupt, 691 * it will do what's needed. Else, it will take the needed 692 * action (reset the device). 693 */ 694 xfer->c_flags |= C_TIMEOU; 695 chp->ch_flags &= ~WDCF_IRQ_WAIT; 696 xfer->c_intr(chp, xfer); 697 } else 698 __wdcerror(chp, "missing untimeout"); 699 splx(s); 700 } 701 702 /* 703 * Probe drive's capabilites, for use by the controller later 704 * Assumes drvp points to an existing drive. 705 * XXX this should be a controller-indep function 706 */ 707 void 708 wdc_probe_caps(drvp) 709 struct ata_drive_datas *drvp; 710 { 711 struct ataparams params, params2; 712 struct channel_softc *chp = drvp->chnl_softc; 713 struct device *drv_dev = drvp->drv_softc; 714 struct wdc_softc *wdc = chp->wdc; 715 int i, printed; 716 char *sep = ""; 717 718 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 719 /* IDENTIFY failed. Can't tell more about the device */ 720 return; 721 } 722 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 723 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 724 /* 725 * Controller claims 16 and 32 bit transfers. 726 * Re-do an IDENTIFY with 32-bit transfers, 727 * and compare results. 728 */ 729 drvp->drive_flags |= DRIVE_CAP32; 730 ata_get_params(drvp, AT_POLL, ¶ms2); 731 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 732 /* Not good. fall back to 16bits */ 733 drvp->drive_flags &= ~DRIVE_CAP32; 734 } else { 735 printf("%s: 32-bits data port\n", drv_dev->dv_xname); 736 } 737 } 738 739 /* An ATAPI device is at last PIO mode 3 */ 740 if (drvp->drive_flags & DRIVE_ATAPI) 741 drvp->PIO_mode = 3; 742 743 /* 744 * It's not in the specs, but it seems that some drive 745 * returns 0xffff in atap_extensions when this field is invalid 746 */ 747 if (params.atap_extensions != 0xffff && 748 (params.atap_extensions & WDC_EXT_MODES)) { 749 printed = 0; 750 /* 751 * XXX some drives report something wrong here (they claim to 752 * support PIO mode 8 !). As mode is coded on 3 bits in 753 * SET FEATURE, limit it to 7 (so limit i to 4). 754 * If higther mode than 7 is found, abort. 755 */ 756 for (i = 7; i >= 0; i--) { 757 if ((params.atap_piomode_supp & (1 << i)) == 0) 758 continue; 759 if (i > 4) 760 return; 761 /* 762 * See if mode is accepted. 763 * If the controller can't set its PIO mode, 764 * assume the defaults are good, so don't try 765 * to set it 766 */ 767 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 768 if (ata_set_mode(drvp, 0x08 | (i + 3), 769 AT_POLL) != CMD_OK) 770 continue; 771 if (!printed) { 772 printf("%s: drive supports PIO mode %d", 773 drv_dev->dv_xname, i + 3); 774 sep = ","; 775 printed = 1; 776 } 777 /* 778 * If controller's driver can't set its PIO mode, 779 * get the highter one for the drive. 780 */ 781 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 782 wdc->pio_mode >= i + 3) { 783 drvp->PIO_mode = i + 3; 784 break; 785 } 786 } 787 if (!printed) { 788 /* 789 * We didn't find a valid PIO mode. 790 * Assume the values returned for DMA are buggy too 791 */ 792 return; 793 } 794 drvp->drive_flags |= DRIVE_MODE; 795 printed = 0; 796 for (i = 7; i >= 0; i--) { 797 if ((params.atap_dmamode_supp & (1 << i)) == 0) 798 continue; 799 if ((wdc->cap & WDC_CAPABILITY_DMA) && 800 (wdc->cap & WDC_CAPABILITY_MODE)) 801 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 802 != CMD_OK) 803 continue; 804 if (!printed) { 805 printf("%s DMA mode %d", sep, i); 806 sep = ","; 807 printed = 1; 808 } 809 if (wdc->cap & WDC_CAPABILITY_DMA) { 810 if ((wdc->cap & WDC_CAPABILITY_MODE) && 811 wdc->dma_mode < i) 812 continue; 813 drvp->DMA_mode = i; 814 drvp->drive_flags |= DRIVE_DMA; 815 } 816 break; 817 } 818 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 819 for (i = 7; i >= 0; i--) { 820 if ((params.atap_udmamode_supp & (1 << i)) 821 == 0) 822 continue; 823 if ((wdc->cap & WDC_CAPABILITY_MODE) && 824 (wdc->cap & WDC_CAPABILITY_UDMA)) 825 if (ata_set_mode(drvp, 0x40 | i, 826 AT_POLL) != CMD_OK) 827 continue; 828 printf("%s UDMA mode %d", sep, i); 829 sep = ","; 830 /* 831 * ATA-4 specs says if a mode is supported, 832 * all lower modes shall be supported. 833 * No need to look further. 834 */ 835 if (wdc->cap & WDC_CAPABILITY_UDMA) { 836 drvp->UDMA_mode = i; 837 drvp->drive_flags |= DRIVE_UDMA; 838 } 839 break; 840 } 841 } 842 printf("\n"); 843 } 844 } 845 846 int 847 wdc_exec_command(drvp, wdc_c) 848 struct ata_drive_datas *drvp; 849 struct wdc_command *wdc_c; 850 { 851 struct channel_softc *chp = drvp->chnl_softc; 852 struct wdc_xfer *xfer; 853 int s, ret; 854 855 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 856 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 857 DEBUG_FUNCS); 858 859 /* set up an xfer and queue. Wait for completion */ 860 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 861 WDC_NOSLEEP); 862 if (xfer == NULL) { 863 return WDC_TRY_AGAIN; 864 } 865 866 if (wdc_c->flags & AT_POLL) 867 xfer->c_flags |= C_POLL; 868 xfer->drive = drvp->drive; 869 xfer->databuf = wdc_c->data; 870 xfer->c_bcount = wdc_c->bcount; 871 xfer->cmd = wdc_c; 872 xfer->c_start = __wdccommand_start; 873 xfer->c_intr = __wdccommand_intr; 874 875 s = splbio(); 876 wdc_exec_xfer(chp, xfer); 877 #ifdef DIAGNOSTIC 878 if ((wdc_c->flags & AT_POLL) != 0 && 879 (wdc_c->flags & AT_DONE) == 0) 880 panic("wdc_exec_command: polled command not done\n"); 881 #endif 882 if (wdc_c->flags & AT_DONE) { 883 ret = WDC_COMPLETE; 884 } else { 885 if (wdc_c->flags & AT_WAIT) { 886 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 887 ret = WDC_COMPLETE; 888 } else { 889 ret = WDC_QUEUED; 890 } 891 } 892 splx(s); 893 return ret; 894 } 895 896 void 897 __wdccommand_start(chp, xfer) 898 struct channel_softc *chp; 899 struct wdc_xfer *xfer; 900 { 901 int drive = xfer->drive; 902 struct wdc_command *wdc_c = xfer->cmd; 903 904 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 905 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 906 DEBUG_FUNCS); 907 908 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 909 WDSD_IBM | (drive << 4)); 910 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 911 wdc_c->timeout) != 0) { 912 wdc_c->flags |= AT_TIMEOU; 913 __wdccommand_done(chp, xfer); 914 } 915 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 916 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 917 if ((wdc_c->flags & AT_POLL) == 0) { 918 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 919 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 920 return; 921 } 922 /* 923 * Polled command. Wait for drive ready or drq. Done in intr(). 924 * Wait for at last 400ns for status bit to be valid. 925 */ 926 delay(10); 927 if (__wdccommand_intr(chp, xfer) == 0) { 928 wdc_c->flags |= AT_TIMEOU; 929 __wdccommand_done(chp, xfer); 930 } 931 } 932 933 int 934 __wdccommand_intr(chp, xfer) 935 struct channel_softc *chp; 936 struct wdc_xfer *xfer; 937 { 938 struct wdc_command *wdc_c = xfer->cmd; 939 int bcount = wdc_c->bcount; 940 char *data = wdc_c->data; 941 942 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 943 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 944 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 945 wdc_c->timeout)) { 946 wdc_c->flags |= AT_ERROR; 947 __wdccommand_done(chp, xfer); 948 return 1; 949 } 950 if (wdc_c->flags & AT_READ) { 951 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 952 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 953 0, (u_int32_t*)data, bcount >> 2); 954 data += bcount & 0xfffffffc; 955 bcount = bcount & 0x03; 956 } 957 if (bcount > 0) 958 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 959 wd_data, (u_int16_t *)data, bcount >> 1); 960 } else if (wdc_c->flags & AT_WRITE) { 961 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 962 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 963 0, (u_int32_t*)data, bcount >> 2); 964 data += bcount & 0xfffffffc; 965 bcount = bcount & 0x03; 966 } 967 if (bcount > 0) 968 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 969 wd_data, (u_int16_t *)data, bcount >> 1); 970 } 971 __wdccommand_done(chp, xfer); 972 return 1; 973 } 974 975 void 976 __wdccommand_done(chp, xfer) 977 struct channel_softc *chp; 978 struct wdc_xfer *xfer; 979 { 980 int needdone = xfer->c_flags & C_NEEDDONE; 981 struct wdc_command *wdc_c = xfer->cmd; 982 983 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 984 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 985 if (chp->ch_status & WDCS_DWF) 986 wdc_c->flags |= AT_DF; 987 if (chp->ch_status & WDCS_ERR) { 988 wdc_c->flags |= AT_ERROR; 989 wdc_c->r_error = chp->ch_error; 990 } 991 wdc_c->flags |= AT_DONE; 992 wdc_free_xfer(chp, xfer); 993 if (needdone) { 994 if (wdc_c->flags & AT_WAIT) 995 wakeup(wdc_c); 996 else 997 wdc_c->callback(wdc_c->callback_arg); 998 } 999 wdcstart(chp->wdc, chp->channel); 1000 return; 1001 } 1002 1003 /* 1004 * Send a command. The drive should be ready. 1005 * Assumes interrupts are blocked. 1006 */ 1007 void 1008 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1009 struct channel_softc *chp; 1010 u_int8_t drive; 1011 u_int8_t command; 1012 u_int16_t cylin; 1013 u_int8_t head, sector, count, precomp; 1014 { 1015 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1016 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1017 chp->channel, drive, command, cylin, head, sector, count, precomp), 1018 DEBUG_FUNCS); 1019 1020 /* Select drive, head, and addressing mode. */ 1021 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1022 WDSD_IBM | (drive << 4) | head); 1023 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1024 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1025 precomp); 1026 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1027 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1028 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1029 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1030 1031 /* Send command. */ 1032 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1033 return; 1034 } 1035 1036 /* 1037 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1038 * tested by the caller. 1039 */ 1040 void 1041 wdccommandshort(chp, drive, command) 1042 struct channel_softc *chp; 1043 int drive; 1044 int command; 1045 { 1046 1047 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1048 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1049 DEBUG_FUNCS); 1050 1051 /* Select drive. */ 1052 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1053 WDSD_IBM | (drive << 4)); 1054 1055 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1056 } 1057 1058 /* Add a command to the queue and start controller. Must be called at splbio */ 1059 1060 void 1061 wdc_exec_xfer(chp, xfer) 1062 struct channel_softc *chp; 1063 struct wdc_xfer *xfer; 1064 { 1065 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1066 chp->channel, xfer->drive), DEBUG_XFERS); 1067 1068 /* complete xfer setup */ 1069 xfer->channel = chp->channel; 1070 1071 /* 1072 * If we are a polled command, and the list is not empty, 1073 * we are doing a dump. Drop the list to allow the polled command 1074 * to complete, we're going to reboot soon anyway. 1075 */ 1076 if ((xfer->c_flags & C_POLL) != 0 && 1077 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1078 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1079 } 1080 /* insert at the end of command list */ 1081 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1082 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1083 chp->ch_flags), DEBUG_XFERS); 1084 wdcstart(chp->wdc, chp->channel); 1085 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1086 } 1087 1088 struct wdc_xfer * 1089 wdc_get_xfer(flags) 1090 int flags; 1091 { 1092 struct wdc_xfer *xfer; 1093 int s; 1094 1095 s = splbio(); 1096 if ((xfer = xfer_free_list.lh_first) != NULL) { 1097 LIST_REMOVE(xfer, free_list); 1098 splx(s); 1099 #ifdef DIAGNOSTIC 1100 if ((xfer->c_flags & C_INUSE) != 0) 1101 panic("wdc_get_xfer: xfer already in use\n"); 1102 #endif 1103 } else { 1104 splx(s); 1105 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1106 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1107 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1108 if (xfer == NULL) 1109 return 0; 1110 #ifdef DIAGNOSTIC 1111 xfer->c_flags &= ~C_INUSE; 1112 #endif 1113 #ifdef WDCDEBUG 1114 wdc_nxfer++; 1115 #endif 1116 } 1117 #ifdef DIAGNOSTIC 1118 if ((xfer->c_flags & C_INUSE) != 0) 1119 panic("wdc_get_xfer: xfer already in use\n"); 1120 #endif 1121 memset(xfer, 0, sizeof(struct wdc_xfer)); 1122 xfer->c_flags = C_INUSE; 1123 return xfer; 1124 } 1125 1126 void 1127 wdc_free_xfer(chp, xfer) 1128 struct channel_softc *chp; 1129 struct wdc_xfer *xfer; 1130 { 1131 struct wdc_softc *wdc = chp->wdc; 1132 int s; 1133 1134 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1135 (*wdc->free_hw)(chp); 1136 s = splbio(); 1137 chp->ch_flags &= ~WDCF_ACTIVE; 1138 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1139 xfer->c_flags &= ~C_INUSE; 1140 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1141 splx(s); 1142 } 1143 1144 static void 1145 __wdcerror(chp, msg) 1146 struct channel_softc *chp; 1147 char *msg; 1148 { 1149 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1150 if (xfer == NULL) 1151 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1152 msg); 1153 else 1154 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1155 xfer->channel, xfer->drive, msg); 1156 } 1157 1158 /* 1159 * the bit bucket 1160 */ 1161 void 1162 wdcbit_bucket(chp, size) 1163 struct channel_softc *chp; 1164 int size; 1165 { 1166 1167 for (; size >= 2; size -= 2) 1168 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1169 if (size) 1170 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1171 } 1172
Indexes created Tue Sep 23 21:09:50 GMT 2025