wdc.c revision 1.44
1 /* $NetBSD: wdc.c,v 1.44 1998/11/20 01:22:37 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(1); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(1); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff) 200 ret_value &= ~0x01; 201 if (st1 == 0xff) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(1); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(1); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices , then rescan and try an ATA command, in case it's an 233 * old drive. 234 * Fill in drive_flags accordingly 235 */ 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 240 WDSD_IBM | (drive << 4)); 241 delay(1); 242 /* Save registers contents */ 243 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 244 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 245 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 246 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 247 248 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 249 "cl=0x%x ch=0x%x\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 251 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 252 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 253 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 254 } 255 } 256 for (drive = 0; drive < 2; drive++) { 257 if ((ret_value & (0x01 << drive)) == 0 || 258 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 259 continue; 260 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 261 WDSD_IBM | (drive << 4)); 262 delay(1); 263 /* 264 * Maybe it's an old device, so don't rely on ATA sig. 265 * Test registers writability (Error register not writable, 266 * but cyllo is), then try an ATA command. 267 */ 268 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 269 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 270 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 271 0x58 || 272 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 273 0xa5) { 274 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 275 "failed\n", 276 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 277 chp->channel, drive), DEBUG_PROBE); 278 ret_value &= ~(0x01 << drive); 279 continue; 280 } 281 if (wait_for_ready(chp, 10000) != 0) { 282 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 283 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 284 chp->channel, drive), DEBUG_PROBE); 285 ret_value &= ~(0x01 << drive); 286 continue; 287 } 288 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 289 WDCC_DIAGNOSE); 290 if (wait_for_ready(chp, 10000) == 0) { 291 chp->ch_drive[drive].drive_flags |= 292 DRIVE_ATA; 293 } else { 294 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 295 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 296 chp->channel, drive), DEBUG_PROBE); 297 ret_value &= ~(0x01 << drive); 298 } 299 } 300 return (ret_value); 301 } 302 303 void 304 wdcattach(chp) 305 struct channel_softc *chp; 306 { 307 int channel_flags, ctrl_flags, i, error; 308 struct ata_atapi_attach aa_link; 309 310 LIST_INIT(&xfer_free_list); 311 for (i = 0; i < 2; i++) { 312 chp->ch_drive[i].chnl_softc = chp; 313 chp->ch_drive[i].drive = i; 314 /* If controller can't do 16bit flag the drives as 32bit */ 315 if ((chp->wdc->cap & 316 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 317 WDC_CAPABILITY_DATA32) 318 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 319 } 320 321 if ((error = wdc_addref(chp)) != 0) { 322 printf("%s: unable to enable controller\n", 323 chp->wdc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (wdcprobe(chp) == 0) { 328 /* If no drives, abort attach here. */ 329 wdc_delref(chp); 330 return; 331 } 332 333 TAILQ_INIT(&chp->ch_queue->sc_xfer); 334 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 335 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 336 337 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 338 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 339 DEBUG_PROBE); 340 341 /* 342 * Attach an ATAPI bus, if needed. 343 */ 344 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 345 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 346 #if NATAPIBUS > 0 347 wdc_atapibus_attach(chp); 348 #else 349 /* 350 * Fills in a fake aa_link and call config_found, so that 351 * the config machinery will print 352 * "atapibus at xxx not configured" 353 */ 354 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 355 aa_link.aa_type = T_ATAPI; 356 aa_link.aa_channel = chp->channel; 357 aa_link.aa_openings = 1; 358 aa_link.aa_drv_data = 0; 359 aa_link.aa_bus_private = NULL; 360 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 361 atapi_print); 362 #endif 363 } 364 365 for (i = 0; i < 2; i++) { 366 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 367 continue; 368 } 369 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 370 aa_link.aa_type = T_ATA; 371 aa_link.aa_channel = chp->channel; 372 aa_link.aa_openings = 1; 373 aa_link.aa_drv_data = &chp->ch_drive[i]; 374 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 375 wdc_probe_caps(&chp->ch_drive[i]); 376 } 377 378 /* 379 * reset drive_flags for unnatached devices, reset state for attached 380 * ones 381 */ 382 for (i = 0; i < 2; i++) { 383 if (chp->ch_drive[i].drv_softc == NULL) 384 chp->ch_drive[i].drive_flags = 0; 385 else 386 chp->ch_drive[i].state = 0; 387 } 388 389 /* 390 * Reset channel. The probe, with some combinations of ATA/ATAPI 391 * devices keep it in a mostly working, but strange state (with busy 392 * led on) 393 */ 394 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 395 wdcreset(chp, VERBOSE); 396 /* 397 * Read status registers to avoid spurious interrupts. 398 */ 399 for (i = 1; i >= 0; i--) { 400 if (chp->ch_drive[i].drive_flags & DRIVE) { 401 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 402 wd_sdh, WDSD_IBM | (i << 4)); 403 if (wait_for_unbusy(chp, 10000) < 0) 404 printf("%s:%d:%d: device busy\n", 405 chp->wdc->sc_dev.dv_xname, 406 chp->channel, i); 407 } 408 } 409 } 410 wdc_delref(chp); 411 } 412 413 /* 414 * Start I/O on a controller, for the given channel. 415 * The first xfer may be not for our channel if the channel queues 416 * are shared. 417 */ 418 void 419 wdcstart(wdc, channel) 420 struct wdc_softc *wdc; 421 int channel; 422 { 423 struct wdc_xfer *xfer; 424 struct channel_softc *chp; 425 426 #ifdef WDC_DIAGNOSTIC 427 int spl1, spl2; 428 429 spl1 = splbio(); 430 spl2 = splbio(); 431 if (spl2 != spl1) { 432 printf("wdcstart: not at splbio()\n"); 433 panic("wdcstart"); 434 } 435 splx(spl2); 436 splx(spl1); 437 #endif /* WDC_DIAGNOSTIC */ 438 439 /* is there a xfer ? */ 440 if ((xfer = wdc->channels[channel].ch_queue->sc_xfer.tqh_first) == NULL) 441 return; 442 chp = &wdc->channels[xfer->channel]; 443 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 444 return; /* channel aleady active */ 445 } 446 #ifdef DIAGNOSTIC 447 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 448 panic("wdcstart: channel waiting for irq\n"); 449 #endif 450 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 451 if (!(*wdc->claim_hw)(chp, 0)) 452 return; 453 454 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 455 xfer->channel, xfer->drive), DEBUG_XFERS); 456 chp->ch_flags |= WDCF_ACTIVE; 457 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 458 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 459 chp->ch_drive[xfer->drive].state = 0; 460 } 461 xfer->c_start(chp, xfer); 462 } 463 464 /* restart an interrupted I/O */ 465 void 466 wdcrestart(v) 467 void *v; 468 { 469 struct channel_softc *chp = v; 470 int s; 471 472 s = splbio(); 473 wdcstart(chp->wdc, chp->channel); 474 splx(s); 475 } 476 477 478 /* 479 * Interrupt routine for the controller. Acknowledge the interrupt, check for 480 * errors on the current operation, mark it done if necessary, and start the 481 * next request. Also check for a partially done transfer, and continue with 482 * the next chunk if so. 483 */ 484 int 485 wdcintr(arg) 486 void *arg; 487 { 488 struct channel_softc *chp = arg; 489 struct wdc_xfer *xfer; 490 491 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 492 #if 0 493 /* Clear the pending interrupt and abort. */ 494 u_int8_t s = 495 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 496 #ifdef WDCDEBUG 497 u_int8_t e = 498 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 499 u_int8_t i = 500 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 501 #else 502 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 503 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 504 #endif 505 506 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 507 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 508 509 if (s & WDCS_DRQ) { 510 int len; 511 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 512 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 513 chp->cmd_ioh, wd_cyl_hi); 514 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 515 len), DEBUG_INTR); 516 wdcbit_bucket (chp, len); 517 } 518 #else 519 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 520 #endif 521 return 0; 522 } 523 524 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 525 untimeout(wdctimeout, chp); 526 chp->ch_flags &= ~WDCF_IRQ_WAIT; 527 xfer = chp->ch_queue->sc_xfer.tqh_first; 528 return xfer->c_intr(chp, xfer); 529 } 530 531 /* Put all disk in RESET state */ 532 void wdc_reset_channel(drvp) 533 struct ata_drive_datas *drvp; 534 { 535 struct channel_softc *chp = drvp->chnl_softc; 536 int drive; 537 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 538 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 539 DEBUG_FUNCS); 540 (void) wdcreset(chp, VERBOSE); 541 for (drive = 0; drive < 2; drive++) { 542 chp->ch_drive[drive].state = 0; 543 } 544 } 545 546 int 547 wdcreset(chp, verb) 548 struct channel_softc *chp; 549 int verb; 550 { 551 int drv_mask1, drv_mask2; 552 553 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 554 WDSD_IBM); /* master */ 555 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 556 WDCTL_RST | WDCTL_IDS); 557 delay(1000); 558 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 559 WDCTL_IDS); 560 delay(1000); 561 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 562 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 563 WDCTL_4BIT); 564 565 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 566 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 567 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 568 if (verb && drv_mask2 != drv_mask1) { 569 printf("%s channel %d: reset failed for", 570 chp->wdc->sc_dev.dv_xname, chp->channel); 571 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 572 printf(" drive 0"); 573 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 574 printf(" drive 1"); 575 printf("\n"); 576 } 577 return (drv_mask1 != drv_mask2) ? 1 : 0; 578 } 579 580 static int 581 __wdcwait_reset(chp, drv_mask) 582 struct channel_softc *chp; 583 int drv_mask; 584 { 585 int timeout; 586 u_int8_t st0, st1; 587 /* wait for BSY to deassert */ 588 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 589 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 590 WDSD_IBM); /* master */ 591 delay(1); 592 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 593 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 594 WDSD_IBM | 0x10); /* slave */ 595 delay(1); 596 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 597 598 if ((drv_mask & 0x01) == 0) { 599 /* no master */ 600 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 601 /* No master, slave is ready, it's done */ 602 return drv_mask; 603 } 604 } else if ((drv_mask & 0x02) == 0) { 605 /* no slave */ 606 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 607 /* No slave, master is ready, it's done */ 608 return drv_mask; 609 } 610 } else { 611 /* Wait for both master and slave to be ready */ 612 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 613 return drv_mask; 614 } 615 } 616 delay(WDCDELAY); 617 } 618 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 619 if (st0 & WDCS_BSY) 620 drv_mask &= ~0x01; 621 if (st1 & WDCS_BSY) 622 drv_mask &= ~0x02; 623 return drv_mask; 624 } 625 626 /* 627 * Wait for a drive to be !BSY, and have mask in its status register. 628 * return -1 for a timeout after "timeout" ms. 629 */ 630 int 631 wdcwait(chp, mask, bits, timeout) 632 struct channel_softc *chp; 633 int mask, bits, timeout; 634 { 635 u_char status; 636 int time = 0; 637 #ifdef WDCNDELAY_DEBUG 638 extern int cold; 639 #endif 640 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 641 chp->channel), DEBUG_STATUS); 642 chp->ch_error = 0; 643 644 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 645 646 for (;;) { 647 chp->ch_status = status = 648 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 649 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 650 break; 651 if (++time > timeout) { 652 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 653 "error %x\n", status, 654 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 655 wd_error)), 656 DEBUG_STATUS); 657 return -1; 658 } 659 delay(WDCDELAY); 660 } 661 if (status & WDCS_ERR) 662 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 663 wd_error); 664 #ifdef WDCNDELAY_DEBUG 665 /* After autoconfig, there should be no long delays. */ 666 if (!cold && time > WDCNDELAY_DEBUG) { 667 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 668 if (xfer == NULL) 669 printf("%s channel %d: warning: busy-wait took %dus\n", 670 chp->wdc->sc_dev.dv_xname, chp->channel, 671 WDCDELAY * time); 672 else 673 printf("%s:%d:%d: warning: busy-wait took %dus\n", 674 chp->wdc->sc_dev.dv_xname, xfer->channel, 675 xfer->drive, 676 WDCDELAY * time); 677 } 678 #endif 679 return 0; 680 } 681 682 void 683 wdctimeout(arg) 684 void *arg; 685 { 686 struct channel_softc *chp = (struct channel_softc *)arg; 687 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 688 int s; 689 690 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 691 692 s = splbio(); 693 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 694 __wdcerror(chp, "lost interrupt"); 695 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 696 "atapi":"ata"); 697 printf("\tc_bcount: %d\n", xfer->c_bcount); 698 printf("\tc_skip: %d\n", xfer->c_skip); 699 /* 700 * Call the interrupt routine. If we just missed and interrupt, 701 * it will do what's needed. Else, it will take the needed 702 * action (reset the device). 703 */ 704 xfer->c_flags |= C_TIMEOU; 705 chp->ch_flags &= ~WDCF_IRQ_WAIT; 706 xfer->c_intr(chp, xfer); 707 } else 708 __wdcerror(chp, "missing untimeout"); 709 splx(s); 710 } 711 712 /* 713 * Probe drive's capabilites, for use by the controller later 714 * Assumes drvp points to an existing drive. 715 * XXX this should be a controller-indep function 716 */ 717 void 718 wdc_probe_caps(drvp) 719 struct ata_drive_datas *drvp; 720 { 721 struct ataparams params, params2; 722 struct channel_softc *chp = drvp->chnl_softc; 723 struct device *drv_dev = drvp->drv_softc; 724 struct wdc_softc *wdc = chp->wdc; 725 int i, printed; 726 char *sep = ""; 727 728 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 729 /* IDENTIFY failed. Can't tell more about the device */ 730 return; 731 } 732 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 733 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 734 /* 735 * Controller claims 16 and 32 bit transfers. 736 * Re-do an IDENTIFY with 32-bit transfers, 737 * and compare results. 738 */ 739 drvp->drive_flags |= DRIVE_CAP32; 740 ata_get_params(drvp, AT_POLL, ¶ms2); 741 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 742 /* Not good. fall back to 16bits */ 743 drvp->drive_flags &= ~DRIVE_CAP32; 744 } else { 745 printf("%s: 32-bits data port\n", drv_dev->dv_xname); 746 } 747 } 748 749 /* An ATAPI device is at last PIO mode 3 */ 750 if (drvp->drive_flags & DRIVE_ATAPI) 751 drvp->PIO_mode = 3; 752 753 /* 754 * It's not in the specs, but it seems that some drive 755 * returns 0xffff in atap_extensions when this field is invalid 756 */ 757 if (params.atap_extensions != 0xffff && 758 (params.atap_extensions & WDC_EXT_MODES)) { 759 printed = 0; 760 /* 761 * XXX some drives report something wrong here (they claim to 762 * support PIO mode 8 !). As mode is coded on 3 bits in 763 * SET FEATURE, limit it to 7 (so limit i to 4). 764 * If higther mode than 7 is found, abort. 765 */ 766 for (i = 7; i >= 0; i--) { 767 if ((params.atap_piomode_supp & (1 << i)) == 0) 768 continue; 769 if (i > 4) 770 return; 771 /* 772 * See if mode is accepted. 773 * If the controller can't set its PIO mode, 774 * assume the defaults are good, so don't try 775 * to set it 776 */ 777 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 778 if (ata_set_mode(drvp, 0x08 | (i + 3), 779 AT_POLL) != CMD_OK) 780 continue; 781 if (!printed) { 782 printf("%s: drive supports PIO mode %d", 783 drv_dev->dv_xname, i + 3); 784 sep = ","; 785 printed = 1; 786 } 787 /* 788 * If controller's driver can't set its PIO mode, 789 * get the highter one for the drive. 790 */ 791 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 792 wdc->pio_mode >= i + 3) { 793 drvp->PIO_mode = i + 3; 794 break; 795 } 796 } 797 if (!printed) { 798 /* 799 * We didn't find a valid PIO mode. 800 * Assume the values returned for DMA are buggy too 801 */ 802 return; 803 } 804 drvp->drive_flags |= DRIVE_MODE; 805 printed = 0; 806 for (i = 7; i >= 0; i--) { 807 if ((params.atap_dmamode_supp & (1 << i)) == 0) 808 continue; 809 if ((wdc->cap & WDC_CAPABILITY_DMA) && 810 (wdc->cap & WDC_CAPABILITY_MODE)) 811 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 812 != CMD_OK) 813 continue; 814 if (!printed) { 815 printf("%s DMA mode %d", sep, i); 816 sep = ","; 817 printed = 1; 818 } 819 if (wdc->cap & WDC_CAPABILITY_DMA) { 820 if ((wdc->cap & WDC_CAPABILITY_MODE) && 821 wdc->dma_mode < i) 822 continue; 823 drvp->DMA_mode = i; 824 drvp->drive_flags |= DRIVE_DMA; 825 } 826 break; 827 } 828 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 829 for (i = 7; i >= 0; i--) { 830 if ((params.atap_udmamode_supp & (1 << i)) 831 == 0) 832 continue; 833 if ((wdc->cap & WDC_CAPABILITY_MODE) && 834 (wdc->cap & WDC_CAPABILITY_UDMA)) 835 if (ata_set_mode(drvp, 0x40 | i, 836 AT_POLL) != CMD_OK) 837 continue; 838 printf("%s UDMA mode %d", sep, i); 839 sep = ","; 840 /* 841 * ATA-4 specs says if a mode is supported, 842 * all lower modes shall be supported. 843 * No need to look further. 844 */ 845 if (wdc->cap & WDC_CAPABILITY_UDMA) { 846 drvp->UDMA_mode = i; 847 drvp->drive_flags |= DRIVE_UDMA; 848 } 849 break; 850 } 851 } 852 printf("\n"); 853 } 854 } 855 856 int 857 wdc_exec_command(drvp, wdc_c) 858 struct ata_drive_datas *drvp; 859 struct wdc_command *wdc_c; 860 { 861 struct channel_softc *chp = drvp->chnl_softc; 862 struct wdc_xfer *xfer; 863 int s, ret; 864 865 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 866 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 867 DEBUG_FUNCS); 868 869 /* set up an xfer and queue. Wait for completion */ 870 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 871 WDC_NOSLEEP); 872 if (xfer == NULL) { 873 return WDC_TRY_AGAIN; 874 } 875 876 if (wdc_c->flags & AT_POLL) 877 xfer->c_flags |= C_POLL; 878 xfer->drive = drvp->drive; 879 xfer->databuf = wdc_c->data; 880 xfer->c_bcount = wdc_c->bcount; 881 xfer->cmd = wdc_c; 882 xfer->c_start = __wdccommand_start; 883 xfer->c_intr = __wdccommand_intr; 884 885 s = splbio(); 886 wdc_exec_xfer(chp, xfer); 887 #ifdef DIAGNOSTIC 888 if ((wdc_c->flags & AT_POLL) != 0 && 889 (wdc_c->flags & AT_DONE) == 0) 890 panic("wdc_exec_command: polled command not done\n"); 891 #endif 892 if (wdc_c->flags & AT_DONE) { 893 ret = WDC_COMPLETE; 894 } else { 895 if (wdc_c->flags & AT_WAIT) { 896 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 897 ret = WDC_COMPLETE; 898 } else { 899 ret = WDC_QUEUED; 900 } 901 } 902 splx(s); 903 return ret; 904 } 905 906 void 907 __wdccommand_start(chp, xfer) 908 struct channel_softc *chp; 909 struct wdc_xfer *xfer; 910 { 911 int drive = xfer->drive; 912 struct wdc_command *wdc_c = xfer->cmd; 913 914 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 915 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 916 DEBUG_FUNCS); 917 918 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 919 WDSD_IBM | (drive << 4)); 920 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 921 wdc_c->timeout) != 0) { 922 wdc_c->flags |= AT_TIMEOU; 923 __wdccommand_done(chp, xfer); 924 } 925 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 926 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 927 if ((wdc_c->flags & AT_POLL) == 0) { 928 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 929 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 930 return; 931 } 932 /* 933 * Polled command. Wait for drive ready or drq. Done in intr(). 934 * Wait for at last 400ns for status bit to be valid. 935 */ 936 delay(10); 937 if (__wdccommand_intr(chp, xfer) == 0) { 938 wdc_c->flags |= AT_TIMEOU; 939 __wdccommand_done(chp, xfer); 940 } 941 } 942 943 int 944 __wdccommand_intr(chp, xfer) 945 struct channel_softc *chp; 946 struct wdc_xfer *xfer; 947 { 948 struct wdc_command *wdc_c = xfer->cmd; 949 int bcount = wdc_c->bcount; 950 char *data = wdc_c->data; 951 952 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 953 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 954 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 955 wdc_c->timeout)) { 956 wdc_c->flags |= AT_ERROR; 957 __wdccommand_done(chp, xfer); 958 return 1; 959 } 960 if (wdc_c->flags & AT_READ) { 961 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 962 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 963 0, (u_int32_t*)data, bcount >> 2); 964 data += bcount & 0xfffffffc; 965 bcount = bcount & 0x03; 966 } 967 if (bcount > 0) 968 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 969 wd_data, (u_int16_t *)data, bcount >> 1); 970 } else if (wdc_c->flags & AT_WRITE) { 971 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 972 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 973 0, (u_int32_t*)data, bcount >> 2); 974 data += bcount & 0xfffffffc; 975 bcount = bcount & 0x03; 976 } 977 if (bcount > 0) 978 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 979 wd_data, (u_int16_t *)data, bcount >> 1); 980 } 981 __wdccommand_done(chp, xfer); 982 return 1; 983 } 984 985 void 986 __wdccommand_done(chp, xfer) 987 struct channel_softc *chp; 988 struct wdc_xfer *xfer; 989 { 990 int needdone = xfer->c_flags & C_NEEDDONE; 991 struct wdc_command *wdc_c = xfer->cmd; 992 993 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 994 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 995 if (chp->ch_status & WDCS_DWF) 996 wdc_c->flags |= AT_DF; 997 if (chp->ch_status & WDCS_ERR) { 998 wdc_c->flags |= AT_ERROR; 999 wdc_c->r_error = chp->ch_error; 1000 } 1001 wdc_c->flags |= AT_DONE; 1002 wdc_free_xfer(chp, xfer); 1003 if (needdone) { 1004 if (wdc_c->flags & AT_WAIT) 1005 wakeup(wdc_c); 1006 else 1007 wdc_c->callback(wdc_c->callback_arg); 1008 } 1009 wdcstart(chp->wdc, chp->channel); 1010 return; 1011 } 1012 1013 /* 1014 * Send a command. The drive should be ready. 1015 * Assumes interrupts are blocked. 1016 */ 1017 void 1018 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1019 struct channel_softc *chp; 1020 u_int8_t drive; 1021 u_int8_t command; 1022 u_int16_t cylin; 1023 u_int8_t head, sector, count, precomp; 1024 { 1025 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1026 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1027 chp->channel, drive, command, cylin, head, sector, count, precomp), 1028 DEBUG_FUNCS); 1029 1030 /* Select drive, head, and addressing mode. */ 1031 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1032 WDSD_IBM | (drive << 4) | head); 1033 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1034 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1035 precomp); 1036 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1037 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1038 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1039 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1040 1041 /* Send command. */ 1042 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1043 return; 1044 } 1045 1046 /* 1047 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1048 * tested by the caller. 1049 */ 1050 void 1051 wdccommandshort(chp, drive, command) 1052 struct channel_softc *chp; 1053 int drive; 1054 int command; 1055 { 1056 1057 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1058 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1059 DEBUG_FUNCS); 1060 1061 /* Select drive. */ 1062 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1063 WDSD_IBM | (drive << 4)); 1064 1065 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1066 } 1067 1068 /* Add a command to the queue and start controller. Must be called at splbio */ 1069 1070 void 1071 wdc_exec_xfer(chp, xfer) 1072 struct channel_softc *chp; 1073 struct wdc_xfer *xfer; 1074 { 1075 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1076 chp->channel, xfer->drive), DEBUG_XFERS); 1077 1078 /* complete xfer setup */ 1079 xfer->channel = chp->channel; 1080 1081 /* 1082 * If we are a polled command, and the list is not empty, 1083 * we are doing a dump. Drop the list to allow the polled command 1084 * to complete, we're going to reboot soon anyway. 1085 */ 1086 if ((xfer->c_flags & C_POLL) != 0 && 1087 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1088 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1089 } 1090 /* insert at the end of command list */ 1091 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1092 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1093 chp->ch_flags), DEBUG_XFERS); 1094 wdcstart(chp->wdc, chp->channel); 1095 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1096 } 1097 1098 struct wdc_xfer * 1099 wdc_get_xfer(flags) 1100 int flags; 1101 { 1102 struct wdc_xfer *xfer; 1103 int s; 1104 1105 s = splbio(); 1106 if ((xfer = xfer_free_list.lh_first) != NULL) { 1107 LIST_REMOVE(xfer, free_list); 1108 splx(s); 1109 #ifdef DIAGNOSTIC 1110 if ((xfer->c_flags & C_INUSE) != 0) 1111 panic("wdc_get_xfer: xfer already in use\n"); 1112 #endif 1113 } else { 1114 splx(s); 1115 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1116 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1117 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1118 if (xfer == NULL) 1119 return 0; 1120 #ifdef DIAGNOSTIC 1121 xfer->c_flags &= ~C_INUSE; 1122 #endif 1123 #ifdef WDCDEBUG 1124 wdc_nxfer++; 1125 #endif 1126 } 1127 #ifdef DIAGNOSTIC 1128 if ((xfer->c_flags & C_INUSE) != 0) 1129 panic("wdc_get_xfer: xfer already in use\n"); 1130 #endif 1131 memset(xfer, 0, sizeof(struct wdc_xfer)); 1132 xfer->c_flags = C_INUSE; 1133 return xfer; 1134 } 1135 1136 void 1137 wdc_free_xfer(chp, xfer) 1138 struct channel_softc *chp; 1139 struct wdc_xfer *xfer; 1140 { 1141 struct wdc_softc *wdc = chp->wdc; 1142 int s; 1143 1144 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1145 (*wdc->free_hw)(chp); 1146 s = splbio(); 1147 chp->ch_flags &= ~WDCF_ACTIVE; 1148 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1149 xfer->c_flags &= ~C_INUSE; 1150 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1151 splx(s); 1152 } 1153 1154 static void 1155 __wdcerror(chp, msg) 1156 struct channel_softc *chp; 1157 char *msg; 1158 { 1159 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1160 if (xfer == NULL) 1161 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1162 msg); 1163 else 1164 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1165 xfer->channel, xfer->drive, msg); 1166 } 1167 1168 /* 1169 * the bit bucket 1170 */ 1171 void 1172 wdcbit_bucket(chp, size) 1173 struct channel_softc *chp; 1174 int size; 1175 { 1176 1177 for (; size >= 2; size -= 2) 1178 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1179 if (size) 1180 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1181 } 1182 1183 int 1184 wdc_addref(chp) 1185 struct channel_softc *chp; 1186 { 1187 struct wdc_softc *wdc = chp->wdc; 1188 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1189 int s, error = 0; 1190 1191 s = splbio(); 1192 if (adapter->scsipi_refcnt++ == 0 && 1193 adapter->scsipi_enable != NULL) { 1194 error = (*adapter->scsipi_enable)(wdc, 1); 1195 if (error) 1196 adapter->scsipi_refcnt--; 1197 } 1198 splx(s); 1199 return (error); 1200 } 1201 1202 void 1203 wdc_delref(chp) 1204 struct channel_softc *chp; 1205 { 1206 struct wdc_softc *wdc = chp->wdc; 1207 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1208 int s; 1209 1210 s = splbio(); 1211 if (adapter->scsipi_refcnt-- == 1 && 1212 adapter->scsipi_enable != NULL) 1213 (void) (*adapter->scsipi_enable)(wdc, 0); 1214 splx(s); 1215 } 1216
Indexes created Fri Sep 26 20:09:58 GMT 2025