wdc.c revision 1.46
1 /* $NetBSD: wdc.c,v 1.46 1998/11/23 23:02:11 kenh Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(1); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(1); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff) 200 ret_value &= ~0x01; 201 if (st1 == 0xff) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(1); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(1); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices , then rescan and try an ATA command, in case it's an 233 * old drive. 234 * Fill in drive_flags accordingly 235 */ 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 240 WDSD_IBM | (drive << 4)); 241 delay(1); 242 /* Save registers contents */ 243 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 244 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 245 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 246 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 247 248 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 249 "cl=0x%x ch=0x%x\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 251 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 252 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 253 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 254 } 255 } 256 for (drive = 0; drive < 2; drive++) { 257 if ((ret_value & (0x01 << drive)) == 0 || 258 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 259 continue; 260 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 261 WDSD_IBM | (drive << 4)); 262 delay(1); 263 /* 264 * Maybe it's an old device, so don't rely on ATA sig. 265 * Test registers writability (Error register not writable, 266 * but cyllo is), then try an ATA command. 267 */ 268 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 269 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 270 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 271 0x58 || 272 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 273 0xa5) { 274 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 275 "failed\n", 276 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 277 chp->channel, drive), DEBUG_PROBE); 278 ret_value &= ~(0x01 << drive); 279 continue; 280 } 281 if (wait_for_ready(chp, 10000) != 0) { 282 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 283 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 284 chp->channel, drive), DEBUG_PROBE); 285 ret_value &= ~(0x01 << drive); 286 continue; 287 } 288 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 289 WDCC_DIAGNOSE); 290 if (wait_for_ready(chp, 10000) == 0) { 291 chp->ch_drive[drive].drive_flags |= 292 DRIVE_ATA; 293 } else { 294 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 295 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 296 chp->channel, drive), DEBUG_PROBE); 297 ret_value &= ~(0x01 << drive); 298 } 299 } 300 return (ret_value); 301 } 302 303 void 304 wdcattach(chp) 305 struct channel_softc *chp; 306 { 307 int channel_flags, ctrl_flags, i, error; 308 struct ata_atapi_attach aa_link; 309 310 LIST_INIT(&xfer_free_list); 311 for (i = 0; i < 2; i++) { 312 chp->ch_drive[i].chnl_softc = chp; 313 chp->ch_drive[i].drive = i; 314 /* If controller can't do 16bit flag the drives as 32bit */ 315 if ((chp->wdc->cap & 316 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 317 WDC_CAPABILITY_DATA32) 318 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 319 } 320 321 if ((error = wdc_addref(chp)) != 0) { 322 printf("%s: unable to enable controller\n", 323 chp->wdc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (wdcprobe(chp) == 0) { 328 /* If no drives, abort attach here. */ 329 wdc_delref(chp); 330 return; 331 } 332 333 TAILQ_INIT(&chp->ch_queue->sc_xfer); 334 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 335 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 336 337 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 338 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 339 DEBUG_PROBE); 340 341 /* 342 * Attach an ATAPI bus, if needed. 343 */ 344 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 345 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 346 #if NATAPIBUS > 0 347 wdc_atapibus_attach(chp); 348 #else 349 /* 350 * Fills in a fake aa_link and call config_found, so that 351 * the config machinery will print 352 * "atapibus at xxx not configured" 353 */ 354 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 355 aa_link.aa_type = T_ATAPI; 356 aa_link.aa_channel = chp->channel; 357 aa_link.aa_openings = 1; 358 aa_link.aa_drv_data = 0; 359 aa_link.aa_bus_private = NULL; 360 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 361 atapi_print); 362 #endif 363 } 364 365 for (i = 0; i < 2; i++) { 366 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 367 continue; 368 } 369 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 370 aa_link.aa_type = T_ATA; 371 aa_link.aa_channel = chp->channel; 372 aa_link.aa_openings = 1; 373 aa_link.aa_drv_data = &chp->ch_drive[i]; 374 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 375 wdc_probe_caps(&chp->ch_drive[i]); 376 } 377 378 /* 379 * reset drive_flags for unnatached devices, reset state for attached 380 * ones 381 */ 382 for (i = 0; i < 2; i++) { 383 if (chp->ch_drive[i].drv_softc == NULL) 384 chp->ch_drive[i].drive_flags = 0; 385 else 386 chp->ch_drive[i].state = 0; 387 } 388 389 /* 390 * Reset channel. The probe, with some combinations of ATA/ATAPI 391 * devices keep it in a mostly working, but strange state (with busy 392 * led on) 393 */ 394 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 395 wdcreset(chp, VERBOSE); 396 /* 397 * Read status registers to avoid spurious interrupts. 398 */ 399 for (i = 1; i >= 0; i--) { 400 if (chp->ch_drive[i].drive_flags & DRIVE) { 401 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 402 wd_sdh, WDSD_IBM | (i << 4)); 403 if (wait_for_unbusy(chp, 10000) < 0) 404 printf("%s:%d:%d: device busy\n", 405 chp->wdc->sc_dev.dv_xname, 406 chp->channel, i); 407 } 408 } 409 } 410 wdc_delref(chp); 411 } 412 413 /* 414 * Start I/O on a controller, for the given channel. 415 * The first xfer may be not for our channel if the channel queues 416 * are shared. 417 */ 418 void 419 wdcstart(chp) 420 struct channel_softc *chp; 421 { 422 struct wdc_xfer *xfer; 423 424 #ifdef WDC_DIAGNOSTIC 425 int spl1, spl2; 426 427 spl1 = splbio(); 428 spl2 = splbio(); 429 if (spl2 != spl1) { 430 printf("wdcstart: not at splbio()\n"); 431 panic("wdcstart"); 432 } 433 splx(spl2); 434 splx(spl1); 435 #endif /* WDC_DIAGNOSTIC */ 436 437 /* is there a xfer ? */ 438 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 439 return; 440 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 441 return; /* channel aleady active */ 442 } 443 #ifdef DIAGNOSTIC 444 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 445 panic("wdcstart: channel waiting for irq\n"); 446 #endif 447 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 448 if (!(*chp->wdc->claim_hw)(chp, 0)) 449 return; 450 451 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 452 xfer->channel, xfer->drive), DEBUG_XFERS); 453 chp->ch_flags |= WDCF_ACTIVE; 454 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 455 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 456 chp->ch_drive[xfer->drive].state = 0; 457 } 458 xfer->c_start(chp, xfer); 459 } 460 461 /* restart an interrupted I/O */ 462 void 463 wdcrestart(v) 464 void *v; 465 { 466 struct channel_softc *chp = v; 467 int s; 468 469 s = splbio(); 470 wdcstart(chp); 471 splx(s); 472 } 473 474 475 /* 476 * Interrupt routine for the controller. Acknowledge the interrupt, check for 477 * errors on the current operation, mark it done if necessary, and start the 478 * next request. Also check for a partially done transfer, and continue with 479 * the next chunk if so. 480 */ 481 int 482 wdcintr(arg) 483 void *arg; 484 { 485 struct channel_softc *chp = arg; 486 struct wdc_xfer *xfer; 487 488 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 489 #if 0 490 /* Clear the pending interrupt and abort. */ 491 u_int8_t s = 492 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 493 #ifdef WDCDEBUG 494 u_int8_t e = 495 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 496 u_int8_t i = 497 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 498 #else 499 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 500 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 501 #endif 502 503 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 504 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 505 506 if (s & WDCS_DRQ) { 507 int len; 508 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 509 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 510 chp->cmd_ioh, wd_cyl_hi); 511 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 512 len), DEBUG_INTR); 513 wdcbit_bucket (chp, len); 514 } 515 #else 516 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 517 #endif 518 return 0; 519 } 520 521 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 522 untimeout(wdctimeout, chp); 523 chp->ch_flags &= ~WDCF_IRQ_WAIT; 524 xfer = chp->ch_queue->sc_xfer.tqh_first; 525 return xfer->c_intr(chp, xfer); 526 } 527 528 /* Put all disk in RESET state */ 529 void wdc_reset_channel(drvp) 530 struct ata_drive_datas *drvp; 531 { 532 struct channel_softc *chp = drvp->chnl_softc; 533 int drive; 534 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 535 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 536 DEBUG_FUNCS); 537 (void) wdcreset(chp, VERBOSE); 538 for (drive = 0; drive < 2; drive++) { 539 chp->ch_drive[drive].state = 0; 540 } 541 } 542 543 int 544 wdcreset(chp, verb) 545 struct channel_softc *chp; 546 int verb; 547 { 548 int drv_mask1, drv_mask2; 549 550 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 551 WDSD_IBM); /* master */ 552 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 553 WDCTL_RST | WDCTL_IDS); 554 delay(1000); 555 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 556 WDCTL_IDS); 557 delay(1000); 558 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 559 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 560 WDCTL_4BIT); 561 562 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 563 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 564 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 565 if (verb && drv_mask2 != drv_mask1) { 566 printf("%s channel %d: reset failed for", 567 chp->wdc->sc_dev.dv_xname, chp->channel); 568 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 569 printf(" drive 0"); 570 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 571 printf(" drive 1"); 572 printf("\n"); 573 } 574 return (drv_mask1 != drv_mask2) ? 1 : 0; 575 } 576 577 static int 578 __wdcwait_reset(chp, drv_mask) 579 struct channel_softc *chp; 580 int drv_mask; 581 { 582 int timeout; 583 u_int8_t st0, st1; 584 /* wait for BSY to deassert */ 585 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 586 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 587 WDSD_IBM); /* master */ 588 delay(1); 589 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 590 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 591 WDSD_IBM | 0x10); /* slave */ 592 delay(1); 593 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 594 595 if ((drv_mask & 0x01) == 0) { 596 /* no master */ 597 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 598 /* No master, slave is ready, it's done */ 599 return drv_mask; 600 } 601 } else if ((drv_mask & 0x02) == 0) { 602 /* no slave */ 603 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 604 /* No slave, master is ready, it's done */ 605 return drv_mask; 606 } 607 } else { 608 /* Wait for both master and slave to be ready */ 609 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 610 return drv_mask; 611 } 612 } 613 delay(WDCDELAY); 614 } 615 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 616 if (st0 & WDCS_BSY) 617 drv_mask &= ~0x01; 618 if (st1 & WDCS_BSY) 619 drv_mask &= ~0x02; 620 return drv_mask; 621 } 622 623 /* 624 * Wait for a drive to be !BSY, and have mask in its status register. 625 * return -1 for a timeout after "timeout" ms. 626 */ 627 int 628 wdcwait(chp, mask, bits, timeout) 629 struct channel_softc *chp; 630 int mask, bits, timeout; 631 { 632 u_char status; 633 int time = 0; 634 #ifdef WDCNDELAY_DEBUG 635 extern int cold; 636 #endif 637 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 638 chp->channel), DEBUG_STATUS); 639 chp->ch_error = 0; 640 641 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 642 643 for (;;) { 644 chp->ch_status = status = 645 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 646 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 647 break; 648 if (++time > timeout) { 649 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 650 "error %x\n", status, 651 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 652 wd_error)), 653 DEBUG_STATUS); 654 return -1; 655 } 656 delay(WDCDELAY); 657 } 658 if (status & WDCS_ERR) 659 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 660 wd_error); 661 #ifdef WDCNDELAY_DEBUG 662 /* After autoconfig, there should be no long delays. */ 663 if (!cold && time > WDCNDELAY_DEBUG) { 664 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 665 if (xfer == NULL) 666 printf("%s channel %d: warning: busy-wait took %dus\n", 667 chp->wdc->sc_dev.dv_xname, chp->channel, 668 WDCDELAY * time); 669 else 670 printf("%s:%d:%d: warning: busy-wait took %dus\n", 671 chp->wdc->sc_dev.dv_xname, xfer->channel, 672 xfer->drive, 673 WDCDELAY * time); 674 } 675 #endif 676 return 0; 677 } 678 679 void 680 wdctimeout(arg) 681 void *arg; 682 { 683 struct channel_softc *chp = (struct channel_softc *)arg; 684 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 685 int s; 686 687 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 688 689 s = splbio(); 690 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 691 __wdcerror(chp, "lost interrupt"); 692 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 693 "atapi":"ata"); 694 printf("\tc_bcount: %d\n", xfer->c_bcount); 695 printf("\tc_skip: %d\n", xfer->c_skip); 696 /* 697 * Call the interrupt routine. If we just missed and interrupt, 698 * it will do what's needed. Else, it will take the needed 699 * action (reset the device). 700 */ 701 xfer->c_flags |= C_TIMEOU; 702 chp->ch_flags &= ~WDCF_IRQ_WAIT; 703 xfer->c_intr(chp, xfer); 704 } else 705 __wdcerror(chp, "missing untimeout"); 706 splx(s); 707 } 708 709 /* 710 * Probe drive's capabilites, for use by the controller later 711 * Assumes drvp points to an existing drive. 712 * XXX this should be a controller-indep function 713 */ 714 void 715 wdc_probe_caps(drvp) 716 struct ata_drive_datas *drvp; 717 { 718 struct ataparams params, params2; 719 struct channel_softc *chp = drvp->chnl_softc; 720 struct device *drv_dev = drvp->drv_softc; 721 struct wdc_softc *wdc = chp->wdc; 722 int i, printed; 723 char *sep = ""; 724 725 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 726 /* IDENTIFY failed. Can't tell more about the device */ 727 return; 728 } 729 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 730 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 731 /* 732 * Controller claims 16 and 32 bit transfers. 733 * Re-do an IDENTIFY with 32-bit transfers, 734 * and compare results. 735 */ 736 drvp->drive_flags |= DRIVE_CAP32; 737 ata_get_params(drvp, AT_POLL, ¶ms2); 738 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 739 /* Not good. fall back to 16bits */ 740 drvp->drive_flags &= ~DRIVE_CAP32; 741 } else { 742 printf("%s: 32-bits data port\n", drv_dev->dv_xname); 743 } 744 } 745 746 /* An ATAPI device is at last PIO mode 3 */ 747 if (drvp->drive_flags & DRIVE_ATAPI) 748 drvp->PIO_mode = 3; 749 750 /* 751 * It's not in the specs, but it seems that some drive 752 * returns 0xffff in atap_extensions when this field is invalid 753 */ 754 if (params.atap_extensions != 0xffff && 755 (params.atap_extensions & WDC_EXT_MODES)) { 756 printed = 0; 757 /* 758 * XXX some drives report something wrong here (they claim to 759 * support PIO mode 8 !). As mode is coded on 3 bits in 760 * SET FEATURE, limit it to 7 (so limit i to 4). 761 * If higther mode than 7 is found, abort. 762 */ 763 for (i = 7; i >= 0; i--) { 764 if ((params.atap_piomode_supp & (1 << i)) == 0) 765 continue; 766 if (i > 4) 767 return; 768 /* 769 * See if mode is accepted. 770 * If the controller can't set its PIO mode, 771 * assume the defaults are good, so don't try 772 * to set it 773 */ 774 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 775 if (ata_set_mode(drvp, 0x08 | (i + 3), 776 AT_POLL) != CMD_OK) 777 continue; 778 if (!printed) { 779 printf("%s: drive supports PIO mode %d", 780 drv_dev->dv_xname, i + 3); 781 sep = ","; 782 printed = 1; 783 } 784 /* 785 * If controller's driver can't set its PIO mode, 786 * get the highter one for the drive. 787 */ 788 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 789 wdc->pio_mode >= i + 3) { 790 drvp->PIO_mode = i + 3; 791 break; 792 } 793 } 794 if (!printed) { 795 /* 796 * We didn't find a valid PIO mode. 797 * Assume the values returned for DMA are buggy too 798 */ 799 return; 800 } 801 drvp->drive_flags |= DRIVE_MODE; 802 printed = 0; 803 for (i = 7; i >= 0; i--) { 804 if ((params.atap_dmamode_supp & (1 << i)) == 0) 805 continue; 806 if ((wdc->cap & WDC_CAPABILITY_DMA) && 807 (wdc->cap & WDC_CAPABILITY_MODE)) 808 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 809 != CMD_OK) 810 continue; 811 if (!printed) { 812 printf("%s DMA mode %d", sep, i); 813 sep = ","; 814 printed = 1; 815 } 816 if (wdc->cap & WDC_CAPABILITY_DMA) { 817 if ((wdc->cap & WDC_CAPABILITY_MODE) && 818 wdc->dma_mode < i) 819 continue; 820 drvp->DMA_mode = i; 821 drvp->drive_flags |= DRIVE_DMA; 822 } 823 break; 824 } 825 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 826 for (i = 7; i >= 0; i--) { 827 if ((params.atap_udmamode_supp & (1 << i)) 828 == 0) 829 continue; 830 if ((wdc->cap & WDC_CAPABILITY_MODE) && 831 (wdc->cap & WDC_CAPABILITY_UDMA)) 832 if (ata_set_mode(drvp, 0x40 | i, 833 AT_POLL) != CMD_OK) 834 continue; 835 printf("%s UDMA mode %d", sep, i); 836 sep = ","; 837 /* 838 * ATA-4 specs says if a mode is supported, 839 * all lower modes shall be supported. 840 * No need to look further. 841 */ 842 if (wdc->cap & WDC_CAPABILITY_UDMA) { 843 drvp->UDMA_mode = i; 844 drvp->drive_flags |= DRIVE_UDMA; 845 } 846 break; 847 } 848 } 849 printf("\n"); 850 } 851 } 852 853 int 854 wdc_exec_command(drvp, wdc_c) 855 struct ata_drive_datas *drvp; 856 struct wdc_command *wdc_c; 857 { 858 struct channel_softc *chp = drvp->chnl_softc; 859 struct wdc_xfer *xfer; 860 int s, ret; 861 862 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 863 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 864 DEBUG_FUNCS); 865 866 /* set up an xfer and queue. Wait for completion */ 867 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 868 WDC_NOSLEEP); 869 if (xfer == NULL) { 870 return WDC_TRY_AGAIN; 871 } 872 873 if (wdc_c->flags & AT_POLL) 874 xfer->c_flags |= C_POLL; 875 xfer->drive = drvp->drive; 876 xfer->databuf = wdc_c->data; 877 xfer->c_bcount = wdc_c->bcount; 878 xfer->cmd = wdc_c; 879 xfer->c_start = __wdccommand_start; 880 xfer->c_intr = __wdccommand_intr; 881 882 s = splbio(); 883 wdc_exec_xfer(chp, xfer); 884 #ifdef DIAGNOSTIC 885 if ((wdc_c->flags & AT_POLL) != 0 && 886 (wdc_c->flags & AT_DONE) == 0) 887 panic("wdc_exec_command: polled command not done\n"); 888 #endif 889 if (wdc_c->flags & AT_DONE) { 890 ret = WDC_COMPLETE; 891 } else { 892 if (wdc_c->flags & AT_WAIT) { 893 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 894 ret = WDC_COMPLETE; 895 } else { 896 ret = WDC_QUEUED; 897 } 898 } 899 splx(s); 900 return ret; 901 } 902 903 void 904 __wdccommand_start(chp, xfer) 905 struct channel_softc *chp; 906 struct wdc_xfer *xfer; 907 { 908 int drive = xfer->drive; 909 struct wdc_command *wdc_c = xfer->cmd; 910 911 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 912 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 913 DEBUG_FUNCS); 914 915 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 916 WDSD_IBM | (drive << 4)); 917 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 918 wdc_c->timeout) != 0) { 919 wdc_c->flags |= AT_TIMEOU; 920 __wdccommand_done(chp, xfer); 921 } 922 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 923 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 924 if ((wdc_c->flags & AT_POLL) == 0) { 925 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 926 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 927 return; 928 } 929 /* 930 * Polled command. Wait for drive ready or drq. Done in intr(). 931 * Wait for at last 400ns for status bit to be valid. 932 */ 933 delay(10); 934 if (__wdccommand_intr(chp, xfer) == 0) { 935 wdc_c->flags |= AT_TIMEOU; 936 __wdccommand_done(chp, xfer); 937 } 938 } 939 940 int 941 __wdccommand_intr(chp, xfer) 942 struct channel_softc *chp; 943 struct wdc_xfer *xfer; 944 { 945 struct wdc_command *wdc_c = xfer->cmd; 946 int bcount = wdc_c->bcount; 947 char *data = wdc_c->data; 948 949 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 950 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 951 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 952 wdc_c->timeout)) { 953 wdc_c->flags |= AT_ERROR; 954 __wdccommand_done(chp, xfer); 955 return 1; 956 } 957 if (wdc_c->flags & AT_READ) { 958 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 959 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 960 0, (u_int32_t*)data, bcount >> 2); 961 data += bcount & 0xfffffffc; 962 bcount = bcount & 0x03; 963 } 964 if (bcount > 0) 965 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 966 wd_data, (u_int16_t *)data, bcount >> 1); 967 } else if (wdc_c->flags & AT_WRITE) { 968 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 969 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 970 0, (u_int32_t*)data, bcount >> 2); 971 data += bcount & 0xfffffffc; 972 bcount = bcount & 0x03; 973 } 974 if (bcount > 0) 975 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 976 wd_data, (u_int16_t *)data, bcount >> 1); 977 } 978 __wdccommand_done(chp, xfer); 979 return 1; 980 } 981 982 void 983 __wdccommand_done(chp, xfer) 984 struct channel_softc *chp; 985 struct wdc_xfer *xfer; 986 { 987 int needdone = xfer->c_flags & C_NEEDDONE; 988 struct wdc_command *wdc_c = xfer->cmd; 989 990 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 991 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 992 if (chp->ch_status & WDCS_DWF) 993 wdc_c->flags |= AT_DF; 994 if (chp->ch_status & WDCS_ERR) { 995 wdc_c->flags |= AT_ERROR; 996 wdc_c->r_error = chp->ch_error; 997 } 998 wdc_c->flags |= AT_DONE; 999 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1000 == 0) { 1001 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1002 wd_sdh); 1003 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1004 wd_cyl_hi) << 8; 1005 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1006 wd_cyl_lo); 1007 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1008 wd_sector); 1009 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1010 wd_seccnt); 1011 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1012 wd_error); 1013 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1014 wd_precomp); 1015 } 1016 wdc_free_xfer(chp, xfer); 1017 if (needdone) { 1018 if (wdc_c->flags & AT_WAIT) 1019 wakeup(wdc_c); 1020 else 1021 wdc_c->callback(wdc_c->callback_arg); 1022 } 1023 wdcstart(chp); 1024 return; 1025 } 1026 1027 /* 1028 * Send a command. The drive should be ready. 1029 * Assumes interrupts are blocked. 1030 */ 1031 void 1032 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1033 struct channel_softc *chp; 1034 u_int8_t drive; 1035 u_int8_t command; 1036 u_int16_t cylin; 1037 u_int8_t head, sector, count, precomp; 1038 { 1039 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1040 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1041 chp->channel, drive, command, cylin, head, sector, count, precomp), 1042 DEBUG_FUNCS); 1043 1044 /* Select drive, head, and addressing mode. */ 1045 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1046 WDSD_IBM | (drive << 4) | head); 1047 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1048 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1049 precomp); 1050 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1051 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1052 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1053 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1054 1055 /* Send command. */ 1056 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1057 return; 1058 } 1059 1060 /* 1061 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1062 * tested by the caller. 1063 */ 1064 void 1065 wdccommandshort(chp, drive, command) 1066 struct channel_softc *chp; 1067 int drive; 1068 int command; 1069 { 1070 1071 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1072 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1073 DEBUG_FUNCS); 1074 1075 /* Select drive. */ 1076 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1077 WDSD_IBM | (drive << 4)); 1078 1079 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1080 } 1081 1082 /* Add a command to the queue and start controller. Must be called at splbio */ 1083 1084 void 1085 wdc_exec_xfer(chp, xfer) 1086 struct channel_softc *chp; 1087 struct wdc_xfer *xfer; 1088 { 1089 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1090 chp->channel, xfer->drive), DEBUG_XFERS); 1091 1092 /* complete xfer setup */ 1093 xfer->channel = chp->channel; 1094 1095 /* 1096 * If we are a polled command, and the list is not empty, 1097 * we are doing a dump. Drop the list to allow the polled command 1098 * to complete, we're going to reboot soon anyway. 1099 */ 1100 if ((xfer->c_flags & C_POLL) != 0 && 1101 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1102 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1103 } 1104 /* insert at the end of command list */ 1105 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1106 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1107 chp->ch_flags), DEBUG_XFERS); 1108 wdcstart(chp); 1109 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1110 } 1111 1112 struct wdc_xfer * 1113 wdc_get_xfer(flags) 1114 int flags; 1115 { 1116 struct wdc_xfer *xfer; 1117 int s; 1118 1119 s = splbio(); 1120 if ((xfer = xfer_free_list.lh_first) != NULL) { 1121 LIST_REMOVE(xfer, free_list); 1122 splx(s); 1123 #ifdef DIAGNOSTIC 1124 if ((xfer->c_flags & C_INUSE) != 0) 1125 panic("wdc_get_xfer: xfer already in use\n"); 1126 #endif 1127 } else { 1128 splx(s); 1129 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1130 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1131 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1132 if (xfer == NULL) 1133 return 0; 1134 #ifdef DIAGNOSTIC 1135 xfer->c_flags &= ~C_INUSE; 1136 #endif 1137 #ifdef WDCDEBUG 1138 wdc_nxfer++; 1139 #endif 1140 } 1141 #ifdef DIAGNOSTIC 1142 if ((xfer->c_flags & C_INUSE) != 0) 1143 panic("wdc_get_xfer: xfer already in use\n"); 1144 #endif 1145 memset(xfer, 0, sizeof(struct wdc_xfer)); 1146 xfer->c_flags = C_INUSE; 1147 return xfer; 1148 } 1149 1150 void 1151 wdc_free_xfer(chp, xfer) 1152 struct channel_softc *chp; 1153 struct wdc_xfer *xfer; 1154 { 1155 struct wdc_softc *wdc = chp->wdc; 1156 int s; 1157 1158 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1159 (*wdc->free_hw)(chp); 1160 s = splbio(); 1161 chp->ch_flags &= ~WDCF_ACTIVE; 1162 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1163 xfer->c_flags &= ~C_INUSE; 1164 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1165 splx(s); 1166 } 1167 1168 static void 1169 __wdcerror(chp, msg) 1170 struct channel_softc *chp; 1171 char *msg; 1172 { 1173 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1174 if (xfer == NULL) 1175 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1176 msg); 1177 else 1178 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1179 xfer->channel, xfer->drive, msg); 1180 } 1181 1182 /* 1183 * the bit bucket 1184 */ 1185 void 1186 wdcbit_bucket(chp, size) 1187 struct channel_softc *chp; 1188 int size; 1189 { 1190 1191 for (; size >= 2; size -= 2) 1192 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1193 if (size) 1194 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1195 } 1196 1197 int 1198 wdc_addref(chp) 1199 struct channel_softc *chp; 1200 { 1201 struct wdc_softc *wdc = chp->wdc; 1202 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1203 int s, error = 0; 1204 1205 s = splbio(); 1206 if (adapter->scsipi_refcnt++ == 0 && 1207 adapter->scsipi_enable != NULL) { 1208 error = (*adapter->scsipi_enable)(wdc, 1); 1209 if (error) 1210 adapter->scsipi_refcnt--; 1211 } 1212 splx(s); 1213 return (error); 1214 } 1215 1216 void 1217 wdc_delref(chp) 1218 struct channel_softc *chp; 1219 { 1220 struct wdc_softc *wdc = chp->wdc; 1221 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1222 int s; 1223 1224 s = splbio(); 1225 if (adapter->scsipi_refcnt-- == 1 && 1226 adapter->scsipi_enable != NULL) 1227 (void) (*adapter->scsipi_enable)(wdc, 0); 1228 splx(s); 1229 } 1230
Indexes created Tue Sep 23 07:09:52 GMT 2025