wdc.c revision 1.47
1 /* $NetBSD: wdc.c,v 1.47 1998/11/29 17:34:49 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(1); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(1); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff) 200 ret_value &= ~0x01; 201 if (st1 == 0xff) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(1); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(1); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices , then rescan and try an ATA command, in case it's an 233 * old drive. 234 * Fill in drive_flags accordingly 235 */ 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 240 WDSD_IBM | (drive << 4)); 241 delay(1); 242 /* Save registers contents */ 243 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 244 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 245 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 246 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 247 248 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 249 "cl=0x%x ch=0x%x\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 251 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 252 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 253 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 254 } 255 } 256 for (drive = 0; drive < 2; drive++) { 257 if ((ret_value & (0x01 << drive)) == 0 || 258 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 259 continue; 260 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 261 WDSD_IBM | (drive << 4)); 262 delay(1); 263 /* 264 * Maybe it's an old device, so don't rely on ATA sig. 265 * Test registers writability (Error register not writable, 266 * but cyllo is), then try an ATA command. 267 */ 268 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 269 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 270 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 271 0x58 || 272 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 273 0xa5) { 274 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 275 "failed\n", 276 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 277 chp->channel, drive), DEBUG_PROBE); 278 ret_value &= ~(0x01 << drive); 279 continue; 280 } 281 if (wait_for_ready(chp, 10000) != 0) { 282 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 283 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 284 chp->channel, drive), DEBUG_PROBE); 285 ret_value &= ~(0x01 << drive); 286 continue; 287 } 288 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 289 WDCC_DIAGNOSE); 290 if (wait_for_ready(chp, 10000) == 0) { 291 chp->ch_drive[drive].drive_flags |= 292 DRIVE_ATA; 293 } else { 294 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 295 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 296 chp->channel, drive), DEBUG_PROBE); 297 ret_value &= ~(0x01 << drive); 298 } 299 } 300 return (ret_value); 301 } 302 303 void 304 wdcattach(chp) 305 struct channel_softc *chp; 306 { 307 int channel_flags, ctrl_flags, i, error; 308 struct ata_atapi_attach aa_link; 309 310 LIST_INIT(&xfer_free_list); 311 for (i = 0; i < 2; i++) { 312 chp->ch_drive[i].chnl_softc = chp; 313 chp->ch_drive[i].drive = i; 314 /* If controller can't do 16bit flag the drives as 32bit */ 315 if ((chp->wdc->cap & 316 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 317 WDC_CAPABILITY_DATA32) 318 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 319 } 320 321 if ((error = wdc_addref(chp)) != 0) { 322 printf("%s: unable to enable controller\n", 323 chp->wdc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (wdcprobe(chp) == 0) { 328 /* If no drives, abort attach here. */ 329 wdc_delref(chp); 330 return; 331 } 332 333 TAILQ_INIT(&chp->ch_queue->sc_xfer); 334 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 335 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 336 337 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 338 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 339 DEBUG_PROBE); 340 341 /* 342 * Attach an ATAPI bus, if needed. 343 */ 344 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 345 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 346 #if NATAPIBUS > 0 347 wdc_atapibus_attach(chp); 348 #else 349 /* 350 * Fills in a fake aa_link and call config_found, so that 351 * the config machinery will print 352 * "atapibus at xxx not configured" 353 */ 354 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 355 aa_link.aa_type = T_ATAPI; 356 aa_link.aa_channel = chp->channel; 357 aa_link.aa_openings = 1; 358 aa_link.aa_drv_data = 0; 359 aa_link.aa_bus_private = NULL; 360 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 361 atapi_print); 362 #endif 363 } 364 365 for (i = 0; i < 2; i++) { 366 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 367 continue; 368 } 369 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 370 aa_link.aa_type = T_ATA; 371 aa_link.aa_channel = chp->channel; 372 aa_link.aa_openings = 1; 373 aa_link.aa_drv_data = &chp->ch_drive[i]; 374 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 375 wdc_probe_caps(&chp->ch_drive[i]); 376 } 377 378 /* 379 * reset drive_flags for unnatached devices, reset state for attached 380 * ones 381 */ 382 for (i = 0; i < 2; i++) { 383 if (chp->ch_drive[i].drv_softc == NULL) 384 chp->ch_drive[i].drive_flags = 0; 385 else 386 chp->ch_drive[i].state = 0; 387 } 388 389 /* 390 * Reset channel. The probe, with some combinations of ATA/ATAPI 391 * devices keep it in a mostly working, but strange state (with busy 392 * led on) 393 */ 394 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 395 wdcreset(chp, VERBOSE); 396 /* 397 * Read status registers to avoid spurious interrupts. 398 */ 399 for (i = 1; i >= 0; i--) { 400 if (chp->ch_drive[i].drive_flags & DRIVE) { 401 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 402 wd_sdh, WDSD_IBM | (i << 4)); 403 if (wait_for_unbusy(chp, 10000) < 0) 404 printf("%s:%d:%d: device busy\n", 405 chp->wdc->sc_dev.dv_xname, 406 chp->channel, i); 407 } 408 } 409 } 410 wdc_delref(chp); 411 } 412 413 /* 414 * Start I/O on a controller, for the given channel. 415 * The first xfer may be not for our channel if the channel queues 416 * are shared. 417 */ 418 void 419 wdcstart(chp) 420 struct channel_softc *chp; 421 { 422 struct wdc_xfer *xfer; 423 struct wdc_softc *wdc = chp->wdc; 424 425 #ifdef WDC_DIAGNOSTIC 426 int spl1, spl2; 427 428 spl1 = splbio(); 429 spl2 = splbio(); 430 if (spl2 != spl1) { 431 printf("wdcstart: not at splbio()\n"); 432 panic("wdcstart"); 433 } 434 splx(spl2); 435 splx(spl1); 436 #endif /* WDC_DIAGNOSTIC */ 437 438 /* is there a xfer ? */ 439 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 440 return; 441 442 /* adjust chp, in case we have a shared queue */ 443 chp = wdc->channels[xfer->channel]; 444 445 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 446 return; /* channel aleady active */ 447 } 448 #ifdef DIAGNOSTIC 449 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 450 panic("wdcstart: channel waiting for irq\n"); 451 #endif 452 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 453 if (!(*chp->wdc->claim_hw)(chp, 0)) 454 return; 455 456 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 457 xfer->channel, xfer->drive), DEBUG_XFERS); 458 chp->ch_flags |= WDCF_ACTIVE; 459 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 460 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 461 chp->ch_drive[xfer->drive].state = 0; 462 } 463 xfer->c_start(chp, xfer); 464 } 465 466 /* restart an interrupted I/O */ 467 void 468 wdcrestart(v) 469 void *v; 470 { 471 struct channel_softc *chp = v; 472 int s; 473 474 s = splbio(); 475 wdcstart(chp); 476 splx(s); 477 } 478 479 480 /* 481 * Interrupt routine for the controller. Acknowledge the interrupt, check for 482 * errors on the current operation, mark it done if necessary, and start the 483 * next request. Also check for a partially done transfer, and continue with 484 * the next chunk if so. 485 */ 486 int 487 wdcintr(arg) 488 void *arg; 489 { 490 struct channel_softc *chp = arg; 491 struct wdc_xfer *xfer; 492 493 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 494 #if 0 495 /* Clear the pending interrupt and abort. */ 496 u_int8_t s = 497 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 498 #ifdef WDCDEBUG 499 u_int8_t e = 500 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 501 u_int8_t i = 502 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 503 #else 504 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 505 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 506 #endif 507 508 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 509 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 510 511 if (s & WDCS_DRQ) { 512 int len; 513 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 514 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 515 chp->cmd_ioh, wd_cyl_hi); 516 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 517 len), DEBUG_INTR); 518 wdcbit_bucket (chp, len); 519 } 520 #else 521 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 522 #endif 523 return 0; 524 } 525 526 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 527 untimeout(wdctimeout, chp); 528 chp->ch_flags &= ~WDCF_IRQ_WAIT; 529 xfer = chp->ch_queue->sc_xfer.tqh_first; 530 return xfer->c_intr(chp, xfer); 531 } 532 533 /* Put all disk in RESET state */ 534 void wdc_reset_channel(drvp) 535 struct ata_drive_datas *drvp; 536 { 537 struct channel_softc *chp = drvp->chnl_softc; 538 int drive; 539 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 540 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 541 DEBUG_FUNCS); 542 (void) wdcreset(chp, VERBOSE); 543 for (drive = 0; drive < 2; drive++) { 544 chp->ch_drive[drive].state = 0; 545 } 546 } 547 548 int 549 wdcreset(chp, verb) 550 struct channel_softc *chp; 551 int verb; 552 { 553 int drv_mask1, drv_mask2; 554 555 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 556 WDSD_IBM); /* master */ 557 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 558 WDCTL_RST | WDCTL_IDS); 559 delay(1000); 560 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 561 WDCTL_IDS); 562 delay(1000); 563 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 564 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 565 WDCTL_4BIT); 566 567 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 568 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 569 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 570 if (verb && drv_mask2 != drv_mask1) { 571 printf("%s channel %d: reset failed for", 572 chp->wdc->sc_dev.dv_xname, chp->channel); 573 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 574 printf(" drive 0"); 575 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 576 printf(" drive 1"); 577 printf("\n"); 578 } 579 return (drv_mask1 != drv_mask2) ? 1 : 0; 580 } 581 582 static int 583 __wdcwait_reset(chp, drv_mask) 584 struct channel_softc *chp; 585 int drv_mask; 586 { 587 int timeout; 588 u_int8_t st0, st1; 589 /* wait for BSY to deassert */ 590 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 591 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 592 WDSD_IBM); /* master */ 593 delay(1); 594 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 595 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 596 WDSD_IBM | 0x10); /* slave */ 597 delay(1); 598 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 599 600 if ((drv_mask & 0x01) == 0) { 601 /* no master */ 602 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 603 /* No master, slave is ready, it's done */ 604 return drv_mask; 605 } 606 } else if ((drv_mask & 0x02) == 0) { 607 /* no slave */ 608 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 609 /* No slave, master is ready, it's done */ 610 return drv_mask; 611 } 612 } else { 613 /* Wait for both master and slave to be ready */ 614 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 615 return drv_mask; 616 } 617 } 618 delay(WDCDELAY); 619 } 620 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 621 if (st0 & WDCS_BSY) 622 drv_mask &= ~0x01; 623 if (st1 & WDCS_BSY) 624 drv_mask &= ~0x02; 625 return drv_mask; 626 } 627 628 /* 629 * Wait for a drive to be !BSY, and have mask in its status register. 630 * return -1 for a timeout after "timeout" ms. 631 */ 632 int 633 wdcwait(chp, mask, bits, timeout) 634 struct channel_softc *chp; 635 int mask, bits, timeout; 636 { 637 u_char status; 638 int time = 0; 639 #ifdef WDCNDELAY_DEBUG 640 extern int cold; 641 #endif 642 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 643 chp->channel), DEBUG_STATUS); 644 chp->ch_error = 0; 645 646 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 647 648 for (;;) { 649 chp->ch_status = status = 650 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 651 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 652 break; 653 if (++time > timeout) { 654 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 655 "error %x\n", status, 656 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 657 wd_error)), 658 DEBUG_STATUS); 659 return -1; 660 } 661 delay(WDCDELAY); 662 } 663 if (status & WDCS_ERR) 664 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 665 wd_error); 666 #ifdef WDCNDELAY_DEBUG 667 /* After autoconfig, there should be no long delays. */ 668 if (!cold && time > WDCNDELAY_DEBUG) { 669 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 670 if (xfer == NULL) 671 printf("%s channel %d: warning: busy-wait took %dus\n", 672 chp->wdc->sc_dev.dv_xname, chp->channel, 673 WDCDELAY * time); 674 else 675 printf("%s:%d:%d: warning: busy-wait took %dus\n", 676 chp->wdc->sc_dev.dv_xname, xfer->channel, 677 xfer->drive, 678 WDCDELAY * time); 679 } 680 #endif 681 return 0; 682 } 683 684 void 685 wdctimeout(arg) 686 void *arg; 687 { 688 struct channel_softc *chp = (struct channel_softc *)arg; 689 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 690 int s; 691 692 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 693 694 s = splbio(); 695 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 696 __wdcerror(chp, "lost interrupt"); 697 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 698 "atapi":"ata"); 699 printf("\tc_bcount: %d\n", xfer->c_bcount); 700 printf("\tc_skip: %d\n", xfer->c_skip); 701 /* 702 * Call the interrupt routine. If we just missed and interrupt, 703 * it will do what's needed. Else, it will take the needed 704 * action (reset the device). 705 */ 706 xfer->c_flags |= C_TIMEOU; 707 chp->ch_flags &= ~WDCF_IRQ_WAIT; 708 xfer->c_intr(chp, xfer); 709 } else 710 __wdcerror(chp, "missing untimeout"); 711 splx(s); 712 } 713 714 /* 715 * Probe drive's capabilites, for use by the controller later 716 * Assumes drvp points to an existing drive. 717 * XXX this should be a controller-indep function 718 */ 719 void 720 wdc_probe_caps(drvp) 721 struct ata_drive_datas *drvp; 722 { 723 struct ataparams params, params2; 724 struct channel_softc *chp = drvp->chnl_softc; 725 struct device *drv_dev = drvp->drv_softc; 726 struct wdc_softc *wdc = chp->wdc; 727 int i, printed; 728 char *sep = ""; 729 730 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 731 /* IDENTIFY failed. Can't tell more about the device */ 732 return; 733 } 734 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 735 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 736 /* 737 * Controller claims 16 and 32 bit transfers. 738 * Re-do an IDENTIFY with 32-bit transfers, 739 * and compare results. 740 */ 741 drvp->drive_flags |= DRIVE_CAP32; 742 ata_get_params(drvp, AT_POLL, ¶ms2); 743 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 744 /* Not good. fall back to 16bits */ 745 drvp->drive_flags &= ~DRIVE_CAP32; 746 } else { 747 printf("%s: 32-bits data port\n", drv_dev->dv_xname); 748 } 749 } 750 751 /* An ATAPI device is at last PIO mode 3 */ 752 if (drvp->drive_flags & DRIVE_ATAPI) 753 drvp->PIO_mode = 3; 754 755 /* 756 * It's not in the specs, but it seems that some drive 757 * returns 0xffff in atap_extensions when this field is invalid 758 */ 759 if (params.atap_extensions != 0xffff && 760 (params.atap_extensions & WDC_EXT_MODES)) { 761 printed = 0; 762 /* 763 * XXX some drives report something wrong here (they claim to 764 * support PIO mode 8 !). As mode is coded on 3 bits in 765 * SET FEATURE, limit it to 7 (so limit i to 4). 766 * If higther mode than 7 is found, abort. 767 */ 768 for (i = 7; i >= 0; i--) { 769 if ((params.atap_piomode_supp & (1 << i)) == 0) 770 continue; 771 if (i > 4) 772 return; 773 /* 774 * See if mode is accepted. 775 * If the controller can't set its PIO mode, 776 * assume the defaults are good, so don't try 777 * to set it 778 */ 779 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 780 if (ata_set_mode(drvp, 0x08 | (i + 3), 781 AT_POLL) != CMD_OK) 782 continue; 783 if (!printed) { 784 printf("%s: drive supports PIO mode %d", 785 drv_dev->dv_xname, i + 3); 786 sep = ","; 787 printed = 1; 788 } 789 /* 790 * If controller's driver can't set its PIO mode, 791 * get the highter one for the drive. 792 */ 793 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 794 wdc->pio_mode >= i + 3) { 795 drvp->PIO_mode = i + 3; 796 break; 797 } 798 } 799 if (!printed) { 800 /* 801 * We didn't find a valid PIO mode. 802 * Assume the values returned for DMA are buggy too 803 */ 804 return; 805 } 806 drvp->drive_flags |= DRIVE_MODE; 807 printed = 0; 808 for (i = 7; i >= 0; i--) { 809 if ((params.atap_dmamode_supp & (1 << i)) == 0) 810 continue; 811 if ((wdc->cap & WDC_CAPABILITY_DMA) && 812 (wdc->cap & WDC_CAPABILITY_MODE)) 813 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 814 != CMD_OK) 815 continue; 816 if (!printed) { 817 printf("%s DMA mode %d", sep, i); 818 sep = ","; 819 printed = 1; 820 } 821 if (wdc->cap & WDC_CAPABILITY_DMA) { 822 if ((wdc->cap & WDC_CAPABILITY_MODE) && 823 wdc->dma_mode < i) 824 continue; 825 drvp->DMA_mode = i; 826 drvp->drive_flags |= DRIVE_DMA; 827 } 828 break; 829 } 830 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 831 for (i = 7; i >= 0; i--) { 832 if ((params.atap_udmamode_supp & (1 << i)) 833 == 0) 834 continue; 835 if ((wdc->cap & WDC_CAPABILITY_MODE) && 836 (wdc->cap & WDC_CAPABILITY_UDMA)) 837 if (ata_set_mode(drvp, 0x40 | i, 838 AT_POLL) != CMD_OK) 839 continue; 840 printf("%s UDMA mode %d", sep, i); 841 sep = ","; 842 /* 843 * ATA-4 specs says if a mode is supported, 844 * all lower modes shall be supported. 845 * No need to look further. 846 */ 847 if (wdc->cap & WDC_CAPABILITY_UDMA) { 848 drvp->UDMA_mode = i; 849 drvp->drive_flags |= DRIVE_UDMA; 850 } 851 break; 852 } 853 } 854 printf("\n"); 855 } 856 } 857 858 int 859 wdc_exec_command(drvp, wdc_c) 860 struct ata_drive_datas *drvp; 861 struct wdc_command *wdc_c; 862 { 863 struct channel_softc *chp = drvp->chnl_softc; 864 struct wdc_xfer *xfer; 865 int s, ret; 866 867 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 868 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 869 DEBUG_FUNCS); 870 871 /* set up an xfer and queue. Wait for completion */ 872 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 873 WDC_NOSLEEP); 874 if (xfer == NULL) { 875 return WDC_TRY_AGAIN; 876 } 877 878 if (wdc_c->flags & AT_POLL) 879 xfer->c_flags |= C_POLL; 880 xfer->drive = drvp->drive; 881 xfer->databuf = wdc_c->data; 882 xfer->c_bcount = wdc_c->bcount; 883 xfer->cmd = wdc_c; 884 xfer->c_start = __wdccommand_start; 885 xfer->c_intr = __wdccommand_intr; 886 887 s = splbio(); 888 wdc_exec_xfer(chp, xfer); 889 #ifdef DIAGNOSTIC 890 if ((wdc_c->flags & AT_POLL) != 0 && 891 (wdc_c->flags & AT_DONE) == 0) 892 panic("wdc_exec_command: polled command not done\n"); 893 #endif 894 if (wdc_c->flags & AT_DONE) { 895 ret = WDC_COMPLETE; 896 } else { 897 if (wdc_c->flags & AT_WAIT) { 898 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 899 ret = WDC_COMPLETE; 900 } else { 901 ret = WDC_QUEUED; 902 } 903 } 904 splx(s); 905 return ret; 906 } 907 908 void 909 __wdccommand_start(chp, xfer) 910 struct channel_softc *chp; 911 struct wdc_xfer *xfer; 912 { 913 int drive = xfer->drive; 914 struct wdc_command *wdc_c = xfer->cmd; 915 916 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 917 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 918 DEBUG_FUNCS); 919 920 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 921 WDSD_IBM | (drive << 4)); 922 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 923 wdc_c->timeout) != 0) { 924 wdc_c->flags |= AT_TIMEOU; 925 __wdccommand_done(chp, xfer); 926 } 927 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 928 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 929 if ((wdc_c->flags & AT_POLL) == 0) { 930 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 931 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 932 return; 933 } 934 /* 935 * Polled command. Wait for drive ready or drq. Done in intr(). 936 * Wait for at last 400ns for status bit to be valid. 937 */ 938 delay(10); 939 if (__wdccommand_intr(chp, xfer) == 0) { 940 wdc_c->flags |= AT_TIMEOU; 941 __wdccommand_done(chp, xfer); 942 } 943 } 944 945 int 946 __wdccommand_intr(chp, xfer) 947 struct channel_softc *chp; 948 struct wdc_xfer *xfer; 949 { 950 struct wdc_command *wdc_c = xfer->cmd; 951 int bcount = wdc_c->bcount; 952 char *data = wdc_c->data; 953 954 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 955 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 956 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 957 wdc_c->timeout)) { 958 wdc_c->flags |= AT_ERROR; 959 __wdccommand_done(chp, xfer); 960 return 1; 961 } 962 if (wdc_c->flags & AT_READ) { 963 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 964 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 965 0, (u_int32_t*)data, bcount >> 2); 966 data += bcount & 0xfffffffc; 967 bcount = bcount & 0x03; 968 } 969 if (bcount > 0) 970 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 971 wd_data, (u_int16_t *)data, bcount >> 1); 972 } else if (wdc_c->flags & AT_WRITE) { 973 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 974 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 975 0, (u_int32_t*)data, bcount >> 2); 976 data += bcount & 0xfffffffc; 977 bcount = bcount & 0x03; 978 } 979 if (bcount > 0) 980 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 981 wd_data, (u_int16_t *)data, bcount >> 1); 982 } 983 __wdccommand_done(chp, xfer); 984 return 1; 985 } 986 987 void 988 __wdccommand_done(chp, xfer) 989 struct channel_softc *chp; 990 struct wdc_xfer *xfer; 991 { 992 int needdone = xfer->c_flags & C_NEEDDONE; 993 struct wdc_command *wdc_c = xfer->cmd; 994 995 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 996 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 997 if (chp->ch_status & WDCS_DWF) 998 wdc_c->flags |= AT_DF; 999 if (chp->ch_status & WDCS_ERR) { 1000 wdc_c->flags |= AT_ERROR; 1001 wdc_c->r_error = chp->ch_error; 1002 } 1003 wdc_c->flags |= AT_DONE; 1004 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1005 == 0) { 1006 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1007 wd_sdh); 1008 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1009 wd_cyl_hi) << 8; 1010 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1011 wd_cyl_lo); 1012 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1013 wd_sector); 1014 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1015 wd_seccnt); 1016 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1017 wd_error); 1018 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1019 wd_precomp); 1020 } 1021 wdc_free_xfer(chp, xfer); 1022 if (needdone) { 1023 if (wdc_c->flags & AT_WAIT) 1024 wakeup(wdc_c); 1025 else 1026 wdc_c->callback(wdc_c->callback_arg); 1027 } 1028 wdcstart(chp); 1029 return; 1030 } 1031 1032 /* 1033 * Send a command. The drive should be ready. 1034 * Assumes interrupts are blocked. 1035 */ 1036 void 1037 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1038 struct channel_softc *chp; 1039 u_int8_t drive; 1040 u_int8_t command; 1041 u_int16_t cylin; 1042 u_int8_t head, sector, count, precomp; 1043 { 1044 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1045 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1046 chp->channel, drive, command, cylin, head, sector, count, precomp), 1047 DEBUG_FUNCS); 1048 1049 /* Select drive, head, and addressing mode. */ 1050 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1051 WDSD_IBM | (drive << 4) | head); 1052 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1053 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1054 precomp); 1055 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1056 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1057 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1058 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1059 1060 /* Send command. */ 1061 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1062 return; 1063 } 1064 1065 /* 1066 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1067 * tested by the caller. 1068 */ 1069 void 1070 wdccommandshort(chp, drive, command) 1071 struct channel_softc *chp; 1072 int drive; 1073 int command; 1074 { 1075 1076 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1077 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1078 DEBUG_FUNCS); 1079 1080 /* Select drive. */ 1081 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1082 WDSD_IBM | (drive << 4)); 1083 1084 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1085 } 1086 1087 /* Add a command to the queue and start controller. Must be called at splbio */ 1088 1089 void 1090 wdc_exec_xfer(chp, xfer) 1091 struct channel_softc *chp; 1092 struct wdc_xfer *xfer; 1093 { 1094 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1095 chp->channel, xfer->drive), DEBUG_XFERS); 1096 1097 /* complete xfer setup */ 1098 xfer->channel = chp->channel; 1099 1100 /* 1101 * If we are a polled command, and the list is not empty, 1102 * we are doing a dump. Drop the list to allow the polled command 1103 * to complete, we're going to reboot soon anyway. 1104 */ 1105 if ((xfer->c_flags & C_POLL) != 0 && 1106 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1107 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1108 } 1109 /* insert at the end of command list */ 1110 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1111 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1112 chp->ch_flags), DEBUG_XFERS); 1113 wdcstart(chp); 1114 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1115 } 1116 1117 struct wdc_xfer * 1118 wdc_get_xfer(flags) 1119 int flags; 1120 { 1121 struct wdc_xfer *xfer; 1122 int s; 1123 1124 s = splbio(); 1125 if ((xfer = xfer_free_list.lh_first) != NULL) { 1126 LIST_REMOVE(xfer, free_list); 1127 splx(s); 1128 #ifdef DIAGNOSTIC 1129 if ((xfer->c_flags & C_INUSE) != 0) 1130 panic("wdc_get_xfer: xfer already in use\n"); 1131 #endif 1132 } else { 1133 splx(s); 1134 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1135 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1136 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1137 if (xfer == NULL) 1138 return 0; 1139 #ifdef DIAGNOSTIC 1140 xfer->c_flags &= ~C_INUSE; 1141 #endif 1142 #ifdef WDCDEBUG 1143 wdc_nxfer++; 1144 #endif 1145 } 1146 #ifdef DIAGNOSTIC 1147 if ((xfer->c_flags & C_INUSE) != 0) 1148 panic("wdc_get_xfer: xfer already in use\n"); 1149 #endif 1150 memset(xfer, 0, sizeof(struct wdc_xfer)); 1151 xfer->c_flags = C_INUSE; 1152 return xfer; 1153 } 1154 1155 void 1156 wdc_free_xfer(chp, xfer) 1157 struct channel_softc *chp; 1158 struct wdc_xfer *xfer; 1159 { 1160 struct wdc_softc *wdc = chp->wdc; 1161 int s; 1162 1163 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1164 (*wdc->free_hw)(chp); 1165 s = splbio(); 1166 chp->ch_flags &= ~WDCF_ACTIVE; 1167 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1168 xfer->c_flags &= ~C_INUSE; 1169 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1170 splx(s); 1171 } 1172 1173 static void 1174 __wdcerror(chp, msg) 1175 struct channel_softc *chp; 1176 char *msg; 1177 { 1178 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1179 if (xfer == NULL) 1180 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1181 msg); 1182 else 1183 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1184 xfer->channel, xfer->drive, msg); 1185 } 1186 1187 /* 1188 * the bit bucket 1189 */ 1190 void 1191 wdcbit_bucket(chp, size) 1192 struct channel_softc *chp; 1193 int size; 1194 { 1195 1196 for (; size >= 2; size -= 2) 1197 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1198 if (size) 1199 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1200 } 1201 1202 int 1203 wdc_addref(chp) 1204 struct channel_softc *chp; 1205 { 1206 struct wdc_softc *wdc = chp->wdc; 1207 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1208 int s, error = 0; 1209 1210 s = splbio(); 1211 if (adapter->scsipi_refcnt++ == 0 && 1212 adapter->scsipi_enable != NULL) { 1213 error = (*adapter->scsipi_enable)(wdc, 1); 1214 if (error) 1215 adapter->scsipi_refcnt--; 1216 } 1217 splx(s); 1218 return (error); 1219 } 1220 1221 void 1222 wdc_delref(chp) 1223 struct channel_softc *chp; 1224 { 1225 struct wdc_softc *wdc = chp->wdc; 1226 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1227 int s; 1228 1229 s = splbio(); 1230 if (adapter->scsipi_refcnt-- == 1 && 1231 adapter->scsipi_enable != NULL) 1232 (void) (*adapter->scsipi_enable)(wdc, 0); 1233 splx(s); 1234 } 1235
Indexes created Thu Sep 25 06:09:39 GMT 2025