wdc.c revision 1.56
1 /* $NetBSD: wdc.c,v 1.56 1999/02/08 15:22:28 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(1); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(1); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff) 200 ret_value &= ~0x01; 201 if (st1 == 0xff) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(1); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(1); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices , then rescan and try an ATA command, in case it's an 233 * old drive. 234 * Fill in drive_flags accordingly 235 */ 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 240 WDSD_IBM | (drive << 4)); 241 delay(1); 242 /* Save registers contents */ 243 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 244 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 245 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 246 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 247 248 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 249 "cl=0x%x ch=0x%x\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 251 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 252 if (sc == 0x01 && sn == 0x01 && cl == 0x14 && ch == 0xeb) { 253 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 254 } 255 } 256 for (drive = 0; drive < 2; drive++) { 257 if ((ret_value & (0x01 << drive)) == 0 || 258 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 259 continue; 260 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 261 WDSD_IBM | (drive << 4)); 262 delay(1); 263 /* 264 * Maybe it's an old device, so don't rely on ATA sig. 265 * Test registers writability (Error register not writable, 266 * but cyllo is), then try an ATA command. 267 */ 268 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 269 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 270 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 271 0x58 || 272 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 273 0xa5) { 274 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 275 "failed\n", 276 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 277 chp->channel, drive), DEBUG_PROBE); 278 ret_value &= ~(0x01 << drive); 279 continue; 280 } 281 if (wait_for_ready(chp, 10000) != 0) { 282 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 283 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 284 chp->channel, drive), DEBUG_PROBE); 285 ret_value &= ~(0x01 << drive); 286 continue; 287 } 288 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 289 WDCC_DIAGNOSE); 290 if (wait_for_ready(chp, 10000) == 0) { 291 chp->ch_drive[drive].drive_flags |= 292 DRIVE_ATA; 293 } else { 294 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 295 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 296 chp->channel, drive), DEBUG_PROBE); 297 ret_value &= ~(0x01 << drive); 298 } 299 } 300 return (ret_value); 301 } 302 303 void 304 wdcattach(chp) 305 struct channel_softc *chp; 306 { 307 int channel_flags, ctrl_flags, i, error; 308 struct ata_atapi_attach aa_link; 309 310 LIST_INIT(&xfer_free_list); 311 for (i = 0; i < 2; i++) { 312 chp->ch_drive[i].chnl_softc = chp; 313 chp->ch_drive[i].drive = i; 314 /* If controller can't do 16bit flag the drives as 32bit */ 315 if ((chp->wdc->cap & 316 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 317 WDC_CAPABILITY_DATA32) 318 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 319 } 320 321 if ((error = wdc_addref(chp)) != 0) { 322 printf("%s: unable to enable controller\n", 323 chp->wdc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (wdcprobe(chp) == 0) { 328 /* If no drives, abort attach here. */ 329 wdc_delref(chp); 330 return; 331 } 332 333 TAILQ_INIT(&chp->ch_queue->sc_xfer); 334 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 335 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 336 337 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 338 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 339 DEBUG_PROBE); 340 341 /* 342 * Attach an ATAPI bus, if needed. 343 */ 344 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 345 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 346 #if NATAPIBUS > 0 347 wdc_atapibus_attach(chp); 348 #else 349 /* 350 * Fills in a fake aa_link and call config_found, so that 351 * the config machinery will print 352 * "atapibus at xxx not configured" 353 */ 354 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 355 aa_link.aa_type = T_ATAPI; 356 aa_link.aa_channel = chp->channel; 357 aa_link.aa_openings = 1; 358 aa_link.aa_drv_data = 0; 359 aa_link.aa_bus_private = NULL; 360 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 361 atapi_print); 362 #endif 363 } 364 365 for (i = 0; i < 2; i++) { 366 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 367 continue; 368 } 369 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 370 aa_link.aa_type = T_ATA; 371 aa_link.aa_channel = chp->channel; 372 aa_link.aa_openings = 1; 373 aa_link.aa_drv_data = &chp->ch_drive[i]; 374 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 375 wdc_probe_caps(&chp->ch_drive[i]); 376 } 377 378 /* 379 * reset drive_flags for unnatached devices, reset state for attached 380 * ones 381 */ 382 for (i = 0; i < 2; i++) { 383 if (chp->ch_drive[i].drv_softc == NULL) 384 chp->ch_drive[i].drive_flags = 0; 385 else 386 chp->ch_drive[i].state = 0; 387 } 388 389 /* 390 * Reset channel. The probe, with some combinations of ATA/ATAPI 391 * devices keep it in a mostly working, but strange state (with busy 392 * led on) 393 */ 394 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 395 wdcreset(chp, VERBOSE); 396 /* 397 * Read status registers to avoid spurious interrupts. 398 */ 399 for (i = 1; i >= 0; i--) { 400 if (chp->ch_drive[i].drive_flags & DRIVE) { 401 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 402 wd_sdh, WDSD_IBM | (i << 4)); 403 if (wait_for_unbusy(chp, 10000) < 0) 404 printf("%s:%d:%d: device busy\n", 405 chp->wdc->sc_dev.dv_xname, 406 chp->channel, i); 407 } 408 } 409 } 410 wdc_delref(chp); 411 } 412 413 /* 414 * Start I/O on a controller, for the given channel. 415 * The first xfer may be not for our channel if the channel queues 416 * are shared. 417 */ 418 void 419 wdcstart(chp) 420 struct channel_softc *chp; 421 { 422 struct wdc_xfer *xfer; 423 424 #ifdef WDC_DIAGNOSTIC 425 int spl1, spl2; 426 427 spl1 = splbio(); 428 spl2 = splbio(); 429 if (spl2 != spl1) { 430 printf("wdcstart: not at splbio()\n"); 431 panic("wdcstart"); 432 } 433 splx(spl2); 434 splx(spl1); 435 #endif /* WDC_DIAGNOSTIC */ 436 437 /* is there a xfer ? */ 438 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 439 return; 440 441 /* adjust chp, in case we have a shared queue */ 442 chp = xfer->chp; 443 444 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 445 return; /* channel aleady active */ 446 } 447 #ifdef DIAGNOSTIC 448 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 449 panic("wdcstart: channel waiting for irq\n"); 450 #endif 451 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 452 if (!(*chp->wdc->claim_hw)(chp, 0)) 453 return; 454 455 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 456 chp->channel, xfer->drive), DEBUG_XFERS); 457 chp->ch_flags |= WDCF_ACTIVE; 458 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 459 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 460 chp->ch_drive[xfer->drive].state = 0; 461 } 462 xfer->c_start(chp, xfer); 463 } 464 465 /* restart an interrupted I/O */ 466 void 467 wdcrestart(v) 468 void *v; 469 { 470 struct channel_softc *chp = v; 471 int s; 472 473 s = splbio(); 474 wdcstart(chp); 475 splx(s); 476 } 477 478 479 /* 480 * Interrupt routine for the controller. Acknowledge the interrupt, check for 481 * errors on the current operation, mark it done if necessary, and start the 482 * next request. Also check for a partially done transfer, and continue with 483 * the next chunk if so. 484 */ 485 int 486 wdcintr(arg) 487 void *arg; 488 { 489 struct channel_softc *chp = arg; 490 struct wdc_xfer *xfer; 491 492 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 493 #if 0 494 /* Clear the pending interrupt and abort. */ 495 u_int8_t s = 496 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 497 #ifdef WDCDEBUG 498 u_int8_t e = 499 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 500 u_int8_t i = 501 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 502 #else 503 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 504 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 505 #endif 506 507 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 508 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 509 510 if (s & WDCS_DRQ) { 511 int len; 512 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 513 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 514 chp->cmd_ioh, wd_cyl_hi); 515 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 516 len), DEBUG_INTR); 517 wdcbit_bucket (chp, len); 518 } 519 #else 520 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 521 #endif 522 return 0; 523 } 524 525 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 526 untimeout(wdctimeout, chp); 527 chp->ch_flags &= ~WDCF_IRQ_WAIT; 528 xfer = chp->ch_queue->sc_xfer.tqh_first; 529 return xfer->c_intr(chp, xfer); 530 } 531 532 /* Put all disk in RESET state */ 533 void wdc_reset_channel(drvp) 534 struct ata_drive_datas *drvp; 535 { 536 struct channel_softc *chp = drvp->chnl_softc; 537 int drive; 538 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 539 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 540 DEBUG_FUNCS); 541 (void) wdcreset(chp, VERBOSE); 542 for (drive = 0; drive < 2; drive++) { 543 chp->ch_drive[drive].state = 0; 544 } 545 } 546 547 int 548 wdcreset(chp, verb) 549 struct channel_softc *chp; 550 int verb; 551 { 552 int drv_mask1, drv_mask2; 553 554 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 555 WDSD_IBM); /* master */ 556 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 557 WDCTL_RST | WDCTL_IDS); 558 delay(1000); 559 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 560 WDCTL_IDS); 561 delay(1000); 562 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 563 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 564 WDCTL_4BIT); 565 566 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 567 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 568 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 569 if (verb && drv_mask2 != drv_mask1) { 570 printf("%s channel %d: reset failed for", 571 chp->wdc->sc_dev.dv_xname, chp->channel); 572 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 573 printf(" drive 0"); 574 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 575 printf(" drive 1"); 576 printf("\n"); 577 } 578 return (drv_mask1 != drv_mask2) ? 1 : 0; 579 } 580 581 static int 582 __wdcwait_reset(chp, drv_mask) 583 struct channel_softc *chp; 584 int drv_mask; 585 { 586 int timeout; 587 u_int8_t st0, st1; 588 /* wait for BSY to deassert */ 589 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 590 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 591 WDSD_IBM); /* master */ 592 delay(1); 593 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 594 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 595 WDSD_IBM | 0x10); /* slave */ 596 delay(1); 597 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 598 599 if ((drv_mask & 0x01) == 0) { 600 /* no master */ 601 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 602 /* No master, slave is ready, it's done */ 603 return drv_mask; 604 } 605 } else if ((drv_mask & 0x02) == 0) { 606 /* no slave */ 607 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 608 /* No slave, master is ready, it's done */ 609 return drv_mask; 610 } 611 } else { 612 /* Wait for both master and slave to be ready */ 613 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 614 return drv_mask; 615 } 616 } 617 delay(WDCDELAY); 618 } 619 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 620 if (st0 & WDCS_BSY) 621 drv_mask &= ~0x01; 622 if (st1 & WDCS_BSY) 623 drv_mask &= ~0x02; 624 return drv_mask; 625 } 626 627 /* 628 * Wait for a drive to be !BSY, and have mask in its status register. 629 * return -1 for a timeout after "timeout" ms. 630 */ 631 int 632 wdcwait(chp, mask, bits, timeout) 633 struct channel_softc *chp; 634 int mask, bits, timeout; 635 { 636 u_char status; 637 int time = 0; 638 #ifdef WDCNDELAY_DEBUG 639 extern int cold; 640 #endif 641 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 642 chp->channel), DEBUG_STATUS); 643 chp->ch_error = 0; 644 645 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 646 647 for (;;) { 648 chp->ch_status = status = 649 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 650 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 651 break; 652 if (++time > timeout) { 653 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 654 "error %x\n", status, 655 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 656 wd_error)), 657 DEBUG_STATUS); 658 return -1; 659 } 660 delay(WDCDELAY); 661 } 662 if (status & WDCS_ERR) 663 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 664 wd_error); 665 #ifdef WDCNDELAY_DEBUG 666 /* After autoconfig, there should be no long delays. */ 667 if (!cold && time > WDCNDELAY_DEBUG) { 668 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 669 if (xfer == NULL) 670 printf("%s channel %d: warning: busy-wait took %dus\n", 671 chp->wdc->sc_dev.dv_xname, chp->channel, 672 WDCDELAY * time); 673 else 674 printf("%s:%d:%d: warning: busy-wait took %dus\n", 675 chp->wdc->sc_dev.dv_xname, chp->channel, 676 xfer->drive, 677 WDCDELAY * time); 678 } 679 #endif 680 return 0; 681 } 682 683 void 684 wdctimeout(arg) 685 void *arg; 686 { 687 struct channel_softc *chp = (struct channel_softc *)arg; 688 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 689 int s; 690 691 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 692 693 s = splbio(); 694 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 695 __wdcerror(chp, "lost interrupt"); 696 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 697 "atapi":"ata"); 698 printf("\tc_bcount: %d\n", xfer->c_bcount); 699 printf("\tc_skip: %d\n", xfer->c_skip); 700 /* 701 * Call the interrupt routine. If we just missed and interrupt, 702 * it will do what's needed. Else, it will take the needed 703 * action (reset the device). 704 */ 705 xfer->c_flags |= C_TIMEOU; 706 chp->ch_flags &= ~WDCF_IRQ_WAIT; 707 xfer->c_intr(chp, xfer); 708 } else 709 __wdcerror(chp, "missing untimeout"); 710 splx(s); 711 } 712 713 /* 714 * Probe drive's capabilites, for use by the controller later 715 * Assumes drvp points to an existing drive. 716 * XXX this should be a controller-indep function 717 */ 718 void 719 wdc_probe_caps(drvp) 720 struct ata_drive_datas *drvp; 721 { 722 struct ataparams params, params2; 723 struct channel_softc *chp = drvp->chnl_softc; 724 struct device *drv_dev = drvp->drv_softc; 725 struct wdc_softc *wdc = chp->wdc; 726 int i, printed; 727 char *sep = ""; 728 int cf_flags; 729 730 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 731 /* IDENTIFY failed. Can't tell more about the device */ 732 return; 733 } 734 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 735 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 736 /* 737 * Controller claims 16 and 32 bit transfers. 738 * Re-do an IDENTIFY with 32-bit transfers, 739 * and compare results. 740 */ 741 drvp->drive_flags |= DRIVE_CAP32; 742 ata_get_params(drvp, AT_POLL, ¶ms2); 743 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 744 /* Not good. fall back to 16bits */ 745 drvp->drive_flags &= ~DRIVE_CAP32; 746 } else { 747 printf("%s: 32-bits data port", drv_dev->dv_xname); 748 } 749 } 750 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 751 if (params.atap_ata_major > 0x01 && 752 params.atap_ata_major != 0xffff) { 753 for (i = 14; i > 0; i--) { 754 if (params.atap_ata_major & (1 << i)) { 755 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 756 printf("%s: ", drv_dev->dv_xname); 757 else 758 printf(", "); 759 printf("ATA version %d\n", i); 760 drvp->ata_vers = i; 761 break; 762 } 763 } 764 } else if (drvp->drive_flags & DRIVE_CAP32) 765 #endif 766 printf("\n"); 767 768 /* An ATAPI device is at last PIO mode 3 */ 769 if (drvp->drive_flags & DRIVE_ATAPI) 770 drvp->PIO_mode = 3; 771 772 /* 773 * It's not in the specs, but it seems that some drive 774 * returns 0xffff in atap_extensions when this field is invalid 775 */ 776 if (params.atap_extensions != 0xffff && 777 (params.atap_extensions & WDC_EXT_MODES)) { 778 printed = 0; 779 /* 780 * XXX some drives report something wrong here (they claim to 781 * support PIO mode 8 !). As mode is coded on 3 bits in 782 * SET FEATURE, limit it to 7 (so limit i to 4). 783 * If higther mode than 7 is found, abort. 784 */ 785 for (i = 7; i >= 0; i--) { 786 if ((params.atap_piomode_supp & (1 << i)) == 0) 787 continue; 788 if (i > 4) 789 return; 790 /* 791 * See if mode is accepted. 792 * If the controller can't set its PIO mode, 793 * assume the defaults are good, so don't try 794 * to set it 795 */ 796 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 797 if (ata_set_mode(drvp, 0x08 | (i + 3), 798 AT_POLL) != CMD_OK) 799 continue; 800 if (!printed) { 801 printf("%s: drive supports PIO mode %d", 802 drv_dev->dv_xname, i + 3); 803 sep = ","; 804 printed = 1; 805 } 806 /* 807 * If controller's driver can't set its PIO mode, 808 * get the highter one for the drive. 809 */ 810 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 811 wdc->PIO_cap >= i + 3) { 812 drvp->PIO_mode = i + 3; 813 drvp->PIO_cap = i + 3; 814 break; 815 } 816 } 817 if (!printed) { 818 /* 819 * We didn't find a valid PIO mode. 820 * Assume the values returned for DMA are buggy too 821 */ 822 return; 823 } 824 drvp->drive_flags |= DRIVE_MODE; 825 printed = 0; 826 for (i = 7; i >= 0; i--) { 827 if ((params.atap_dmamode_supp & (1 << i)) == 0) 828 continue; 829 if ((wdc->cap & WDC_CAPABILITY_DMA) && 830 (wdc->cap & WDC_CAPABILITY_MODE)) 831 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 832 != CMD_OK) 833 continue; 834 if (!printed) { 835 printf("%s DMA mode %d", sep, i); 836 sep = ","; 837 printed = 1; 838 } 839 if (wdc->cap & WDC_CAPABILITY_DMA) { 840 if ((wdc->cap & WDC_CAPABILITY_MODE) && 841 wdc->DMA_cap < i) 842 continue; 843 drvp->DMA_mode = i; 844 drvp->DMA_cap = i; 845 drvp->drive_flags |= DRIVE_DMA; 846 } 847 break; 848 } 849 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 850 for (i = 7; i >= 0; i--) { 851 if ((params.atap_udmamode_supp & (1 << i)) 852 == 0) 853 continue; 854 if ((wdc->cap & WDC_CAPABILITY_MODE) && 855 (wdc->cap & WDC_CAPABILITY_UDMA)) 856 if (ata_set_mode(drvp, 0x40 | i, 857 AT_POLL) != CMD_OK) 858 continue; 859 printf("%s Ultra-DMA mode %d", sep, i); 860 sep = ","; 861 if (wdc->cap & WDC_CAPABILITY_UDMA) { 862 if ((wdc->cap & WDC_CAPABILITY_MODE) && 863 wdc->UDMA_cap < i) 864 continue; 865 drvp->UDMA_mode = i; 866 drvp->UDMA_cap = i; 867 drvp->drive_flags |= DRIVE_UDMA; 868 } 869 break; 870 } 871 } 872 printf("\n"); 873 } 874 875 /* Try to guess ATA version here, if it didn't get reported */ 876 if (drvp->ata_vers == 0) { 877 if (drvp->drive_flags & DRIVE_UDMA) 878 drvp->ata_vers = 4; /* should be at last ATA-4 */ 879 else if (drvp->PIO_cap > 2) 880 drvp->ata_vers = 2; /* should be at last ATA-2 */ 881 } 882 cf_flags = drv_dev->dv_cfdata->cf_flags; 883 if (cf_flags & ATA_CONFIG_PIO_SET) { 884 drvp->PIO_mode = 885 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 886 drvp->drive_flags |= DRIVE_MODE; 887 } 888 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 889 /* don't care about DMA modes */ 890 return; 891 } 892 if (cf_flags & ATA_CONFIG_DMA_SET) { 893 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 894 ATA_CONFIG_DMA_DISABLE) { 895 drvp->drive_flags &= ~DRIVE_DMA; 896 } else { 897 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 898 ATA_CONFIG_DMA_OFF; 899 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 900 } 901 } 902 if (cf_flags & ATA_CONFIG_UDMA_SET) { 903 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 904 ATA_CONFIG_UDMA_DISABLE) { 905 drvp->drive_flags &= ~DRIVE_UDMA; 906 } else { 907 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 908 ATA_CONFIG_UDMA_OFF; 909 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 910 } 911 } 912 } 913 914 /* 915 * downgrade the transfer mode of a drive after an error. return 1 if 916 * downgrade was possible, 0 otherwise. 917 */ 918 int 919 wdc_downgrade_mode(drvp) 920 struct ata_drive_datas *drvp; 921 { 922 struct channel_softc *chp = drvp->chnl_softc; 923 struct device *drv_dev = drvp->drv_softc; 924 struct wdc_softc *wdc = chp->wdc; 925 int cf_flags = drv_dev->dv_cfdata->cf_flags; 926 927 /* if drive or controller don't know its mode, we can't do much */ 928 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 929 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 930 return 0; 931 /* current drive mode was set by a config flag, let it this way */ 932 if ((cf_flags & ATA_CONFIG_PIO_SET) || 933 (cf_flags & ATA_CONFIG_DMA_SET) || 934 (cf_flags & ATA_CONFIG_UDMA_SET)) 935 return 0; 936 937 if (drvp->drive_flags & DRIVE_UDMA) { 938 drvp->drive_flags &= ~DRIVE_UDMA; 939 drvp->drive_flags |= DRIVE_DMA; 940 drvp->DMA_mode = drvp->DMA_cap; 941 printf("%s: transfer error, downgrading to DMA mode %d\n", 942 drv_dev->dv_xname, drvp->DMA_mode); 943 } else if (drvp->drive_flags & DRIVE_DMA) { 944 drvp->drive_flags &= ~DRIVE_DMA; 945 drvp->PIO_mode = drvp->PIO_cap; 946 printf("%s: transfer error, downgrading to PIO mode %d\n", 947 drv_dev->dv_xname, drvp->PIO_mode); 948 } else /* already using PIO, can't downgrade */ 949 return 0; 950 951 wdc->set_modes(chp); 952 /* reset the channel, which will shedule all drives for setup */ 953 wdc_reset_channel(drvp); 954 return 1; 955 } 956 957 int 958 wdc_exec_command(drvp, wdc_c) 959 struct ata_drive_datas *drvp; 960 struct wdc_command *wdc_c; 961 { 962 struct channel_softc *chp = drvp->chnl_softc; 963 struct wdc_xfer *xfer; 964 int s, ret; 965 966 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 967 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 968 DEBUG_FUNCS); 969 970 /* set up an xfer and queue. Wait for completion */ 971 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 972 WDC_NOSLEEP); 973 if (xfer == NULL) { 974 return WDC_TRY_AGAIN; 975 } 976 977 if (wdc_c->flags & AT_POLL) 978 xfer->c_flags |= C_POLL; 979 xfer->drive = drvp->drive; 980 xfer->databuf = wdc_c->data; 981 xfer->c_bcount = wdc_c->bcount; 982 xfer->cmd = wdc_c; 983 xfer->c_start = __wdccommand_start; 984 xfer->c_intr = __wdccommand_intr; 985 986 s = splbio(); 987 wdc_exec_xfer(chp, xfer); 988 #ifdef DIAGNOSTIC 989 if ((wdc_c->flags & AT_POLL) != 0 && 990 (wdc_c->flags & AT_DONE) == 0) 991 panic("wdc_exec_command: polled command not done\n"); 992 #endif 993 if (wdc_c->flags & AT_DONE) { 994 ret = WDC_COMPLETE; 995 } else { 996 if (wdc_c->flags & AT_WAIT) { 997 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 998 ret = WDC_COMPLETE; 999 } else { 1000 ret = WDC_QUEUED; 1001 } 1002 } 1003 splx(s); 1004 return ret; 1005 } 1006 1007 void 1008 __wdccommand_start(chp, xfer) 1009 struct channel_softc *chp; 1010 struct wdc_xfer *xfer; 1011 { 1012 int drive = xfer->drive; 1013 struct wdc_command *wdc_c = xfer->cmd; 1014 1015 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1016 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1017 DEBUG_FUNCS); 1018 1019 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1020 WDSD_IBM | (drive << 4)); 1021 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1022 wdc_c->timeout) != 0) { 1023 wdc_c->flags |= AT_TIMEOU; 1024 __wdccommand_done(chp, xfer); 1025 return; 1026 } 1027 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1028 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1029 if ((wdc_c->flags & AT_POLL) == 0) { 1030 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1031 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1032 return; 1033 } 1034 /* 1035 * Polled command. Wait for drive ready or drq. Done in intr(). 1036 * Wait for at last 400ns for status bit to be valid. 1037 */ 1038 delay(10); 1039 if (__wdccommand_intr(chp, xfer) == 0) { 1040 wdc_c->flags |= AT_TIMEOU; 1041 __wdccommand_done(chp, xfer); 1042 } 1043 } 1044 1045 int 1046 __wdccommand_intr(chp, xfer) 1047 struct channel_softc *chp; 1048 struct wdc_xfer *xfer; 1049 { 1050 struct wdc_command *wdc_c = xfer->cmd; 1051 int bcount = wdc_c->bcount; 1052 char *data = wdc_c->data; 1053 1054 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1055 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1056 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1057 wdc_c->timeout)) { 1058 wdc_c->flags |= AT_ERROR; 1059 __wdccommand_done(chp, xfer); 1060 return 1; 1061 } 1062 if (wdc_c->flags & AT_READ) { 1063 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1064 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1065 0, (u_int32_t*)data, bcount >> 2); 1066 data += bcount & 0xfffffffc; 1067 bcount = bcount & 0x03; 1068 } 1069 if (bcount > 0) 1070 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1071 wd_data, (u_int16_t *)data, bcount >> 1); 1072 } else if (wdc_c->flags & AT_WRITE) { 1073 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1074 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1075 0, (u_int32_t*)data, bcount >> 2); 1076 data += bcount & 0xfffffffc; 1077 bcount = bcount & 0x03; 1078 } 1079 if (bcount > 0) 1080 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1081 wd_data, (u_int16_t *)data, bcount >> 1); 1082 } 1083 __wdccommand_done(chp, xfer); 1084 return 1; 1085 } 1086 1087 void 1088 __wdccommand_done(chp, xfer) 1089 struct channel_softc *chp; 1090 struct wdc_xfer *xfer; 1091 { 1092 int needdone = xfer->c_flags & C_NEEDDONE; 1093 struct wdc_command *wdc_c = xfer->cmd; 1094 1095 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1096 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1097 if (chp->ch_status & WDCS_DWF) 1098 wdc_c->flags |= AT_DF; 1099 if (chp->ch_status & WDCS_ERR) { 1100 wdc_c->flags |= AT_ERROR; 1101 wdc_c->r_error = chp->ch_error; 1102 } 1103 wdc_c->flags |= AT_DONE; 1104 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1105 == 0) { 1106 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1107 wd_sdh); 1108 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1109 wd_cyl_hi) << 8; 1110 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1111 wd_cyl_lo); 1112 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1113 wd_sector); 1114 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1115 wd_seccnt); 1116 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1117 wd_error); 1118 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1119 wd_precomp); 1120 } 1121 wdc_free_xfer(chp, xfer); 1122 if (needdone) { 1123 if (wdc_c->flags & AT_WAIT) 1124 wakeup(wdc_c); 1125 else 1126 wdc_c->callback(wdc_c->callback_arg); 1127 } 1128 wdcstart(chp); 1129 return; 1130 } 1131 1132 /* 1133 * Send a command. The drive should be ready. 1134 * Assumes interrupts are blocked. 1135 */ 1136 void 1137 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1138 struct channel_softc *chp; 1139 u_int8_t drive; 1140 u_int8_t command; 1141 u_int16_t cylin; 1142 u_int8_t head, sector, count, precomp; 1143 { 1144 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1145 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1146 chp->channel, drive, command, cylin, head, sector, count, precomp), 1147 DEBUG_FUNCS); 1148 1149 /* Select drive, head, and addressing mode. */ 1150 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1151 WDSD_IBM | (drive << 4) | head); 1152 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1153 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1154 precomp); 1155 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1156 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1157 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1158 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1159 1160 /* Send command. */ 1161 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1162 return; 1163 } 1164 1165 /* 1166 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1167 * tested by the caller. 1168 */ 1169 void 1170 wdccommandshort(chp, drive, command) 1171 struct channel_softc *chp; 1172 int drive; 1173 int command; 1174 { 1175 1176 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1177 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1178 DEBUG_FUNCS); 1179 1180 /* Select drive. */ 1181 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1182 WDSD_IBM | (drive << 4)); 1183 1184 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1185 } 1186 1187 /* Add a command to the queue and start controller. Must be called at splbio */ 1188 1189 void 1190 wdc_exec_xfer(chp, xfer) 1191 struct channel_softc *chp; 1192 struct wdc_xfer *xfer; 1193 { 1194 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1195 chp->channel, xfer->drive), DEBUG_XFERS); 1196 1197 /* complete xfer setup */ 1198 xfer->chp = chp; 1199 1200 /* 1201 * If we are a polled command, and the list is not empty, 1202 * we are doing a dump. Drop the list to allow the polled command 1203 * to complete, we're going to reboot soon anyway. 1204 */ 1205 if ((xfer->c_flags & C_POLL) != 0 && 1206 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1207 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1208 } 1209 /* insert at the end of command list */ 1210 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1211 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1212 chp->ch_flags), DEBUG_XFERS); 1213 wdcstart(chp); 1214 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1215 } 1216 1217 struct wdc_xfer * 1218 wdc_get_xfer(flags) 1219 int flags; 1220 { 1221 struct wdc_xfer *xfer; 1222 int s; 1223 1224 s = splbio(); 1225 if ((xfer = xfer_free_list.lh_first) != NULL) { 1226 LIST_REMOVE(xfer, free_list); 1227 splx(s); 1228 #ifdef DIAGNOSTIC 1229 if ((xfer->c_flags & C_INUSE) != 0) 1230 panic("wdc_get_xfer: xfer already in use\n"); 1231 #endif 1232 } else { 1233 splx(s); 1234 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1235 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1236 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1237 if (xfer == NULL) 1238 return 0; 1239 #ifdef DIAGNOSTIC 1240 xfer->c_flags &= ~C_INUSE; 1241 #endif 1242 #ifdef WDCDEBUG 1243 wdc_nxfer++; 1244 #endif 1245 } 1246 #ifdef DIAGNOSTIC 1247 if ((xfer->c_flags & C_INUSE) != 0) 1248 panic("wdc_get_xfer: xfer already in use\n"); 1249 #endif 1250 memset(xfer, 0, sizeof(struct wdc_xfer)); 1251 xfer->c_flags = C_INUSE; 1252 return xfer; 1253 } 1254 1255 void 1256 wdc_free_xfer(chp, xfer) 1257 struct channel_softc *chp; 1258 struct wdc_xfer *xfer; 1259 { 1260 struct wdc_softc *wdc = chp->wdc; 1261 int s; 1262 1263 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1264 (*wdc->free_hw)(chp); 1265 s = splbio(); 1266 chp->ch_flags &= ~WDCF_ACTIVE; 1267 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1268 xfer->c_flags &= ~C_INUSE; 1269 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1270 splx(s); 1271 } 1272 1273 static void 1274 __wdcerror(chp, msg) 1275 struct channel_softc *chp; 1276 char *msg; 1277 { 1278 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1279 if (xfer == NULL) 1280 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1281 msg); 1282 else 1283 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1284 chp->channel, xfer->drive, msg); 1285 } 1286 1287 /* 1288 * the bit bucket 1289 */ 1290 void 1291 wdcbit_bucket(chp, size) 1292 struct channel_softc *chp; 1293 int size; 1294 { 1295 1296 for (; size >= 2; size -= 2) 1297 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1298 if (size) 1299 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1300 } 1301 1302 int 1303 wdc_addref(chp) 1304 struct channel_softc *chp; 1305 { 1306 struct wdc_softc *wdc = chp->wdc; 1307 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1308 int s, error = 0; 1309 1310 s = splbio(); 1311 if (adapter->scsipi_refcnt++ == 0 && 1312 adapter->scsipi_enable != NULL) { 1313 error = (*adapter->scsipi_enable)(wdc, 1); 1314 if (error) 1315 adapter->scsipi_refcnt--; 1316 } 1317 splx(s); 1318 return (error); 1319 } 1320 1321 void 1322 wdc_delref(chp) 1323 struct channel_softc *chp; 1324 { 1325 struct wdc_softc *wdc = chp->wdc; 1326 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1327 int s; 1328 1329 s = splbio(); 1330 if (adapter->scsipi_refcnt-- == 1 && 1331 adapter->scsipi_enable != NULL) 1332 (void) (*adapter->scsipi_enable)(wdc, 0); 1333 splx(s); 1334 } 1335
Indexes created Mon Sep 22 10:09:38 GMT 2025