wdc.c revision 1.57
1 /* $NetBSD: wdc.c,v 1.57 1999/02/15 18:47:59 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #define WDCDEBUG 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/conf.h> 80 #include <sys/buf.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <vm/vm.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 91 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 92 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 93 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 94 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 95 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 96 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 97 98 #include <dev/ata/atavar.h> 99 #include <dev/ata/atareg.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #include "atapibus.h" 104 105 #define WDCDELAY 100 /* 100 microseconds */ 106 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 107 #if 0 108 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 109 #define WDCNDELAY_DEBUG 50 110 #endif 111 112 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 113 114 static void __wdcerror __P((struct channel_softc*, char *)); 115 static int __wdcwait_reset __P((struct channel_softc *, int)); 116 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 117 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 118 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 int wdprint __P((void *, const char *)); 120 121 122 #define DEBUG_INTR 0x01 123 #define DEBUG_XFERS 0x02 124 #define DEBUG_STATUS 0x04 125 #define DEBUG_FUNCS 0x08 126 #define DEBUG_PROBE 0x10 127 #ifdef WDCDEBUG 128 int wdcdebug_mask = 0; 129 int wdc_nxfer = 0; 130 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 131 #else 132 #define WDCDEBUG_PRINT(args, level) 133 #endif 134 135 int 136 wdprint(aux, pnp) 137 void *aux; 138 const char *pnp; 139 { 140 struct ata_atapi_attach *aa_link = aux; 141 if (pnp) 142 printf("drive at %s", pnp); 143 printf(" channel %d drive %d", aa_link->aa_channel, 144 aa_link->aa_drv_data->drive); 145 return (UNCONF); 146 } 147 148 int 149 atapi_print(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct ata_atapi_attach *aa_link = aux; 154 if (pnp) 155 printf("atapibus at %s", pnp); 156 printf(" channel %d", aa_link->aa_channel); 157 return (UNCONF); 158 } 159 160 /* Test to see controller with at last one attached drive is there. 161 * Returns a bit for each possible drive found (0x01 for drive 0, 162 * 0x02 for drive 1). 163 * Logic: 164 * - If a status register is at 0xff, assume there is no drive here 165 * (ISA has pull-up resistors). If no drive at all -> return. 166 * - reset the controller, wait for it to complete (may take up to 31s !). 167 * If timeout -> return. 168 * - test ATA/ATAPI signatures. If at last one drive found -> return. 169 * - try an ATA command on the master. 170 */ 171 172 int 173 wdcprobe(chp) 174 struct channel_softc *chp; 175 { 176 u_int8_t st0, st1, sc, sn, cl, ch; 177 u_int8_t ret_value = 0x03; 178 u_int8_t drive; 179 180 /* 181 * Sanity check to see if the wdc channel responds at all. 182 */ 183 184 if (chp->wdc == NULL || 185 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 187 WDSD_IBM); 188 delay(1); 189 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM | 0x10); 192 delay(1); 193 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 195 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 196 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 197 chp->channel, st0, st1), DEBUG_PROBE); 198 199 if (st0 == 0xff) 200 ret_value &= ~0x01; 201 if (st1 == 0xff) 202 ret_value &= ~0x02; 203 if (ret_value == 0) 204 return 0; 205 } 206 207 /* assert SRST, wait for reset to complete */ 208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 209 WDSD_IBM); 210 delay(1); 211 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 212 WDCTL_RST | WDCTL_IDS); 213 DELAY(1000); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_IDS); 216 delay(1000); 217 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 219 delay(1); 220 221 ret_value = __wdcwait_reset(chp, ret_value); 222 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 223 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 224 ret_value), DEBUG_PROBE); 225 226 /* if reset failed, there's nothing here */ 227 if (ret_value == 0) 228 return 0; 229 230 /* 231 * Test presence of drives. First test register signatures looking for 232 * ATAPI devices , then rescan and try an ATA command, in case it's an 233 * old drive. 234 * Fill in drive_flags accordingly 235 */ 236 for (drive = 0; drive < 2; drive++) { 237 if ((ret_value & (0x01 << drive)) == 0) 238 continue; 239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 240 WDSD_IBM | (drive << 4)); 241 delay(1); 242 /* Save registers contents */ 243 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 244 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 245 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 246 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 247 248 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 249 "cl=0x%x ch=0x%x\n", 250 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 251 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 252 /* 253 * sc is supposted to be 0x1 for ATAPI but at last one drive 254 * set it to 0x0. 255 */ 256 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 257 cl == 0x14 && ch == 0xeb) { 258 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 259 } 260 } 261 for (drive = 0; drive < 2; drive++) { 262 if ((ret_value & (0x01 << drive)) == 0 || 263 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 264 continue; 265 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 266 WDSD_IBM | (drive << 4)); 267 delay(1); 268 /* 269 * Maybe it's an old device, so don't rely on ATA sig. 270 * Test registers writability (Error register not writable, 271 * but cyllo is), then try an ATA command. 272 */ 273 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 274 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 275 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 276 0x58 || 277 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 278 0xa5) { 279 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 280 "failed\n", 281 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 282 chp->channel, drive), DEBUG_PROBE); 283 ret_value &= ~(0x01 << drive); 284 continue; 285 } 286 if (wait_for_ready(chp, 10000) != 0) { 287 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 288 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 289 chp->channel, drive), DEBUG_PROBE); 290 ret_value &= ~(0x01 << drive); 291 continue; 292 } 293 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 294 WDCC_DIAGNOSE); 295 if (wait_for_ready(chp, 10000) == 0) { 296 chp->ch_drive[drive].drive_flags |= 297 DRIVE_ATA; 298 } else { 299 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 300 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 301 chp->channel, drive), DEBUG_PROBE); 302 ret_value &= ~(0x01 << drive); 303 } 304 } 305 return (ret_value); 306 } 307 308 void 309 wdcattach(chp) 310 struct channel_softc *chp; 311 { 312 int channel_flags, ctrl_flags, i, error; 313 struct ata_atapi_attach aa_link; 314 315 LIST_INIT(&xfer_free_list); 316 for (i = 0; i < 2; i++) { 317 chp->ch_drive[i].chnl_softc = chp; 318 chp->ch_drive[i].drive = i; 319 /* If controller can't do 16bit flag the drives as 32bit */ 320 if ((chp->wdc->cap & 321 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 322 WDC_CAPABILITY_DATA32) 323 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 324 } 325 326 if ((error = wdc_addref(chp)) != 0) { 327 printf("%s: unable to enable controller\n", 328 chp->wdc->sc_dev.dv_xname); 329 return; 330 } 331 332 if (wdcprobe(chp) == 0) { 333 /* If no drives, abort attach here. */ 334 wdc_delref(chp); 335 return; 336 } 337 338 TAILQ_INIT(&chp->ch_queue->sc_xfer); 339 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 340 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 341 342 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 343 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 344 DEBUG_PROBE); 345 346 /* 347 * Attach an ATAPI bus, if needed. 348 */ 349 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 350 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 351 #if NATAPIBUS > 0 352 wdc_atapibus_attach(chp); 353 #else 354 /* 355 * Fills in a fake aa_link and call config_found, so that 356 * the config machinery will print 357 * "atapibus at xxx not configured" 358 */ 359 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 360 aa_link.aa_type = T_ATAPI; 361 aa_link.aa_channel = chp->channel; 362 aa_link.aa_openings = 1; 363 aa_link.aa_drv_data = 0; 364 aa_link.aa_bus_private = NULL; 365 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 366 atapi_print); 367 #endif 368 } 369 370 for (i = 0; i < 2; i++) { 371 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 372 continue; 373 } 374 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 375 aa_link.aa_type = T_ATA; 376 aa_link.aa_channel = chp->channel; 377 aa_link.aa_openings = 1; 378 aa_link.aa_drv_data = &chp->ch_drive[i]; 379 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 380 wdc_probe_caps(&chp->ch_drive[i]); 381 } 382 383 /* 384 * reset drive_flags for unnatached devices, reset state for attached 385 * ones 386 */ 387 for (i = 0; i < 2; i++) { 388 if (chp->ch_drive[i].drv_softc == NULL) 389 chp->ch_drive[i].drive_flags = 0; 390 else 391 chp->ch_drive[i].state = 0; 392 } 393 394 /* 395 * Reset channel. The probe, with some combinations of ATA/ATAPI 396 * devices keep it in a mostly working, but strange state (with busy 397 * led on) 398 */ 399 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 400 wdcreset(chp, VERBOSE); 401 /* 402 * Read status registers to avoid spurious interrupts. 403 */ 404 for (i = 1; i >= 0; i--) { 405 if (chp->ch_drive[i].drive_flags & DRIVE) { 406 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 407 wd_sdh, WDSD_IBM | (i << 4)); 408 if (wait_for_unbusy(chp, 10000) < 0) 409 printf("%s:%d:%d: device busy\n", 410 chp->wdc->sc_dev.dv_xname, 411 chp->channel, i); 412 } 413 } 414 } 415 wdc_delref(chp); 416 } 417 418 /* 419 * Start I/O on a controller, for the given channel. 420 * The first xfer may be not for our channel if the channel queues 421 * are shared. 422 */ 423 void 424 wdcstart(chp) 425 struct channel_softc *chp; 426 { 427 struct wdc_xfer *xfer; 428 429 #ifdef WDC_DIAGNOSTIC 430 int spl1, spl2; 431 432 spl1 = splbio(); 433 spl2 = splbio(); 434 if (spl2 != spl1) { 435 printf("wdcstart: not at splbio()\n"); 436 panic("wdcstart"); 437 } 438 splx(spl2); 439 splx(spl1); 440 #endif /* WDC_DIAGNOSTIC */ 441 442 /* is there a xfer ? */ 443 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 444 return; 445 446 /* adjust chp, in case we have a shared queue */ 447 chp = xfer->chp; 448 449 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 450 return; /* channel aleady active */ 451 } 452 #ifdef DIAGNOSTIC 453 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 454 panic("wdcstart: channel waiting for irq\n"); 455 #endif 456 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 457 if (!(*chp->wdc->claim_hw)(chp, 0)) 458 return; 459 460 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 461 chp->channel, xfer->drive), DEBUG_XFERS); 462 chp->ch_flags |= WDCF_ACTIVE; 463 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 464 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 465 chp->ch_drive[xfer->drive].state = 0; 466 } 467 xfer->c_start(chp, xfer); 468 } 469 470 /* restart an interrupted I/O */ 471 void 472 wdcrestart(v) 473 void *v; 474 { 475 struct channel_softc *chp = v; 476 int s; 477 478 s = splbio(); 479 wdcstart(chp); 480 splx(s); 481 } 482 483 484 /* 485 * Interrupt routine for the controller. Acknowledge the interrupt, check for 486 * errors on the current operation, mark it done if necessary, and start the 487 * next request. Also check for a partially done transfer, and continue with 488 * the next chunk if so. 489 */ 490 int 491 wdcintr(arg) 492 void *arg; 493 { 494 struct channel_softc *chp = arg; 495 struct wdc_xfer *xfer; 496 497 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 498 #if 0 499 /* Clear the pending interrupt and abort. */ 500 u_int8_t s = 501 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 502 #ifdef WDCDEBUG 503 u_int8_t e = 504 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 505 u_int8_t i = 506 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 507 #else 508 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 509 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 510 #endif 511 512 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 513 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 514 515 if (s & WDCS_DRQ) { 516 int len; 517 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 518 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 519 chp->cmd_ioh, wd_cyl_hi); 520 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 521 len), DEBUG_INTR); 522 wdcbit_bucket (chp, len); 523 } 524 #else 525 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 526 #endif 527 return 0; 528 } 529 530 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 531 untimeout(wdctimeout, chp); 532 chp->ch_flags &= ~WDCF_IRQ_WAIT; 533 xfer = chp->ch_queue->sc_xfer.tqh_first; 534 return xfer->c_intr(chp, xfer); 535 } 536 537 /* Put all disk in RESET state */ 538 void wdc_reset_channel(drvp) 539 struct ata_drive_datas *drvp; 540 { 541 struct channel_softc *chp = drvp->chnl_softc; 542 int drive; 543 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 544 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 545 DEBUG_FUNCS); 546 (void) wdcreset(chp, VERBOSE); 547 for (drive = 0; drive < 2; drive++) { 548 chp->ch_drive[drive].state = 0; 549 } 550 } 551 552 int 553 wdcreset(chp, verb) 554 struct channel_softc *chp; 555 int verb; 556 { 557 int drv_mask1, drv_mask2; 558 559 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 560 WDSD_IBM); /* master */ 561 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 562 WDCTL_RST | WDCTL_IDS); 563 delay(1000); 564 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 565 WDCTL_IDS); 566 delay(1000); 567 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 568 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 569 WDCTL_4BIT); 570 571 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 572 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 573 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 574 if (verb && drv_mask2 != drv_mask1) { 575 printf("%s channel %d: reset failed for", 576 chp->wdc->sc_dev.dv_xname, chp->channel); 577 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 578 printf(" drive 0"); 579 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 580 printf(" drive 1"); 581 printf("\n"); 582 } 583 return (drv_mask1 != drv_mask2) ? 1 : 0; 584 } 585 586 static int 587 __wdcwait_reset(chp, drv_mask) 588 struct channel_softc *chp; 589 int drv_mask; 590 { 591 int timeout; 592 u_int8_t st0, st1; 593 /* wait for BSY to deassert */ 594 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 595 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 596 WDSD_IBM); /* master */ 597 delay(1); 598 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 599 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 600 WDSD_IBM | 0x10); /* slave */ 601 delay(1); 602 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 603 604 if ((drv_mask & 0x01) == 0) { 605 /* no master */ 606 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 607 /* No master, slave is ready, it's done */ 608 return drv_mask; 609 } 610 } else if ((drv_mask & 0x02) == 0) { 611 /* no slave */ 612 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 613 /* No slave, master is ready, it's done */ 614 return drv_mask; 615 } 616 } else { 617 /* Wait for both master and slave to be ready */ 618 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 619 return drv_mask; 620 } 621 } 622 delay(WDCDELAY); 623 } 624 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 625 if (st0 & WDCS_BSY) 626 drv_mask &= ~0x01; 627 if (st1 & WDCS_BSY) 628 drv_mask &= ~0x02; 629 return drv_mask; 630 } 631 632 /* 633 * Wait for a drive to be !BSY, and have mask in its status register. 634 * return -1 for a timeout after "timeout" ms. 635 */ 636 int 637 wdcwait(chp, mask, bits, timeout) 638 struct channel_softc *chp; 639 int mask, bits, timeout; 640 { 641 u_char status; 642 int time = 0; 643 #ifdef WDCNDELAY_DEBUG 644 extern int cold; 645 #endif 646 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc->sc_dev.dv_xname, 647 chp->channel), DEBUG_STATUS); 648 chp->ch_error = 0; 649 650 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 651 652 for (;;) { 653 chp->ch_status = status = 654 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 655 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 656 break; 657 if (++time > timeout) { 658 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 659 "error %x\n", status, 660 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 661 wd_error)), 662 DEBUG_STATUS); 663 return -1; 664 } 665 delay(WDCDELAY); 666 } 667 if (status & WDCS_ERR) 668 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 669 wd_error); 670 #ifdef WDCNDELAY_DEBUG 671 /* After autoconfig, there should be no long delays. */ 672 if (!cold && time > WDCNDELAY_DEBUG) { 673 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 674 if (xfer == NULL) 675 printf("%s channel %d: warning: busy-wait took %dus\n", 676 chp->wdc->sc_dev.dv_xname, chp->channel, 677 WDCDELAY * time); 678 else 679 printf("%s:%d:%d: warning: busy-wait took %dus\n", 680 chp->wdc->sc_dev.dv_xname, chp->channel, 681 xfer->drive, 682 WDCDELAY * time); 683 } 684 #endif 685 return 0; 686 } 687 688 void 689 wdctimeout(arg) 690 void *arg; 691 { 692 struct channel_softc *chp = (struct channel_softc *)arg; 693 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 694 int s; 695 696 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 697 698 s = splbio(); 699 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 700 __wdcerror(chp, "lost interrupt"); 701 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 702 "atapi":"ata"); 703 printf("\tc_bcount: %d\n", xfer->c_bcount); 704 printf("\tc_skip: %d\n", xfer->c_skip); 705 /* 706 * Call the interrupt routine. If we just missed and interrupt, 707 * it will do what's needed. Else, it will take the needed 708 * action (reset the device). 709 */ 710 xfer->c_flags |= C_TIMEOU; 711 chp->ch_flags &= ~WDCF_IRQ_WAIT; 712 xfer->c_intr(chp, xfer); 713 } else 714 __wdcerror(chp, "missing untimeout"); 715 splx(s); 716 } 717 718 /* 719 * Probe drive's capabilites, for use by the controller later 720 * Assumes drvp points to an existing drive. 721 * XXX this should be a controller-indep function 722 */ 723 void 724 wdc_probe_caps(drvp) 725 struct ata_drive_datas *drvp; 726 { 727 struct ataparams params, params2; 728 struct channel_softc *chp = drvp->chnl_softc; 729 struct device *drv_dev = drvp->drv_softc; 730 struct wdc_softc *wdc = chp->wdc; 731 int i, printed; 732 char *sep = ""; 733 int cf_flags; 734 735 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 736 /* IDENTIFY failed. Can't tell more about the device */ 737 return; 738 } 739 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 740 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 741 /* 742 * Controller claims 16 and 32 bit transfers. 743 * Re-do an IDENTIFY with 32-bit transfers, 744 * and compare results. 745 */ 746 drvp->drive_flags |= DRIVE_CAP32; 747 ata_get_params(drvp, AT_POLL, ¶ms2); 748 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 749 /* Not good. fall back to 16bits */ 750 drvp->drive_flags &= ~DRIVE_CAP32; 751 } else { 752 printf("%s: 32-bits data port", drv_dev->dv_xname); 753 } 754 } 755 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 756 if (params.atap_ata_major > 0x01 && 757 params.atap_ata_major != 0xffff) { 758 for (i = 14; i > 0; i--) { 759 if (params.atap_ata_major & (1 << i)) { 760 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 761 printf("%s: ", drv_dev->dv_xname); 762 else 763 printf(", "); 764 printf("ATA version %d\n", i); 765 drvp->ata_vers = i; 766 break; 767 } 768 } 769 } else if (drvp->drive_flags & DRIVE_CAP32) 770 #endif 771 printf("\n"); 772 773 /* An ATAPI device is at last PIO mode 3 */ 774 if (drvp->drive_flags & DRIVE_ATAPI) 775 drvp->PIO_mode = 3; 776 777 /* 778 * It's not in the specs, but it seems that some drive 779 * returns 0xffff in atap_extensions when this field is invalid 780 */ 781 if (params.atap_extensions != 0xffff && 782 (params.atap_extensions & WDC_EXT_MODES)) { 783 printed = 0; 784 /* 785 * XXX some drives report something wrong here (they claim to 786 * support PIO mode 8 !). As mode is coded on 3 bits in 787 * SET FEATURE, limit it to 7 (so limit i to 4). 788 * If higther mode than 7 is found, abort. 789 */ 790 for (i = 7; i >= 0; i--) { 791 if ((params.atap_piomode_supp & (1 << i)) == 0) 792 continue; 793 if (i > 4) 794 return; 795 /* 796 * See if mode is accepted. 797 * If the controller can't set its PIO mode, 798 * assume the defaults are good, so don't try 799 * to set it 800 */ 801 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 802 if (ata_set_mode(drvp, 0x08 | (i + 3), 803 AT_POLL) != CMD_OK) 804 continue; 805 if (!printed) { 806 printf("%s: drive supports PIO mode %d", 807 drv_dev->dv_xname, i + 3); 808 sep = ","; 809 printed = 1; 810 } 811 /* 812 * If controller's driver can't set its PIO mode, 813 * get the highter one for the drive. 814 */ 815 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 816 wdc->PIO_cap >= i + 3) { 817 drvp->PIO_mode = i + 3; 818 drvp->PIO_cap = i + 3; 819 break; 820 } 821 } 822 if (!printed) { 823 /* 824 * We didn't find a valid PIO mode. 825 * Assume the values returned for DMA are buggy too 826 */ 827 return; 828 } 829 drvp->drive_flags |= DRIVE_MODE; 830 printed = 0; 831 for (i = 7; i >= 0; i--) { 832 if ((params.atap_dmamode_supp & (1 << i)) == 0) 833 continue; 834 if ((wdc->cap & WDC_CAPABILITY_DMA) && 835 (wdc->cap & WDC_CAPABILITY_MODE)) 836 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 837 != CMD_OK) 838 continue; 839 if (!printed) { 840 printf("%s DMA mode %d", sep, i); 841 sep = ","; 842 printed = 1; 843 } 844 if (wdc->cap & WDC_CAPABILITY_DMA) { 845 if ((wdc->cap & WDC_CAPABILITY_MODE) && 846 wdc->DMA_cap < i) 847 continue; 848 drvp->DMA_mode = i; 849 drvp->DMA_cap = i; 850 drvp->drive_flags |= DRIVE_DMA; 851 } 852 break; 853 } 854 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 855 for (i = 7; i >= 0; i--) { 856 if ((params.atap_udmamode_supp & (1 << i)) 857 == 0) 858 continue; 859 if ((wdc->cap & WDC_CAPABILITY_MODE) && 860 (wdc->cap & WDC_CAPABILITY_UDMA)) 861 if (ata_set_mode(drvp, 0x40 | i, 862 AT_POLL) != CMD_OK) 863 continue; 864 printf("%s Ultra-DMA mode %d", sep, i); 865 sep = ","; 866 if (wdc->cap & WDC_CAPABILITY_UDMA) { 867 if ((wdc->cap & WDC_CAPABILITY_MODE) && 868 wdc->UDMA_cap < i) 869 continue; 870 drvp->UDMA_mode = i; 871 drvp->UDMA_cap = i; 872 drvp->drive_flags |= DRIVE_UDMA; 873 } 874 break; 875 } 876 } 877 printf("\n"); 878 } 879 880 /* Try to guess ATA version here, if it didn't get reported */ 881 if (drvp->ata_vers == 0) { 882 if (drvp->drive_flags & DRIVE_UDMA) 883 drvp->ata_vers = 4; /* should be at last ATA-4 */ 884 else if (drvp->PIO_cap > 2) 885 drvp->ata_vers = 2; /* should be at last ATA-2 */ 886 } 887 cf_flags = drv_dev->dv_cfdata->cf_flags; 888 if (cf_flags & ATA_CONFIG_PIO_SET) { 889 drvp->PIO_mode = 890 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 891 drvp->drive_flags |= DRIVE_MODE; 892 } 893 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 894 /* don't care about DMA modes */ 895 return; 896 } 897 if (cf_flags & ATA_CONFIG_DMA_SET) { 898 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 899 ATA_CONFIG_DMA_DISABLE) { 900 drvp->drive_flags &= ~DRIVE_DMA; 901 } else { 902 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 903 ATA_CONFIG_DMA_OFF; 904 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 905 } 906 } 907 if (cf_flags & ATA_CONFIG_UDMA_SET) { 908 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 909 ATA_CONFIG_UDMA_DISABLE) { 910 drvp->drive_flags &= ~DRIVE_UDMA; 911 } else { 912 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 913 ATA_CONFIG_UDMA_OFF; 914 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 915 } 916 } 917 } 918 919 /* 920 * downgrade the transfer mode of a drive after an error. return 1 if 921 * downgrade was possible, 0 otherwise. 922 */ 923 int 924 wdc_downgrade_mode(drvp) 925 struct ata_drive_datas *drvp; 926 { 927 struct channel_softc *chp = drvp->chnl_softc; 928 struct device *drv_dev = drvp->drv_softc; 929 struct wdc_softc *wdc = chp->wdc; 930 int cf_flags = drv_dev->dv_cfdata->cf_flags; 931 932 /* if drive or controller don't know its mode, we can't do much */ 933 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 934 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 935 return 0; 936 /* current drive mode was set by a config flag, let it this way */ 937 if ((cf_flags & ATA_CONFIG_PIO_SET) || 938 (cf_flags & ATA_CONFIG_DMA_SET) || 939 (cf_flags & ATA_CONFIG_UDMA_SET)) 940 return 0; 941 942 if (drvp->drive_flags & DRIVE_UDMA) { 943 drvp->drive_flags &= ~DRIVE_UDMA; 944 drvp->drive_flags |= DRIVE_DMA; 945 drvp->DMA_mode = drvp->DMA_cap; 946 printf("%s: transfer error, downgrading to DMA mode %d\n", 947 drv_dev->dv_xname, drvp->DMA_mode); 948 } else if (drvp->drive_flags & DRIVE_DMA) { 949 drvp->drive_flags &= ~DRIVE_DMA; 950 drvp->PIO_mode = drvp->PIO_cap; 951 printf("%s: transfer error, downgrading to PIO mode %d\n", 952 drv_dev->dv_xname, drvp->PIO_mode); 953 } else /* already using PIO, can't downgrade */ 954 return 0; 955 956 wdc->set_modes(chp); 957 /* reset the channel, which will shedule all drives for setup */ 958 wdc_reset_channel(drvp); 959 return 1; 960 } 961 962 int 963 wdc_exec_command(drvp, wdc_c) 964 struct ata_drive_datas *drvp; 965 struct wdc_command *wdc_c; 966 { 967 struct channel_softc *chp = drvp->chnl_softc; 968 struct wdc_xfer *xfer; 969 int s, ret; 970 971 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 972 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 973 DEBUG_FUNCS); 974 975 /* set up an xfer and queue. Wait for completion */ 976 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 977 WDC_NOSLEEP); 978 if (xfer == NULL) { 979 return WDC_TRY_AGAIN; 980 } 981 982 if (wdc_c->flags & AT_POLL) 983 xfer->c_flags |= C_POLL; 984 xfer->drive = drvp->drive; 985 xfer->databuf = wdc_c->data; 986 xfer->c_bcount = wdc_c->bcount; 987 xfer->cmd = wdc_c; 988 xfer->c_start = __wdccommand_start; 989 xfer->c_intr = __wdccommand_intr; 990 991 s = splbio(); 992 wdc_exec_xfer(chp, xfer); 993 #ifdef DIAGNOSTIC 994 if ((wdc_c->flags & AT_POLL) != 0 && 995 (wdc_c->flags & AT_DONE) == 0) 996 panic("wdc_exec_command: polled command not done\n"); 997 #endif 998 if (wdc_c->flags & AT_DONE) { 999 ret = WDC_COMPLETE; 1000 } else { 1001 if (wdc_c->flags & AT_WAIT) { 1002 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1003 ret = WDC_COMPLETE; 1004 } else { 1005 ret = WDC_QUEUED; 1006 } 1007 } 1008 splx(s); 1009 return ret; 1010 } 1011 1012 void 1013 __wdccommand_start(chp, xfer) 1014 struct channel_softc *chp; 1015 struct wdc_xfer *xfer; 1016 { 1017 int drive = xfer->drive; 1018 struct wdc_command *wdc_c = xfer->cmd; 1019 1020 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1021 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1022 DEBUG_FUNCS); 1023 1024 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1025 WDSD_IBM | (drive << 4)); 1026 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1027 wdc_c->timeout) != 0) { 1028 wdc_c->flags |= AT_TIMEOU; 1029 __wdccommand_done(chp, xfer); 1030 return; 1031 } 1032 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1033 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1034 if ((wdc_c->flags & AT_POLL) == 0) { 1035 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1036 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1037 return; 1038 } 1039 /* 1040 * Polled command. Wait for drive ready or drq. Done in intr(). 1041 * Wait for at last 400ns for status bit to be valid. 1042 */ 1043 delay(10); 1044 if (__wdccommand_intr(chp, xfer) == 0) { 1045 wdc_c->flags |= AT_TIMEOU; 1046 __wdccommand_done(chp, xfer); 1047 } 1048 } 1049 1050 int 1051 __wdccommand_intr(chp, xfer) 1052 struct channel_softc *chp; 1053 struct wdc_xfer *xfer; 1054 { 1055 struct wdc_command *wdc_c = xfer->cmd; 1056 int bcount = wdc_c->bcount; 1057 char *data = wdc_c->data; 1058 1059 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1060 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1061 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1062 wdc_c->timeout)) { 1063 wdc_c->flags |= AT_ERROR; 1064 __wdccommand_done(chp, xfer); 1065 return 1; 1066 } 1067 if (wdc_c->flags & AT_READ) { 1068 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1069 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1070 0, (u_int32_t*)data, bcount >> 2); 1071 data += bcount & 0xfffffffc; 1072 bcount = bcount & 0x03; 1073 } 1074 if (bcount > 0) 1075 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1076 wd_data, (u_int16_t *)data, bcount >> 1); 1077 } else if (wdc_c->flags & AT_WRITE) { 1078 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1079 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1080 0, (u_int32_t*)data, bcount >> 2); 1081 data += bcount & 0xfffffffc; 1082 bcount = bcount & 0x03; 1083 } 1084 if (bcount > 0) 1085 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1086 wd_data, (u_int16_t *)data, bcount >> 1); 1087 } 1088 __wdccommand_done(chp, xfer); 1089 return 1; 1090 } 1091 1092 void 1093 __wdccommand_done(chp, xfer) 1094 struct channel_softc *chp; 1095 struct wdc_xfer *xfer; 1096 { 1097 int needdone = xfer->c_flags & C_NEEDDONE; 1098 struct wdc_command *wdc_c = xfer->cmd; 1099 1100 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1101 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1102 if (chp->ch_status & WDCS_DWF) 1103 wdc_c->flags |= AT_DF; 1104 if (chp->ch_status & WDCS_ERR) { 1105 wdc_c->flags |= AT_ERROR; 1106 wdc_c->r_error = chp->ch_error; 1107 } 1108 wdc_c->flags |= AT_DONE; 1109 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1110 == 0) { 1111 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1112 wd_sdh); 1113 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1114 wd_cyl_hi) << 8; 1115 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1116 wd_cyl_lo); 1117 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1118 wd_sector); 1119 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1120 wd_seccnt); 1121 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1122 wd_error); 1123 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1124 wd_precomp); 1125 } 1126 wdc_free_xfer(chp, xfer); 1127 if (needdone) { 1128 if (wdc_c->flags & AT_WAIT) 1129 wakeup(wdc_c); 1130 else 1131 wdc_c->callback(wdc_c->callback_arg); 1132 } 1133 wdcstart(chp); 1134 return; 1135 } 1136 1137 /* 1138 * Send a command. The drive should be ready. 1139 * Assumes interrupts are blocked. 1140 */ 1141 void 1142 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1143 struct channel_softc *chp; 1144 u_int8_t drive; 1145 u_int8_t command; 1146 u_int16_t cylin; 1147 u_int8_t head, sector, count, precomp; 1148 { 1149 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1150 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1151 chp->channel, drive, command, cylin, head, sector, count, precomp), 1152 DEBUG_FUNCS); 1153 1154 /* Select drive, head, and addressing mode. */ 1155 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1156 WDSD_IBM | (drive << 4) | head); 1157 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1158 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1159 precomp); 1160 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1161 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1162 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1163 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1164 1165 /* Send command. */ 1166 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1167 return; 1168 } 1169 1170 /* 1171 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1172 * tested by the caller. 1173 */ 1174 void 1175 wdccommandshort(chp, drive, command) 1176 struct channel_softc *chp; 1177 int drive; 1178 int command; 1179 { 1180 1181 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1182 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1183 DEBUG_FUNCS); 1184 1185 /* Select drive. */ 1186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1187 WDSD_IBM | (drive << 4)); 1188 1189 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1190 } 1191 1192 /* Add a command to the queue and start controller. Must be called at splbio */ 1193 1194 void 1195 wdc_exec_xfer(chp, xfer) 1196 struct channel_softc *chp; 1197 struct wdc_xfer *xfer; 1198 { 1199 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1200 chp->channel, xfer->drive), DEBUG_XFERS); 1201 1202 /* complete xfer setup */ 1203 xfer->chp = chp; 1204 1205 /* 1206 * If we are a polled command, and the list is not empty, 1207 * we are doing a dump. Drop the list to allow the polled command 1208 * to complete, we're going to reboot soon anyway. 1209 */ 1210 if ((xfer->c_flags & C_POLL) != 0 && 1211 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1212 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1213 } 1214 /* insert at the end of command list */ 1215 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1216 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1217 chp->ch_flags), DEBUG_XFERS); 1218 wdcstart(chp); 1219 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1220 } 1221 1222 struct wdc_xfer * 1223 wdc_get_xfer(flags) 1224 int flags; 1225 { 1226 struct wdc_xfer *xfer; 1227 int s; 1228 1229 s = splbio(); 1230 if ((xfer = xfer_free_list.lh_first) != NULL) { 1231 LIST_REMOVE(xfer, free_list); 1232 splx(s); 1233 #ifdef DIAGNOSTIC 1234 if ((xfer->c_flags & C_INUSE) != 0) 1235 panic("wdc_get_xfer: xfer already in use\n"); 1236 #endif 1237 } else { 1238 splx(s); 1239 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1240 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1241 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1242 if (xfer == NULL) 1243 return 0; 1244 #ifdef DIAGNOSTIC 1245 xfer->c_flags &= ~C_INUSE; 1246 #endif 1247 #ifdef WDCDEBUG 1248 wdc_nxfer++; 1249 #endif 1250 } 1251 #ifdef DIAGNOSTIC 1252 if ((xfer->c_flags & C_INUSE) != 0) 1253 panic("wdc_get_xfer: xfer already in use\n"); 1254 #endif 1255 memset(xfer, 0, sizeof(struct wdc_xfer)); 1256 xfer->c_flags = C_INUSE; 1257 return xfer; 1258 } 1259 1260 void 1261 wdc_free_xfer(chp, xfer) 1262 struct channel_softc *chp; 1263 struct wdc_xfer *xfer; 1264 { 1265 struct wdc_softc *wdc = chp->wdc; 1266 int s; 1267 1268 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1269 (*wdc->free_hw)(chp); 1270 s = splbio(); 1271 chp->ch_flags &= ~WDCF_ACTIVE; 1272 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1273 xfer->c_flags &= ~C_INUSE; 1274 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1275 splx(s); 1276 } 1277 1278 static void 1279 __wdcerror(chp, msg) 1280 struct channel_softc *chp; 1281 char *msg; 1282 { 1283 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1284 if (xfer == NULL) 1285 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1286 msg); 1287 else 1288 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1289 chp->channel, xfer->drive, msg); 1290 } 1291 1292 /* 1293 * the bit bucket 1294 */ 1295 void 1296 wdcbit_bucket(chp, size) 1297 struct channel_softc *chp; 1298 int size; 1299 { 1300 1301 for (; size >= 2; size -= 2) 1302 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1303 if (size) 1304 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1305 } 1306 1307 int 1308 wdc_addref(chp) 1309 struct channel_softc *chp; 1310 { 1311 struct wdc_softc *wdc = chp->wdc; 1312 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1313 int s, error = 0; 1314 1315 s = splbio(); 1316 if (adapter->scsipi_refcnt++ == 0 && 1317 adapter->scsipi_enable != NULL) { 1318 error = (*adapter->scsipi_enable)(wdc, 1); 1319 if (error) 1320 adapter->scsipi_refcnt--; 1321 } 1322 splx(s); 1323 return (error); 1324 } 1325 1326 void 1327 wdc_delref(chp) 1328 struct channel_softc *chp; 1329 { 1330 struct wdc_softc *wdc = chp->wdc; 1331 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1332 int s; 1333 1334 s = splbio(); 1335 if (adapter->scsipi_refcnt-- == 1 && 1336 adapter->scsipi_enable != NULL) 1337 (void) (*adapter->scsipi_enable)(wdc, 0); 1338 splx(s); 1339 } 1340
Indexes created Thu Sep 25 02:09:54 GMT 2025