wdc.c revision 1.60
1 /* $NetBSD: wdc.c,v 1.60 1999/02/21 02:07:52 abs Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(1); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(1); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(1); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(1); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices , then rescan and try an ATA command, in case it's an 235 * old drive. 236 * Fill in drive_flags accordingly 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(1); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } 262 } 263 for (drive = 0; drive < 2; drive++) { 264 if ((ret_value & (0x01 << drive)) == 0 || 265 (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) != 0) 266 continue; 267 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 268 WDSD_IBM | (drive << 4)); 269 delay(1); 270 /* 271 * Maybe it's an old device, so don't rely on ATA sig. 272 * Test registers writability (Error register not writable, 273 * but cyllo is), then try an ATA command. 274 */ 275 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 276 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 277 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 278 0x58 || 279 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 280 0xa5) { 281 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 282 "failed\n", 283 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 284 chp->channel, drive), DEBUG_PROBE); 285 ret_value &= ~(0x01 << drive); 286 continue; 287 } 288 if (wait_for_ready(chp, 10000) != 0) { 289 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 290 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 291 chp->channel, drive), DEBUG_PROBE); 292 ret_value &= ~(0x01 << drive); 293 continue; 294 } 295 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 296 WDCC_DIAGNOSE); 297 if (wait_for_ready(chp, 10000) == 0) { 298 chp->ch_drive[drive].drive_flags |= 299 DRIVE_ATA; 300 } else { 301 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_DIAGNOSE failed\n", 302 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 303 chp->channel, drive), DEBUG_PROBE); 304 ret_value &= ~(0x01 << drive); 305 } 306 } 307 return (ret_value); 308 } 309 310 void 311 wdcattach(chp) 312 struct channel_softc *chp; 313 { 314 int channel_flags, ctrl_flags, i, error; 315 struct ata_atapi_attach aa_link; 316 317 LIST_INIT(&xfer_free_list); 318 for (i = 0; i < 2; i++) { 319 chp->ch_drive[i].chnl_softc = chp; 320 chp->ch_drive[i].drive = i; 321 /* If controller can't do 16bit flag the drives as 32bit */ 322 if ((chp->wdc->cap & 323 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 324 WDC_CAPABILITY_DATA32) 325 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 326 } 327 328 if ((error = wdc_addref(chp)) != 0) { 329 printf("%s: unable to enable controller\n", 330 chp->wdc->sc_dev.dv_xname); 331 return; 332 } 333 334 if (wdcprobe(chp) == 0) { 335 /* If no drives, abort attach here. */ 336 wdc_delref(chp); 337 return; 338 } 339 340 TAILQ_INIT(&chp->ch_queue->sc_xfer); 341 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 342 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 343 344 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 345 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 346 DEBUG_PROBE); 347 348 /* 349 * Attach an ATAPI bus, if needed. 350 */ 351 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 352 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 353 #if NATAPIBUS > 0 354 wdc_atapibus_attach(chp); 355 #else 356 /* 357 * Fills in a fake aa_link and call config_found, so that 358 * the config machinery will print 359 * "atapibus at xxx not configured" 360 */ 361 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 362 aa_link.aa_type = T_ATAPI; 363 aa_link.aa_channel = chp->channel; 364 aa_link.aa_openings = 1; 365 aa_link.aa_drv_data = 0; 366 aa_link.aa_bus_private = NULL; 367 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 368 atapi_print); 369 #endif 370 } 371 372 for (i = 0; i < 2; i++) { 373 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 374 continue; 375 } 376 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 377 aa_link.aa_type = T_ATA; 378 aa_link.aa_channel = chp->channel; 379 aa_link.aa_openings = 1; 380 aa_link.aa_drv_data = &chp->ch_drive[i]; 381 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 382 wdc_probe_caps(&chp->ch_drive[i]); 383 } 384 385 /* 386 * reset drive_flags for unnatached devices, reset state for attached 387 * ones 388 */ 389 for (i = 0; i < 2; i++) { 390 if (chp->ch_drive[i].drv_softc == NULL) 391 chp->ch_drive[i].drive_flags = 0; 392 else 393 chp->ch_drive[i].state = 0; 394 } 395 396 /* 397 * Reset channel. The probe, with some combinations of ATA/ATAPI 398 * devices keep it in a mostly working, but strange state (with busy 399 * led on) 400 */ 401 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 402 wdcreset(chp, VERBOSE); 403 /* 404 * Read status registers to avoid spurious interrupts. 405 */ 406 for (i = 1; i >= 0; i--) { 407 if (chp->ch_drive[i].drive_flags & DRIVE) { 408 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 409 wd_sdh, WDSD_IBM | (i << 4)); 410 if (wait_for_unbusy(chp, 10000) < 0) 411 printf("%s:%d:%d: device busy\n", 412 chp->wdc->sc_dev.dv_xname, 413 chp->channel, i); 414 } 415 } 416 } 417 wdc_delref(chp); 418 } 419 420 /* 421 * Start I/O on a controller, for the given channel. 422 * The first xfer may be not for our channel if the channel queues 423 * are shared. 424 */ 425 void 426 wdcstart(chp) 427 struct channel_softc *chp; 428 { 429 struct wdc_xfer *xfer; 430 431 #ifdef WDC_DIAGNOSTIC 432 int spl1, spl2; 433 434 spl1 = splbio(); 435 spl2 = splbio(); 436 if (spl2 != spl1) { 437 printf("wdcstart: not at splbio()\n"); 438 panic("wdcstart"); 439 } 440 splx(spl2); 441 splx(spl1); 442 #endif /* WDC_DIAGNOSTIC */ 443 444 /* is there a xfer ? */ 445 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 446 return; 447 448 /* adjust chp, in case we have a shared queue */ 449 chp = xfer->chp; 450 451 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 452 return; /* channel aleady active */ 453 } 454 #ifdef DIAGNOSTIC 455 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 456 panic("wdcstart: channel waiting for irq\n"); 457 #endif 458 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 459 if (!(*chp->wdc->claim_hw)(chp, 0)) 460 return; 461 462 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 463 chp->channel, xfer->drive), DEBUG_XFERS); 464 chp->ch_flags |= WDCF_ACTIVE; 465 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 466 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 467 chp->ch_drive[xfer->drive].state = 0; 468 } 469 xfer->c_start(chp, xfer); 470 } 471 472 /* restart an interrupted I/O */ 473 void 474 wdcrestart(v) 475 void *v; 476 { 477 struct channel_softc *chp = v; 478 int s; 479 480 s = splbio(); 481 wdcstart(chp); 482 splx(s); 483 } 484 485 486 /* 487 * Interrupt routine for the controller. Acknowledge the interrupt, check for 488 * errors on the current operation, mark it done if necessary, and start the 489 * next request. Also check for a partially done transfer, and continue with 490 * the next chunk if so. 491 */ 492 int 493 wdcintr(arg) 494 void *arg; 495 { 496 struct channel_softc *chp = arg; 497 struct wdc_xfer *xfer; 498 499 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 500 #if 0 501 /* Clear the pending interrupt and abort. */ 502 u_int8_t s = 503 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 504 #ifdef WDCDEBUG 505 u_int8_t e = 506 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 507 u_int8_t i = 508 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 509 #else 510 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 511 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 512 #endif 513 514 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 515 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 516 517 if (s & WDCS_DRQ) { 518 int len; 519 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 520 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 521 chp->cmd_ioh, wd_cyl_hi); 522 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 523 len), DEBUG_INTR); 524 wdcbit_bucket (chp, len); 525 } 526 #else 527 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 528 #endif 529 return 0; 530 } 531 532 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 533 untimeout(wdctimeout, chp); 534 chp->ch_flags &= ~WDCF_IRQ_WAIT; 535 xfer = chp->ch_queue->sc_xfer.tqh_first; 536 return xfer->c_intr(chp, xfer); 537 } 538 539 /* Put all disk in RESET state */ 540 void wdc_reset_channel(drvp) 541 struct ata_drive_datas *drvp; 542 { 543 struct channel_softc *chp = drvp->chnl_softc; 544 int drive; 545 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 546 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 547 DEBUG_FUNCS); 548 (void) wdcreset(chp, VERBOSE); 549 for (drive = 0; drive < 2; drive++) { 550 chp->ch_drive[drive].state = 0; 551 } 552 } 553 554 int 555 wdcreset(chp, verb) 556 struct channel_softc *chp; 557 int verb; 558 { 559 int drv_mask1, drv_mask2; 560 561 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 562 WDSD_IBM); /* master */ 563 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 564 WDCTL_RST | WDCTL_IDS); 565 delay(1000); 566 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 567 WDCTL_IDS); 568 delay(1000); 569 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 570 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 571 WDCTL_4BIT); 572 573 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 574 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 575 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 576 if (verb && drv_mask2 != drv_mask1) { 577 printf("%s channel %d: reset failed for", 578 chp->wdc->sc_dev.dv_xname, chp->channel); 579 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 580 printf(" drive 0"); 581 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 582 printf(" drive 1"); 583 printf("\n"); 584 } 585 return (drv_mask1 != drv_mask2) ? 1 : 0; 586 } 587 588 static int 589 __wdcwait_reset(chp, drv_mask) 590 struct channel_softc *chp; 591 int drv_mask; 592 { 593 int timeout; 594 u_int8_t st0, st1; 595 /* wait for BSY to deassert */ 596 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 597 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 598 WDSD_IBM); /* master */ 599 delay(1); 600 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 601 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 602 WDSD_IBM | 0x10); /* slave */ 603 delay(1); 604 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 605 606 if ((drv_mask & 0x01) == 0) { 607 /* no master */ 608 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 609 /* No master, slave is ready, it's done */ 610 return drv_mask; 611 } 612 } else if ((drv_mask & 0x02) == 0) { 613 /* no slave */ 614 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 615 /* No slave, master is ready, it's done */ 616 return drv_mask; 617 } 618 } else { 619 /* Wait for both master and slave to be ready */ 620 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 621 return drv_mask; 622 } 623 } 624 delay(WDCDELAY); 625 } 626 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 627 if (st0 & WDCS_BSY) 628 drv_mask &= ~0x01; 629 if (st1 & WDCS_BSY) 630 drv_mask &= ~0x02; 631 return drv_mask; 632 } 633 634 /* 635 * Wait for a drive to be !BSY, and have mask in its status register. 636 * return -1 for a timeout after "timeout" ms. 637 */ 638 int 639 wdcwait(chp, mask, bits, timeout) 640 struct channel_softc *chp; 641 int mask, bits, timeout; 642 { 643 u_char status; 644 int time = 0; 645 #ifdef WDCNDELAY_DEBUG 646 extern int cold; 647 #endif 648 649 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 650 :"none", chp->channel), DEBUG_STATUS); 651 chp->ch_error = 0; 652 653 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 654 655 for (;;) { 656 chp->ch_status = status = 657 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 658 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 659 break; 660 if (++time > timeout) { 661 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 662 "error %x\n", status, 663 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 664 wd_error)), 665 DEBUG_STATUS); 666 return -1; 667 } 668 delay(WDCDELAY); 669 } 670 if (status & WDCS_ERR) 671 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 672 wd_error); 673 #ifdef WDCNDELAY_DEBUG 674 /* After autoconfig, there should be no long delays. */ 675 if (!cold && time > WDCNDELAY_DEBUG) { 676 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 677 if (xfer == NULL) 678 printf("%s channel %d: warning: busy-wait took %dus\n", 679 chp->wdc->sc_dev.dv_xname, chp->channel, 680 WDCDELAY * time); 681 else 682 printf("%s:%d:%d: warning: busy-wait took %dus\n", 683 chp->wdc->sc_dev.dv_xname, chp->channel, 684 xfer->drive, 685 WDCDELAY * time); 686 } 687 #endif 688 return 0; 689 } 690 691 void 692 wdctimeout(arg) 693 void *arg; 694 { 695 struct channel_softc *chp = (struct channel_softc *)arg; 696 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 697 int s; 698 699 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 700 701 s = splbio(); 702 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 703 __wdcerror(chp, "lost interrupt"); 704 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 705 "atapi":"ata"); 706 printf("\tc_bcount: %d\n", xfer->c_bcount); 707 printf("\tc_skip: %d\n", xfer->c_skip); 708 /* 709 * Call the interrupt routine. If we just missed and interrupt, 710 * it will do what's needed. Else, it will take the needed 711 * action (reset the device). 712 */ 713 xfer->c_flags |= C_TIMEOU; 714 chp->ch_flags &= ~WDCF_IRQ_WAIT; 715 xfer->c_intr(chp, xfer); 716 } else 717 __wdcerror(chp, "missing untimeout"); 718 splx(s); 719 } 720 721 /* 722 * Probe drive's capabilites, for use by the controller later 723 * Assumes drvp points to an existing drive. 724 * XXX this should be a controller-indep function 725 */ 726 void 727 wdc_probe_caps(drvp) 728 struct ata_drive_datas *drvp; 729 { 730 struct ataparams params, params2; 731 struct channel_softc *chp = drvp->chnl_softc; 732 struct device *drv_dev = drvp->drv_softc; 733 struct wdc_softc *wdc = chp->wdc; 734 int i, printed; 735 char *sep = ""; 736 int cf_flags; 737 738 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 739 /* IDENTIFY failed. Can't tell more about the device */ 740 return; 741 } 742 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 743 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 744 /* 745 * Controller claims 16 and 32 bit transfers. 746 * Re-do an IDENTIFY with 32-bit transfers, 747 * and compare results. 748 */ 749 drvp->drive_flags |= DRIVE_CAP32; 750 ata_get_params(drvp, AT_POLL, ¶ms2); 751 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 752 /* Not good. fall back to 16bits */ 753 drvp->drive_flags &= ~DRIVE_CAP32; 754 } else { 755 printf("%s: 32-bits data port", drv_dev->dv_xname); 756 } 757 } 758 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 759 if (params.atap_ata_major > 0x01 && 760 params.atap_ata_major != 0xffff) { 761 for (i = 14; i > 0; i--) { 762 if (params.atap_ata_major & (1 << i)) { 763 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 764 printf("%s: ", drv_dev->dv_xname); 765 else 766 printf(", "); 767 printf("ATA version %d\n", i); 768 drvp->ata_vers = i; 769 break; 770 } 771 } 772 } else 773 #endif 774 if (drvp->drive_flags & DRIVE_CAP32) 775 printf("\n"); 776 777 /* An ATAPI device is at last PIO mode 3 */ 778 if (drvp->drive_flags & DRIVE_ATAPI) 779 drvp->PIO_mode = 3; 780 781 /* 782 * It's not in the specs, but it seems that some drive 783 * returns 0xffff in atap_extensions when this field is invalid 784 */ 785 if (params.atap_extensions != 0xffff && 786 (params.atap_extensions & WDC_EXT_MODES)) { 787 printed = 0; 788 /* 789 * XXX some drives report something wrong here (they claim to 790 * support PIO mode 8 !). As mode is coded on 3 bits in 791 * SET FEATURE, limit it to 7 (so limit i to 4). 792 * If higther mode than 7 is found, abort. 793 */ 794 for (i = 7; i >= 0; i--) { 795 if ((params.atap_piomode_supp & (1 << i)) == 0) 796 continue; 797 if (i > 4) 798 return; 799 /* 800 * See if mode is accepted. 801 * If the controller can't set its PIO mode, 802 * assume the defaults are good, so don't try 803 * to set it 804 */ 805 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 806 if (ata_set_mode(drvp, 0x08 | (i + 3), 807 AT_POLL) != CMD_OK) 808 continue; 809 if (!printed) { 810 printf("%s: drive supports PIO mode %d", 811 drv_dev->dv_xname, i + 3); 812 sep = ","; 813 printed = 1; 814 } 815 /* 816 * If controller's driver can't set its PIO mode, 817 * get the highter one for the drive. 818 */ 819 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 820 wdc->PIO_cap >= i + 3) { 821 drvp->PIO_mode = i + 3; 822 drvp->PIO_cap = i + 3; 823 break; 824 } 825 } 826 if (!printed) { 827 /* 828 * We didn't find a valid PIO mode. 829 * Assume the values returned for DMA are buggy too 830 */ 831 return; 832 } 833 drvp->drive_flags |= DRIVE_MODE; 834 printed = 0; 835 for (i = 7; i >= 0; i--) { 836 if ((params.atap_dmamode_supp & (1 << i)) == 0) 837 continue; 838 if ((wdc->cap & WDC_CAPABILITY_DMA) && 839 (wdc->cap & WDC_CAPABILITY_MODE)) 840 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 841 != CMD_OK) 842 continue; 843 if (!printed) { 844 printf("%s DMA mode %d", sep, i); 845 sep = ","; 846 printed = 1; 847 } 848 if (wdc->cap & WDC_CAPABILITY_DMA) { 849 if ((wdc->cap & WDC_CAPABILITY_MODE) && 850 wdc->DMA_cap < i) 851 continue; 852 drvp->DMA_mode = i; 853 drvp->DMA_cap = i; 854 drvp->drive_flags |= DRIVE_DMA; 855 } 856 break; 857 } 858 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 859 for (i = 7; i >= 0; i--) { 860 if ((params.atap_udmamode_supp & (1 << i)) 861 == 0) 862 continue; 863 if ((wdc->cap & WDC_CAPABILITY_MODE) && 864 (wdc->cap & WDC_CAPABILITY_UDMA)) 865 if (ata_set_mode(drvp, 0x40 | i, 866 AT_POLL) != CMD_OK) 867 continue; 868 printf("%s Ultra-DMA mode %d", sep, i); 869 sep = ","; 870 if (wdc->cap & WDC_CAPABILITY_UDMA) { 871 if ((wdc->cap & WDC_CAPABILITY_MODE) && 872 wdc->UDMA_cap < i) 873 continue; 874 drvp->UDMA_mode = i; 875 drvp->UDMA_cap = i; 876 drvp->drive_flags |= DRIVE_UDMA; 877 } 878 break; 879 } 880 } 881 printf("\n"); 882 } 883 884 /* Try to guess ATA version here, if it didn't get reported */ 885 if (drvp->ata_vers == 0) { 886 if (drvp->drive_flags & DRIVE_UDMA) 887 drvp->ata_vers = 4; /* should be at last ATA-4 */ 888 else if (drvp->PIO_cap > 2) 889 drvp->ata_vers = 2; /* should be at last ATA-2 */ 890 } 891 cf_flags = drv_dev->dv_cfdata->cf_flags; 892 if (cf_flags & ATA_CONFIG_PIO_SET) { 893 drvp->PIO_mode = 894 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 895 drvp->drive_flags |= DRIVE_MODE; 896 } 897 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 898 /* don't care about DMA modes */ 899 return; 900 } 901 if (cf_flags & ATA_CONFIG_DMA_SET) { 902 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 903 ATA_CONFIG_DMA_DISABLE) { 904 drvp->drive_flags &= ~DRIVE_DMA; 905 } else { 906 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 907 ATA_CONFIG_DMA_OFF; 908 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 909 } 910 } 911 if (cf_flags & ATA_CONFIG_UDMA_SET) { 912 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 913 ATA_CONFIG_UDMA_DISABLE) { 914 drvp->drive_flags &= ~DRIVE_UDMA; 915 } else { 916 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 917 ATA_CONFIG_UDMA_OFF; 918 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 919 } 920 } 921 } 922 923 /* 924 * downgrade the transfer mode of a drive after an error. return 1 if 925 * downgrade was possible, 0 otherwise. 926 */ 927 int 928 wdc_downgrade_mode(drvp) 929 struct ata_drive_datas *drvp; 930 { 931 struct channel_softc *chp = drvp->chnl_softc; 932 struct device *drv_dev = drvp->drv_softc; 933 struct wdc_softc *wdc = chp->wdc; 934 int cf_flags = drv_dev->dv_cfdata->cf_flags; 935 936 /* if drive or controller don't know its mode, we can't do much */ 937 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 938 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 939 return 0; 940 /* current drive mode was set by a config flag, let it this way */ 941 if ((cf_flags & ATA_CONFIG_PIO_SET) || 942 (cf_flags & ATA_CONFIG_DMA_SET) || 943 (cf_flags & ATA_CONFIG_UDMA_SET)) 944 return 0; 945 946 if (drvp->drive_flags & DRIVE_UDMA) { 947 drvp->drive_flags &= ~DRIVE_UDMA; 948 drvp->drive_flags |= DRIVE_DMA; 949 drvp->DMA_mode = drvp->DMA_cap; 950 printf("%s: transfer error, downgrading to DMA mode %d\n", 951 drv_dev->dv_xname, drvp->DMA_mode); 952 } else if (drvp->drive_flags & DRIVE_DMA) { 953 drvp->drive_flags &= ~DRIVE_DMA; 954 drvp->PIO_mode = drvp->PIO_cap; 955 printf("%s: transfer error, downgrading to PIO mode %d\n", 956 drv_dev->dv_xname, drvp->PIO_mode); 957 } else /* already using PIO, can't downgrade */ 958 return 0; 959 960 wdc->set_modes(chp); 961 /* reset the channel, which will shedule all drives for setup */ 962 wdc_reset_channel(drvp); 963 return 1; 964 } 965 966 int 967 wdc_exec_command(drvp, wdc_c) 968 struct ata_drive_datas *drvp; 969 struct wdc_command *wdc_c; 970 { 971 struct channel_softc *chp = drvp->chnl_softc; 972 struct wdc_xfer *xfer; 973 int s, ret; 974 975 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 976 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 977 DEBUG_FUNCS); 978 979 /* set up an xfer and queue. Wait for completion */ 980 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 981 WDC_NOSLEEP); 982 if (xfer == NULL) { 983 return WDC_TRY_AGAIN; 984 } 985 986 if (wdc_c->flags & AT_POLL) 987 xfer->c_flags |= C_POLL; 988 xfer->drive = drvp->drive; 989 xfer->databuf = wdc_c->data; 990 xfer->c_bcount = wdc_c->bcount; 991 xfer->cmd = wdc_c; 992 xfer->c_start = __wdccommand_start; 993 xfer->c_intr = __wdccommand_intr; 994 995 s = splbio(); 996 wdc_exec_xfer(chp, xfer); 997 #ifdef DIAGNOSTIC 998 if ((wdc_c->flags & AT_POLL) != 0 && 999 (wdc_c->flags & AT_DONE) == 0) 1000 panic("wdc_exec_command: polled command not done\n"); 1001 #endif 1002 if (wdc_c->flags & AT_DONE) { 1003 ret = WDC_COMPLETE; 1004 } else { 1005 if (wdc_c->flags & AT_WAIT) { 1006 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1007 ret = WDC_COMPLETE; 1008 } else { 1009 ret = WDC_QUEUED; 1010 } 1011 } 1012 splx(s); 1013 return ret; 1014 } 1015 1016 void 1017 __wdccommand_start(chp, xfer) 1018 struct channel_softc *chp; 1019 struct wdc_xfer *xfer; 1020 { 1021 int drive = xfer->drive; 1022 struct wdc_command *wdc_c = xfer->cmd; 1023 1024 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1025 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1026 DEBUG_FUNCS); 1027 1028 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1029 WDSD_IBM | (drive << 4)); 1030 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1031 wdc_c->timeout) != 0) { 1032 wdc_c->flags |= AT_TIMEOU; 1033 __wdccommand_done(chp, xfer); 1034 return; 1035 } 1036 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1037 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1038 if ((wdc_c->flags & AT_POLL) == 0) { 1039 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1040 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1041 return; 1042 } 1043 /* 1044 * Polled command. Wait for drive ready or drq. Done in intr(). 1045 * Wait for at last 400ns for status bit to be valid. 1046 */ 1047 delay(10); 1048 if (__wdccommand_intr(chp, xfer) == 0) { 1049 wdc_c->flags |= AT_TIMEOU; 1050 __wdccommand_done(chp, xfer); 1051 } 1052 } 1053 1054 int 1055 __wdccommand_intr(chp, xfer) 1056 struct channel_softc *chp; 1057 struct wdc_xfer *xfer; 1058 { 1059 struct wdc_command *wdc_c = xfer->cmd; 1060 int bcount = wdc_c->bcount; 1061 char *data = wdc_c->data; 1062 1063 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1064 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1065 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1066 wdc_c->timeout)) { 1067 wdc_c->flags |= AT_ERROR; 1068 __wdccommand_done(chp, xfer); 1069 return 1; 1070 } 1071 if (wdc_c->flags & AT_READ) { 1072 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1073 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1074 0, (u_int32_t*)data, bcount >> 2); 1075 data += bcount & 0xfffffffc; 1076 bcount = bcount & 0x03; 1077 } 1078 if (bcount > 0) 1079 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1080 wd_data, (u_int16_t *)data, bcount >> 1); 1081 } else if (wdc_c->flags & AT_WRITE) { 1082 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1083 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1084 0, (u_int32_t*)data, bcount >> 2); 1085 data += bcount & 0xfffffffc; 1086 bcount = bcount & 0x03; 1087 } 1088 if (bcount > 0) 1089 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1090 wd_data, (u_int16_t *)data, bcount >> 1); 1091 } 1092 __wdccommand_done(chp, xfer); 1093 return 1; 1094 } 1095 1096 void 1097 __wdccommand_done(chp, xfer) 1098 struct channel_softc *chp; 1099 struct wdc_xfer *xfer; 1100 { 1101 int needdone = xfer->c_flags & C_NEEDDONE; 1102 struct wdc_command *wdc_c = xfer->cmd; 1103 1104 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1105 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1106 if (chp->ch_status & WDCS_DWF) 1107 wdc_c->flags |= AT_DF; 1108 if (chp->ch_status & WDCS_ERR) { 1109 wdc_c->flags |= AT_ERROR; 1110 wdc_c->r_error = chp->ch_error; 1111 } 1112 wdc_c->flags |= AT_DONE; 1113 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1114 == 0) { 1115 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1116 wd_sdh); 1117 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1118 wd_cyl_hi) << 8; 1119 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1120 wd_cyl_lo); 1121 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1122 wd_sector); 1123 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1124 wd_seccnt); 1125 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1126 wd_error); 1127 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1128 wd_precomp); 1129 } 1130 wdc_free_xfer(chp, xfer); 1131 if (needdone) { 1132 if (wdc_c->flags & AT_WAIT) 1133 wakeup(wdc_c); 1134 else 1135 wdc_c->callback(wdc_c->callback_arg); 1136 } 1137 wdcstart(chp); 1138 return; 1139 } 1140 1141 /* 1142 * Send a command. The drive should be ready. 1143 * Assumes interrupts are blocked. 1144 */ 1145 void 1146 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1147 struct channel_softc *chp; 1148 u_int8_t drive; 1149 u_int8_t command; 1150 u_int16_t cylin; 1151 u_int8_t head, sector, count, precomp; 1152 { 1153 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1154 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1155 chp->channel, drive, command, cylin, head, sector, count, precomp), 1156 DEBUG_FUNCS); 1157 1158 /* Select drive, head, and addressing mode. */ 1159 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1160 WDSD_IBM | (drive << 4) | head); 1161 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1162 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1163 precomp); 1164 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1165 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1166 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1167 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1168 1169 /* Send command. */ 1170 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1171 return; 1172 } 1173 1174 /* 1175 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1176 * tested by the caller. 1177 */ 1178 void 1179 wdccommandshort(chp, drive, command) 1180 struct channel_softc *chp; 1181 int drive; 1182 int command; 1183 { 1184 1185 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1186 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1187 DEBUG_FUNCS); 1188 1189 /* Select drive. */ 1190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1191 WDSD_IBM | (drive << 4)); 1192 1193 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1194 } 1195 1196 /* Add a command to the queue and start controller. Must be called at splbio */ 1197 1198 void 1199 wdc_exec_xfer(chp, xfer) 1200 struct channel_softc *chp; 1201 struct wdc_xfer *xfer; 1202 { 1203 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1204 chp->channel, xfer->drive), DEBUG_XFERS); 1205 1206 /* complete xfer setup */ 1207 xfer->chp = chp; 1208 1209 /* 1210 * If we are a polled command, and the list is not empty, 1211 * we are doing a dump. Drop the list to allow the polled command 1212 * to complete, we're going to reboot soon anyway. 1213 */ 1214 if ((xfer->c_flags & C_POLL) != 0 && 1215 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1216 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1217 } 1218 /* insert at the end of command list */ 1219 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1220 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1221 chp->ch_flags), DEBUG_XFERS); 1222 wdcstart(chp); 1223 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1224 } 1225 1226 struct wdc_xfer * 1227 wdc_get_xfer(flags) 1228 int flags; 1229 { 1230 struct wdc_xfer *xfer; 1231 int s; 1232 1233 s = splbio(); 1234 if ((xfer = xfer_free_list.lh_first) != NULL) { 1235 LIST_REMOVE(xfer, free_list); 1236 splx(s); 1237 #ifdef DIAGNOSTIC 1238 if ((xfer->c_flags & C_INUSE) != 0) 1239 panic("wdc_get_xfer: xfer already in use\n"); 1240 #endif 1241 } else { 1242 splx(s); 1243 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1244 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1245 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1246 if (xfer == NULL) 1247 return 0; 1248 #ifdef DIAGNOSTIC 1249 xfer->c_flags &= ~C_INUSE; 1250 #endif 1251 #ifdef WDCDEBUG 1252 wdc_nxfer++; 1253 #endif 1254 } 1255 #ifdef DIAGNOSTIC 1256 if ((xfer->c_flags & C_INUSE) != 0) 1257 panic("wdc_get_xfer: xfer already in use\n"); 1258 #endif 1259 memset(xfer, 0, sizeof(struct wdc_xfer)); 1260 xfer->c_flags = C_INUSE; 1261 return xfer; 1262 } 1263 1264 void 1265 wdc_free_xfer(chp, xfer) 1266 struct channel_softc *chp; 1267 struct wdc_xfer *xfer; 1268 { 1269 struct wdc_softc *wdc = chp->wdc; 1270 int s; 1271 1272 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1273 (*wdc->free_hw)(chp); 1274 s = splbio(); 1275 chp->ch_flags &= ~WDCF_ACTIVE; 1276 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1277 xfer->c_flags &= ~C_INUSE; 1278 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1279 splx(s); 1280 } 1281 1282 static void 1283 __wdcerror(chp, msg) 1284 struct channel_softc *chp; 1285 char *msg; 1286 { 1287 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1288 if (xfer == NULL) 1289 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1290 msg); 1291 else 1292 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1293 chp->channel, xfer->drive, msg); 1294 } 1295 1296 /* 1297 * the bit bucket 1298 */ 1299 void 1300 wdcbit_bucket(chp, size) 1301 struct channel_softc *chp; 1302 int size; 1303 { 1304 1305 for (; size >= 2; size -= 2) 1306 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1307 if (size) 1308 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1309 } 1310 1311 int 1312 wdc_addref(chp) 1313 struct channel_softc *chp; 1314 { 1315 struct wdc_softc *wdc = chp->wdc; 1316 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1317 int s, error = 0; 1318 1319 s = splbio(); 1320 if (adapter->scsipi_refcnt++ == 0 && 1321 adapter->scsipi_enable != NULL) { 1322 error = (*adapter->scsipi_enable)(wdc, 1); 1323 if (error) 1324 adapter->scsipi_refcnt--; 1325 } 1326 splx(s); 1327 return (error); 1328 } 1329 1330 void 1331 wdc_delref(chp) 1332 struct channel_softc *chp; 1333 { 1334 struct wdc_softc *wdc = chp->wdc; 1335 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1336 int s; 1337 1338 s = splbio(); 1339 if (adapter->scsipi_refcnt-- == 1 && 1340 adapter->scsipi_enable != NULL) 1341 (void) (*adapter->scsipi_enable)(wdc, 0); 1342 splx(s); 1343 } 1344
Indexes created Wed Sep 24 05:09:52 GMT 2025