wdc.c revision 1.63
1 /* $NetBSD: wdc.c,v 1.63 1999/03/25 16:17:36 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(1); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(1); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(1); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(1); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices , then rescan and try an ATA command, in case it's an 235 * old drive. 236 * Fill in drive_flags accordingly 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(1); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else if (sc == 0x01 && sn == 0x01 && 262 cl == 0x00 && ch == 0x00) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 264 } 265 } 266 /* 267 * Maybe there's an old device, try to detect it if we didn't 268 * find a ATA or ATAPI device. 269 */ 270 if ((chp->ch_drive[0].drive_flags & DRIVE) != 0 || 271 (chp->ch_drive[1].drive_flags & DRIVE) != 0) 272 return (ret_value); 273 for (drive = 0; drive < 2; drive++) { 274 if ((ret_value & (0x01 << drive)) == 0) 275 continue; 276 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 277 WDSD_IBM | (drive << 4)); 278 delay(1); 279 /* 280 * Test registers writability (Error register not writable, 281 * but cyllo is), then try an ATA command. 282 */ 283 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 284 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 285 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 286 0x58 || 287 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 288 0xa5) { 289 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 290 "failed\n", 291 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 292 chp->channel, drive), DEBUG_PROBE); 293 ret_value &= ~(0x01 << drive); 294 continue; 295 } 296 if (wait_for_ready(chp, 10000) != 0) { 297 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 298 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 299 chp->channel, drive), DEBUG_PROBE); 300 ret_value &= ~(0x01 << drive); 301 continue; 302 } 303 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 304 WDCC_RECAL); 305 if (wait_for_ready(chp, 10000) == 0) { 306 chp->ch_drive[drive].drive_flags |= 307 DRIVE_OLD; 308 } else { 309 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 310 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 311 chp->channel, drive), DEBUG_PROBE); 312 ret_value &= ~(0x01 << drive); 313 } 314 } 315 return (ret_value); 316 } 317 318 void 319 wdcattach(chp) 320 struct channel_softc *chp; 321 { 322 int channel_flags, ctrl_flags, i, error; 323 struct ata_atapi_attach aa_link; 324 struct ataparams params; 325 static int inited = 0; 326 327 if ((error = wdc_addref(chp)) != 0) { 328 printf("%s: unable to enable controller\n", 329 chp->wdc->sc_dev.dv_xname); 330 return; 331 } 332 333 if (wdcprobe(chp) == 0) { 334 /* If no drives, abort attach here. */ 335 wdc_delref(chp); 336 return; 337 } 338 339 /* init list only once */ 340 if (inited == 0) { 341 LIST_INIT(&xfer_free_list); 342 inited++; 343 } 344 TAILQ_INIT(&chp->ch_queue->sc_xfer); 345 346 for (i = 0; i < 2; i++) { 347 chp->ch_drive[i].chnl_softc = chp; 348 chp->ch_drive[i].drive = i; 349 /* If controller can't do 16bit flag the drives as 32bit */ 350 if ((chp->wdc->cap & 351 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 352 WDC_CAPABILITY_DATA32) 353 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 354 355 /* Issue a IDENTIFY command, to try to detect slave ghost */ 356 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) != 357 CMD_OK) { 358 chp->ch_drive[i].drive_flags &= 359 ~(DRIVE_ATA | DRIVE_ATAPI); 360 } 361 /* 362 * XXX some drives (e.g. some revisions of ZIP) are both ATA 363 * and ATAPI 364 */ 365 if (chp->ch_drive[i].drive_flags & DRIVE_ATA) { 366 if ((params.atap_config & WDC_CFG_ATAPI_MASK) == 367 WDC_CFG_ATAPI) { 368 chp->ch_drive[i].drive_flags &= ~DRIVE_ATA; 369 chp->ch_drive[i].drive_flags |= DRIVE_ATAPI; 370 } 371 } 372 } 373 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 374 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 375 376 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 377 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 378 DEBUG_PROBE); 379 380 /* 381 * Attach an ATAPI bus, if needed. 382 */ 383 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 384 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 385 #if NATAPIBUS > 0 386 wdc_atapibus_attach(chp); 387 #else 388 /* 389 * Fills in a fake aa_link and call config_found, so that 390 * the config machinery will print 391 * "atapibus at xxx not configured" 392 */ 393 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 394 aa_link.aa_type = T_ATAPI; 395 aa_link.aa_channel = chp->channel; 396 aa_link.aa_openings = 1; 397 aa_link.aa_drv_data = 0; 398 aa_link.aa_bus_private = NULL; 399 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 400 atapi_print); 401 #endif 402 } 403 404 for (i = 0; i < 2; i++) { 405 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 406 continue; 407 } 408 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 409 aa_link.aa_type = T_ATA; 410 aa_link.aa_channel = chp->channel; 411 aa_link.aa_openings = 1; 412 aa_link.aa_drv_data = &chp->ch_drive[i]; 413 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 414 wdc_probe_caps(&chp->ch_drive[i]); 415 } 416 417 /* 418 * reset drive_flags for unnatached devices, reset state for attached 419 * ones 420 */ 421 for (i = 0; i < 2; i++) { 422 if (chp->ch_drive[i].drv_softc == NULL) 423 chp->ch_drive[i].drive_flags = 0; 424 else 425 chp->ch_drive[i].state = 0; 426 } 427 428 /* 429 * Reset channel. The probe, with some combinations of ATA/ATAPI 430 * devices keep it in a mostly working, but strange state (with busy 431 * led on) 432 */ 433 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 434 wdcreset(chp, VERBOSE); 435 /* 436 * Read status registers to avoid spurious interrupts. 437 */ 438 for (i = 1; i >= 0; i--) { 439 if (chp->ch_drive[i].drive_flags & DRIVE) { 440 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 441 wd_sdh, WDSD_IBM | (i << 4)); 442 if (wait_for_unbusy(chp, 10000) < 0) 443 printf("%s:%d:%d: device busy\n", 444 chp->wdc->sc_dev.dv_xname, 445 chp->channel, i); 446 } 447 } 448 } 449 wdc_delref(chp); 450 } 451 452 /* 453 * Start I/O on a controller, for the given channel. 454 * The first xfer may be not for our channel if the channel queues 455 * are shared. 456 */ 457 void 458 wdcstart(chp) 459 struct channel_softc *chp; 460 { 461 struct wdc_xfer *xfer; 462 463 #ifdef WDC_DIAGNOSTIC 464 int spl1, spl2; 465 466 spl1 = splbio(); 467 spl2 = splbio(); 468 if (spl2 != spl1) { 469 printf("wdcstart: not at splbio()\n"); 470 panic("wdcstart"); 471 } 472 splx(spl2); 473 splx(spl1); 474 #endif /* WDC_DIAGNOSTIC */ 475 476 /* is there a xfer ? */ 477 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 478 return; 479 480 /* adjust chp, in case we have a shared queue */ 481 chp = xfer->chp; 482 483 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 484 return; /* channel aleady active */ 485 } 486 #ifdef DIAGNOSTIC 487 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 488 panic("wdcstart: channel waiting for irq\n"); 489 #endif 490 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 491 if (!(*chp->wdc->claim_hw)(chp, 0)) 492 return; 493 494 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 495 chp->channel, xfer->drive), DEBUG_XFERS); 496 chp->ch_flags |= WDCF_ACTIVE; 497 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 498 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 499 chp->ch_drive[xfer->drive].state = 0; 500 } 501 xfer->c_start(chp, xfer); 502 } 503 504 /* restart an interrupted I/O */ 505 void 506 wdcrestart(v) 507 void *v; 508 { 509 struct channel_softc *chp = v; 510 int s; 511 512 s = splbio(); 513 wdcstart(chp); 514 splx(s); 515 } 516 517 518 /* 519 * Interrupt routine for the controller. Acknowledge the interrupt, check for 520 * errors on the current operation, mark it done if necessary, and start the 521 * next request. Also check for a partially done transfer, and continue with 522 * the next chunk if so. 523 */ 524 int 525 wdcintr(arg) 526 void *arg; 527 { 528 struct channel_softc *chp = arg; 529 struct wdc_xfer *xfer; 530 531 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 532 #if 0 533 /* Clear the pending interrupt and abort. */ 534 u_int8_t s = 535 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 536 #ifdef WDCDEBUG 537 u_int8_t e = 538 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 539 u_int8_t i = 540 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 541 #else 542 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 543 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 544 #endif 545 546 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 547 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 548 549 if (s & WDCS_DRQ) { 550 int len; 551 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 552 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 553 chp->cmd_ioh, wd_cyl_hi); 554 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 555 len), DEBUG_INTR); 556 wdcbit_bucket (chp, len); 557 } 558 #else 559 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 560 #endif 561 return 0; 562 } 563 564 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 565 untimeout(wdctimeout, chp); 566 chp->ch_flags &= ~WDCF_IRQ_WAIT; 567 xfer = chp->ch_queue->sc_xfer.tqh_first; 568 return xfer->c_intr(chp, xfer); 569 } 570 571 /* Put all disk in RESET state */ 572 void wdc_reset_channel(drvp) 573 struct ata_drive_datas *drvp; 574 { 575 struct channel_softc *chp = drvp->chnl_softc; 576 int drive; 577 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 578 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 579 DEBUG_FUNCS); 580 (void) wdcreset(chp, VERBOSE); 581 for (drive = 0; drive < 2; drive++) { 582 chp->ch_drive[drive].state = 0; 583 } 584 } 585 586 int 587 wdcreset(chp, verb) 588 struct channel_softc *chp; 589 int verb; 590 { 591 int drv_mask1, drv_mask2; 592 593 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 594 WDSD_IBM); /* master */ 595 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 596 WDCTL_RST | WDCTL_IDS); 597 delay(1000); 598 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 599 WDCTL_IDS); 600 delay(1000); 601 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 602 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 603 WDCTL_4BIT); 604 605 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 606 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 607 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 608 if (verb && drv_mask2 != drv_mask1) { 609 printf("%s channel %d: reset failed for", 610 chp->wdc->sc_dev.dv_xname, chp->channel); 611 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 612 printf(" drive 0"); 613 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 614 printf(" drive 1"); 615 printf("\n"); 616 } 617 return (drv_mask1 != drv_mask2) ? 1 : 0; 618 } 619 620 static int 621 __wdcwait_reset(chp, drv_mask) 622 struct channel_softc *chp; 623 int drv_mask; 624 { 625 int timeout; 626 u_int8_t st0, st1; 627 /* wait for BSY to deassert */ 628 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 629 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 630 WDSD_IBM); /* master */ 631 delay(1); 632 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 633 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 634 WDSD_IBM | 0x10); /* slave */ 635 delay(1); 636 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 637 638 if ((drv_mask & 0x01) == 0) { 639 /* no master */ 640 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 641 /* No master, slave is ready, it's done */ 642 return drv_mask; 643 } 644 } else if ((drv_mask & 0x02) == 0) { 645 /* no slave */ 646 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 647 /* No slave, master is ready, it's done */ 648 return drv_mask; 649 } 650 } else { 651 /* Wait for both master and slave to be ready */ 652 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 653 return drv_mask; 654 } 655 } 656 delay(WDCDELAY); 657 } 658 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 659 if (st0 & WDCS_BSY) 660 drv_mask &= ~0x01; 661 if (st1 & WDCS_BSY) 662 drv_mask &= ~0x02; 663 return drv_mask; 664 } 665 666 /* 667 * Wait for a drive to be !BSY, and have mask in its status register. 668 * return -1 for a timeout after "timeout" ms. 669 */ 670 int 671 wdcwait(chp, mask, bits, timeout) 672 struct channel_softc *chp; 673 int mask, bits, timeout; 674 { 675 u_char status; 676 int time = 0; 677 #ifdef WDCNDELAY_DEBUG 678 extern int cold; 679 #endif 680 681 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 682 :"none", chp->channel), DEBUG_STATUS); 683 chp->ch_error = 0; 684 685 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 686 687 for (;;) { 688 chp->ch_status = status = 689 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 690 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 691 break; 692 if (++time > timeout) { 693 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 694 "error %x\n", status, 695 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 696 wd_error)), 697 DEBUG_STATUS); 698 return -1; 699 } 700 delay(WDCDELAY); 701 } 702 if (status & WDCS_ERR) 703 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 704 wd_error); 705 #ifdef WDCNDELAY_DEBUG 706 /* After autoconfig, there should be no long delays. */ 707 if (!cold && time > WDCNDELAY_DEBUG) { 708 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 709 if (xfer == NULL) 710 printf("%s channel %d: warning: busy-wait took %dus\n", 711 chp->wdc->sc_dev.dv_xname, chp->channel, 712 WDCDELAY * time); 713 else 714 printf("%s:%d:%d: warning: busy-wait took %dus\n", 715 chp->wdc->sc_dev.dv_xname, chp->channel, 716 xfer->drive, 717 WDCDELAY * time); 718 } 719 #endif 720 return 0; 721 } 722 723 void 724 wdctimeout(arg) 725 void *arg; 726 { 727 struct channel_softc *chp = (struct channel_softc *)arg; 728 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 729 int s; 730 731 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 732 733 s = splbio(); 734 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 735 __wdcerror(chp, "lost interrupt"); 736 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 737 "atapi":"ata"); 738 printf("\tc_bcount: %d\n", xfer->c_bcount); 739 printf("\tc_skip: %d\n", xfer->c_skip); 740 /* 741 * Call the interrupt routine. If we just missed and interrupt, 742 * it will do what's needed. Else, it will take the needed 743 * action (reset the device). 744 */ 745 xfer->c_flags |= C_TIMEOU; 746 chp->ch_flags &= ~WDCF_IRQ_WAIT; 747 xfer->c_intr(chp, xfer); 748 } else 749 __wdcerror(chp, "missing untimeout"); 750 splx(s); 751 } 752 753 /* 754 * Probe drive's capabilites, for use by the controller later 755 * Assumes drvp points to an existing drive. 756 * XXX this should be a controller-indep function 757 */ 758 void 759 wdc_probe_caps(drvp) 760 struct ata_drive_datas *drvp; 761 { 762 struct ataparams params, params2; 763 struct channel_softc *chp = drvp->chnl_softc; 764 struct device *drv_dev = drvp->drv_softc; 765 struct wdc_softc *wdc = chp->wdc; 766 int i, printed; 767 char *sep = ""; 768 int cf_flags; 769 770 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 771 /* IDENTIFY failed. Can't tell more about the device */ 772 return; 773 } 774 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 775 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 776 /* 777 * Controller claims 16 and 32 bit transfers. 778 * Re-do an IDENTIFY with 32-bit transfers, 779 * and compare results. 780 */ 781 drvp->drive_flags |= DRIVE_CAP32; 782 ata_get_params(drvp, AT_POLL, ¶ms2); 783 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 784 /* Not good. fall back to 16bits */ 785 drvp->drive_flags &= ~DRIVE_CAP32; 786 } else { 787 printf("%s: 32-bits data port", drv_dev->dv_xname); 788 } 789 } 790 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 791 if (params.atap_ata_major > 0x01 && 792 params.atap_ata_major != 0xffff) { 793 for (i = 14; i > 0; i--) { 794 if (params.atap_ata_major & (1 << i)) { 795 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 796 printf("%s: ", drv_dev->dv_xname); 797 else 798 printf(", "); 799 printf("ATA version %d\n", i); 800 drvp->ata_vers = i; 801 break; 802 } 803 } 804 } else 805 #endif 806 if (drvp->drive_flags & DRIVE_CAP32) 807 printf("\n"); 808 809 /* An ATAPI device is at last PIO mode 3 */ 810 if (drvp->drive_flags & DRIVE_ATAPI) 811 drvp->PIO_mode = 3; 812 813 /* 814 * It's not in the specs, but it seems that some drive 815 * returns 0xffff in atap_extensions when this field is invalid 816 */ 817 if (params.atap_extensions != 0xffff && 818 (params.atap_extensions & WDC_EXT_MODES)) { 819 printed = 0; 820 /* 821 * XXX some drives report something wrong here (they claim to 822 * support PIO mode 8 !). As mode is coded on 3 bits in 823 * SET FEATURE, limit it to 7 (so limit i to 4). 824 * If higther mode than 7 is found, abort. 825 */ 826 for (i = 7; i >= 0; i--) { 827 if ((params.atap_piomode_supp & (1 << i)) == 0) 828 continue; 829 if (i > 4) 830 return; 831 /* 832 * See if mode is accepted. 833 * If the controller can't set its PIO mode, 834 * assume the defaults are good, so don't try 835 * to set it 836 */ 837 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 838 if (ata_set_mode(drvp, 0x08 | (i + 3), 839 AT_POLL) != CMD_OK) 840 continue; 841 if (!printed) { 842 printf("%s: drive supports PIO mode %d", 843 drv_dev->dv_xname, i + 3); 844 sep = ","; 845 printed = 1; 846 } 847 /* 848 * If controller's driver can't set its PIO mode, 849 * get the highter one for the drive. 850 */ 851 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 852 wdc->PIO_cap >= i + 3) { 853 drvp->PIO_mode = i + 3; 854 drvp->PIO_cap = i + 3; 855 break; 856 } 857 } 858 if (!printed) { 859 /* 860 * We didn't find a valid PIO mode. 861 * Assume the values returned for DMA are buggy too 862 */ 863 return; 864 } 865 drvp->drive_flags |= DRIVE_MODE; 866 printed = 0; 867 for (i = 7; i >= 0; i--) { 868 if ((params.atap_dmamode_supp & (1 << i)) == 0) 869 continue; 870 if ((wdc->cap & WDC_CAPABILITY_DMA) && 871 (wdc->cap & WDC_CAPABILITY_MODE)) 872 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 873 != CMD_OK) 874 continue; 875 if (!printed) { 876 printf("%s DMA mode %d", sep, i); 877 sep = ","; 878 printed = 1; 879 } 880 if (wdc->cap & WDC_CAPABILITY_DMA) { 881 if ((wdc->cap & WDC_CAPABILITY_MODE) && 882 wdc->DMA_cap < i) 883 continue; 884 drvp->DMA_mode = i; 885 drvp->DMA_cap = i; 886 drvp->drive_flags |= DRIVE_DMA; 887 } 888 break; 889 } 890 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 891 for (i = 7; i >= 0; i--) { 892 if ((params.atap_udmamode_supp & (1 << i)) 893 == 0) 894 continue; 895 if ((wdc->cap & WDC_CAPABILITY_MODE) && 896 (wdc->cap & WDC_CAPABILITY_UDMA)) 897 if (ata_set_mode(drvp, 0x40 | i, 898 AT_POLL) != CMD_OK) 899 continue; 900 printf("%s Ultra-DMA mode %d", sep, i); 901 sep = ","; 902 if (wdc->cap & WDC_CAPABILITY_UDMA) { 903 if ((wdc->cap & WDC_CAPABILITY_MODE) && 904 wdc->UDMA_cap < i) 905 continue; 906 drvp->UDMA_mode = i; 907 drvp->UDMA_cap = i; 908 drvp->drive_flags |= DRIVE_UDMA; 909 } 910 break; 911 } 912 } 913 printf("\n"); 914 } 915 916 /* Try to guess ATA version here, if it didn't get reported */ 917 if (drvp->ata_vers == 0) { 918 if (drvp->drive_flags & DRIVE_UDMA) 919 drvp->ata_vers = 4; /* should be at last ATA-4 */ 920 else if (drvp->PIO_cap > 2) 921 drvp->ata_vers = 2; /* should be at last ATA-2 */ 922 } 923 cf_flags = drv_dev->dv_cfdata->cf_flags; 924 if (cf_flags & ATA_CONFIG_PIO_SET) { 925 drvp->PIO_mode = 926 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 927 drvp->drive_flags |= DRIVE_MODE; 928 } 929 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 930 /* don't care about DMA modes */ 931 return; 932 } 933 if (cf_flags & ATA_CONFIG_DMA_SET) { 934 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 935 ATA_CONFIG_DMA_DISABLE) { 936 drvp->drive_flags &= ~DRIVE_DMA; 937 } else { 938 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 939 ATA_CONFIG_DMA_OFF; 940 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 941 } 942 } 943 if (cf_flags & ATA_CONFIG_UDMA_SET) { 944 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 945 ATA_CONFIG_UDMA_DISABLE) { 946 drvp->drive_flags &= ~DRIVE_UDMA; 947 } else { 948 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 949 ATA_CONFIG_UDMA_OFF; 950 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 951 } 952 } 953 } 954 955 /* 956 * downgrade the transfer mode of a drive after an error. return 1 if 957 * downgrade was possible, 0 otherwise. 958 */ 959 int 960 wdc_downgrade_mode(drvp) 961 struct ata_drive_datas *drvp; 962 { 963 struct channel_softc *chp = drvp->chnl_softc; 964 struct device *drv_dev = drvp->drv_softc; 965 struct wdc_softc *wdc = chp->wdc; 966 int cf_flags = drv_dev->dv_cfdata->cf_flags; 967 968 /* if drive or controller don't know its mode, we can't do much */ 969 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 970 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 971 return 0; 972 /* current drive mode was set by a config flag, let it this way */ 973 if ((cf_flags & ATA_CONFIG_PIO_SET) || 974 (cf_flags & ATA_CONFIG_DMA_SET) || 975 (cf_flags & ATA_CONFIG_UDMA_SET)) 976 return 0; 977 978 /* 979 * If we were using ultra-DMA, don't downgrade to multiword DMA 980 * if we noticed a CRC error. It has been noticed that CRC errors 981 * in ultra-DMA lead to silent data corruption in multiword DMA. 982 * Data corruption is less likely to occur in PIO mode. 983 */ 984 985 if ((drvp->drive_flags & DRIVE_UDMA) && 986 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 987 drvp->drive_flags &= ~DRIVE_UDMA; 988 drvp->drive_flags |= DRIVE_DMA; 989 drvp->DMA_mode = drvp->DMA_cap; 990 printf("%s: transfer error, downgrading to DMA mode %d\n", 991 drv_dev->dv_xname, drvp->DMA_mode); 992 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 993 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 994 drvp->PIO_mode = drvp->PIO_cap; 995 printf("%s: transfer error, downgrading to PIO mode %d\n", 996 drv_dev->dv_xname, drvp->PIO_mode); 997 } else /* already using PIO, can't downgrade */ 998 return 0; 999 1000 wdc->set_modes(chp); 1001 /* reset the channel, which will shedule all drives for setup */ 1002 wdc_reset_channel(drvp); 1003 return 1; 1004 } 1005 1006 int 1007 wdc_exec_command(drvp, wdc_c) 1008 struct ata_drive_datas *drvp; 1009 struct wdc_command *wdc_c; 1010 { 1011 struct channel_softc *chp = drvp->chnl_softc; 1012 struct wdc_xfer *xfer; 1013 int s, ret; 1014 1015 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1016 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1017 DEBUG_FUNCS); 1018 1019 /* set up an xfer and queue. Wait for completion */ 1020 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1021 WDC_NOSLEEP); 1022 if (xfer == NULL) { 1023 return WDC_TRY_AGAIN; 1024 } 1025 1026 if (wdc_c->flags & AT_POLL) 1027 xfer->c_flags |= C_POLL; 1028 xfer->drive = drvp->drive; 1029 xfer->databuf = wdc_c->data; 1030 xfer->c_bcount = wdc_c->bcount; 1031 xfer->cmd = wdc_c; 1032 xfer->c_start = __wdccommand_start; 1033 xfer->c_intr = __wdccommand_intr; 1034 1035 s = splbio(); 1036 wdc_exec_xfer(chp, xfer); 1037 #ifdef DIAGNOSTIC 1038 if ((wdc_c->flags & AT_POLL) != 0 && 1039 (wdc_c->flags & AT_DONE) == 0) 1040 panic("wdc_exec_command: polled command not done\n"); 1041 #endif 1042 if (wdc_c->flags & AT_DONE) { 1043 ret = WDC_COMPLETE; 1044 } else { 1045 if (wdc_c->flags & AT_WAIT) { 1046 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1047 ret = WDC_COMPLETE; 1048 } else { 1049 ret = WDC_QUEUED; 1050 } 1051 } 1052 splx(s); 1053 return ret; 1054 } 1055 1056 void 1057 __wdccommand_start(chp, xfer) 1058 struct channel_softc *chp; 1059 struct wdc_xfer *xfer; 1060 { 1061 int drive = xfer->drive; 1062 struct wdc_command *wdc_c = xfer->cmd; 1063 1064 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1065 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1066 DEBUG_FUNCS); 1067 1068 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1069 WDSD_IBM | (drive << 4)); 1070 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1071 wdc_c->timeout) != 0) { 1072 wdc_c->flags |= AT_TIMEOU; 1073 __wdccommand_done(chp, xfer); 1074 return; 1075 } 1076 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1077 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1078 if ((wdc_c->flags & AT_POLL) == 0) { 1079 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1080 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1081 return; 1082 } 1083 /* 1084 * Polled command. Wait for drive ready or drq. Done in intr(). 1085 * Wait for at last 400ns for status bit to be valid. 1086 */ 1087 delay(10); 1088 __wdccommand_intr(chp, xfer); 1089 } 1090 1091 int 1092 __wdccommand_intr(chp, xfer) 1093 struct channel_softc *chp; 1094 struct wdc_xfer *xfer; 1095 { 1096 struct wdc_command *wdc_c = xfer->cmd; 1097 int bcount = wdc_c->bcount; 1098 char *data = wdc_c->data; 1099 1100 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1101 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1102 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1103 (wdc_c->flags & AT_POLL) ? wdc_c->timeout : 0)) { 1104 if ((xfer->c_flags & C_TIMEOU) == 0) 1105 return 0; /* IRQ was not for us */ 1106 wdc_c->flags |= AT_TIMEOU; 1107 __wdccommand_done(chp, xfer); 1108 return 1; 1109 } 1110 if (wdc_c->flags & AT_READ) { 1111 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1112 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1113 0, (u_int32_t*)data, bcount >> 2); 1114 data += bcount & 0xfffffffc; 1115 bcount = bcount & 0x03; 1116 } 1117 if (bcount > 0) 1118 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1119 wd_data, (u_int16_t *)data, bcount >> 1); 1120 } else if (wdc_c->flags & AT_WRITE) { 1121 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1122 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1123 0, (u_int32_t*)data, bcount >> 2); 1124 data += bcount & 0xfffffffc; 1125 bcount = bcount & 0x03; 1126 } 1127 if (bcount > 0) 1128 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1129 wd_data, (u_int16_t *)data, bcount >> 1); 1130 } 1131 __wdccommand_done(chp, xfer); 1132 return 1; 1133 } 1134 1135 void 1136 __wdccommand_done(chp, xfer) 1137 struct channel_softc *chp; 1138 struct wdc_xfer *xfer; 1139 { 1140 int needdone = xfer->c_flags & C_NEEDDONE; 1141 struct wdc_command *wdc_c = xfer->cmd; 1142 1143 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1144 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1145 if (chp->ch_status & WDCS_DWF) 1146 wdc_c->flags |= AT_DF; 1147 if (chp->ch_status & WDCS_ERR) { 1148 wdc_c->flags |= AT_ERROR; 1149 wdc_c->r_error = chp->ch_error; 1150 } 1151 wdc_c->flags |= AT_DONE; 1152 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1153 == 0) { 1154 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1155 wd_sdh); 1156 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1157 wd_cyl_hi) << 8; 1158 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1159 wd_cyl_lo); 1160 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1161 wd_sector); 1162 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1163 wd_seccnt); 1164 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1165 wd_error); 1166 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1167 wd_precomp); 1168 } 1169 wdc_free_xfer(chp, xfer); 1170 if (needdone) { 1171 if (wdc_c->flags & AT_WAIT) 1172 wakeup(wdc_c); 1173 else 1174 wdc_c->callback(wdc_c->callback_arg); 1175 } 1176 wdcstart(chp); 1177 return; 1178 } 1179 1180 /* 1181 * Send a command. The drive should be ready. 1182 * Assumes interrupts are blocked. 1183 */ 1184 void 1185 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1186 struct channel_softc *chp; 1187 u_int8_t drive; 1188 u_int8_t command; 1189 u_int16_t cylin; 1190 u_int8_t head, sector, count, precomp; 1191 { 1192 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1193 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1194 chp->channel, drive, command, cylin, head, sector, count, precomp), 1195 DEBUG_FUNCS); 1196 1197 /* Select drive, head, and addressing mode. */ 1198 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1199 WDSD_IBM | (drive << 4) | head); 1200 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1201 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1202 precomp); 1203 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1204 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1205 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1207 1208 /* Send command. */ 1209 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1210 return; 1211 } 1212 1213 /* 1214 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1215 * tested by the caller. 1216 */ 1217 void 1218 wdccommandshort(chp, drive, command) 1219 struct channel_softc *chp; 1220 int drive; 1221 int command; 1222 { 1223 1224 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1225 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1226 DEBUG_FUNCS); 1227 1228 /* Select drive. */ 1229 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1230 WDSD_IBM | (drive << 4)); 1231 1232 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1233 } 1234 1235 /* Add a command to the queue and start controller. Must be called at splbio */ 1236 1237 void 1238 wdc_exec_xfer(chp, xfer) 1239 struct channel_softc *chp; 1240 struct wdc_xfer *xfer; 1241 { 1242 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1243 chp->channel, xfer->drive), DEBUG_XFERS); 1244 1245 /* complete xfer setup */ 1246 xfer->chp = chp; 1247 1248 /* 1249 * If we are a polled command, and the list is not empty, 1250 * we are doing a dump. Drop the list to allow the polled command 1251 * to complete, we're going to reboot soon anyway. 1252 */ 1253 if ((xfer->c_flags & C_POLL) != 0 && 1254 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1255 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1256 } 1257 /* insert at the end of command list */ 1258 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1259 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1260 chp->ch_flags), DEBUG_XFERS); 1261 wdcstart(chp); 1262 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1263 } 1264 1265 struct wdc_xfer * 1266 wdc_get_xfer(flags) 1267 int flags; 1268 { 1269 struct wdc_xfer *xfer; 1270 int s; 1271 1272 s = splbio(); 1273 if ((xfer = xfer_free_list.lh_first) != NULL) { 1274 LIST_REMOVE(xfer, free_list); 1275 splx(s); 1276 #ifdef DIAGNOSTIC 1277 if ((xfer->c_flags & C_INUSE) != 0) 1278 panic("wdc_get_xfer: xfer already in use\n"); 1279 #endif 1280 } else { 1281 splx(s); 1282 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1283 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1284 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1285 if (xfer == NULL) 1286 return 0; 1287 #ifdef DIAGNOSTIC 1288 xfer->c_flags &= ~C_INUSE; 1289 #endif 1290 #ifdef WDCDEBUG 1291 wdc_nxfer++; 1292 #endif 1293 } 1294 #ifdef DIAGNOSTIC 1295 if ((xfer->c_flags & C_INUSE) != 0) 1296 panic("wdc_get_xfer: xfer already in use\n"); 1297 #endif 1298 memset(xfer, 0, sizeof(struct wdc_xfer)); 1299 xfer->c_flags = C_INUSE; 1300 return xfer; 1301 } 1302 1303 void 1304 wdc_free_xfer(chp, xfer) 1305 struct channel_softc *chp; 1306 struct wdc_xfer *xfer; 1307 { 1308 struct wdc_softc *wdc = chp->wdc; 1309 int s; 1310 1311 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1312 (*wdc->free_hw)(chp); 1313 s = splbio(); 1314 chp->ch_flags &= ~WDCF_ACTIVE; 1315 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1316 xfer->c_flags &= ~C_INUSE; 1317 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1318 splx(s); 1319 } 1320 1321 static void 1322 __wdcerror(chp, msg) 1323 struct channel_softc *chp; 1324 char *msg; 1325 { 1326 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1327 if (xfer == NULL) 1328 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1329 msg); 1330 else 1331 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1332 chp->channel, xfer->drive, msg); 1333 } 1334 1335 /* 1336 * the bit bucket 1337 */ 1338 void 1339 wdcbit_bucket(chp, size) 1340 struct channel_softc *chp; 1341 int size; 1342 { 1343 1344 for (; size >= 2; size -= 2) 1345 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1346 if (size) 1347 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1348 } 1349 1350 int 1351 wdc_addref(chp) 1352 struct channel_softc *chp; 1353 { 1354 struct wdc_softc *wdc = chp->wdc; 1355 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1356 int s, error = 0; 1357 1358 s = splbio(); 1359 if (adapter->scsipi_refcnt++ == 0 && 1360 adapter->scsipi_enable != NULL) { 1361 error = (*adapter->scsipi_enable)(wdc, 1); 1362 if (error) 1363 adapter->scsipi_refcnt--; 1364 } 1365 splx(s); 1366 return (error); 1367 } 1368 1369 void 1370 wdc_delref(chp) 1371 struct channel_softc *chp; 1372 { 1373 struct wdc_softc *wdc = chp->wdc; 1374 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1375 int s; 1376 1377 s = splbio(); 1378 if (adapter->scsipi_refcnt-- == 1 && 1379 adapter->scsipi_enable != NULL) 1380 (void) (*adapter->scsipi_enable)(wdc, 0); 1381 splx(s); 1382 } 1383
Indexes created Tue Sep 23 21:09:50 GMT 2025