wdc.c revision 1.65
1 /* $NetBSD: wdc.c,v 1.65 1999/03/31 11:18:31 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(10); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(10); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(10); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(10); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices , then rescan and try an ATA command, in case it's an 235 * old drive. 236 * Fill in drive_flags accordingly 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(10); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else if (sc == 0x01 && sn == 0x01 && 262 cl == 0x00 && ch == 0x00) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 264 } 265 } 266 /* 267 * Maybe there's an old device, try to detect it if we didn't 268 * find a ATA or ATAPI device. 269 */ 270 if ((chp->ch_drive[0].drive_flags & DRIVE) != 0 || 271 (chp->ch_drive[1].drive_flags & DRIVE) != 0) 272 return (ret_value); 273 for (drive = 0; drive < 2; drive++) { 274 if ((ret_value & (0x01 << drive)) == 0) 275 continue; 276 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 277 WDSD_IBM | (drive << 4)); 278 delay(10); 279 /* 280 * Test registers writability (Error register not writable, 281 * but cyllo is), then try an ATA command. 282 */ 283 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 284 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 285 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 286 0x58 || 287 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 288 0xa5) { 289 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 290 "failed\n", 291 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 292 chp->channel, drive), DEBUG_PROBE); 293 ret_value &= ~(0x01 << drive); 294 continue; 295 } 296 if (wait_for_ready(chp, 10000) != 0) { 297 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 298 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 299 chp->channel, drive), DEBUG_PROBE); 300 ret_value &= ~(0x01 << drive); 301 continue; 302 } 303 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 304 WDCC_RECAL); 305 if (wait_for_ready(chp, 10000) == 0) { 306 chp->ch_drive[drive].drive_flags |= 307 DRIVE_OLD; 308 } else { 309 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 310 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 311 chp->channel, drive), DEBUG_PROBE); 312 ret_value &= ~(0x01 << drive); 313 } 314 } 315 return (ret_value); 316 } 317 318 void 319 wdcattach(chp) 320 struct channel_softc *chp; 321 { 322 int channel_flags, ctrl_flags, i, error; 323 struct ata_atapi_attach aa_link; 324 struct ataparams params; 325 static int inited = 0; 326 327 if ((error = wdc_addref(chp)) != 0) { 328 printf("%s: unable to enable controller\n", 329 chp->wdc->sc_dev.dv_xname); 330 return; 331 } 332 333 if (wdcprobe(chp) == 0) { 334 /* If no drives, abort attach here. */ 335 wdc_delref(chp); 336 return; 337 } 338 339 /* init list only once */ 340 if (inited == 0) { 341 LIST_INIT(&xfer_free_list); 342 inited++; 343 } 344 TAILQ_INIT(&chp->ch_queue->sc_xfer); 345 346 for (i = 0; i < 2; i++) { 347 chp->ch_drive[i].chnl_softc = chp; 348 chp->ch_drive[i].drive = i; 349 /* If controller can't do 16bit flag the drives as 32bit */ 350 if ((chp->wdc->cap & 351 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 352 WDC_CAPABILITY_DATA32) 353 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 354 355 /* Issue a IDENTIFY command, to try to detect slave ghost */ 356 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) != 357 CMD_OK) { 358 chp->ch_drive[i].drive_flags &= 359 ~(DRIVE_ATA | DRIVE_ATAPI); 360 } 361 } 362 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 363 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 364 365 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 366 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 367 DEBUG_PROBE); 368 369 /* 370 * Attach an ATAPI bus, if needed. 371 */ 372 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 373 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 374 #if NATAPIBUS > 0 375 wdc_atapibus_attach(chp); 376 #else 377 /* 378 * Fills in a fake aa_link and call config_found, so that 379 * the config machinery will print 380 * "atapibus at xxx not configured" 381 */ 382 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 383 aa_link.aa_type = T_ATAPI; 384 aa_link.aa_channel = chp->channel; 385 aa_link.aa_openings = 1; 386 aa_link.aa_drv_data = 0; 387 aa_link.aa_bus_private = NULL; 388 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 389 atapi_print); 390 #endif 391 } 392 393 for (i = 0; i < 2; i++) { 394 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 395 continue; 396 } 397 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 398 aa_link.aa_type = T_ATA; 399 aa_link.aa_channel = chp->channel; 400 aa_link.aa_openings = 1; 401 aa_link.aa_drv_data = &chp->ch_drive[i]; 402 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 403 wdc_probe_caps(&chp->ch_drive[i]); 404 } 405 406 /* 407 * reset drive_flags for unnatached devices, reset state for attached 408 * ones 409 */ 410 for (i = 0; i < 2; i++) { 411 if (chp->ch_drive[i].drv_softc == NULL) 412 chp->ch_drive[i].drive_flags = 0; 413 else 414 chp->ch_drive[i].state = 0; 415 } 416 417 /* 418 * Reset channel. The probe, with some combinations of ATA/ATAPI 419 * devices keep it in a mostly working, but strange state (with busy 420 * led on) 421 */ 422 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 423 wdcreset(chp, VERBOSE); 424 /* 425 * Read status registers to avoid spurious interrupts. 426 */ 427 for (i = 1; i >= 0; i--) { 428 if (chp->ch_drive[i].drive_flags & DRIVE) { 429 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 430 wd_sdh, WDSD_IBM | (i << 4)); 431 if (wait_for_unbusy(chp, 10000) < 0) 432 printf("%s:%d:%d: device busy\n", 433 chp->wdc->sc_dev.dv_xname, 434 chp->channel, i); 435 } 436 } 437 } 438 wdc_delref(chp); 439 } 440 441 /* 442 * Start I/O on a controller, for the given channel. 443 * The first xfer may be not for our channel if the channel queues 444 * are shared. 445 */ 446 void 447 wdcstart(chp) 448 struct channel_softc *chp; 449 { 450 struct wdc_xfer *xfer; 451 452 #ifdef WDC_DIAGNOSTIC 453 int spl1, spl2; 454 455 spl1 = splbio(); 456 spl2 = splbio(); 457 if (spl2 != spl1) { 458 printf("wdcstart: not at splbio()\n"); 459 panic("wdcstart"); 460 } 461 splx(spl2); 462 splx(spl1); 463 #endif /* WDC_DIAGNOSTIC */ 464 465 /* is there a xfer ? */ 466 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 467 return; 468 469 /* adjust chp, in case we have a shared queue */ 470 chp = xfer->chp; 471 472 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 473 return; /* channel aleady active */ 474 } 475 #ifdef DIAGNOSTIC 476 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 477 panic("wdcstart: channel waiting for irq\n"); 478 #endif 479 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 480 if (!(*chp->wdc->claim_hw)(chp, 0)) 481 return; 482 483 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 484 chp->channel, xfer->drive), DEBUG_XFERS); 485 chp->ch_flags |= WDCF_ACTIVE; 486 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 487 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 488 chp->ch_drive[xfer->drive].state = 0; 489 } 490 xfer->c_start(chp, xfer); 491 } 492 493 /* restart an interrupted I/O */ 494 void 495 wdcrestart(v) 496 void *v; 497 { 498 struct channel_softc *chp = v; 499 int s; 500 501 s = splbio(); 502 wdcstart(chp); 503 splx(s); 504 } 505 506 507 /* 508 * Interrupt routine for the controller. Acknowledge the interrupt, check for 509 * errors on the current operation, mark it done if necessary, and start the 510 * next request. Also check for a partially done transfer, and continue with 511 * the next chunk if so. 512 */ 513 int 514 wdcintr(arg) 515 void *arg; 516 { 517 struct channel_softc *chp = arg; 518 struct wdc_xfer *xfer; 519 520 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 521 #if 0 522 /* Clear the pending interrupt and abort. */ 523 u_int8_t s = 524 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 525 #ifdef WDCDEBUG 526 u_int8_t e = 527 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 528 u_int8_t i = 529 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 530 #else 531 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 532 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 533 #endif 534 535 WDCDEBUG_PRINT(("wdcintr: inactive controller, " 536 "punting st=%02x er=%02x irr=%02x\n", s, e, i), DEBUG_INTR); 537 538 if (s & WDCS_DRQ) { 539 int len; 540 len = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 541 wd_cyl_lo) + 256 * bus_space_read_1(chp->cmd_iot, 542 chp->cmd_ioh, wd_cyl_hi); 543 WDCDEBUG_PRINT(("wdcintr: clearing up %d bytes\n", 544 len), DEBUG_INTR); 545 wdcbit_bucket (chp, len); 546 } 547 #else 548 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 549 #endif 550 return 0; 551 } 552 553 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 554 untimeout(wdctimeout, chp); 555 chp->ch_flags &= ~WDCF_IRQ_WAIT; 556 xfer = chp->ch_queue->sc_xfer.tqh_first; 557 return xfer->c_intr(chp, xfer); 558 } 559 560 /* Put all disk in RESET state */ 561 void wdc_reset_channel(drvp) 562 struct ata_drive_datas *drvp; 563 { 564 struct channel_softc *chp = drvp->chnl_softc; 565 int drive; 566 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 567 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 568 DEBUG_FUNCS); 569 (void) wdcreset(chp, VERBOSE); 570 for (drive = 0; drive < 2; drive++) { 571 chp->ch_drive[drive].state = 0; 572 } 573 } 574 575 int 576 wdcreset(chp, verb) 577 struct channel_softc *chp; 578 int verb; 579 { 580 int drv_mask1, drv_mask2; 581 582 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 583 WDSD_IBM); /* master */ 584 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 585 WDCTL_RST | WDCTL_IDS); 586 delay(1000); 587 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 588 WDCTL_IDS); 589 delay(1000); 590 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 591 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 592 WDCTL_4BIT); 593 594 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 595 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 596 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 597 if (verb && drv_mask2 != drv_mask1) { 598 printf("%s channel %d: reset failed for", 599 chp->wdc->sc_dev.dv_xname, chp->channel); 600 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 601 printf(" drive 0"); 602 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 603 printf(" drive 1"); 604 printf("\n"); 605 } 606 return (drv_mask1 != drv_mask2) ? 1 : 0; 607 } 608 609 static int 610 __wdcwait_reset(chp, drv_mask) 611 struct channel_softc *chp; 612 int drv_mask; 613 { 614 int timeout; 615 u_int8_t st0, st1; 616 /* wait for BSY to deassert */ 617 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 618 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 619 WDSD_IBM); /* master */ 620 delay(10); 621 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 622 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 623 WDSD_IBM | 0x10); /* slave */ 624 delay(10); 625 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 626 627 if ((drv_mask & 0x01) == 0) { 628 /* no master */ 629 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 630 /* No master, slave is ready, it's done */ 631 goto end; 632 } 633 } else if ((drv_mask & 0x02) == 0) { 634 /* no slave */ 635 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 636 /* No slave, master is ready, it's done */ 637 goto end; 638 } 639 } else { 640 /* Wait for both master and slave to be ready */ 641 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 642 goto end; 643 } 644 } 645 delay(WDCDELAY); 646 } 647 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 648 if (st0 & WDCS_BSY) 649 drv_mask &= ~0x01; 650 if (st1 & WDCS_BSY) 651 drv_mask &= ~0x02; 652 end: 653 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 654 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 655 st0, st1), DEBUG_PROBE); 656 657 return drv_mask; 658 } 659 660 /* 661 * Wait for a drive to be !BSY, and have mask in its status register. 662 * return -1 for a timeout after "timeout" ms. 663 */ 664 int 665 wdcwait(chp, mask, bits, timeout) 666 struct channel_softc *chp; 667 int mask, bits, timeout; 668 { 669 u_char status; 670 int time = 0; 671 #ifdef WDCNDELAY_DEBUG 672 extern int cold; 673 #endif 674 675 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 676 :"none", chp->channel), DEBUG_STATUS); 677 chp->ch_error = 0; 678 679 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 680 681 for (;;) { 682 chp->ch_status = status = 683 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 684 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 685 break; 686 if (++time > timeout) { 687 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 688 "error %x\n", status, 689 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 690 wd_error)), 691 DEBUG_STATUS); 692 return -1; 693 } 694 delay(WDCDELAY); 695 } 696 if (status & WDCS_ERR) 697 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 698 wd_error); 699 #ifdef WDCNDELAY_DEBUG 700 /* After autoconfig, there should be no long delays. */ 701 if (!cold && time > WDCNDELAY_DEBUG) { 702 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 703 if (xfer == NULL) 704 printf("%s channel %d: warning: busy-wait took %dus\n", 705 chp->wdc->sc_dev.dv_xname, chp->channel, 706 WDCDELAY * time); 707 else 708 printf("%s:%d:%d: warning: busy-wait took %dus\n", 709 chp->wdc->sc_dev.dv_xname, chp->channel, 710 xfer->drive, 711 WDCDELAY * time); 712 } 713 #endif 714 return 0; 715 } 716 717 void 718 wdctimeout(arg) 719 void *arg; 720 { 721 struct channel_softc *chp = (struct channel_softc *)arg; 722 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 723 int s; 724 725 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 726 727 s = splbio(); 728 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 729 __wdcerror(chp, "lost interrupt"); 730 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 731 "atapi":"ata"); 732 printf("\tc_bcount: %d\n", xfer->c_bcount); 733 printf("\tc_skip: %d\n", xfer->c_skip); 734 /* 735 * Call the interrupt routine. If we just missed and interrupt, 736 * it will do what's needed. Else, it will take the needed 737 * action (reset the device). 738 */ 739 xfer->c_flags |= C_TIMEOU; 740 chp->ch_flags &= ~WDCF_IRQ_WAIT; 741 xfer->c_intr(chp, xfer); 742 } else 743 __wdcerror(chp, "missing untimeout"); 744 splx(s); 745 } 746 747 /* 748 * Probe drive's capabilites, for use by the controller later 749 * Assumes drvp points to an existing drive. 750 * XXX this should be a controller-indep function 751 */ 752 void 753 wdc_probe_caps(drvp) 754 struct ata_drive_datas *drvp; 755 { 756 struct ataparams params, params2; 757 struct channel_softc *chp = drvp->chnl_softc; 758 struct device *drv_dev = drvp->drv_softc; 759 struct wdc_softc *wdc = chp->wdc; 760 int i, printed; 761 char *sep = ""; 762 int cf_flags; 763 764 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 765 /* IDENTIFY failed. Can't tell more about the device */ 766 return; 767 } 768 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 769 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 770 /* 771 * Controller claims 16 and 32 bit transfers. 772 * Re-do an IDENTIFY with 32-bit transfers, 773 * and compare results. 774 */ 775 drvp->drive_flags |= DRIVE_CAP32; 776 ata_get_params(drvp, AT_POLL, ¶ms2); 777 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 778 /* Not good. fall back to 16bits */ 779 drvp->drive_flags &= ~DRIVE_CAP32; 780 } else { 781 printf("%s: 32-bits data port", drv_dev->dv_xname); 782 } 783 } 784 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 785 if (params.atap_ata_major > 0x01 && 786 params.atap_ata_major != 0xffff) { 787 for (i = 14; i > 0; i--) { 788 if (params.atap_ata_major & (1 << i)) { 789 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 790 printf("%s: ", drv_dev->dv_xname); 791 else 792 printf(", "); 793 printf("ATA version %d\n", i); 794 drvp->ata_vers = i; 795 break; 796 } 797 } 798 } else 799 #endif 800 if (drvp->drive_flags & DRIVE_CAP32) 801 printf("\n"); 802 803 /* An ATAPI device is at last PIO mode 3 */ 804 if (drvp->drive_flags & DRIVE_ATAPI) 805 drvp->PIO_mode = 3; 806 807 /* 808 * It's not in the specs, but it seems that some drive 809 * returns 0xffff in atap_extensions when this field is invalid 810 */ 811 if (params.atap_extensions != 0xffff && 812 (params.atap_extensions & WDC_EXT_MODES)) { 813 printed = 0; 814 /* 815 * XXX some drives report something wrong here (they claim to 816 * support PIO mode 8 !). As mode is coded on 3 bits in 817 * SET FEATURE, limit it to 7 (so limit i to 4). 818 * If higther mode than 7 is found, abort. 819 */ 820 for (i = 7; i >= 0; i--) { 821 if ((params.atap_piomode_supp & (1 << i)) == 0) 822 continue; 823 if (i > 4) 824 return; 825 /* 826 * See if mode is accepted. 827 * If the controller can't set its PIO mode, 828 * assume the defaults are good, so don't try 829 * to set it 830 */ 831 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 832 if (ata_set_mode(drvp, 0x08 | (i + 3), 833 AT_POLL) != CMD_OK) 834 continue; 835 if (!printed) { 836 printf("%s: drive supports PIO mode %d", 837 drv_dev->dv_xname, i + 3); 838 sep = ","; 839 printed = 1; 840 } 841 /* 842 * If controller's driver can't set its PIO mode, 843 * get the highter one for the drive. 844 */ 845 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 846 wdc->PIO_cap >= i + 3) { 847 drvp->PIO_mode = i + 3; 848 drvp->PIO_cap = i + 3; 849 break; 850 } 851 } 852 if (!printed) { 853 /* 854 * We didn't find a valid PIO mode. 855 * Assume the values returned for DMA are buggy too 856 */ 857 return; 858 } 859 drvp->drive_flags |= DRIVE_MODE; 860 printed = 0; 861 for (i = 7; i >= 0; i--) { 862 if ((params.atap_dmamode_supp & (1 << i)) == 0) 863 continue; 864 if ((wdc->cap & WDC_CAPABILITY_DMA) && 865 (wdc->cap & WDC_CAPABILITY_MODE)) 866 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 867 != CMD_OK) 868 continue; 869 if (!printed) { 870 printf("%s DMA mode %d", sep, i); 871 sep = ","; 872 printed = 1; 873 } 874 if (wdc->cap & WDC_CAPABILITY_DMA) { 875 if ((wdc->cap & WDC_CAPABILITY_MODE) && 876 wdc->DMA_cap < i) 877 continue; 878 drvp->DMA_mode = i; 879 drvp->DMA_cap = i; 880 drvp->drive_flags |= DRIVE_DMA; 881 } 882 break; 883 } 884 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 885 for (i = 7; i >= 0; i--) { 886 if ((params.atap_udmamode_supp & (1 << i)) 887 == 0) 888 continue; 889 if ((wdc->cap & WDC_CAPABILITY_MODE) && 890 (wdc->cap & WDC_CAPABILITY_UDMA)) 891 if (ata_set_mode(drvp, 0x40 | i, 892 AT_POLL) != CMD_OK) 893 continue; 894 printf("%s Ultra-DMA mode %d", sep, i); 895 sep = ","; 896 if (wdc->cap & WDC_CAPABILITY_UDMA) { 897 if ((wdc->cap & WDC_CAPABILITY_MODE) && 898 wdc->UDMA_cap < i) 899 continue; 900 drvp->UDMA_mode = i; 901 drvp->UDMA_cap = i; 902 drvp->drive_flags |= DRIVE_UDMA; 903 } 904 break; 905 } 906 } 907 printf("\n"); 908 } 909 910 /* Try to guess ATA version here, if it didn't get reported */ 911 if (drvp->ata_vers == 0) { 912 if (drvp->drive_flags & DRIVE_UDMA) 913 drvp->ata_vers = 4; /* should be at last ATA-4 */ 914 else if (drvp->PIO_cap > 2) 915 drvp->ata_vers = 2; /* should be at last ATA-2 */ 916 } 917 cf_flags = drv_dev->dv_cfdata->cf_flags; 918 if (cf_flags & ATA_CONFIG_PIO_SET) { 919 drvp->PIO_mode = 920 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 921 drvp->drive_flags |= DRIVE_MODE; 922 } 923 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 924 /* don't care about DMA modes */ 925 return; 926 } 927 if (cf_flags & ATA_CONFIG_DMA_SET) { 928 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 929 ATA_CONFIG_DMA_DISABLE) { 930 drvp->drive_flags &= ~DRIVE_DMA; 931 } else { 932 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 933 ATA_CONFIG_DMA_OFF; 934 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 935 } 936 } 937 if (cf_flags & ATA_CONFIG_UDMA_SET) { 938 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 939 ATA_CONFIG_UDMA_DISABLE) { 940 drvp->drive_flags &= ~DRIVE_UDMA; 941 } else { 942 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 943 ATA_CONFIG_UDMA_OFF; 944 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 945 } 946 } 947 } 948 949 /* 950 * downgrade the transfer mode of a drive after an error. return 1 if 951 * downgrade was possible, 0 otherwise. 952 */ 953 int 954 wdc_downgrade_mode(drvp) 955 struct ata_drive_datas *drvp; 956 { 957 struct channel_softc *chp = drvp->chnl_softc; 958 struct device *drv_dev = drvp->drv_softc; 959 struct wdc_softc *wdc = chp->wdc; 960 int cf_flags = drv_dev->dv_cfdata->cf_flags; 961 962 /* if drive or controller don't know its mode, we can't do much */ 963 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 964 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 965 return 0; 966 /* current drive mode was set by a config flag, let it this way */ 967 if ((cf_flags & ATA_CONFIG_PIO_SET) || 968 (cf_flags & ATA_CONFIG_DMA_SET) || 969 (cf_flags & ATA_CONFIG_UDMA_SET)) 970 return 0; 971 972 /* 973 * If we were using ultra-DMA, don't downgrade to multiword DMA 974 * if we noticed a CRC error. It has been noticed that CRC errors 975 * in ultra-DMA lead to silent data corruption in multiword DMA. 976 * Data corruption is less likely to occur in PIO mode. 977 */ 978 979 if ((drvp->drive_flags & DRIVE_UDMA) && 980 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 981 drvp->drive_flags &= ~DRIVE_UDMA; 982 drvp->drive_flags |= DRIVE_DMA; 983 drvp->DMA_mode = drvp->DMA_cap; 984 printf("%s: transfer error, downgrading to DMA mode %d\n", 985 drv_dev->dv_xname, drvp->DMA_mode); 986 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 987 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 988 drvp->PIO_mode = drvp->PIO_cap; 989 printf("%s: transfer error, downgrading to PIO mode %d\n", 990 drv_dev->dv_xname, drvp->PIO_mode); 991 } else /* already using PIO, can't downgrade */ 992 return 0; 993 994 wdc->set_modes(chp); 995 /* reset the channel, which will shedule all drives for setup */ 996 wdc_reset_channel(drvp); 997 return 1; 998 } 999 1000 int 1001 wdc_exec_command(drvp, wdc_c) 1002 struct ata_drive_datas *drvp; 1003 struct wdc_command *wdc_c; 1004 { 1005 struct channel_softc *chp = drvp->chnl_softc; 1006 struct wdc_xfer *xfer; 1007 int s, ret; 1008 1009 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1010 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1011 DEBUG_FUNCS); 1012 1013 /* set up an xfer and queue. Wait for completion */ 1014 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1015 WDC_NOSLEEP); 1016 if (xfer == NULL) { 1017 return WDC_TRY_AGAIN; 1018 } 1019 1020 if (wdc_c->flags & AT_POLL) 1021 xfer->c_flags |= C_POLL; 1022 xfer->drive = drvp->drive; 1023 xfer->databuf = wdc_c->data; 1024 xfer->c_bcount = wdc_c->bcount; 1025 xfer->cmd = wdc_c; 1026 xfer->c_start = __wdccommand_start; 1027 xfer->c_intr = __wdccommand_intr; 1028 1029 s = splbio(); 1030 wdc_exec_xfer(chp, xfer); 1031 #ifdef DIAGNOSTIC 1032 if ((wdc_c->flags & AT_POLL) != 0 && 1033 (wdc_c->flags & AT_DONE) == 0) 1034 panic("wdc_exec_command: polled command not done\n"); 1035 #endif 1036 if (wdc_c->flags & AT_DONE) { 1037 ret = WDC_COMPLETE; 1038 } else { 1039 if (wdc_c->flags & AT_WAIT) { 1040 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1041 ret = WDC_COMPLETE; 1042 } else { 1043 ret = WDC_QUEUED; 1044 } 1045 } 1046 splx(s); 1047 return ret; 1048 } 1049 1050 void 1051 __wdccommand_start(chp, xfer) 1052 struct channel_softc *chp; 1053 struct wdc_xfer *xfer; 1054 { 1055 int drive = xfer->drive; 1056 struct wdc_command *wdc_c = xfer->cmd; 1057 1058 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1059 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1060 DEBUG_FUNCS); 1061 1062 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1063 WDSD_IBM | (drive << 4)); 1064 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1065 wdc_c->timeout) != 0) { 1066 wdc_c->flags |= AT_TIMEOU; 1067 __wdccommand_done(chp, xfer); 1068 return; 1069 } 1070 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1071 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1072 if ((wdc_c->flags & AT_POLL) == 0) { 1073 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1074 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1075 return; 1076 } 1077 /* 1078 * Polled command. Wait for drive ready or drq. Done in intr(). 1079 * Wait for at last 400ns for status bit to be valid. 1080 */ 1081 delay(10); 1082 __wdccommand_intr(chp, xfer); 1083 } 1084 1085 int 1086 __wdccommand_intr(chp, xfer) 1087 struct channel_softc *chp; 1088 struct wdc_xfer *xfer; 1089 { 1090 struct wdc_command *wdc_c = xfer->cmd; 1091 int bcount = wdc_c->bcount; 1092 char *data = wdc_c->data; 1093 1094 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1095 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1096 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1097 (wdc_c->flags & AT_POLL) ? wdc_c->timeout : 0)) { 1098 if ((xfer->c_flags & C_TIMEOU) == 0 && 1099 (wdc_c->flags & AT_POLL) == 0) 1100 return 0; /* IRQ was not for us */ 1101 wdc_c->flags |= AT_TIMEOU; 1102 __wdccommand_done(chp, xfer); 1103 return 1; 1104 } 1105 if (wdc_c->flags & AT_READ) { 1106 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1107 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1108 0, (u_int32_t*)data, bcount >> 2); 1109 data += bcount & 0xfffffffc; 1110 bcount = bcount & 0x03; 1111 } 1112 if (bcount > 0) 1113 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1114 wd_data, (u_int16_t *)data, bcount >> 1); 1115 } else if (wdc_c->flags & AT_WRITE) { 1116 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1117 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1118 0, (u_int32_t*)data, bcount >> 2); 1119 data += bcount & 0xfffffffc; 1120 bcount = bcount & 0x03; 1121 } 1122 if (bcount > 0) 1123 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1124 wd_data, (u_int16_t *)data, bcount >> 1); 1125 } 1126 __wdccommand_done(chp, xfer); 1127 return 1; 1128 } 1129 1130 void 1131 __wdccommand_done(chp, xfer) 1132 struct channel_softc *chp; 1133 struct wdc_xfer *xfer; 1134 { 1135 int needdone = xfer->c_flags & C_NEEDDONE; 1136 struct wdc_command *wdc_c = xfer->cmd; 1137 1138 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1139 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1140 if (chp->ch_status & WDCS_DWF) 1141 wdc_c->flags |= AT_DF; 1142 if (chp->ch_status & WDCS_ERR) { 1143 wdc_c->flags |= AT_ERROR; 1144 wdc_c->r_error = chp->ch_error; 1145 } 1146 wdc_c->flags |= AT_DONE; 1147 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1148 == 0) { 1149 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1150 wd_sdh); 1151 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1152 wd_cyl_hi) << 8; 1153 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1154 wd_cyl_lo); 1155 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1156 wd_sector); 1157 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1158 wd_seccnt); 1159 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1160 wd_error); 1161 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1162 wd_precomp); 1163 } 1164 wdc_free_xfer(chp, xfer); 1165 if (needdone) { 1166 if (wdc_c->flags & AT_WAIT) 1167 wakeup(wdc_c); 1168 else 1169 wdc_c->callback(wdc_c->callback_arg); 1170 } 1171 wdcstart(chp); 1172 return; 1173 } 1174 1175 /* 1176 * Send a command. The drive should be ready. 1177 * Assumes interrupts are blocked. 1178 */ 1179 void 1180 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1181 struct channel_softc *chp; 1182 u_int8_t drive; 1183 u_int8_t command; 1184 u_int16_t cylin; 1185 u_int8_t head, sector, count, precomp; 1186 { 1187 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1188 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1189 chp->channel, drive, command, cylin, head, sector, count, precomp), 1190 DEBUG_FUNCS); 1191 1192 /* Select drive, head, and addressing mode. */ 1193 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1194 WDSD_IBM | (drive << 4) | head); 1195 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1196 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1197 precomp); 1198 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1199 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1200 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1201 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1202 1203 /* Send command. */ 1204 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1205 return; 1206 } 1207 1208 /* 1209 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1210 * tested by the caller. 1211 */ 1212 void 1213 wdccommandshort(chp, drive, command) 1214 struct channel_softc *chp; 1215 int drive; 1216 int command; 1217 { 1218 1219 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1220 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1221 DEBUG_FUNCS); 1222 1223 /* Select drive. */ 1224 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1225 WDSD_IBM | (drive << 4)); 1226 1227 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1228 } 1229 1230 /* Add a command to the queue and start controller. Must be called at splbio */ 1231 1232 void 1233 wdc_exec_xfer(chp, xfer) 1234 struct channel_softc *chp; 1235 struct wdc_xfer *xfer; 1236 { 1237 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1238 chp->channel, xfer->drive), DEBUG_XFERS); 1239 1240 /* complete xfer setup */ 1241 xfer->chp = chp; 1242 1243 /* 1244 * If we are a polled command, and the list is not empty, 1245 * we are doing a dump. Drop the list to allow the polled command 1246 * to complete, we're going to reboot soon anyway. 1247 */ 1248 if ((xfer->c_flags & C_POLL) != 0 && 1249 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1250 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1251 } 1252 /* insert at the end of command list */ 1253 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1254 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1255 chp->ch_flags), DEBUG_XFERS); 1256 wdcstart(chp); 1257 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1258 } 1259 1260 struct wdc_xfer * 1261 wdc_get_xfer(flags) 1262 int flags; 1263 { 1264 struct wdc_xfer *xfer; 1265 int s; 1266 1267 s = splbio(); 1268 if ((xfer = xfer_free_list.lh_first) != NULL) { 1269 LIST_REMOVE(xfer, free_list); 1270 splx(s); 1271 #ifdef DIAGNOSTIC 1272 if ((xfer->c_flags & C_INUSE) != 0) 1273 panic("wdc_get_xfer: xfer already in use\n"); 1274 #endif 1275 } else { 1276 splx(s); 1277 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1278 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1279 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1280 if (xfer == NULL) 1281 return 0; 1282 #ifdef DIAGNOSTIC 1283 xfer->c_flags &= ~C_INUSE; 1284 #endif 1285 #ifdef WDCDEBUG 1286 wdc_nxfer++; 1287 #endif 1288 } 1289 #ifdef DIAGNOSTIC 1290 if ((xfer->c_flags & C_INUSE) != 0) 1291 panic("wdc_get_xfer: xfer already in use\n"); 1292 #endif 1293 memset(xfer, 0, sizeof(struct wdc_xfer)); 1294 xfer->c_flags = C_INUSE; 1295 return xfer; 1296 } 1297 1298 void 1299 wdc_free_xfer(chp, xfer) 1300 struct channel_softc *chp; 1301 struct wdc_xfer *xfer; 1302 { 1303 struct wdc_softc *wdc = chp->wdc; 1304 int s; 1305 1306 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1307 (*wdc->free_hw)(chp); 1308 s = splbio(); 1309 chp->ch_flags &= ~WDCF_ACTIVE; 1310 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1311 xfer->c_flags &= ~C_INUSE; 1312 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1313 splx(s); 1314 } 1315 1316 static void 1317 __wdcerror(chp, msg) 1318 struct channel_softc *chp; 1319 char *msg; 1320 { 1321 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1322 if (xfer == NULL) 1323 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1324 msg); 1325 else 1326 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1327 chp->channel, xfer->drive, msg); 1328 } 1329 1330 /* 1331 * the bit bucket 1332 */ 1333 void 1334 wdcbit_bucket(chp, size) 1335 struct channel_softc *chp; 1336 int size; 1337 { 1338 1339 for (; size >= 2; size -= 2) 1340 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1341 if (size) 1342 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1343 } 1344 1345 int 1346 wdc_addref(chp) 1347 struct channel_softc *chp; 1348 { 1349 struct wdc_softc *wdc = chp->wdc; 1350 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1351 int s, error = 0; 1352 1353 s = splbio(); 1354 if (adapter->scsipi_refcnt++ == 0 && 1355 adapter->scsipi_enable != NULL) { 1356 error = (*adapter->scsipi_enable)(wdc, 1); 1357 if (error) 1358 adapter->scsipi_refcnt--; 1359 } 1360 splx(s); 1361 return (error); 1362 } 1363 1364 void 1365 wdc_delref(chp) 1366 struct channel_softc *chp; 1367 { 1368 struct wdc_softc *wdc = chp->wdc; 1369 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1370 int s; 1371 1372 s = splbio(); 1373 if (adapter->scsipi_refcnt-- == 1 && 1374 adapter->scsipi_enable != NULL) 1375 (void) (*adapter->scsipi_enable)(wdc, 0); 1376 splx(s); 1377 } 1378
Indexes created Wed Sep 24 05:09:52 GMT 2025