wdc.c revision 1.66
1 /* $NetBSD: wdc.c,v 1.66 1999/04/01 21:46:29 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(10); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(10); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(10); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(10); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices , then rescan and try an ATA command, in case it's an 235 * old drive. 236 * Fill in drive_flags accordingly 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(10); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else if (sc == 0x01 && sn == 0x01 && 262 cl == 0x00 && ch == 0x00) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 264 } 265 } 266 /* 267 * Maybe there's an old device, try to detect it if we didn't 268 * find a ATA or ATAPI device. 269 */ 270 if ((chp->ch_drive[0].drive_flags & DRIVE) != 0 || 271 (chp->ch_drive[1].drive_flags & DRIVE) != 0) 272 return (ret_value); 273 for (drive = 0; drive < 2; drive++) { 274 if ((ret_value & (0x01 << drive)) == 0) 275 continue; 276 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 277 WDSD_IBM | (drive << 4)); 278 delay(10); 279 /* 280 * Test registers writability (Error register not writable, 281 * but cyllo is), then try an ATA command. 282 */ 283 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_error, 0x58); 284 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, 0xa5); 285 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error) == 286 0x58 || 287 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo) != 288 0xa5) { 289 WDCDEBUG_PRINT(("%s:%d:%d: register writability " 290 "failed\n", 291 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 292 chp->channel, drive), DEBUG_PROBE); 293 ret_value &= ~(0x01 << drive); 294 continue; 295 } 296 if (wait_for_ready(chp, 10000) != 0) { 297 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 298 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 299 chp->channel, drive), DEBUG_PROBE); 300 ret_value &= ~(0x01 << drive); 301 continue; 302 } 303 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, 304 WDCC_RECAL); 305 if (wait_for_ready(chp, 10000) == 0) { 306 chp->ch_drive[drive].drive_flags |= 307 DRIVE_OLD; 308 } else { 309 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 310 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 311 chp->channel, drive), DEBUG_PROBE); 312 ret_value &= ~(0x01 << drive); 313 } 314 } 315 return (ret_value); 316 } 317 318 void 319 wdcattach(chp) 320 struct channel_softc *chp; 321 { 322 int channel_flags, ctrl_flags, i, error; 323 struct ata_atapi_attach aa_link; 324 struct ataparams params; 325 static int inited = 0; 326 327 if ((error = wdc_addref(chp)) != 0) { 328 printf("%s: unable to enable controller\n", 329 chp->wdc->sc_dev.dv_xname); 330 return; 331 } 332 333 if (wdcprobe(chp) == 0) { 334 /* If no drives, abort attach here. */ 335 wdc_delref(chp); 336 return; 337 } 338 339 /* init list only once */ 340 if (inited == 0) { 341 LIST_INIT(&xfer_free_list); 342 inited++; 343 } 344 TAILQ_INIT(&chp->ch_queue->sc_xfer); 345 346 for (i = 0; i < 2; i++) { 347 chp->ch_drive[i].chnl_softc = chp; 348 chp->ch_drive[i].drive = i; 349 /* If controller can't do 16bit flag the drives as 32bit */ 350 if ((chp->wdc->cap & 351 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 352 WDC_CAPABILITY_DATA32) 353 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 354 355 /* Issue a IDENTIFY command, to try to detect slave ghost */ 356 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) != 357 CMD_OK) { 358 chp->ch_drive[i].drive_flags &= 359 ~(DRIVE_ATA | DRIVE_ATAPI); 360 } 361 } 362 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 363 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 364 365 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 366 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 367 DEBUG_PROBE); 368 369 /* 370 * Attach an ATAPI bus, if needed. 371 */ 372 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 373 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 374 #if NATAPIBUS > 0 375 wdc_atapibus_attach(chp); 376 #else 377 /* 378 * Fills in a fake aa_link and call config_found, so that 379 * the config machinery will print 380 * "atapibus at xxx not configured" 381 */ 382 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 383 aa_link.aa_type = T_ATAPI; 384 aa_link.aa_channel = chp->channel; 385 aa_link.aa_openings = 1; 386 aa_link.aa_drv_data = 0; 387 aa_link.aa_bus_private = NULL; 388 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 389 atapi_print); 390 #endif 391 } 392 393 for (i = 0; i < 2; i++) { 394 if ((chp->ch_drive[i].drive_flags & DRIVE_ATA) == 0) { 395 continue; 396 } 397 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 398 aa_link.aa_type = T_ATA; 399 aa_link.aa_channel = chp->channel; 400 aa_link.aa_openings = 1; 401 aa_link.aa_drv_data = &chp->ch_drive[i]; 402 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 403 wdc_probe_caps(&chp->ch_drive[i]); 404 } 405 406 /* 407 * reset drive_flags for unnatached devices, reset state for attached 408 * ones 409 */ 410 for (i = 0; i < 2; i++) { 411 if (chp->ch_drive[i].drv_softc == NULL) 412 chp->ch_drive[i].drive_flags = 0; 413 else 414 chp->ch_drive[i].state = 0; 415 } 416 417 /* 418 * Reset channel. The probe, with some combinations of ATA/ATAPI 419 * devices keep it in a mostly working, but strange state (with busy 420 * led on) 421 */ 422 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 423 wdcreset(chp, VERBOSE); 424 /* 425 * Read status registers to avoid spurious interrupts. 426 */ 427 for (i = 1; i >= 0; i--) { 428 if (chp->ch_drive[i].drive_flags & DRIVE) { 429 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 430 wd_sdh, WDSD_IBM | (i << 4)); 431 if (wait_for_unbusy(chp, 10000) < 0) 432 printf("%s:%d:%d: device busy\n", 433 chp->wdc->sc_dev.dv_xname, 434 chp->channel, i); 435 } 436 } 437 } 438 wdc_delref(chp); 439 } 440 441 /* 442 * Start I/O on a controller, for the given channel. 443 * The first xfer may be not for our channel if the channel queues 444 * are shared. 445 */ 446 void 447 wdcstart(chp) 448 struct channel_softc *chp; 449 { 450 struct wdc_xfer *xfer; 451 452 #ifdef WDC_DIAGNOSTIC 453 int spl1, spl2; 454 455 spl1 = splbio(); 456 spl2 = splbio(); 457 if (spl2 != spl1) { 458 printf("wdcstart: not at splbio()\n"); 459 panic("wdcstart"); 460 } 461 splx(spl2); 462 splx(spl1); 463 #endif /* WDC_DIAGNOSTIC */ 464 465 /* is there a xfer ? */ 466 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 467 return; 468 469 /* adjust chp, in case we have a shared queue */ 470 chp = xfer->chp; 471 472 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 473 return; /* channel aleady active */ 474 } 475 #ifdef DIAGNOSTIC 476 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 477 panic("wdcstart: channel waiting for irq\n"); 478 #endif 479 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 480 if (!(*chp->wdc->claim_hw)(chp, 0)) 481 return; 482 483 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 484 chp->channel, xfer->drive), DEBUG_XFERS); 485 chp->ch_flags |= WDCF_ACTIVE; 486 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 487 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 488 chp->ch_drive[xfer->drive].state = 0; 489 } 490 xfer->c_start(chp, xfer); 491 } 492 493 /* restart an interrupted I/O */ 494 void 495 wdcrestart(v) 496 void *v; 497 { 498 struct channel_softc *chp = v; 499 int s; 500 501 s = splbio(); 502 wdcstart(chp); 503 splx(s); 504 } 505 506 507 /* 508 * Interrupt routine for the controller. Acknowledge the interrupt, check for 509 * errors on the current operation, mark it done if necessary, and start the 510 * next request. Also check for a partially done transfer, and continue with 511 * the next chunk if so. 512 */ 513 int 514 wdcintr(arg) 515 void *arg; 516 { 517 struct channel_softc *chp = arg; 518 struct wdc_xfer *xfer; 519 520 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 521 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 522 return 0; 523 } 524 525 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 526 untimeout(wdctimeout, chp); 527 chp->ch_flags &= ~WDCF_IRQ_WAIT; 528 xfer = chp->ch_queue->sc_xfer.tqh_first; 529 return xfer->c_intr(chp, xfer, 1); 530 } 531 532 /* Put all disk in RESET state */ 533 void wdc_reset_channel(drvp) 534 struct ata_drive_datas *drvp; 535 { 536 struct channel_softc *chp = drvp->chnl_softc; 537 int drive; 538 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 539 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 540 DEBUG_FUNCS); 541 (void) wdcreset(chp, VERBOSE); 542 for (drive = 0; drive < 2; drive++) { 543 chp->ch_drive[drive].state = 0; 544 } 545 } 546 547 int 548 wdcreset(chp, verb) 549 struct channel_softc *chp; 550 int verb; 551 { 552 int drv_mask1, drv_mask2; 553 554 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 555 WDSD_IBM); /* master */ 556 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 557 WDCTL_RST | WDCTL_IDS); 558 delay(1000); 559 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 560 WDCTL_IDS); 561 delay(1000); 562 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 563 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 564 WDCTL_4BIT); 565 566 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 567 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 568 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 569 if (verb && drv_mask2 != drv_mask1) { 570 printf("%s channel %d: reset failed for", 571 chp->wdc->sc_dev.dv_xname, chp->channel); 572 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 573 printf(" drive 0"); 574 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 575 printf(" drive 1"); 576 printf("\n"); 577 } 578 return (drv_mask1 != drv_mask2) ? 1 : 0; 579 } 580 581 static int 582 __wdcwait_reset(chp, drv_mask) 583 struct channel_softc *chp; 584 int drv_mask; 585 { 586 int timeout; 587 u_int8_t st0, st1; 588 /* wait for BSY to deassert */ 589 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 590 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 591 WDSD_IBM); /* master */ 592 delay(10); 593 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 594 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 595 WDSD_IBM | 0x10); /* slave */ 596 delay(10); 597 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 598 599 if ((drv_mask & 0x01) == 0) { 600 /* no master */ 601 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 602 /* No master, slave is ready, it's done */ 603 goto end; 604 } 605 } else if ((drv_mask & 0x02) == 0) { 606 /* no slave */ 607 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 608 /* No slave, master is ready, it's done */ 609 goto end; 610 } 611 } else { 612 /* Wait for both master and slave to be ready */ 613 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 614 goto end; 615 } 616 } 617 delay(WDCDELAY); 618 } 619 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 620 if (st0 & WDCS_BSY) 621 drv_mask &= ~0x01; 622 if (st1 & WDCS_BSY) 623 drv_mask &= ~0x02; 624 end: 625 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 626 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 627 st0, st1), DEBUG_PROBE); 628 629 return drv_mask; 630 } 631 632 /* 633 * Wait for a drive to be !BSY, and have mask in its status register. 634 * return -1 for a timeout after "timeout" ms. 635 */ 636 int 637 wdcwait(chp, mask, bits, timeout) 638 struct channel_softc *chp; 639 int mask, bits, timeout; 640 { 641 u_char status; 642 int time = 0; 643 #ifdef WDCNDELAY_DEBUG 644 extern int cold; 645 #endif 646 647 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 648 :"none", chp->channel), DEBUG_STATUS); 649 chp->ch_error = 0; 650 651 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 652 653 for (;;) { 654 chp->ch_status = status = 655 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 656 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 657 break; 658 if (++time > timeout) { 659 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 660 "error %x\n", status, 661 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 662 wd_error)), 663 DEBUG_STATUS); 664 return -1; 665 } 666 delay(WDCDELAY); 667 } 668 if (status & WDCS_ERR) 669 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 670 wd_error); 671 #ifdef WDCNDELAY_DEBUG 672 /* After autoconfig, there should be no long delays. */ 673 if (!cold && time > WDCNDELAY_DEBUG) { 674 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 675 if (xfer == NULL) 676 printf("%s channel %d: warning: busy-wait took %dus\n", 677 chp->wdc->sc_dev.dv_xname, chp->channel, 678 WDCDELAY * time); 679 else 680 printf("%s:%d:%d: warning: busy-wait took %dus\n", 681 chp->wdc->sc_dev.dv_xname, chp->channel, 682 xfer->drive, 683 WDCDELAY * time); 684 } 685 #endif 686 return 0; 687 } 688 689 void 690 wdctimeout(arg) 691 void *arg; 692 { 693 struct channel_softc *chp = (struct channel_softc *)arg; 694 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 695 int s; 696 697 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 698 699 s = splbio(); 700 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 701 __wdcerror(chp, "lost interrupt"); 702 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 703 "atapi":"ata"); 704 printf("\tc_bcount: %d\n", xfer->c_bcount); 705 printf("\tc_skip: %d\n", xfer->c_skip); 706 /* 707 * Call the interrupt routine. If we just missed and interrupt, 708 * it will do what's needed. Else, it will take the needed 709 * action (reset the device). 710 */ 711 xfer->c_flags |= C_TIMEOU; 712 chp->ch_flags &= ~WDCF_IRQ_WAIT; 713 xfer->c_intr(chp, xfer, 1); 714 } else 715 __wdcerror(chp, "missing untimeout"); 716 splx(s); 717 } 718 719 /* 720 * Probe drive's capabilites, for use by the controller later 721 * Assumes drvp points to an existing drive. 722 * XXX this should be a controller-indep function 723 */ 724 void 725 wdc_probe_caps(drvp) 726 struct ata_drive_datas *drvp; 727 { 728 struct ataparams params, params2; 729 struct channel_softc *chp = drvp->chnl_softc; 730 struct device *drv_dev = drvp->drv_softc; 731 struct wdc_softc *wdc = chp->wdc; 732 int i, printed; 733 char *sep = ""; 734 int cf_flags; 735 736 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 737 /* IDENTIFY failed. Can't tell more about the device */ 738 return; 739 } 740 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 741 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 742 /* 743 * Controller claims 16 and 32 bit transfers. 744 * Re-do an IDENTIFY with 32-bit transfers, 745 * and compare results. 746 */ 747 drvp->drive_flags |= DRIVE_CAP32; 748 ata_get_params(drvp, AT_POLL, ¶ms2); 749 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 750 /* Not good. fall back to 16bits */ 751 drvp->drive_flags &= ~DRIVE_CAP32; 752 } else { 753 printf("%s: 32-bits data port", drv_dev->dv_xname); 754 } 755 } 756 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 757 if (params.atap_ata_major > 0x01 && 758 params.atap_ata_major != 0xffff) { 759 for (i = 14; i > 0; i--) { 760 if (params.atap_ata_major & (1 << i)) { 761 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 762 printf("%s: ", drv_dev->dv_xname); 763 else 764 printf(", "); 765 printf("ATA version %d\n", i); 766 drvp->ata_vers = i; 767 break; 768 } 769 } 770 } else 771 #endif 772 if (drvp->drive_flags & DRIVE_CAP32) 773 printf("\n"); 774 775 /* An ATAPI device is at last PIO mode 3 */ 776 if (drvp->drive_flags & DRIVE_ATAPI) 777 drvp->PIO_mode = 3; 778 779 /* 780 * It's not in the specs, but it seems that some drive 781 * returns 0xffff in atap_extensions when this field is invalid 782 */ 783 if (params.atap_extensions != 0xffff && 784 (params.atap_extensions & WDC_EXT_MODES)) { 785 printed = 0; 786 /* 787 * XXX some drives report something wrong here (they claim to 788 * support PIO mode 8 !). As mode is coded on 3 bits in 789 * SET FEATURE, limit it to 7 (so limit i to 4). 790 * If higther mode than 7 is found, abort. 791 */ 792 for (i = 7; i >= 0; i--) { 793 if ((params.atap_piomode_supp & (1 << i)) == 0) 794 continue; 795 if (i > 4) 796 return; 797 /* 798 * See if mode is accepted. 799 * If the controller can't set its PIO mode, 800 * assume the defaults are good, so don't try 801 * to set it 802 */ 803 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 804 if (ata_set_mode(drvp, 0x08 | (i + 3), 805 AT_POLL) != CMD_OK) 806 continue; 807 if (!printed) { 808 printf("%s: drive supports PIO mode %d", 809 drv_dev->dv_xname, i + 3); 810 sep = ","; 811 printed = 1; 812 } 813 /* 814 * If controller's driver can't set its PIO mode, 815 * get the highter one for the drive. 816 */ 817 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 818 wdc->PIO_cap >= i + 3) { 819 drvp->PIO_mode = i + 3; 820 drvp->PIO_cap = i + 3; 821 break; 822 } 823 } 824 if (!printed) { 825 /* 826 * We didn't find a valid PIO mode. 827 * Assume the values returned for DMA are buggy too 828 */ 829 return; 830 } 831 drvp->drive_flags |= DRIVE_MODE; 832 printed = 0; 833 for (i = 7; i >= 0; i--) { 834 if ((params.atap_dmamode_supp & (1 << i)) == 0) 835 continue; 836 if ((wdc->cap & WDC_CAPABILITY_DMA) && 837 (wdc->cap & WDC_CAPABILITY_MODE)) 838 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 839 != CMD_OK) 840 continue; 841 if (!printed) { 842 printf("%s DMA mode %d", sep, i); 843 sep = ","; 844 printed = 1; 845 } 846 if (wdc->cap & WDC_CAPABILITY_DMA) { 847 if ((wdc->cap & WDC_CAPABILITY_MODE) && 848 wdc->DMA_cap < i) 849 continue; 850 drvp->DMA_mode = i; 851 drvp->DMA_cap = i; 852 drvp->drive_flags |= DRIVE_DMA; 853 } 854 break; 855 } 856 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 857 for (i = 7; i >= 0; i--) { 858 if ((params.atap_udmamode_supp & (1 << i)) 859 == 0) 860 continue; 861 if ((wdc->cap & WDC_CAPABILITY_MODE) && 862 (wdc->cap & WDC_CAPABILITY_UDMA)) 863 if (ata_set_mode(drvp, 0x40 | i, 864 AT_POLL) != CMD_OK) 865 continue; 866 printf("%s Ultra-DMA mode %d", sep, i); 867 sep = ","; 868 if (wdc->cap & WDC_CAPABILITY_UDMA) { 869 if ((wdc->cap & WDC_CAPABILITY_MODE) && 870 wdc->UDMA_cap < i) 871 continue; 872 drvp->UDMA_mode = i; 873 drvp->UDMA_cap = i; 874 drvp->drive_flags |= DRIVE_UDMA; 875 } 876 break; 877 } 878 } 879 printf("\n"); 880 } 881 882 /* Try to guess ATA version here, if it didn't get reported */ 883 if (drvp->ata_vers == 0) { 884 if (drvp->drive_flags & DRIVE_UDMA) 885 drvp->ata_vers = 4; /* should be at last ATA-4 */ 886 else if (drvp->PIO_cap > 2) 887 drvp->ata_vers = 2; /* should be at last ATA-2 */ 888 } 889 cf_flags = drv_dev->dv_cfdata->cf_flags; 890 if (cf_flags & ATA_CONFIG_PIO_SET) { 891 drvp->PIO_mode = 892 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 893 drvp->drive_flags |= DRIVE_MODE; 894 } 895 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 896 /* don't care about DMA modes */ 897 return; 898 } 899 if (cf_flags & ATA_CONFIG_DMA_SET) { 900 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 901 ATA_CONFIG_DMA_DISABLE) { 902 drvp->drive_flags &= ~DRIVE_DMA; 903 } else { 904 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 905 ATA_CONFIG_DMA_OFF; 906 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 907 } 908 } 909 if (cf_flags & ATA_CONFIG_UDMA_SET) { 910 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 911 ATA_CONFIG_UDMA_DISABLE) { 912 drvp->drive_flags &= ~DRIVE_UDMA; 913 } else { 914 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 915 ATA_CONFIG_UDMA_OFF; 916 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 917 } 918 } 919 } 920 921 /* 922 * downgrade the transfer mode of a drive after an error. return 1 if 923 * downgrade was possible, 0 otherwise. 924 */ 925 int 926 wdc_downgrade_mode(drvp) 927 struct ata_drive_datas *drvp; 928 { 929 struct channel_softc *chp = drvp->chnl_softc; 930 struct device *drv_dev = drvp->drv_softc; 931 struct wdc_softc *wdc = chp->wdc; 932 int cf_flags = drv_dev->dv_cfdata->cf_flags; 933 934 /* if drive or controller don't know its mode, we can't do much */ 935 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 936 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 937 return 0; 938 /* current drive mode was set by a config flag, let it this way */ 939 if ((cf_flags & ATA_CONFIG_PIO_SET) || 940 (cf_flags & ATA_CONFIG_DMA_SET) || 941 (cf_flags & ATA_CONFIG_UDMA_SET)) 942 return 0; 943 944 /* 945 * If we were using ultra-DMA, don't downgrade to multiword DMA 946 * if we noticed a CRC error. It has been noticed that CRC errors 947 * in ultra-DMA lead to silent data corruption in multiword DMA. 948 * Data corruption is less likely to occur in PIO mode. 949 */ 950 951 if ((drvp->drive_flags & DRIVE_UDMA) && 952 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 953 drvp->drive_flags &= ~DRIVE_UDMA; 954 drvp->drive_flags |= DRIVE_DMA; 955 drvp->DMA_mode = drvp->DMA_cap; 956 printf("%s: transfer error, downgrading to DMA mode %d\n", 957 drv_dev->dv_xname, drvp->DMA_mode); 958 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 959 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 960 drvp->PIO_mode = drvp->PIO_cap; 961 printf("%s: transfer error, downgrading to PIO mode %d\n", 962 drv_dev->dv_xname, drvp->PIO_mode); 963 } else /* already using PIO, can't downgrade */ 964 return 0; 965 966 wdc->set_modes(chp); 967 /* reset the channel, which will shedule all drives for setup */ 968 wdc_reset_channel(drvp); 969 return 1; 970 } 971 972 int 973 wdc_exec_command(drvp, wdc_c) 974 struct ata_drive_datas *drvp; 975 struct wdc_command *wdc_c; 976 { 977 struct channel_softc *chp = drvp->chnl_softc; 978 struct wdc_xfer *xfer; 979 int s, ret; 980 981 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 982 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 983 DEBUG_FUNCS); 984 985 /* set up an xfer and queue. Wait for completion */ 986 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 987 WDC_NOSLEEP); 988 if (xfer == NULL) { 989 return WDC_TRY_AGAIN; 990 } 991 992 if (wdc_c->flags & AT_POLL) 993 xfer->c_flags |= C_POLL; 994 xfer->drive = drvp->drive; 995 xfer->databuf = wdc_c->data; 996 xfer->c_bcount = wdc_c->bcount; 997 xfer->cmd = wdc_c; 998 xfer->c_start = __wdccommand_start; 999 xfer->c_intr = __wdccommand_intr; 1000 1001 s = splbio(); 1002 wdc_exec_xfer(chp, xfer); 1003 #ifdef DIAGNOSTIC 1004 if ((wdc_c->flags & AT_POLL) != 0 && 1005 (wdc_c->flags & AT_DONE) == 0) 1006 panic("wdc_exec_command: polled command not done\n"); 1007 #endif 1008 if (wdc_c->flags & AT_DONE) { 1009 ret = WDC_COMPLETE; 1010 } else { 1011 if (wdc_c->flags & AT_WAIT) { 1012 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1013 ret = WDC_COMPLETE; 1014 } else { 1015 ret = WDC_QUEUED; 1016 } 1017 } 1018 splx(s); 1019 return ret; 1020 } 1021 1022 void 1023 __wdccommand_start(chp, xfer) 1024 struct channel_softc *chp; 1025 struct wdc_xfer *xfer; 1026 { 1027 int drive = xfer->drive; 1028 struct wdc_command *wdc_c = xfer->cmd; 1029 1030 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1031 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1032 DEBUG_FUNCS); 1033 1034 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1035 WDSD_IBM | (drive << 4)); 1036 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1037 wdc_c->timeout) != 0) { 1038 wdc_c->flags |= AT_TIMEOU; 1039 __wdccommand_done(chp, xfer); 1040 return; 1041 } 1042 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1043 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1044 if ((wdc_c->flags & AT_POLL) == 0) { 1045 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1046 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1047 return; 1048 } 1049 /* 1050 * Polled command. Wait for drive ready or drq. Done in intr(). 1051 * Wait for at last 400ns for status bit to be valid. 1052 */ 1053 delay(10); 1054 __wdccommand_intr(chp, xfer, 0); 1055 } 1056 1057 int 1058 __wdccommand_intr(chp, xfer, irq) 1059 struct channel_softc *chp; 1060 struct wdc_xfer *xfer; 1061 int irq; 1062 { 1063 struct wdc_command *wdc_c = xfer->cmd; 1064 int bcount = wdc_c->bcount; 1065 char *data = wdc_c->data; 1066 1067 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1068 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1069 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1070 (irq == 0) ? wdc_c->timeout : 0)) { 1071 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1072 return 0; /* IRQ was not for us */ 1073 wdc_c->flags |= AT_TIMEOU; 1074 __wdccommand_done(chp, xfer); 1075 return 1; 1076 } 1077 if (wdc_c->flags & AT_READ) { 1078 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1079 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1080 0, (u_int32_t*)data, bcount >> 2); 1081 data += bcount & 0xfffffffc; 1082 bcount = bcount & 0x03; 1083 } 1084 if (bcount > 0) 1085 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1086 wd_data, (u_int16_t *)data, bcount >> 1); 1087 } else if (wdc_c->flags & AT_WRITE) { 1088 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1089 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1090 0, (u_int32_t*)data, bcount >> 2); 1091 data += bcount & 0xfffffffc; 1092 bcount = bcount & 0x03; 1093 } 1094 if (bcount > 0) 1095 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1096 wd_data, (u_int16_t *)data, bcount >> 1); 1097 } 1098 __wdccommand_done(chp, xfer); 1099 return 1; 1100 } 1101 1102 void 1103 __wdccommand_done(chp, xfer) 1104 struct channel_softc *chp; 1105 struct wdc_xfer *xfer; 1106 { 1107 int needdone = xfer->c_flags & C_NEEDDONE; 1108 struct wdc_command *wdc_c = xfer->cmd; 1109 1110 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1111 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1112 if (chp->ch_status & WDCS_DWF) 1113 wdc_c->flags |= AT_DF; 1114 if (chp->ch_status & WDCS_ERR) { 1115 wdc_c->flags |= AT_ERROR; 1116 wdc_c->r_error = chp->ch_error; 1117 } 1118 wdc_c->flags |= AT_DONE; 1119 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1120 == 0) { 1121 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1122 wd_sdh); 1123 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1124 wd_cyl_hi) << 8; 1125 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1126 wd_cyl_lo); 1127 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1128 wd_sector); 1129 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1130 wd_seccnt); 1131 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1132 wd_error); 1133 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1134 wd_precomp); 1135 } 1136 wdc_free_xfer(chp, xfer); 1137 if (needdone) { 1138 if (wdc_c->flags & AT_WAIT) 1139 wakeup(wdc_c); 1140 else 1141 wdc_c->callback(wdc_c->callback_arg); 1142 } 1143 wdcstart(chp); 1144 return; 1145 } 1146 1147 /* 1148 * Send a command. The drive should be ready. 1149 * Assumes interrupts are blocked. 1150 */ 1151 void 1152 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1153 struct channel_softc *chp; 1154 u_int8_t drive; 1155 u_int8_t command; 1156 u_int16_t cylin; 1157 u_int8_t head, sector, count, precomp; 1158 { 1159 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1160 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1161 chp->channel, drive, command, cylin, head, sector, count, precomp), 1162 DEBUG_FUNCS); 1163 1164 /* Select drive, head, and addressing mode. */ 1165 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1166 WDSD_IBM | (drive << 4) | head); 1167 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1168 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1169 precomp); 1170 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1171 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1172 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1173 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1174 1175 /* Send command. */ 1176 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1177 return; 1178 } 1179 1180 /* 1181 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1182 * tested by the caller. 1183 */ 1184 void 1185 wdccommandshort(chp, drive, command) 1186 struct channel_softc *chp; 1187 int drive; 1188 int command; 1189 { 1190 1191 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1192 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1193 DEBUG_FUNCS); 1194 1195 /* Select drive. */ 1196 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1197 WDSD_IBM | (drive << 4)); 1198 1199 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1200 } 1201 1202 /* Add a command to the queue and start controller. Must be called at splbio */ 1203 1204 void 1205 wdc_exec_xfer(chp, xfer) 1206 struct channel_softc *chp; 1207 struct wdc_xfer *xfer; 1208 { 1209 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1210 chp->channel, xfer->drive), DEBUG_XFERS); 1211 1212 /* complete xfer setup */ 1213 xfer->chp = chp; 1214 1215 /* 1216 * If we are a polled command, and the list is not empty, 1217 * we are doing a dump. Drop the list to allow the polled command 1218 * to complete, we're going to reboot soon anyway. 1219 */ 1220 if ((xfer->c_flags & C_POLL) != 0 && 1221 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1222 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1223 } 1224 /* insert at the end of command list */ 1225 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1226 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1227 chp->ch_flags), DEBUG_XFERS); 1228 wdcstart(chp); 1229 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1230 } 1231 1232 struct wdc_xfer * 1233 wdc_get_xfer(flags) 1234 int flags; 1235 { 1236 struct wdc_xfer *xfer; 1237 int s; 1238 1239 s = splbio(); 1240 if ((xfer = xfer_free_list.lh_first) != NULL) { 1241 LIST_REMOVE(xfer, free_list); 1242 splx(s); 1243 #ifdef DIAGNOSTIC 1244 if ((xfer->c_flags & C_INUSE) != 0) 1245 panic("wdc_get_xfer: xfer already in use\n"); 1246 #endif 1247 } else { 1248 splx(s); 1249 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1250 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1251 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1252 if (xfer == NULL) 1253 return 0; 1254 #ifdef DIAGNOSTIC 1255 xfer->c_flags &= ~C_INUSE; 1256 #endif 1257 #ifdef WDCDEBUG 1258 wdc_nxfer++; 1259 #endif 1260 } 1261 #ifdef DIAGNOSTIC 1262 if ((xfer->c_flags & C_INUSE) != 0) 1263 panic("wdc_get_xfer: xfer already in use\n"); 1264 #endif 1265 memset(xfer, 0, sizeof(struct wdc_xfer)); 1266 xfer->c_flags = C_INUSE; 1267 return xfer; 1268 } 1269 1270 void 1271 wdc_free_xfer(chp, xfer) 1272 struct channel_softc *chp; 1273 struct wdc_xfer *xfer; 1274 { 1275 struct wdc_softc *wdc = chp->wdc; 1276 int s; 1277 1278 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1279 (*wdc->free_hw)(chp); 1280 s = splbio(); 1281 chp->ch_flags &= ~WDCF_ACTIVE; 1282 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1283 xfer->c_flags &= ~C_INUSE; 1284 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1285 splx(s); 1286 } 1287 1288 static void 1289 __wdcerror(chp, msg) 1290 struct channel_softc *chp; 1291 char *msg; 1292 { 1293 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1294 if (xfer == NULL) 1295 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1296 msg); 1297 else 1298 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1299 chp->channel, xfer->drive, msg); 1300 } 1301 1302 /* 1303 * the bit bucket 1304 */ 1305 void 1306 wdcbit_bucket(chp, size) 1307 struct channel_softc *chp; 1308 int size; 1309 { 1310 1311 for (; size >= 2; size -= 2) 1312 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1313 if (size) 1314 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1315 } 1316 1317 int 1318 wdc_addref(chp) 1319 struct channel_softc *chp; 1320 { 1321 struct wdc_softc *wdc = chp->wdc; 1322 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1323 int s, error = 0; 1324 1325 s = splbio(); 1326 if (adapter->scsipi_refcnt++ == 0 && 1327 adapter->scsipi_enable != NULL) { 1328 error = (*adapter->scsipi_enable)(wdc, 1); 1329 if (error) 1330 adapter->scsipi_refcnt--; 1331 } 1332 splx(s); 1333 return (error); 1334 } 1335 1336 void 1337 wdc_delref(chp) 1338 struct channel_softc *chp; 1339 { 1340 struct wdc_softc *wdc = chp->wdc; 1341 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1342 int s; 1343 1344 s = splbio(); 1345 if (adapter->scsipi_refcnt-- == 1 && 1346 adapter->scsipi_enable != NULL) 1347 (void) (*adapter->scsipi_enable)(wdc, 0); 1348 splx(s); 1349 } 1350
Indexes created Wed Sep 24 14:09:57 GMT 2025