wdc.c revision 1.67
1 /* $NetBSD: wdc.c,v 1.67 1999/04/11 20:50:28 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(10); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(10); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(10); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(10); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices. If it's not an ATAPI and reset said there may be 235 * something here assume it's ATA or OLD. Ghost will be killed later in 236 * attach routine. 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(10); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0 - or maybe it's the controller. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 263 if (chp->wdc == NULL || 264 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 265 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 266 } 267 } 268 return (ret_value); 269 } 270 271 void 272 wdcattach(chp) 273 struct channel_softc *chp; 274 { 275 int channel_flags, ctrl_flags, i, error; 276 struct ata_atapi_attach aa_link; 277 struct ataparams params; 278 static int inited = 0; 279 280 if ((error = wdc_addref(chp)) != 0) { 281 printf("%s: unable to enable controller\n", 282 chp->wdc->sc_dev.dv_xname); 283 return; 284 } 285 286 if (wdcprobe(chp) == 0) { 287 /* If no drives, abort attach here. */ 288 wdc_delref(chp); 289 return; 290 } 291 292 /* init list only once */ 293 if (inited == 0) { 294 LIST_INIT(&xfer_free_list); 295 inited++; 296 } 297 TAILQ_INIT(&chp->ch_queue->sc_xfer); 298 299 for (i = 0; i < 2; i++) { 300 chp->ch_drive[i].chnl_softc = chp; 301 chp->ch_drive[i].drive = i; 302 /* If controller can't do 16bit flag the drives as 32bit */ 303 if ((chp->wdc->cap & 304 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 305 WDC_CAPABILITY_DATA32) 306 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 307 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 308 continue; 309 310 /* Issue a IDENTIFY command, to try to detect slave ghost */ 311 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) == 312 CMD_OK) { 313 /* If IDENTIFY succeded, this is not an OLD ctrl */ 314 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 315 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 316 } else { 317 chp->ch_drive[i].drive_flags &= 318 ~(DRIVE_ATA | DRIVE_ATAPI); 319 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 320 chp->wdc->sc_dev.dv_xname, 321 chp->channel, i), DEBUG_PROBE); 322 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 323 continue; 324 /* Pre-ATA drive ? */ 325 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 326 WDSD_IBM | (i << 4)); 327 delay(100); 328 if (wait_for_ready(chp, 10000) != 0) { 329 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 330 chp->wdc->sc_dev.dv_xname, 331 chp->channel, i), DEBUG_PROBE); 332 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 333 continue; 334 } 335 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 336 wd_command, WDCC_RECAL); 337 if (wait_for_ready(chp, 10000) != 0) { 338 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 339 chp->wdc->sc_dev.dv_xname, 340 chp->channel, i), DEBUG_PROBE); 341 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 342 } 343 } 344 } 345 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 346 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 347 348 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 349 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 350 DEBUG_PROBE); 351 352 /* If no drives, abort here */ 353 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 354 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 355 return; 356 357 /* 358 * Attach an ATAPI bus, if needed. 359 */ 360 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 361 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 362 #if NATAPIBUS > 0 363 wdc_atapibus_attach(chp); 364 #else 365 /* 366 * Fills in a fake aa_link and call config_found, so that 367 * the config machinery will print 368 * "atapibus at xxx not configured" 369 */ 370 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 371 aa_link.aa_type = T_ATAPI; 372 aa_link.aa_channel = chp->channel; 373 aa_link.aa_openings = 1; 374 aa_link.aa_drv_data = 0; 375 aa_link.aa_bus_private = NULL; 376 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 377 atapi_print); 378 #endif 379 } 380 381 for (i = 0; i < 2; i++) { 382 if ((chp->ch_drive[i].drive_flags & 383 (DRIVE_ATA | DRIVE_OLD)) == 0) { 384 continue; 385 } 386 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 387 aa_link.aa_type = T_ATA; 388 aa_link.aa_channel = chp->channel; 389 aa_link.aa_openings = 1; 390 aa_link.aa_drv_data = &chp->ch_drive[i]; 391 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 392 wdc_probe_caps(&chp->ch_drive[i]); 393 } 394 395 /* 396 * reset drive_flags for unnatached devices, reset state for attached 397 * ones 398 */ 399 for (i = 0; i < 2; i++) { 400 if (chp->ch_drive[i].drv_softc == NULL) 401 chp->ch_drive[i].drive_flags = 0; 402 else 403 chp->ch_drive[i].state = 0; 404 } 405 406 /* 407 * Reset channel. The probe, with some combinations of ATA/ATAPI 408 * devices keep it in a mostly working, but strange state (with busy 409 * led on) 410 */ 411 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 412 wdcreset(chp, VERBOSE); 413 /* 414 * Read status registers to avoid spurious interrupts. 415 */ 416 for (i = 1; i >= 0; i--) { 417 if (chp->ch_drive[i].drive_flags & DRIVE) { 418 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 419 wd_sdh, WDSD_IBM | (i << 4)); 420 if (wait_for_unbusy(chp, 10000) < 0) 421 printf("%s:%d:%d: device busy\n", 422 chp->wdc->sc_dev.dv_xname, 423 chp->channel, i); 424 } 425 } 426 } 427 wdc_delref(chp); 428 } 429 430 /* 431 * Start I/O on a controller, for the given channel. 432 * The first xfer may be not for our channel if the channel queues 433 * are shared. 434 */ 435 void 436 wdcstart(chp) 437 struct channel_softc *chp; 438 { 439 struct wdc_xfer *xfer; 440 441 #ifdef WDC_DIAGNOSTIC 442 int spl1, spl2; 443 444 spl1 = splbio(); 445 spl2 = splbio(); 446 if (spl2 != spl1) { 447 printf("wdcstart: not at splbio()\n"); 448 panic("wdcstart"); 449 } 450 splx(spl2); 451 splx(spl1); 452 #endif /* WDC_DIAGNOSTIC */ 453 454 /* is there a xfer ? */ 455 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 456 return; 457 458 /* adjust chp, in case we have a shared queue */ 459 chp = xfer->chp; 460 461 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 462 return; /* channel aleady active */ 463 } 464 #ifdef DIAGNOSTIC 465 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 466 panic("wdcstart: channel waiting for irq\n"); 467 #endif 468 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 469 if (!(*chp->wdc->claim_hw)(chp, 0)) 470 return; 471 472 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 473 chp->channel, xfer->drive), DEBUG_XFERS); 474 chp->ch_flags |= WDCF_ACTIVE; 475 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 476 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 477 chp->ch_drive[xfer->drive].state = 0; 478 } 479 xfer->c_start(chp, xfer); 480 } 481 482 /* restart an interrupted I/O */ 483 void 484 wdcrestart(v) 485 void *v; 486 { 487 struct channel_softc *chp = v; 488 int s; 489 490 s = splbio(); 491 wdcstart(chp); 492 splx(s); 493 } 494 495 496 /* 497 * Interrupt routine for the controller. Acknowledge the interrupt, check for 498 * errors on the current operation, mark it done if necessary, and start the 499 * next request. Also check for a partially done transfer, and continue with 500 * the next chunk if so. 501 */ 502 int 503 wdcintr(arg) 504 void *arg; 505 { 506 struct channel_softc *chp = arg; 507 struct wdc_xfer *xfer; 508 509 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 510 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 511 return 0; 512 } 513 514 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 515 untimeout(wdctimeout, chp); 516 chp->ch_flags &= ~WDCF_IRQ_WAIT; 517 xfer = chp->ch_queue->sc_xfer.tqh_first; 518 return xfer->c_intr(chp, xfer, 1); 519 } 520 521 /* Put all disk in RESET state */ 522 void wdc_reset_channel(drvp) 523 struct ata_drive_datas *drvp; 524 { 525 struct channel_softc *chp = drvp->chnl_softc; 526 int drive; 527 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 528 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 529 DEBUG_FUNCS); 530 (void) wdcreset(chp, VERBOSE); 531 for (drive = 0; drive < 2; drive++) { 532 chp->ch_drive[drive].state = 0; 533 } 534 } 535 536 int 537 wdcreset(chp, verb) 538 struct channel_softc *chp; 539 int verb; 540 { 541 int drv_mask1, drv_mask2; 542 543 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 544 WDSD_IBM); /* master */ 545 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 546 WDCTL_RST | WDCTL_IDS); 547 delay(1000); 548 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 549 WDCTL_IDS); 550 delay(1000); 551 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 552 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 553 WDCTL_4BIT); 554 555 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 556 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 557 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 558 if (verb && drv_mask2 != drv_mask1) { 559 printf("%s channel %d: reset failed for", 560 chp->wdc->sc_dev.dv_xname, chp->channel); 561 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 562 printf(" drive 0"); 563 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 564 printf(" drive 1"); 565 printf("\n"); 566 } 567 return (drv_mask1 != drv_mask2) ? 1 : 0; 568 } 569 570 static int 571 __wdcwait_reset(chp, drv_mask) 572 struct channel_softc *chp; 573 int drv_mask; 574 { 575 int timeout; 576 u_int8_t st0, st1; 577 /* wait for BSY to deassert */ 578 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 579 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 580 WDSD_IBM); /* master */ 581 delay(10); 582 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 583 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 584 WDSD_IBM | 0x10); /* slave */ 585 delay(10); 586 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 587 588 if ((drv_mask & 0x01) == 0) { 589 /* no master */ 590 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 591 /* No master, slave is ready, it's done */ 592 goto end; 593 } 594 } else if ((drv_mask & 0x02) == 0) { 595 /* no slave */ 596 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 597 /* No slave, master is ready, it's done */ 598 goto end; 599 } 600 } else { 601 /* Wait for both master and slave to be ready */ 602 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 603 goto end; 604 } 605 } 606 delay(WDCDELAY); 607 } 608 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 609 if (st0 & WDCS_BSY) 610 drv_mask &= ~0x01; 611 if (st1 & WDCS_BSY) 612 drv_mask &= ~0x02; 613 end: 614 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 615 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 616 st0, st1), DEBUG_PROBE); 617 618 return drv_mask; 619 } 620 621 /* 622 * Wait for a drive to be !BSY, and have mask in its status register. 623 * return -1 for a timeout after "timeout" ms. 624 */ 625 int 626 wdcwait(chp, mask, bits, timeout) 627 struct channel_softc *chp; 628 int mask, bits, timeout; 629 { 630 u_char status; 631 int time = 0; 632 #ifdef WDCNDELAY_DEBUG 633 extern int cold; 634 #endif 635 636 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 637 :"none", chp->channel), DEBUG_STATUS); 638 chp->ch_error = 0; 639 640 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 641 642 for (;;) { 643 chp->ch_status = status = 644 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 645 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 646 break; 647 if (++time > timeout) { 648 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 649 "error %x\n", status, 650 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 651 wd_error)), 652 DEBUG_STATUS); 653 return -1; 654 } 655 delay(WDCDELAY); 656 } 657 if (status & WDCS_ERR) 658 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 659 wd_error); 660 #ifdef WDCNDELAY_DEBUG 661 /* After autoconfig, there should be no long delays. */ 662 if (!cold && time > WDCNDELAY_DEBUG) { 663 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 664 if (xfer == NULL) 665 printf("%s channel %d: warning: busy-wait took %dus\n", 666 chp->wdc->sc_dev.dv_xname, chp->channel, 667 WDCDELAY * time); 668 else 669 printf("%s:%d:%d: warning: busy-wait took %dus\n", 670 chp->wdc->sc_dev.dv_xname, chp->channel, 671 xfer->drive, 672 WDCDELAY * time); 673 } 674 #endif 675 return 0; 676 } 677 678 void 679 wdctimeout(arg) 680 void *arg; 681 { 682 struct channel_softc *chp = (struct channel_softc *)arg; 683 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 684 int s; 685 686 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 687 688 s = splbio(); 689 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 690 __wdcerror(chp, "lost interrupt"); 691 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 692 "atapi":"ata"); 693 printf("\tc_bcount: %d\n", xfer->c_bcount); 694 printf("\tc_skip: %d\n", xfer->c_skip); 695 /* 696 * Call the interrupt routine. If we just missed and interrupt, 697 * it will do what's needed. Else, it will take the needed 698 * action (reset the device). 699 */ 700 xfer->c_flags |= C_TIMEOU; 701 chp->ch_flags &= ~WDCF_IRQ_WAIT; 702 xfer->c_intr(chp, xfer, 1); 703 } else 704 __wdcerror(chp, "missing untimeout"); 705 splx(s); 706 } 707 708 /* 709 * Probe drive's capabilites, for use by the controller later 710 * Assumes drvp points to an existing drive. 711 * XXX this should be a controller-indep function 712 */ 713 void 714 wdc_probe_caps(drvp) 715 struct ata_drive_datas *drvp; 716 { 717 struct ataparams params, params2; 718 struct channel_softc *chp = drvp->chnl_softc; 719 struct device *drv_dev = drvp->drv_softc; 720 struct wdc_softc *wdc = chp->wdc; 721 int i, printed; 722 char *sep = ""; 723 int cf_flags; 724 725 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 726 /* IDENTIFY failed. Can't tell more about the device */ 727 return; 728 } 729 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 730 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 731 /* 732 * Controller claims 16 and 32 bit transfers. 733 * Re-do an IDENTIFY with 32-bit transfers, 734 * and compare results. 735 */ 736 drvp->drive_flags |= DRIVE_CAP32; 737 ata_get_params(drvp, AT_POLL, ¶ms2); 738 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 739 /* Not good. fall back to 16bits */ 740 drvp->drive_flags &= ~DRIVE_CAP32; 741 } else { 742 printf("%s: 32-bits data port", drv_dev->dv_xname); 743 } 744 } 745 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 746 if (params.atap_ata_major > 0x01 && 747 params.atap_ata_major != 0xffff) { 748 for (i = 14; i > 0; i--) { 749 if (params.atap_ata_major & (1 << i)) { 750 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 751 printf("%s: ", drv_dev->dv_xname); 752 else 753 printf(", "); 754 printf("ATA version %d\n", i); 755 drvp->ata_vers = i; 756 break; 757 } 758 } 759 } else 760 #endif 761 if (drvp->drive_flags & DRIVE_CAP32) 762 printf("\n"); 763 764 /* An ATAPI device is at last PIO mode 3 */ 765 if (drvp->drive_flags & DRIVE_ATAPI) 766 drvp->PIO_mode = 3; 767 768 /* 769 * It's not in the specs, but it seems that some drive 770 * returns 0xffff in atap_extensions when this field is invalid 771 */ 772 if (params.atap_extensions != 0xffff && 773 (params.atap_extensions & WDC_EXT_MODES)) { 774 printed = 0; 775 /* 776 * XXX some drives report something wrong here (they claim to 777 * support PIO mode 8 !). As mode is coded on 3 bits in 778 * SET FEATURE, limit it to 7 (so limit i to 4). 779 * If higther mode than 7 is found, abort. 780 */ 781 for (i = 7; i >= 0; i--) { 782 if ((params.atap_piomode_supp & (1 << i)) == 0) 783 continue; 784 if (i > 4) 785 return; 786 /* 787 * See if mode is accepted. 788 * If the controller can't set its PIO mode, 789 * assume the defaults are good, so don't try 790 * to set it 791 */ 792 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 793 if (ata_set_mode(drvp, 0x08 | (i + 3), 794 AT_POLL) != CMD_OK) 795 continue; 796 if (!printed) { 797 printf("%s: drive supports PIO mode %d", 798 drv_dev->dv_xname, i + 3); 799 sep = ","; 800 printed = 1; 801 } 802 /* 803 * If controller's driver can't set its PIO mode, 804 * get the highter one for the drive. 805 */ 806 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 807 wdc->PIO_cap >= i + 3) { 808 drvp->PIO_mode = i + 3; 809 drvp->PIO_cap = i + 3; 810 break; 811 } 812 } 813 if (!printed) { 814 /* 815 * We didn't find a valid PIO mode. 816 * Assume the values returned for DMA are buggy too 817 */ 818 return; 819 } 820 drvp->drive_flags |= DRIVE_MODE; 821 printed = 0; 822 for (i = 7; i >= 0; i--) { 823 if ((params.atap_dmamode_supp & (1 << i)) == 0) 824 continue; 825 if ((wdc->cap & WDC_CAPABILITY_DMA) && 826 (wdc->cap & WDC_CAPABILITY_MODE)) 827 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 828 != CMD_OK) 829 continue; 830 if (!printed) { 831 printf("%s DMA mode %d", sep, i); 832 sep = ","; 833 printed = 1; 834 } 835 if (wdc->cap & WDC_CAPABILITY_DMA) { 836 if ((wdc->cap & WDC_CAPABILITY_MODE) && 837 wdc->DMA_cap < i) 838 continue; 839 drvp->DMA_mode = i; 840 drvp->DMA_cap = i; 841 drvp->drive_flags |= DRIVE_DMA; 842 } 843 break; 844 } 845 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 846 for (i = 7; i >= 0; i--) { 847 if ((params.atap_udmamode_supp & (1 << i)) 848 == 0) 849 continue; 850 if ((wdc->cap & WDC_CAPABILITY_MODE) && 851 (wdc->cap & WDC_CAPABILITY_UDMA)) 852 if (ata_set_mode(drvp, 0x40 | i, 853 AT_POLL) != CMD_OK) 854 continue; 855 printf("%s Ultra-DMA mode %d", sep, i); 856 sep = ","; 857 if (wdc->cap & WDC_CAPABILITY_UDMA) { 858 if ((wdc->cap & WDC_CAPABILITY_MODE) && 859 wdc->UDMA_cap < i) 860 continue; 861 drvp->UDMA_mode = i; 862 drvp->UDMA_cap = i; 863 drvp->drive_flags |= DRIVE_UDMA; 864 } 865 break; 866 } 867 } 868 printf("\n"); 869 } 870 871 /* Try to guess ATA version here, if it didn't get reported */ 872 if (drvp->ata_vers == 0) { 873 if (drvp->drive_flags & DRIVE_UDMA) 874 drvp->ata_vers = 4; /* should be at last ATA-4 */ 875 else if (drvp->PIO_cap > 2) 876 drvp->ata_vers = 2; /* should be at last ATA-2 */ 877 } 878 cf_flags = drv_dev->dv_cfdata->cf_flags; 879 if (cf_flags & ATA_CONFIG_PIO_SET) { 880 drvp->PIO_mode = 881 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 882 drvp->drive_flags |= DRIVE_MODE; 883 } 884 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 885 /* don't care about DMA modes */ 886 return; 887 } 888 if (cf_flags & ATA_CONFIG_DMA_SET) { 889 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 890 ATA_CONFIG_DMA_DISABLE) { 891 drvp->drive_flags &= ~DRIVE_DMA; 892 } else { 893 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 894 ATA_CONFIG_DMA_OFF; 895 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 896 } 897 } 898 if (cf_flags & ATA_CONFIG_UDMA_SET) { 899 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 900 ATA_CONFIG_UDMA_DISABLE) { 901 drvp->drive_flags &= ~DRIVE_UDMA; 902 } else { 903 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 904 ATA_CONFIG_UDMA_OFF; 905 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 906 } 907 } 908 } 909 910 /* 911 * downgrade the transfer mode of a drive after an error. return 1 if 912 * downgrade was possible, 0 otherwise. 913 */ 914 int 915 wdc_downgrade_mode(drvp) 916 struct ata_drive_datas *drvp; 917 { 918 struct channel_softc *chp = drvp->chnl_softc; 919 struct device *drv_dev = drvp->drv_softc; 920 struct wdc_softc *wdc = chp->wdc; 921 int cf_flags = drv_dev->dv_cfdata->cf_flags; 922 923 /* if drive or controller don't know its mode, we can't do much */ 924 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 925 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 926 return 0; 927 /* current drive mode was set by a config flag, let it this way */ 928 if ((cf_flags & ATA_CONFIG_PIO_SET) || 929 (cf_flags & ATA_CONFIG_DMA_SET) || 930 (cf_flags & ATA_CONFIG_UDMA_SET)) 931 return 0; 932 933 /* 934 * If we were using ultra-DMA, don't downgrade to multiword DMA 935 * if we noticed a CRC error. It has been noticed that CRC errors 936 * in ultra-DMA lead to silent data corruption in multiword DMA. 937 * Data corruption is less likely to occur in PIO mode. 938 */ 939 940 if ((drvp->drive_flags & DRIVE_UDMA) && 941 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 942 drvp->drive_flags &= ~DRIVE_UDMA; 943 drvp->drive_flags |= DRIVE_DMA; 944 drvp->DMA_mode = drvp->DMA_cap; 945 printf("%s: transfer error, downgrading to DMA mode %d\n", 946 drv_dev->dv_xname, drvp->DMA_mode); 947 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 948 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 949 drvp->PIO_mode = drvp->PIO_cap; 950 printf("%s: transfer error, downgrading to PIO mode %d\n", 951 drv_dev->dv_xname, drvp->PIO_mode); 952 } else /* already using PIO, can't downgrade */ 953 return 0; 954 955 wdc->set_modes(chp); 956 /* reset the channel, which will shedule all drives for setup */ 957 wdc_reset_channel(drvp); 958 return 1; 959 } 960 961 int 962 wdc_exec_command(drvp, wdc_c) 963 struct ata_drive_datas *drvp; 964 struct wdc_command *wdc_c; 965 { 966 struct channel_softc *chp = drvp->chnl_softc; 967 struct wdc_xfer *xfer; 968 int s, ret; 969 970 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 971 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 972 DEBUG_FUNCS); 973 974 /* set up an xfer and queue. Wait for completion */ 975 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 976 WDC_NOSLEEP); 977 if (xfer == NULL) { 978 return WDC_TRY_AGAIN; 979 } 980 981 if (wdc_c->flags & AT_POLL) 982 xfer->c_flags |= C_POLL; 983 xfer->drive = drvp->drive; 984 xfer->databuf = wdc_c->data; 985 xfer->c_bcount = wdc_c->bcount; 986 xfer->cmd = wdc_c; 987 xfer->c_start = __wdccommand_start; 988 xfer->c_intr = __wdccommand_intr; 989 990 s = splbio(); 991 wdc_exec_xfer(chp, xfer); 992 #ifdef DIAGNOSTIC 993 if ((wdc_c->flags & AT_POLL) != 0 && 994 (wdc_c->flags & AT_DONE) == 0) 995 panic("wdc_exec_command: polled command not done\n"); 996 #endif 997 if (wdc_c->flags & AT_DONE) { 998 ret = WDC_COMPLETE; 999 } else { 1000 if (wdc_c->flags & AT_WAIT) { 1001 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1002 ret = WDC_COMPLETE; 1003 } else { 1004 ret = WDC_QUEUED; 1005 } 1006 } 1007 splx(s); 1008 return ret; 1009 } 1010 1011 void 1012 __wdccommand_start(chp, xfer) 1013 struct channel_softc *chp; 1014 struct wdc_xfer *xfer; 1015 { 1016 int drive = xfer->drive; 1017 struct wdc_command *wdc_c = xfer->cmd; 1018 1019 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1020 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1021 DEBUG_FUNCS); 1022 1023 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1024 WDSD_IBM | (drive << 4)); 1025 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1026 wdc_c->timeout) != 0) { 1027 wdc_c->flags |= AT_TIMEOU; 1028 __wdccommand_done(chp, xfer); 1029 return; 1030 } 1031 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1032 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1033 if ((wdc_c->flags & AT_POLL) == 0) { 1034 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1035 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1036 return; 1037 } 1038 /* 1039 * Polled command. Wait for drive ready or drq. Done in intr(). 1040 * Wait for at last 400ns for status bit to be valid. 1041 */ 1042 delay(10); 1043 __wdccommand_intr(chp, xfer, 0); 1044 } 1045 1046 int 1047 __wdccommand_intr(chp, xfer, irq) 1048 struct channel_softc *chp; 1049 struct wdc_xfer *xfer; 1050 int irq; 1051 { 1052 struct wdc_command *wdc_c = xfer->cmd; 1053 int bcount = wdc_c->bcount; 1054 char *data = wdc_c->data; 1055 1056 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1057 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1058 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1059 (irq == 0) ? wdc_c->timeout : 0)) { 1060 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1061 return 0; /* IRQ was not for us */ 1062 wdc_c->flags |= AT_TIMEOU; 1063 __wdccommand_done(chp, xfer); 1064 return 1; 1065 } 1066 if (wdc_c->flags & AT_READ) { 1067 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1068 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1069 0, (u_int32_t*)data, bcount >> 2); 1070 data += bcount & 0xfffffffc; 1071 bcount = bcount & 0x03; 1072 } 1073 if (bcount > 0) 1074 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1075 wd_data, (u_int16_t *)data, bcount >> 1); 1076 } else if (wdc_c->flags & AT_WRITE) { 1077 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1078 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1079 0, (u_int32_t*)data, bcount >> 2); 1080 data += bcount & 0xfffffffc; 1081 bcount = bcount & 0x03; 1082 } 1083 if (bcount > 0) 1084 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1085 wd_data, (u_int16_t *)data, bcount >> 1); 1086 } 1087 __wdccommand_done(chp, xfer); 1088 return 1; 1089 } 1090 1091 void 1092 __wdccommand_done(chp, xfer) 1093 struct channel_softc *chp; 1094 struct wdc_xfer *xfer; 1095 { 1096 int needdone = xfer->c_flags & C_NEEDDONE; 1097 struct wdc_command *wdc_c = xfer->cmd; 1098 1099 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1100 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1101 if (chp->ch_status & WDCS_DWF) 1102 wdc_c->flags |= AT_DF; 1103 if (chp->ch_status & WDCS_ERR) { 1104 wdc_c->flags |= AT_ERROR; 1105 wdc_c->r_error = chp->ch_error; 1106 } 1107 wdc_c->flags |= AT_DONE; 1108 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1109 == 0) { 1110 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1111 wd_sdh); 1112 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1113 wd_cyl_hi) << 8; 1114 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1115 wd_cyl_lo); 1116 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1117 wd_sector); 1118 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1119 wd_seccnt); 1120 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1121 wd_error); 1122 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1123 wd_precomp); 1124 } 1125 wdc_free_xfer(chp, xfer); 1126 if (needdone) { 1127 if (wdc_c->flags & AT_WAIT) 1128 wakeup(wdc_c); 1129 else 1130 wdc_c->callback(wdc_c->callback_arg); 1131 } 1132 wdcstart(chp); 1133 return; 1134 } 1135 1136 /* 1137 * Send a command. The drive should be ready. 1138 * Assumes interrupts are blocked. 1139 */ 1140 void 1141 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1142 struct channel_softc *chp; 1143 u_int8_t drive; 1144 u_int8_t command; 1145 u_int16_t cylin; 1146 u_int8_t head, sector, count, precomp; 1147 { 1148 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1149 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1150 chp->channel, drive, command, cylin, head, sector, count, precomp), 1151 DEBUG_FUNCS); 1152 1153 /* Select drive, head, and addressing mode. */ 1154 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1155 WDSD_IBM | (drive << 4) | head); 1156 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1157 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1158 precomp); 1159 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1160 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1161 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1162 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1163 1164 /* Send command. */ 1165 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1166 return; 1167 } 1168 1169 /* 1170 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1171 * tested by the caller. 1172 */ 1173 void 1174 wdccommandshort(chp, drive, command) 1175 struct channel_softc *chp; 1176 int drive; 1177 int command; 1178 { 1179 1180 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1181 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1182 DEBUG_FUNCS); 1183 1184 /* Select drive. */ 1185 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1186 WDSD_IBM | (drive << 4)); 1187 1188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1189 } 1190 1191 /* Add a command to the queue and start controller. Must be called at splbio */ 1192 1193 void 1194 wdc_exec_xfer(chp, xfer) 1195 struct channel_softc *chp; 1196 struct wdc_xfer *xfer; 1197 { 1198 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1199 chp->channel, xfer->drive), DEBUG_XFERS); 1200 1201 /* complete xfer setup */ 1202 xfer->chp = chp; 1203 1204 /* 1205 * If we are a polled command, and the list is not empty, 1206 * we are doing a dump. Drop the list to allow the polled command 1207 * to complete, we're going to reboot soon anyway. 1208 */ 1209 if ((xfer->c_flags & C_POLL) != 0 && 1210 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1211 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1212 } 1213 /* insert at the end of command list */ 1214 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1215 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1216 chp->ch_flags), DEBUG_XFERS); 1217 wdcstart(chp); 1218 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1219 } 1220 1221 struct wdc_xfer * 1222 wdc_get_xfer(flags) 1223 int flags; 1224 { 1225 struct wdc_xfer *xfer; 1226 int s; 1227 1228 s = splbio(); 1229 if ((xfer = xfer_free_list.lh_first) != NULL) { 1230 LIST_REMOVE(xfer, free_list); 1231 splx(s); 1232 #ifdef DIAGNOSTIC 1233 if ((xfer->c_flags & C_INUSE) != 0) 1234 panic("wdc_get_xfer: xfer already in use\n"); 1235 #endif 1236 } else { 1237 splx(s); 1238 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1239 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1240 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1241 if (xfer == NULL) 1242 return 0; 1243 #ifdef DIAGNOSTIC 1244 xfer->c_flags &= ~C_INUSE; 1245 #endif 1246 #ifdef WDCDEBUG 1247 wdc_nxfer++; 1248 #endif 1249 } 1250 #ifdef DIAGNOSTIC 1251 if ((xfer->c_flags & C_INUSE) != 0) 1252 panic("wdc_get_xfer: xfer already in use\n"); 1253 #endif 1254 memset(xfer, 0, sizeof(struct wdc_xfer)); 1255 xfer->c_flags = C_INUSE; 1256 return xfer; 1257 } 1258 1259 void 1260 wdc_free_xfer(chp, xfer) 1261 struct channel_softc *chp; 1262 struct wdc_xfer *xfer; 1263 { 1264 struct wdc_softc *wdc = chp->wdc; 1265 int s; 1266 1267 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1268 (*wdc->free_hw)(chp); 1269 s = splbio(); 1270 chp->ch_flags &= ~WDCF_ACTIVE; 1271 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1272 xfer->c_flags &= ~C_INUSE; 1273 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1274 splx(s); 1275 } 1276 1277 static void 1278 __wdcerror(chp, msg) 1279 struct channel_softc *chp; 1280 char *msg; 1281 { 1282 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1283 if (xfer == NULL) 1284 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1285 msg); 1286 else 1287 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1288 chp->channel, xfer->drive, msg); 1289 } 1290 1291 /* 1292 * the bit bucket 1293 */ 1294 void 1295 wdcbit_bucket(chp, size) 1296 struct channel_softc *chp; 1297 int size; 1298 { 1299 1300 for (; size >= 2; size -= 2) 1301 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1302 if (size) 1303 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1304 } 1305 1306 int 1307 wdc_addref(chp) 1308 struct channel_softc *chp; 1309 { 1310 struct wdc_softc *wdc = chp->wdc; 1311 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1312 int s, error = 0; 1313 1314 s = splbio(); 1315 if (adapter->scsipi_refcnt++ == 0 && 1316 adapter->scsipi_enable != NULL) { 1317 error = (*adapter->scsipi_enable)(wdc, 1); 1318 if (error) 1319 adapter->scsipi_refcnt--; 1320 } 1321 splx(s); 1322 return (error); 1323 } 1324 1325 void 1326 wdc_delref(chp) 1327 struct channel_softc *chp; 1328 { 1329 struct wdc_softc *wdc = chp->wdc; 1330 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1331 int s; 1332 1333 s = splbio(); 1334 if (adapter->scsipi_refcnt-- == 1 && 1335 adapter->scsipi_enable != NULL) 1336 (void) (*adapter->scsipi_enable)(wdc, 0); 1337 splx(s); 1338 } 1339
Indexes created Tue Sep 23 07:09:52 GMT 2025