wdc.c revision 1.68
1 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(10); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(10); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(10); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(10); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices. If it's not an ATAPI and reset said there may be 235 * something here assume it's ATA or OLD. Ghost will be killed later in 236 * attach routine. 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(10); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0 - or maybe it's the controller. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 263 if (chp->wdc == NULL || 264 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 265 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 266 } 267 } 268 return (ret_value); 269 } 270 271 void 272 wdcattach(chp) 273 struct channel_softc *chp; 274 { 275 int channel_flags, ctrl_flags, i, error; 276 struct ata_atapi_attach aa_link; 277 struct ataparams params; 278 static int inited = 0; 279 280 if ((error = wdc_addref(chp)) != 0) { 281 printf("%s: unable to enable controller\n", 282 chp->wdc->sc_dev.dv_xname); 283 return; 284 } 285 286 if (wdcprobe(chp) == 0) { 287 /* If no drives, abort attach here. */ 288 wdc_delref(chp); 289 return; 290 } 291 292 /* init list only once */ 293 if (inited == 0) { 294 LIST_INIT(&xfer_free_list); 295 inited++; 296 } 297 TAILQ_INIT(&chp->ch_queue->sc_xfer); 298 299 for (i = 0; i < 2; i++) { 300 chp->ch_drive[i].chnl_softc = chp; 301 chp->ch_drive[i].drive = i; 302 /* If controller can't do 16bit flag the drives as 32bit */ 303 if ((chp->wdc->cap & 304 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 305 WDC_CAPABILITY_DATA32) 306 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 307 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 308 continue; 309 310 /* Issue a IDENTIFY command, to try to detect slave ghost */ 311 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) == 312 CMD_OK) { 313 /* If IDENTIFY succeded, this is not an OLD ctrl */ 314 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 315 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 316 } else { 317 chp->ch_drive[i].drive_flags &= 318 ~(DRIVE_ATA | DRIVE_ATAPI); 319 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 320 chp->wdc->sc_dev.dv_xname, 321 chp->channel, i), DEBUG_PROBE); 322 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 323 continue; 324 /* 325 * Pre-ATA drive ? 326 * Test registers writability (Error register not 327 * writable, but cyllo is), then try an ATA command. 328 */ 329 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 330 WDSD_IBM | (i << 4)); 331 delay(10); 332 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 333 wd_error, 0x58); 334 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 335 wd_cyl_lo, 0xa5); 336 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 337 wd_error == 0x58) || 338 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 339 wd_cyl_lo) != 0xa5) { 340 WDCDEBUG_PRINT(("%s:%d:%d: register " 341 "writability failed\n", 342 chp->wdc->sc_dev.dv_xname, 343 chp->channel, i), DEBUG_PROBE); 344 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 345 } 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 347 WDSD_IBM | (i << 4)); 348 delay(100); 349 if (wait_for_ready(chp, 10000) != 0) { 350 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 351 chp->wdc->sc_dev.dv_xname, 352 chp->channel, i), DEBUG_PROBE); 353 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 354 continue; 355 } 356 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 357 wd_command, WDCC_RECAL); 358 if (wait_for_ready(chp, 10000) != 0) { 359 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 360 chp->wdc->sc_dev.dv_xname, 361 chp->channel, i), DEBUG_PROBE); 362 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 363 } 364 } 365 } 366 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 367 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 368 369 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 370 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 371 DEBUG_PROBE); 372 373 /* If no drives, abort here */ 374 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 375 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 376 return; 377 378 /* 379 * Attach an ATAPI bus, if needed. 380 */ 381 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 382 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 383 #if NATAPIBUS > 0 384 wdc_atapibus_attach(chp); 385 #else 386 /* 387 * Fills in a fake aa_link and call config_found, so that 388 * the config machinery will print 389 * "atapibus at xxx not configured" 390 */ 391 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 392 aa_link.aa_type = T_ATAPI; 393 aa_link.aa_channel = chp->channel; 394 aa_link.aa_openings = 1; 395 aa_link.aa_drv_data = 0; 396 aa_link.aa_bus_private = NULL; 397 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 398 atapi_print); 399 #endif 400 } 401 402 for (i = 0; i < 2; i++) { 403 if ((chp->ch_drive[i].drive_flags & 404 (DRIVE_ATA | DRIVE_OLD)) == 0) { 405 continue; 406 } 407 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 408 aa_link.aa_type = T_ATA; 409 aa_link.aa_channel = chp->channel; 410 aa_link.aa_openings = 1; 411 aa_link.aa_drv_data = &chp->ch_drive[i]; 412 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 413 wdc_probe_caps(&chp->ch_drive[i]); 414 } 415 416 /* 417 * reset drive_flags for unnatached devices, reset state for attached 418 * ones 419 */ 420 for (i = 0; i < 2; i++) { 421 if (chp->ch_drive[i].drv_softc == NULL) 422 chp->ch_drive[i].drive_flags = 0; 423 else 424 chp->ch_drive[i].state = 0; 425 } 426 427 /* 428 * Reset channel. The probe, with some combinations of ATA/ATAPI 429 * devices keep it in a mostly working, but strange state (with busy 430 * led on) 431 */ 432 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 433 wdcreset(chp, VERBOSE); 434 /* 435 * Read status registers to avoid spurious interrupts. 436 */ 437 for (i = 1; i >= 0; i--) { 438 if (chp->ch_drive[i].drive_flags & DRIVE) { 439 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 440 wd_sdh, WDSD_IBM | (i << 4)); 441 if (wait_for_unbusy(chp, 10000) < 0) 442 printf("%s:%d:%d: device busy\n", 443 chp->wdc->sc_dev.dv_xname, 444 chp->channel, i); 445 } 446 } 447 } 448 wdc_delref(chp); 449 } 450 451 /* 452 * Start I/O on a controller, for the given channel. 453 * The first xfer may be not for our channel if the channel queues 454 * are shared. 455 */ 456 void 457 wdcstart(chp) 458 struct channel_softc *chp; 459 { 460 struct wdc_xfer *xfer; 461 462 #ifdef WDC_DIAGNOSTIC 463 int spl1, spl2; 464 465 spl1 = splbio(); 466 spl2 = splbio(); 467 if (spl2 != spl1) { 468 printf("wdcstart: not at splbio()\n"); 469 panic("wdcstart"); 470 } 471 splx(spl2); 472 splx(spl1); 473 #endif /* WDC_DIAGNOSTIC */ 474 475 /* is there a xfer ? */ 476 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 477 return; 478 479 /* adjust chp, in case we have a shared queue */ 480 chp = xfer->chp; 481 482 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 483 return; /* channel aleady active */ 484 } 485 #ifdef DIAGNOSTIC 486 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 487 panic("wdcstart: channel waiting for irq\n"); 488 #endif 489 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 490 if (!(*chp->wdc->claim_hw)(chp, 0)) 491 return; 492 493 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 494 chp->channel, xfer->drive), DEBUG_XFERS); 495 chp->ch_flags |= WDCF_ACTIVE; 496 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 497 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 498 chp->ch_drive[xfer->drive].state = 0; 499 } 500 xfer->c_start(chp, xfer); 501 } 502 503 /* restart an interrupted I/O */ 504 void 505 wdcrestart(v) 506 void *v; 507 { 508 struct channel_softc *chp = v; 509 int s; 510 511 s = splbio(); 512 wdcstart(chp); 513 splx(s); 514 } 515 516 517 /* 518 * Interrupt routine for the controller. Acknowledge the interrupt, check for 519 * errors on the current operation, mark it done if necessary, and start the 520 * next request. Also check for a partially done transfer, and continue with 521 * the next chunk if so. 522 */ 523 int 524 wdcintr(arg) 525 void *arg; 526 { 527 struct channel_softc *chp = arg; 528 struct wdc_xfer *xfer; 529 530 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 531 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 532 return 0; 533 } 534 535 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 536 untimeout(wdctimeout, chp); 537 chp->ch_flags &= ~WDCF_IRQ_WAIT; 538 xfer = chp->ch_queue->sc_xfer.tqh_first; 539 return xfer->c_intr(chp, xfer, 1); 540 } 541 542 /* Put all disk in RESET state */ 543 void wdc_reset_channel(drvp) 544 struct ata_drive_datas *drvp; 545 { 546 struct channel_softc *chp = drvp->chnl_softc; 547 int drive; 548 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 549 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 550 DEBUG_FUNCS); 551 (void) wdcreset(chp, VERBOSE); 552 for (drive = 0; drive < 2; drive++) { 553 chp->ch_drive[drive].state = 0; 554 } 555 } 556 557 int 558 wdcreset(chp, verb) 559 struct channel_softc *chp; 560 int verb; 561 { 562 int drv_mask1, drv_mask2; 563 564 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 565 WDSD_IBM); /* master */ 566 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 567 WDCTL_RST | WDCTL_IDS); 568 delay(1000); 569 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 570 WDCTL_IDS); 571 delay(1000); 572 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 573 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 574 WDCTL_4BIT); 575 576 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 577 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 578 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 579 if (verb && drv_mask2 != drv_mask1) { 580 printf("%s channel %d: reset failed for", 581 chp->wdc->sc_dev.dv_xname, chp->channel); 582 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 583 printf(" drive 0"); 584 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 585 printf(" drive 1"); 586 printf("\n"); 587 } 588 return (drv_mask1 != drv_mask2) ? 1 : 0; 589 } 590 591 static int 592 __wdcwait_reset(chp, drv_mask) 593 struct channel_softc *chp; 594 int drv_mask; 595 { 596 int timeout; 597 u_int8_t st0, st1; 598 /* wait for BSY to deassert */ 599 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 600 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 601 WDSD_IBM); /* master */ 602 delay(10); 603 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 604 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 605 WDSD_IBM | 0x10); /* slave */ 606 delay(10); 607 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 608 609 if ((drv_mask & 0x01) == 0) { 610 /* no master */ 611 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 612 /* No master, slave is ready, it's done */ 613 goto end; 614 } 615 } else if ((drv_mask & 0x02) == 0) { 616 /* no slave */ 617 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 618 /* No slave, master is ready, it's done */ 619 goto end; 620 } 621 } else { 622 /* Wait for both master and slave to be ready */ 623 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 624 goto end; 625 } 626 } 627 delay(WDCDELAY); 628 } 629 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 630 if (st0 & WDCS_BSY) 631 drv_mask &= ~0x01; 632 if (st1 & WDCS_BSY) 633 drv_mask &= ~0x02; 634 end: 635 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 636 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 637 st0, st1), DEBUG_PROBE); 638 639 return drv_mask; 640 } 641 642 /* 643 * Wait for a drive to be !BSY, and have mask in its status register. 644 * return -1 for a timeout after "timeout" ms. 645 */ 646 int 647 wdcwait(chp, mask, bits, timeout) 648 struct channel_softc *chp; 649 int mask, bits, timeout; 650 { 651 u_char status; 652 int time = 0; 653 #ifdef WDCNDELAY_DEBUG 654 extern int cold; 655 #endif 656 657 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 658 :"none", chp->channel), DEBUG_STATUS); 659 chp->ch_error = 0; 660 661 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 662 663 for (;;) { 664 chp->ch_status = status = 665 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 666 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 667 break; 668 if (++time > timeout) { 669 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 670 "error %x\n", status, 671 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 672 wd_error)), 673 DEBUG_STATUS); 674 return -1; 675 } 676 delay(WDCDELAY); 677 } 678 if (status & WDCS_ERR) 679 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 680 wd_error); 681 #ifdef WDCNDELAY_DEBUG 682 /* After autoconfig, there should be no long delays. */ 683 if (!cold && time > WDCNDELAY_DEBUG) { 684 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 685 if (xfer == NULL) 686 printf("%s channel %d: warning: busy-wait took %dus\n", 687 chp->wdc->sc_dev.dv_xname, chp->channel, 688 WDCDELAY * time); 689 else 690 printf("%s:%d:%d: warning: busy-wait took %dus\n", 691 chp->wdc->sc_dev.dv_xname, chp->channel, 692 xfer->drive, 693 WDCDELAY * time); 694 } 695 #endif 696 return 0; 697 } 698 699 void 700 wdctimeout(arg) 701 void *arg; 702 { 703 struct channel_softc *chp = (struct channel_softc *)arg; 704 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 705 int s; 706 707 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 708 709 s = splbio(); 710 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 711 __wdcerror(chp, "lost interrupt"); 712 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 713 "atapi":"ata"); 714 printf("\tc_bcount: %d\n", xfer->c_bcount); 715 printf("\tc_skip: %d\n", xfer->c_skip); 716 /* 717 * Call the interrupt routine. If we just missed and interrupt, 718 * it will do what's needed. Else, it will take the needed 719 * action (reset the device). 720 */ 721 xfer->c_flags |= C_TIMEOU; 722 chp->ch_flags &= ~WDCF_IRQ_WAIT; 723 xfer->c_intr(chp, xfer, 1); 724 } else 725 __wdcerror(chp, "missing untimeout"); 726 splx(s); 727 } 728 729 /* 730 * Probe drive's capabilites, for use by the controller later 731 * Assumes drvp points to an existing drive. 732 * XXX this should be a controller-indep function 733 */ 734 void 735 wdc_probe_caps(drvp) 736 struct ata_drive_datas *drvp; 737 { 738 struct ataparams params, params2; 739 struct channel_softc *chp = drvp->chnl_softc; 740 struct device *drv_dev = drvp->drv_softc; 741 struct wdc_softc *wdc = chp->wdc; 742 int i, printed; 743 char *sep = ""; 744 int cf_flags; 745 746 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 747 /* IDENTIFY failed. Can't tell more about the device */ 748 return; 749 } 750 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 751 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 752 /* 753 * Controller claims 16 and 32 bit transfers. 754 * Re-do an IDENTIFY with 32-bit transfers, 755 * and compare results. 756 */ 757 drvp->drive_flags |= DRIVE_CAP32; 758 ata_get_params(drvp, AT_POLL, ¶ms2); 759 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 760 /* Not good. fall back to 16bits */ 761 drvp->drive_flags &= ~DRIVE_CAP32; 762 } else { 763 printf("%s: 32-bits data port", drv_dev->dv_xname); 764 } 765 } 766 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 767 if (params.atap_ata_major > 0x01 && 768 params.atap_ata_major != 0xffff) { 769 for (i = 14; i > 0; i--) { 770 if (params.atap_ata_major & (1 << i)) { 771 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 772 printf("%s: ", drv_dev->dv_xname); 773 else 774 printf(", "); 775 printf("ATA version %d\n", i); 776 drvp->ata_vers = i; 777 break; 778 } 779 } 780 } else 781 #endif 782 if (drvp->drive_flags & DRIVE_CAP32) 783 printf("\n"); 784 785 /* An ATAPI device is at last PIO mode 3 */ 786 if (drvp->drive_flags & DRIVE_ATAPI) 787 drvp->PIO_mode = 3; 788 789 /* 790 * It's not in the specs, but it seems that some drive 791 * returns 0xffff in atap_extensions when this field is invalid 792 */ 793 if (params.atap_extensions != 0xffff && 794 (params.atap_extensions & WDC_EXT_MODES)) { 795 printed = 0; 796 /* 797 * XXX some drives report something wrong here (they claim to 798 * support PIO mode 8 !). As mode is coded on 3 bits in 799 * SET FEATURE, limit it to 7 (so limit i to 4). 800 * If higther mode than 7 is found, abort. 801 */ 802 for (i = 7; i >= 0; i--) { 803 if ((params.atap_piomode_supp & (1 << i)) == 0) 804 continue; 805 if (i > 4) 806 return; 807 /* 808 * See if mode is accepted. 809 * If the controller can't set its PIO mode, 810 * assume the defaults are good, so don't try 811 * to set it 812 */ 813 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 814 if (ata_set_mode(drvp, 0x08 | (i + 3), 815 AT_POLL) != CMD_OK) 816 continue; 817 if (!printed) { 818 printf("%s: drive supports PIO mode %d", 819 drv_dev->dv_xname, i + 3); 820 sep = ","; 821 printed = 1; 822 } 823 /* 824 * If controller's driver can't set its PIO mode, 825 * get the highter one for the drive. 826 */ 827 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 828 wdc->PIO_cap >= i + 3) { 829 drvp->PIO_mode = i + 3; 830 drvp->PIO_cap = i + 3; 831 break; 832 } 833 } 834 if (!printed) { 835 /* 836 * We didn't find a valid PIO mode. 837 * Assume the values returned for DMA are buggy too 838 */ 839 return; 840 } 841 drvp->drive_flags |= DRIVE_MODE; 842 printed = 0; 843 for (i = 7; i >= 0; i--) { 844 if ((params.atap_dmamode_supp & (1 << i)) == 0) 845 continue; 846 if ((wdc->cap & WDC_CAPABILITY_DMA) && 847 (wdc->cap & WDC_CAPABILITY_MODE)) 848 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 849 != CMD_OK) 850 continue; 851 if (!printed) { 852 printf("%s DMA mode %d", sep, i); 853 sep = ","; 854 printed = 1; 855 } 856 if (wdc->cap & WDC_CAPABILITY_DMA) { 857 if ((wdc->cap & WDC_CAPABILITY_MODE) && 858 wdc->DMA_cap < i) 859 continue; 860 drvp->DMA_mode = i; 861 drvp->DMA_cap = i; 862 drvp->drive_flags |= DRIVE_DMA; 863 } 864 break; 865 } 866 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 867 for (i = 7; i >= 0; i--) { 868 if ((params.atap_udmamode_supp & (1 << i)) 869 == 0) 870 continue; 871 if ((wdc->cap & WDC_CAPABILITY_MODE) && 872 (wdc->cap & WDC_CAPABILITY_UDMA)) 873 if (ata_set_mode(drvp, 0x40 | i, 874 AT_POLL) != CMD_OK) 875 continue; 876 printf("%s Ultra-DMA mode %d", sep, i); 877 sep = ","; 878 if (wdc->cap & WDC_CAPABILITY_UDMA) { 879 if ((wdc->cap & WDC_CAPABILITY_MODE) && 880 wdc->UDMA_cap < i) 881 continue; 882 drvp->UDMA_mode = i; 883 drvp->UDMA_cap = i; 884 drvp->drive_flags |= DRIVE_UDMA; 885 } 886 break; 887 } 888 } 889 printf("\n"); 890 } 891 892 /* Try to guess ATA version here, if it didn't get reported */ 893 if (drvp->ata_vers == 0) { 894 if (drvp->drive_flags & DRIVE_UDMA) 895 drvp->ata_vers = 4; /* should be at last ATA-4 */ 896 else if (drvp->PIO_cap > 2) 897 drvp->ata_vers = 2; /* should be at last ATA-2 */ 898 } 899 cf_flags = drv_dev->dv_cfdata->cf_flags; 900 if (cf_flags & ATA_CONFIG_PIO_SET) { 901 drvp->PIO_mode = 902 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 903 drvp->drive_flags |= DRIVE_MODE; 904 } 905 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 906 /* don't care about DMA modes */ 907 return; 908 } 909 if (cf_flags & ATA_CONFIG_DMA_SET) { 910 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 911 ATA_CONFIG_DMA_DISABLE) { 912 drvp->drive_flags &= ~DRIVE_DMA; 913 } else { 914 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 915 ATA_CONFIG_DMA_OFF; 916 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 917 } 918 } 919 if (cf_flags & ATA_CONFIG_UDMA_SET) { 920 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 921 ATA_CONFIG_UDMA_DISABLE) { 922 drvp->drive_flags &= ~DRIVE_UDMA; 923 } else { 924 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 925 ATA_CONFIG_UDMA_OFF; 926 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 927 } 928 } 929 } 930 931 /* 932 * downgrade the transfer mode of a drive after an error. return 1 if 933 * downgrade was possible, 0 otherwise. 934 */ 935 int 936 wdc_downgrade_mode(drvp) 937 struct ata_drive_datas *drvp; 938 { 939 struct channel_softc *chp = drvp->chnl_softc; 940 struct device *drv_dev = drvp->drv_softc; 941 struct wdc_softc *wdc = chp->wdc; 942 int cf_flags = drv_dev->dv_cfdata->cf_flags; 943 944 /* if drive or controller don't know its mode, we can't do much */ 945 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 946 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 947 return 0; 948 /* current drive mode was set by a config flag, let it this way */ 949 if ((cf_flags & ATA_CONFIG_PIO_SET) || 950 (cf_flags & ATA_CONFIG_DMA_SET) || 951 (cf_flags & ATA_CONFIG_UDMA_SET)) 952 return 0; 953 954 /* 955 * If we were using ultra-DMA, don't downgrade to multiword DMA 956 * if we noticed a CRC error. It has been noticed that CRC errors 957 * in ultra-DMA lead to silent data corruption in multiword DMA. 958 * Data corruption is less likely to occur in PIO mode. 959 */ 960 961 if ((drvp->drive_flags & DRIVE_UDMA) && 962 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 963 drvp->drive_flags &= ~DRIVE_UDMA; 964 drvp->drive_flags |= DRIVE_DMA; 965 drvp->DMA_mode = drvp->DMA_cap; 966 printf("%s: transfer error, downgrading to DMA mode %d\n", 967 drv_dev->dv_xname, drvp->DMA_mode); 968 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 969 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 970 drvp->PIO_mode = drvp->PIO_cap; 971 printf("%s: transfer error, downgrading to PIO mode %d\n", 972 drv_dev->dv_xname, drvp->PIO_mode); 973 } else /* already using PIO, can't downgrade */ 974 return 0; 975 976 wdc->set_modes(chp); 977 /* reset the channel, which will shedule all drives for setup */ 978 wdc_reset_channel(drvp); 979 return 1; 980 } 981 982 int 983 wdc_exec_command(drvp, wdc_c) 984 struct ata_drive_datas *drvp; 985 struct wdc_command *wdc_c; 986 { 987 struct channel_softc *chp = drvp->chnl_softc; 988 struct wdc_xfer *xfer; 989 int s, ret; 990 991 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 992 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 993 DEBUG_FUNCS); 994 995 /* set up an xfer and queue. Wait for completion */ 996 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 997 WDC_NOSLEEP); 998 if (xfer == NULL) { 999 return WDC_TRY_AGAIN; 1000 } 1001 1002 if (wdc_c->flags & AT_POLL) 1003 xfer->c_flags |= C_POLL; 1004 xfer->drive = drvp->drive; 1005 xfer->databuf = wdc_c->data; 1006 xfer->c_bcount = wdc_c->bcount; 1007 xfer->cmd = wdc_c; 1008 xfer->c_start = __wdccommand_start; 1009 xfer->c_intr = __wdccommand_intr; 1010 1011 s = splbio(); 1012 wdc_exec_xfer(chp, xfer); 1013 #ifdef DIAGNOSTIC 1014 if ((wdc_c->flags & AT_POLL) != 0 && 1015 (wdc_c->flags & AT_DONE) == 0) 1016 panic("wdc_exec_command: polled command not done\n"); 1017 #endif 1018 if (wdc_c->flags & AT_DONE) { 1019 ret = WDC_COMPLETE; 1020 } else { 1021 if (wdc_c->flags & AT_WAIT) { 1022 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1023 ret = WDC_COMPLETE; 1024 } else { 1025 ret = WDC_QUEUED; 1026 } 1027 } 1028 splx(s); 1029 return ret; 1030 } 1031 1032 void 1033 __wdccommand_start(chp, xfer) 1034 struct channel_softc *chp; 1035 struct wdc_xfer *xfer; 1036 { 1037 int drive = xfer->drive; 1038 struct wdc_command *wdc_c = xfer->cmd; 1039 1040 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1041 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1042 DEBUG_FUNCS); 1043 1044 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1045 WDSD_IBM | (drive << 4)); 1046 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1047 wdc_c->timeout) != 0) { 1048 wdc_c->flags |= AT_TIMEOU; 1049 __wdccommand_done(chp, xfer); 1050 return; 1051 } 1052 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1053 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1054 if ((wdc_c->flags & AT_POLL) == 0) { 1055 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1056 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1057 return; 1058 } 1059 /* 1060 * Polled command. Wait for drive ready or drq. Done in intr(). 1061 * Wait for at last 400ns for status bit to be valid. 1062 */ 1063 delay(10); 1064 __wdccommand_intr(chp, xfer, 0); 1065 } 1066 1067 int 1068 __wdccommand_intr(chp, xfer, irq) 1069 struct channel_softc *chp; 1070 struct wdc_xfer *xfer; 1071 int irq; 1072 { 1073 struct wdc_command *wdc_c = xfer->cmd; 1074 int bcount = wdc_c->bcount; 1075 char *data = wdc_c->data; 1076 1077 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1078 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1079 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1080 (irq == 0) ? wdc_c->timeout : 0)) { 1081 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1082 return 0; /* IRQ was not for us */ 1083 wdc_c->flags |= AT_TIMEOU; 1084 __wdccommand_done(chp, xfer); 1085 return 1; 1086 } 1087 if (wdc_c->flags & AT_READ) { 1088 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1089 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1090 0, (u_int32_t*)data, bcount >> 2); 1091 data += bcount & 0xfffffffc; 1092 bcount = bcount & 0x03; 1093 } 1094 if (bcount > 0) 1095 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1096 wd_data, (u_int16_t *)data, bcount >> 1); 1097 } else if (wdc_c->flags & AT_WRITE) { 1098 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1099 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1100 0, (u_int32_t*)data, bcount >> 2); 1101 data += bcount & 0xfffffffc; 1102 bcount = bcount & 0x03; 1103 } 1104 if (bcount > 0) 1105 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1106 wd_data, (u_int16_t *)data, bcount >> 1); 1107 } 1108 __wdccommand_done(chp, xfer); 1109 return 1; 1110 } 1111 1112 void 1113 __wdccommand_done(chp, xfer) 1114 struct channel_softc *chp; 1115 struct wdc_xfer *xfer; 1116 { 1117 int needdone = xfer->c_flags & C_NEEDDONE; 1118 struct wdc_command *wdc_c = xfer->cmd; 1119 1120 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1121 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1122 if (chp->ch_status & WDCS_DWF) 1123 wdc_c->flags |= AT_DF; 1124 if (chp->ch_status & WDCS_ERR) { 1125 wdc_c->flags |= AT_ERROR; 1126 wdc_c->r_error = chp->ch_error; 1127 } 1128 wdc_c->flags |= AT_DONE; 1129 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1130 == 0) { 1131 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1132 wd_sdh); 1133 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1134 wd_cyl_hi) << 8; 1135 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1136 wd_cyl_lo); 1137 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1138 wd_sector); 1139 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1140 wd_seccnt); 1141 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1142 wd_error); 1143 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1144 wd_precomp); 1145 } 1146 wdc_free_xfer(chp, xfer); 1147 if (needdone) { 1148 if (wdc_c->flags & AT_WAIT) 1149 wakeup(wdc_c); 1150 else 1151 wdc_c->callback(wdc_c->callback_arg); 1152 } 1153 wdcstart(chp); 1154 return; 1155 } 1156 1157 /* 1158 * Send a command. The drive should be ready. 1159 * Assumes interrupts are blocked. 1160 */ 1161 void 1162 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1163 struct channel_softc *chp; 1164 u_int8_t drive; 1165 u_int8_t command; 1166 u_int16_t cylin; 1167 u_int8_t head, sector, count, precomp; 1168 { 1169 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1170 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1171 chp->channel, drive, command, cylin, head, sector, count, precomp), 1172 DEBUG_FUNCS); 1173 1174 /* Select drive, head, and addressing mode. */ 1175 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1176 WDSD_IBM | (drive << 4) | head); 1177 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1178 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1179 precomp); 1180 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1181 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1182 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1183 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1184 1185 /* Send command. */ 1186 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1187 return; 1188 } 1189 1190 /* 1191 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1192 * tested by the caller. 1193 */ 1194 void 1195 wdccommandshort(chp, drive, command) 1196 struct channel_softc *chp; 1197 int drive; 1198 int command; 1199 { 1200 1201 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1202 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1203 DEBUG_FUNCS); 1204 1205 /* Select drive. */ 1206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1207 WDSD_IBM | (drive << 4)); 1208 1209 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1210 } 1211 1212 /* Add a command to the queue and start controller. Must be called at splbio */ 1213 1214 void 1215 wdc_exec_xfer(chp, xfer) 1216 struct channel_softc *chp; 1217 struct wdc_xfer *xfer; 1218 { 1219 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1220 chp->channel, xfer->drive), DEBUG_XFERS); 1221 1222 /* complete xfer setup */ 1223 xfer->chp = chp; 1224 1225 /* 1226 * If we are a polled command, and the list is not empty, 1227 * we are doing a dump. Drop the list to allow the polled command 1228 * to complete, we're going to reboot soon anyway. 1229 */ 1230 if ((xfer->c_flags & C_POLL) != 0 && 1231 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1232 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1233 } 1234 /* insert at the end of command list */ 1235 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1236 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1237 chp->ch_flags), DEBUG_XFERS); 1238 wdcstart(chp); 1239 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1240 } 1241 1242 struct wdc_xfer * 1243 wdc_get_xfer(flags) 1244 int flags; 1245 { 1246 struct wdc_xfer *xfer; 1247 int s; 1248 1249 s = splbio(); 1250 if ((xfer = xfer_free_list.lh_first) != NULL) { 1251 LIST_REMOVE(xfer, free_list); 1252 splx(s); 1253 #ifdef DIAGNOSTIC 1254 if ((xfer->c_flags & C_INUSE) != 0) 1255 panic("wdc_get_xfer: xfer already in use\n"); 1256 #endif 1257 } else { 1258 splx(s); 1259 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1260 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1261 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1262 if (xfer == NULL) 1263 return 0; 1264 #ifdef DIAGNOSTIC 1265 xfer->c_flags &= ~C_INUSE; 1266 #endif 1267 #ifdef WDCDEBUG 1268 wdc_nxfer++; 1269 #endif 1270 } 1271 #ifdef DIAGNOSTIC 1272 if ((xfer->c_flags & C_INUSE) != 0) 1273 panic("wdc_get_xfer: xfer already in use\n"); 1274 #endif 1275 memset(xfer, 0, sizeof(struct wdc_xfer)); 1276 xfer->c_flags = C_INUSE; 1277 return xfer; 1278 } 1279 1280 void 1281 wdc_free_xfer(chp, xfer) 1282 struct channel_softc *chp; 1283 struct wdc_xfer *xfer; 1284 { 1285 struct wdc_softc *wdc = chp->wdc; 1286 int s; 1287 1288 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1289 (*wdc->free_hw)(chp); 1290 s = splbio(); 1291 chp->ch_flags &= ~WDCF_ACTIVE; 1292 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1293 xfer->c_flags &= ~C_INUSE; 1294 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1295 splx(s); 1296 } 1297 1298 static void 1299 __wdcerror(chp, msg) 1300 struct channel_softc *chp; 1301 char *msg; 1302 { 1303 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1304 if (xfer == NULL) 1305 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1306 msg); 1307 else 1308 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1309 chp->channel, xfer->drive, msg); 1310 } 1311 1312 /* 1313 * the bit bucket 1314 */ 1315 void 1316 wdcbit_bucket(chp, size) 1317 struct channel_softc *chp; 1318 int size; 1319 { 1320 1321 for (; size >= 2; size -= 2) 1322 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1323 if (size) 1324 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1325 } 1326 1327 int 1328 wdc_addref(chp) 1329 struct channel_softc *chp; 1330 { 1331 struct wdc_softc *wdc = chp->wdc; 1332 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1333 int s, error = 0; 1334 1335 s = splbio(); 1336 if (adapter->scsipi_refcnt++ == 0 && 1337 adapter->scsipi_enable != NULL) { 1338 error = (*adapter->scsipi_enable)(wdc, 1); 1339 if (error) 1340 adapter->scsipi_refcnt--; 1341 } 1342 splx(s); 1343 return (error); 1344 } 1345 1346 void 1347 wdc_delref(chp) 1348 struct channel_softc *chp; 1349 { 1350 struct wdc_softc *wdc = chp->wdc; 1351 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1352 int s; 1353 1354 s = splbio(); 1355 if (adapter->scsipi_refcnt-- == 1 && 1356 adapter->scsipi_enable != NULL) 1357 (void) (*adapter->scsipi_enable)(wdc, 0); 1358 splx(s); 1359 } 1360
Indexes created Fri Sep 26 20:09:58 GMT 2025