wdc.c revision 1.70
1 /* $NetBSD: wdc.c,v 1.70 1999/08/06 12:00:25 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <vm/vm.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "atapibus.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 LIST_HEAD(xfer_free_list, wdc_xfer) xfer_free_list; 115 116 static void __wdcerror __P((struct channel_softc*, char *)); 117 static int __wdcwait_reset __P((struct channel_softc *, int)); 118 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 119 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 120 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 121 int wdprint __P((void *, const char *)); 122 123 124 #define DEBUG_INTR 0x01 125 #define DEBUG_XFERS 0x02 126 #define DEBUG_STATUS 0x04 127 #define DEBUG_FUNCS 0x08 128 #define DEBUG_PROBE 0x10 129 #ifdef WDCDEBUG 130 int wdcdebug_mask = 0; 131 int wdc_nxfer = 0; 132 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 133 #else 134 #define WDCDEBUG_PRINT(args, level) 135 #endif 136 137 int 138 wdprint(aux, pnp) 139 void *aux; 140 const char *pnp; 141 { 142 struct ata_atapi_attach *aa_link = aux; 143 if (pnp) 144 printf("drive at %s", pnp); 145 printf(" channel %d drive %d", aa_link->aa_channel, 146 aa_link->aa_drv_data->drive); 147 return (UNCONF); 148 } 149 150 int 151 atapi_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 struct ata_atapi_attach *aa_link = aux; 156 if (pnp) 157 printf("atapibus at %s", pnp); 158 printf(" channel %d", aa_link->aa_channel); 159 return (UNCONF); 160 } 161 162 /* Test to see controller with at last one attached drive is there. 163 * Returns a bit for each possible drive found (0x01 for drive 0, 164 * 0x02 for drive 1). 165 * Logic: 166 * - If a status register is at 0xff, assume there is no drive here 167 * (ISA has pull-up resistors). If no drive at all -> return. 168 * - reset the controller, wait for it to complete (may take up to 31s !). 169 * If timeout -> return. 170 * - test ATA/ATAPI signatures. If at last one drive found -> return. 171 * - try an ATA command on the master. 172 */ 173 174 int 175 wdcprobe(chp) 176 struct channel_softc *chp; 177 { 178 u_int8_t st0, st1, sc, sn, cl, ch; 179 u_int8_t ret_value = 0x03; 180 u_int8_t drive; 181 182 /* 183 * Sanity check to see if the wdc channel responds at all. 184 */ 185 186 if (chp->wdc == NULL || 187 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 188 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 189 WDSD_IBM); 190 delay(10); 191 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 192 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 193 WDSD_IBM | 0x10); 194 delay(10); 195 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 196 197 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 198 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 199 chp->channel, st0, st1), DEBUG_PROBE); 200 201 if (st0 == 0xff) 202 ret_value &= ~0x01; 203 if (st1 == 0xff) 204 ret_value &= ~0x02; 205 if (ret_value == 0) 206 return 0; 207 } 208 209 /* assert SRST, wait for reset to complete */ 210 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 211 WDSD_IBM); 212 delay(10); 213 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 214 WDCTL_RST | WDCTL_IDS); 215 DELAY(1000); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_IDS); 218 delay(1000); 219 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 220 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 221 delay(10); 222 223 ret_value = __wdcwait_reset(chp, ret_value); 224 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 225 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 226 ret_value), DEBUG_PROBE); 227 228 /* if reset failed, there's nothing here */ 229 if (ret_value == 0) 230 return 0; 231 232 /* 233 * Test presence of drives. First test register signatures looking for 234 * ATAPI devices. If it's not an ATAPI and reset said there may be 235 * something here assume it's ATA or OLD. Ghost will be killed later in 236 * attach routine. 237 */ 238 for (drive = 0; drive < 2; drive++) { 239 if ((ret_value & (0x01 << drive)) == 0) 240 continue; 241 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 242 WDSD_IBM | (drive << 4)); 243 delay(10); 244 /* Save registers contents */ 245 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 246 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 247 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 248 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 249 250 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 251 "cl=0x%x ch=0x%x\n", 252 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 253 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 254 /* 255 * sc is supposted to be 0x1 for ATAPI but at last one drive 256 * set it to 0x0 - or maybe it's the controller. 257 */ 258 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 259 cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 263 if (chp->wdc == NULL || 264 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 265 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 266 } 267 } 268 return (ret_value); 269 } 270 271 void 272 wdcattach(chp) 273 struct channel_softc *chp; 274 { 275 int channel_flags, ctrl_flags, i, error; 276 struct ata_atapi_attach aa_link; 277 struct ataparams params; 278 static int inited = 0; 279 280 if ((error = wdc_addref(chp)) != 0) { 281 printf("%s: unable to enable controller\n", 282 chp->wdc->sc_dev.dv_xname); 283 return; 284 } 285 286 if (wdcprobe(chp) == 0) { 287 /* If no drives, abort attach here. */ 288 wdc_delref(chp); 289 return; 290 } 291 292 /* init list only once */ 293 if (inited == 0) { 294 LIST_INIT(&xfer_free_list); 295 inited++; 296 } 297 TAILQ_INIT(&chp->ch_queue->sc_xfer); 298 299 for (i = 0; i < 2; i++) { 300 chp->ch_drive[i].chnl_softc = chp; 301 chp->ch_drive[i].drive = i; 302 /* If controller can't do 16bit flag the drives as 32bit */ 303 if ((chp->wdc->cap & 304 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 305 WDC_CAPABILITY_DATA32) 306 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 307 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 308 continue; 309 310 /* Issue a IDENTIFY command, to try to detect slave ghost */ 311 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) == 312 CMD_OK) { 313 /* If IDENTIFY succeded, this is not an OLD ctrl */ 314 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 315 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 316 } else { 317 chp->ch_drive[i].drive_flags &= 318 ~(DRIVE_ATA | DRIVE_ATAPI); 319 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 320 chp->wdc->sc_dev.dv_xname, 321 chp->channel, i), DEBUG_PROBE); 322 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 323 continue; 324 /* 325 * Pre-ATA drive ? 326 * Test registers writability (Error register not 327 * writable, but cyllo is), then try an ATA command. 328 */ 329 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 330 WDSD_IBM | (i << 4)); 331 delay(10); 332 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 333 wd_error, 0x58); 334 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 335 wd_cyl_lo, 0xa5); 336 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 337 wd_error == 0x58) || 338 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 339 wd_cyl_lo) != 0xa5) { 340 WDCDEBUG_PRINT(("%s:%d:%d: register " 341 "writability failed\n", 342 chp->wdc->sc_dev.dv_xname, 343 chp->channel, i), DEBUG_PROBE); 344 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 345 } 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 347 WDSD_IBM | (i << 4)); 348 delay(100); 349 if (wait_for_ready(chp, 10000) != 0) { 350 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 351 chp->wdc->sc_dev.dv_xname, 352 chp->channel, i), DEBUG_PROBE); 353 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 354 continue; 355 } 356 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 357 wd_command, WDCC_RECAL); 358 if (wait_for_ready(chp, 10000) != 0) { 359 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 360 chp->wdc->sc_dev.dv_xname, 361 chp->channel, i), DEBUG_PROBE); 362 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 363 } 364 } 365 } 366 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 367 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 368 369 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 370 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 371 DEBUG_PROBE); 372 373 /* If no drives, abort here */ 374 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 375 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 376 return; 377 378 /* 379 * Attach an ATAPI bus, if needed. 380 */ 381 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 382 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 383 #if NATAPIBUS > 0 384 wdc_atapibus_attach(chp); 385 #else 386 /* 387 * Fills in a fake aa_link and call config_found, so that 388 * the config machinery will print 389 * "atapibus at xxx not configured" 390 */ 391 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 392 aa_link.aa_type = T_ATAPI; 393 aa_link.aa_channel = chp->channel; 394 aa_link.aa_openings = 1; 395 aa_link.aa_drv_data = 0; 396 aa_link.aa_bus_private = NULL; 397 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 398 atapi_print); 399 #endif 400 } 401 402 for (i = 0; i < 2; i++) { 403 if ((chp->ch_drive[i].drive_flags & 404 (DRIVE_ATA | DRIVE_OLD)) == 0) { 405 continue; 406 } 407 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 408 aa_link.aa_type = T_ATA; 409 aa_link.aa_channel = chp->channel; 410 aa_link.aa_openings = 1; 411 aa_link.aa_drv_data = &chp->ch_drive[i]; 412 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 413 wdc_probe_caps(&chp->ch_drive[i]); 414 } 415 416 /* 417 * reset drive_flags for unnatached devices, reset state for attached 418 * ones 419 */ 420 for (i = 0; i < 2; i++) { 421 if (chp->ch_drive[i].drv_softc == NULL) 422 chp->ch_drive[i].drive_flags = 0; 423 else 424 chp->ch_drive[i].state = 0; 425 } 426 427 /* 428 * Reset channel. The probe, with some combinations of ATA/ATAPI 429 * devices keep it in a mostly working, but strange state (with busy 430 * led on) 431 */ 432 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 433 wdcreset(chp, VERBOSE); 434 /* 435 * Read status registers to avoid spurious interrupts. 436 */ 437 for (i = 1; i >= 0; i--) { 438 if (chp->ch_drive[i].drive_flags & DRIVE) { 439 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 440 wd_sdh, WDSD_IBM | (i << 4)); 441 if (wait_for_unbusy(chp, 10000) < 0) 442 printf("%s:%d:%d: device busy\n", 443 chp->wdc->sc_dev.dv_xname, 444 chp->channel, i); 445 } 446 } 447 } 448 wdc_delref(chp); 449 } 450 451 /* 452 * Start I/O on a controller, for the given channel. 453 * The first xfer may be not for our channel if the channel queues 454 * are shared. 455 */ 456 void 457 wdcstart(chp) 458 struct channel_softc *chp; 459 { 460 struct wdc_xfer *xfer; 461 462 #ifdef WDC_DIAGNOSTIC 463 int spl1, spl2; 464 465 spl1 = splbio(); 466 spl2 = splbio(); 467 if (spl2 != spl1) { 468 printf("wdcstart: not at splbio()\n"); 469 panic("wdcstart"); 470 } 471 splx(spl2); 472 splx(spl1); 473 #endif /* WDC_DIAGNOSTIC */ 474 475 /* is there a xfer ? */ 476 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 477 return; 478 479 /* adjust chp, in case we have a shared queue */ 480 chp = xfer->chp; 481 482 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 483 return; /* channel aleady active */ 484 } 485 #ifdef DIAGNOSTIC 486 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 487 panic("wdcstart: channel waiting for irq\n"); 488 #endif 489 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 490 if (!(*chp->wdc->claim_hw)(chp, 0)) 491 return; 492 493 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 494 chp->channel, xfer->drive), DEBUG_XFERS); 495 chp->ch_flags |= WDCF_ACTIVE; 496 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 497 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 498 chp->ch_drive[xfer->drive].state = 0; 499 } 500 xfer->c_start(chp, xfer); 501 } 502 503 /* restart an interrupted I/O */ 504 void 505 wdcrestart(v) 506 void *v; 507 { 508 struct channel_softc *chp = v; 509 int s; 510 511 s = splbio(); 512 wdcstart(chp); 513 splx(s); 514 } 515 516 517 /* 518 * Interrupt routine for the controller. Acknowledge the interrupt, check for 519 * errors on the current operation, mark it done if necessary, and start the 520 * next request. Also check for a partially done transfer, and continue with 521 * the next chunk if so. 522 */ 523 int 524 wdcintr(arg) 525 void *arg; 526 { 527 struct channel_softc *chp = arg; 528 struct wdc_xfer *xfer; 529 530 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 531 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 532 return 0; 533 } 534 535 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 536 chp->ch_flags &= ~WDCF_IRQ_WAIT; 537 xfer = chp->ch_queue->sc_xfer.tqh_first; 538 return xfer->c_intr(chp, xfer, 1); 539 } 540 541 /* Put all disk in RESET state */ 542 void wdc_reset_channel(drvp) 543 struct ata_drive_datas *drvp; 544 { 545 struct channel_softc *chp = drvp->chnl_softc; 546 int drive; 547 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 548 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 549 DEBUG_FUNCS); 550 (void) wdcreset(chp, VERBOSE); 551 for (drive = 0; drive < 2; drive++) { 552 chp->ch_drive[drive].state = 0; 553 } 554 } 555 556 int 557 wdcreset(chp, verb) 558 struct channel_softc *chp; 559 int verb; 560 { 561 int drv_mask1, drv_mask2; 562 563 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 564 WDSD_IBM); /* master */ 565 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 566 WDCTL_RST | WDCTL_IDS); 567 delay(1000); 568 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 569 WDCTL_IDS); 570 delay(1000); 571 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 572 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 573 WDCTL_4BIT); 574 575 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 576 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 577 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 578 if (verb && drv_mask2 != drv_mask1) { 579 printf("%s channel %d: reset failed for", 580 chp->wdc->sc_dev.dv_xname, chp->channel); 581 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 582 printf(" drive 0"); 583 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 584 printf(" drive 1"); 585 printf("\n"); 586 } 587 return (drv_mask1 != drv_mask2) ? 1 : 0; 588 } 589 590 static int 591 __wdcwait_reset(chp, drv_mask) 592 struct channel_softc *chp; 593 int drv_mask; 594 { 595 int timeout; 596 u_int8_t st0, st1; 597 #ifdef WDCDEBUG 598 u_int8_t sc0, sn0, cl0, ch0; 599 u_int8_t sc1, sn1, cl1, ch1; 600 #endif 601 /* wait for BSY to deassert */ 602 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 603 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 604 WDSD_IBM); /* master */ 605 delay(10); 606 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 607 #ifdef WDCDEBUG 608 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 609 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 610 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 611 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 612 #endif 613 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 614 WDSD_IBM | 0x10); /* slave */ 615 delay(10); 616 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 617 #ifdef WDCDEBUG 618 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 619 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 620 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 621 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 622 #endif 623 624 if ((drv_mask & 0x01) == 0) { 625 /* no master */ 626 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 627 /* No master, slave is ready, it's done */ 628 goto end; 629 } 630 } else if ((drv_mask & 0x02) == 0) { 631 /* no slave */ 632 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 633 /* No slave, master is ready, it's done */ 634 goto end; 635 } 636 } else { 637 /* Wait for both master and slave to be ready */ 638 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 639 goto end; 640 } 641 } 642 delay(WDCDELAY); 643 } 644 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 645 if (st0 & WDCS_BSY) 646 drv_mask &= ~0x01; 647 if (st1 & WDCS_BSY) 648 drv_mask &= ~0x02; 649 end: 650 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 651 "cl=0x%x ch=0x%x\n", 652 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 653 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 654 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 655 "cl=0x%x ch=0x%x\n", 656 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 657 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 658 659 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 660 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 661 st0, st1), DEBUG_PROBE); 662 663 return drv_mask; 664 } 665 666 /* 667 * Wait for a drive to be !BSY, and have mask in its status register. 668 * return -1 for a timeout after "timeout" ms. 669 */ 670 int 671 wdcwait(chp, mask, bits, timeout) 672 struct channel_softc *chp; 673 int mask, bits, timeout; 674 { 675 u_char status; 676 int time = 0; 677 #ifdef WDCNDELAY_DEBUG 678 extern int cold; 679 #endif 680 681 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 682 :"none", chp->channel), DEBUG_STATUS); 683 chp->ch_error = 0; 684 685 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 686 687 for (;;) { 688 chp->ch_status = status = 689 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 690 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 691 break; 692 if (++time > timeout) { 693 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 694 "error %x\n", status, 695 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 696 wd_error)), 697 DEBUG_STATUS); 698 return -1; 699 } 700 delay(WDCDELAY); 701 } 702 if (status & WDCS_ERR) 703 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 704 wd_error); 705 #ifdef WDCNDELAY_DEBUG 706 /* After autoconfig, there should be no long delays. */ 707 if (!cold && time > WDCNDELAY_DEBUG) { 708 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 709 if (xfer == NULL) 710 printf("%s channel %d: warning: busy-wait took %dus\n", 711 chp->wdc->sc_dev.dv_xname, chp->channel, 712 WDCDELAY * time); 713 else 714 printf("%s:%d:%d: warning: busy-wait took %dus\n", 715 chp->wdc->sc_dev.dv_xname, chp->channel, 716 xfer->drive, 717 WDCDELAY * time); 718 } 719 #endif 720 return 0; 721 } 722 723 void 724 wdctimeout(arg) 725 void *arg; 726 { 727 struct channel_softc *chp = (struct channel_softc *)arg; 728 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 729 int s; 730 731 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 732 733 s = splbio(); 734 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 735 __wdcerror(chp, "lost interrupt"); 736 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 737 "atapi":"ata"); 738 printf("\tc_bcount: %d\n", xfer->c_bcount); 739 printf("\tc_skip: %d\n", xfer->c_skip); 740 /* 741 * Call the interrupt routine. If we just missed and interrupt, 742 * it will do what's needed. Else, it will take the needed 743 * action (reset the device). 744 * Before that we need to reinstall the timeout callback, 745 * in case it will miss another irq while in this transfer 746 * We arbitray chose it to be 1s 747 */ 748 timeout(wdctimeout, chp, hz); 749 xfer->c_flags |= C_TIMEOU; 750 chp->ch_flags &= ~WDCF_IRQ_WAIT; 751 xfer->c_intr(chp, xfer, 1); 752 } else 753 __wdcerror(chp, "missing untimeout"); 754 splx(s); 755 } 756 757 /* 758 * Probe drive's capabilites, for use by the controller later 759 * Assumes drvp points to an existing drive. 760 * XXX this should be a controller-indep function 761 */ 762 void 763 wdc_probe_caps(drvp) 764 struct ata_drive_datas *drvp; 765 { 766 struct ataparams params, params2; 767 struct channel_softc *chp = drvp->chnl_softc; 768 struct device *drv_dev = drvp->drv_softc; 769 struct wdc_softc *wdc = chp->wdc; 770 int i, printed; 771 char *sep = ""; 772 int cf_flags; 773 774 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 775 /* IDENTIFY failed. Can't tell more about the device */ 776 return; 777 } 778 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 779 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 780 /* 781 * Controller claims 16 and 32 bit transfers. 782 * Re-do an IDENTIFY with 32-bit transfers, 783 * and compare results. 784 */ 785 drvp->drive_flags |= DRIVE_CAP32; 786 ata_get_params(drvp, AT_POLL, ¶ms2); 787 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 788 /* Not good. fall back to 16bits */ 789 drvp->drive_flags &= ~DRIVE_CAP32; 790 } else { 791 printf("%s: 32-bits data port", drv_dev->dv_xname); 792 } 793 } 794 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 795 if (params.atap_ata_major > 0x01 && 796 params.atap_ata_major != 0xffff) { 797 for (i = 14; i > 0; i--) { 798 if (params.atap_ata_major & (1 << i)) { 799 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 800 printf("%s: ", drv_dev->dv_xname); 801 else 802 printf(", "); 803 printf("ATA version %d\n", i); 804 drvp->ata_vers = i; 805 break; 806 } 807 } 808 } else 809 #endif 810 if (drvp->drive_flags & DRIVE_CAP32) 811 printf("\n"); 812 813 /* An ATAPI device is at last PIO mode 3 */ 814 if (drvp->drive_flags & DRIVE_ATAPI) 815 drvp->PIO_mode = 3; 816 817 /* 818 * It's not in the specs, but it seems that some drive 819 * returns 0xffff in atap_extensions when this field is invalid 820 */ 821 if (params.atap_extensions != 0xffff && 822 (params.atap_extensions & WDC_EXT_MODES)) { 823 printed = 0; 824 /* 825 * XXX some drives report something wrong here (they claim to 826 * support PIO mode 8 !). As mode is coded on 3 bits in 827 * SET FEATURE, limit it to 7 (so limit i to 4). 828 * If higther mode than 7 is found, abort. 829 */ 830 for (i = 7; i >= 0; i--) { 831 if ((params.atap_piomode_supp & (1 << i)) == 0) 832 continue; 833 if (i > 4) 834 return; 835 /* 836 * See if mode is accepted. 837 * If the controller can't set its PIO mode, 838 * assume the defaults are good, so don't try 839 * to set it 840 */ 841 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 842 if (ata_set_mode(drvp, 0x08 | (i + 3), 843 AT_POLL) != CMD_OK) 844 continue; 845 if (!printed) { 846 printf("%s: drive supports PIO mode %d", 847 drv_dev->dv_xname, i + 3); 848 sep = ","; 849 printed = 1; 850 } 851 /* 852 * If controller's driver can't set its PIO mode, 853 * get the highter one for the drive. 854 */ 855 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 856 wdc->PIO_cap >= i + 3) { 857 drvp->PIO_mode = i + 3; 858 drvp->PIO_cap = i + 3; 859 break; 860 } 861 } 862 if (!printed) { 863 /* 864 * We didn't find a valid PIO mode. 865 * Assume the values returned for DMA are buggy too 866 */ 867 return; 868 } 869 drvp->drive_flags |= DRIVE_MODE; 870 printed = 0; 871 for (i = 7; i >= 0; i--) { 872 if ((params.atap_dmamode_supp & (1 << i)) == 0) 873 continue; 874 if ((wdc->cap & WDC_CAPABILITY_DMA) && 875 (wdc->cap & WDC_CAPABILITY_MODE)) 876 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 877 != CMD_OK) 878 continue; 879 if (!printed) { 880 printf("%s DMA mode %d", sep, i); 881 sep = ","; 882 printed = 1; 883 } 884 if (wdc->cap & WDC_CAPABILITY_DMA) { 885 if ((wdc->cap & WDC_CAPABILITY_MODE) && 886 wdc->DMA_cap < i) 887 continue; 888 drvp->DMA_mode = i; 889 drvp->DMA_cap = i; 890 drvp->drive_flags |= DRIVE_DMA; 891 } 892 break; 893 } 894 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 895 for (i = 7; i >= 0; i--) { 896 if ((params.atap_udmamode_supp & (1 << i)) 897 == 0) 898 continue; 899 if ((wdc->cap & WDC_CAPABILITY_MODE) && 900 (wdc->cap & WDC_CAPABILITY_UDMA)) 901 if (ata_set_mode(drvp, 0x40 | i, 902 AT_POLL) != CMD_OK) 903 continue; 904 printf("%s Ultra-DMA mode %d", sep, i); 905 sep = ","; 906 if (wdc->cap & WDC_CAPABILITY_UDMA) { 907 if ((wdc->cap & WDC_CAPABILITY_MODE) && 908 wdc->UDMA_cap < i) 909 continue; 910 drvp->UDMA_mode = i; 911 drvp->UDMA_cap = i; 912 drvp->drive_flags |= DRIVE_UDMA; 913 } 914 break; 915 } 916 } 917 printf("\n"); 918 } 919 920 /* Try to guess ATA version here, if it didn't get reported */ 921 if (drvp->ata_vers == 0) { 922 if (drvp->drive_flags & DRIVE_UDMA) 923 drvp->ata_vers = 4; /* should be at last ATA-4 */ 924 else if (drvp->PIO_cap > 2) 925 drvp->ata_vers = 2; /* should be at last ATA-2 */ 926 } 927 cf_flags = drv_dev->dv_cfdata->cf_flags; 928 if (cf_flags & ATA_CONFIG_PIO_SET) { 929 drvp->PIO_mode = 930 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 931 drvp->drive_flags |= DRIVE_MODE; 932 } 933 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 934 /* don't care about DMA modes */ 935 return; 936 } 937 if (cf_flags & ATA_CONFIG_DMA_SET) { 938 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 939 ATA_CONFIG_DMA_DISABLE) { 940 drvp->drive_flags &= ~DRIVE_DMA; 941 } else { 942 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 943 ATA_CONFIG_DMA_OFF; 944 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 945 } 946 } 947 if (cf_flags & ATA_CONFIG_UDMA_SET) { 948 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 949 ATA_CONFIG_UDMA_DISABLE) { 950 drvp->drive_flags &= ~DRIVE_UDMA; 951 } else { 952 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 953 ATA_CONFIG_UDMA_OFF; 954 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 955 } 956 } 957 } 958 959 /* 960 * downgrade the transfer mode of a drive after an error. return 1 if 961 * downgrade was possible, 0 otherwise. 962 */ 963 int 964 wdc_downgrade_mode(drvp) 965 struct ata_drive_datas *drvp; 966 { 967 struct channel_softc *chp = drvp->chnl_softc; 968 struct device *drv_dev = drvp->drv_softc; 969 struct wdc_softc *wdc = chp->wdc; 970 int cf_flags = drv_dev->dv_cfdata->cf_flags; 971 972 /* if drive or controller don't know its mode, we can't do much */ 973 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 974 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 975 return 0; 976 /* current drive mode was set by a config flag, let it this way */ 977 if ((cf_flags & ATA_CONFIG_PIO_SET) || 978 (cf_flags & ATA_CONFIG_DMA_SET) || 979 (cf_flags & ATA_CONFIG_UDMA_SET)) 980 return 0; 981 982 /* 983 * If we were using ultra-DMA, don't downgrade to multiword DMA 984 * if we noticed a CRC error. It has been noticed that CRC errors 985 * in ultra-DMA lead to silent data corruption in multiword DMA. 986 * Data corruption is less likely to occur in PIO mode. 987 */ 988 989 if ((drvp->drive_flags & DRIVE_UDMA) && 990 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 991 drvp->drive_flags &= ~DRIVE_UDMA; 992 drvp->drive_flags |= DRIVE_DMA; 993 drvp->DMA_mode = drvp->DMA_cap; 994 printf("%s: transfer error, downgrading to DMA mode %d\n", 995 drv_dev->dv_xname, drvp->DMA_mode); 996 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 997 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 998 drvp->PIO_mode = drvp->PIO_cap; 999 printf("%s: transfer error, downgrading to PIO mode %d\n", 1000 drv_dev->dv_xname, drvp->PIO_mode); 1001 } else /* already using PIO, can't downgrade */ 1002 return 0; 1003 1004 wdc->set_modes(chp); 1005 /* reset the channel, which will shedule all drives for setup */ 1006 wdc_reset_channel(drvp); 1007 return 1; 1008 } 1009 1010 int 1011 wdc_exec_command(drvp, wdc_c) 1012 struct ata_drive_datas *drvp; 1013 struct wdc_command *wdc_c; 1014 { 1015 struct channel_softc *chp = drvp->chnl_softc; 1016 struct wdc_xfer *xfer; 1017 int s, ret; 1018 1019 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1020 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1021 DEBUG_FUNCS); 1022 1023 /* set up an xfer and queue. Wait for completion */ 1024 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1025 WDC_NOSLEEP); 1026 if (xfer == NULL) { 1027 return WDC_TRY_AGAIN; 1028 } 1029 1030 if (wdc_c->flags & AT_POLL) 1031 xfer->c_flags |= C_POLL; 1032 xfer->drive = drvp->drive; 1033 xfer->databuf = wdc_c->data; 1034 xfer->c_bcount = wdc_c->bcount; 1035 xfer->cmd = wdc_c; 1036 xfer->c_start = __wdccommand_start; 1037 xfer->c_intr = __wdccommand_intr; 1038 1039 s = splbio(); 1040 wdc_exec_xfer(chp, xfer); 1041 #ifdef DIAGNOSTIC 1042 if ((wdc_c->flags & AT_POLL) != 0 && 1043 (wdc_c->flags & AT_DONE) == 0) 1044 panic("wdc_exec_command: polled command not done\n"); 1045 #endif 1046 if (wdc_c->flags & AT_DONE) { 1047 ret = WDC_COMPLETE; 1048 } else { 1049 if (wdc_c->flags & AT_WAIT) { 1050 while ((wdc_c->flags & AT_DONE) == 0) { 1051 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1052 } 1053 ret = WDC_COMPLETE; 1054 } else { 1055 ret = WDC_QUEUED; 1056 } 1057 } 1058 splx(s); 1059 return ret; 1060 } 1061 1062 void 1063 __wdccommand_start(chp, xfer) 1064 struct channel_softc *chp; 1065 struct wdc_xfer *xfer; 1066 { 1067 int drive = xfer->drive; 1068 struct wdc_command *wdc_c = xfer->cmd; 1069 1070 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1071 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1072 DEBUG_FUNCS); 1073 1074 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1075 WDSD_IBM | (drive << 4)); 1076 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1077 wdc_c->timeout) != 0) { 1078 wdc_c->flags |= AT_TIMEOU; 1079 __wdccommand_done(chp, xfer); 1080 return; 1081 } 1082 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1083 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1084 if ((wdc_c->flags & AT_POLL) == 0) { 1085 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1086 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1087 return; 1088 } 1089 /* 1090 * Polled command. Wait for drive ready or drq. Done in intr(). 1091 * Wait for at last 400ns for status bit to be valid. 1092 */ 1093 delay(10); 1094 __wdccommand_intr(chp, xfer, 0); 1095 } 1096 1097 int 1098 __wdccommand_intr(chp, xfer, irq) 1099 struct channel_softc *chp; 1100 struct wdc_xfer *xfer; 1101 int irq; 1102 { 1103 struct wdc_command *wdc_c = xfer->cmd; 1104 int bcount = wdc_c->bcount; 1105 char *data = wdc_c->data; 1106 1107 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1108 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1109 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1110 (irq == 0) ? wdc_c->timeout : 0)) { 1111 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1112 return 0; /* IRQ was not for us */ 1113 wdc_c->flags |= AT_TIMEOU; 1114 __wdccommand_done(chp, xfer); 1115 return 1; 1116 } 1117 if (wdc_c->flags & AT_READ) { 1118 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1119 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1120 0, (u_int32_t*)data, bcount >> 2); 1121 data += bcount & 0xfffffffc; 1122 bcount = bcount & 0x03; 1123 } 1124 if (bcount > 0) 1125 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1126 wd_data, (u_int16_t *)data, bcount >> 1); 1127 } else if (wdc_c->flags & AT_WRITE) { 1128 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1129 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1130 0, (u_int32_t*)data, bcount >> 2); 1131 data += bcount & 0xfffffffc; 1132 bcount = bcount & 0x03; 1133 } 1134 if (bcount > 0) 1135 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1136 wd_data, (u_int16_t *)data, bcount >> 1); 1137 } 1138 __wdccommand_done(chp, xfer); 1139 return 1; 1140 } 1141 1142 void 1143 __wdccommand_done(chp, xfer) 1144 struct channel_softc *chp; 1145 struct wdc_xfer *xfer; 1146 { 1147 int needdone = xfer->c_flags & C_NEEDDONE; 1148 struct wdc_command *wdc_c = xfer->cmd; 1149 1150 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1151 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1152 1153 untimeout(wdctimeout, chp); 1154 1155 if (chp->ch_status & WDCS_DWF) 1156 wdc_c->flags |= AT_DF; 1157 if (chp->ch_status & WDCS_ERR) { 1158 wdc_c->flags |= AT_ERROR; 1159 wdc_c->r_error = chp->ch_error; 1160 } 1161 wdc_c->flags |= AT_DONE; 1162 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1163 == 0) { 1164 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1165 wd_sdh); 1166 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1167 wd_cyl_hi) << 8; 1168 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1169 wd_cyl_lo); 1170 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1171 wd_sector); 1172 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1173 wd_seccnt); 1174 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1175 wd_error); 1176 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1177 wd_precomp); 1178 } 1179 wdc_free_xfer(chp, xfer); 1180 if (needdone) { 1181 if (wdc_c->flags & AT_WAIT) 1182 wakeup(wdc_c); 1183 else 1184 wdc_c->callback(wdc_c->callback_arg); 1185 } 1186 wdcstart(chp); 1187 return; 1188 } 1189 1190 /* 1191 * Send a command. The drive should be ready. 1192 * Assumes interrupts are blocked. 1193 */ 1194 void 1195 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1196 struct channel_softc *chp; 1197 u_int8_t drive; 1198 u_int8_t command; 1199 u_int16_t cylin; 1200 u_int8_t head, sector, count, precomp; 1201 { 1202 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1203 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1204 chp->channel, drive, command, cylin, head, sector, count, precomp), 1205 DEBUG_FUNCS); 1206 1207 /* Select drive, head, and addressing mode. */ 1208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1209 WDSD_IBM | (drive << 4) | head); 1210 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1211 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1212 precomp); 1213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1214 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1215 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1216 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1217 1218 /* Send command. */ 1219 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1220 return; 1221 } 1222 1223 /* 1224 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1225 * tested by the caller. 1226 */ 1227 void 1228 wdccommandshort(chp, drive, command) 1229 struct channel_softc *chp; 1230 int drive; 1231 int command; 1232 { 1233 1234 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1235 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1236 DEBUG_FUNCS); 1237 1238 /* Select drive. */ 1239 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1240 WDSD_IBM | (drive << 4)); 1241 1242 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1243 } 1244 1245 /* Add a command to the queue and start controller. Must be called at splbio */ 1246 1247 void 1248 wdc_exec_xfer(chp, xfer) 1249 struct channel_softc *chp; 1250 struct wdc_xfer *xfer; 1251 { 1252 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1253 chp->channel, xfer->drive), DEBUG_XFERS); 1254 1255 /* complete xfer setup */ 1256 xfer->chp = chp; 1257 1258 /* 1259 * If we are a polled command, and the list is not empty, 1260 * we are doing a dump. Drop the list to allow the polled command 1261 * to complete, we're going to reboot soon anyway. 1262 */ 1263 if ((xfer->c_flags & C_POLL) != 0 && 1264 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1265 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1266 } 1267 /* insert at the end of command list */ 1268 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1269 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1270 chp->ch_flags), DEBUG_XFERS); 1271 wdcstart(chp); 1272 xfer->c_flags |= C_NEEDDONE; /* we can now call upper level done() */ 1273 } 1274 1275 struct wdc_xfer * 1276 wdc_get_xfer(flags) 1277 int flags; 1278 { 1279 struct wdc_xfer *xfer; 1280 int s; 1281 1282 s = splbio(); 1283 if ((xfer = xfer_free_list.lh_first) != NULL) { 1284 LIST_REMOVE(xfer, free_list); 1285 splx(s); 1286 #ifdef DIAGNOSTIC 1287 if ((xfer->c_flags & C_INUSE) != 0) 1288 panic("wdc_get_xfer: xfer already in use\n"); 1289 #endif 1290 } else { 1291 splx(s); 1292 WDCDEBUG_PRINT(("wdc:making xfer %d\n",wdc_nxfer), DEBUG_XFERS); 1293 xfer = malloc(sizeof(*xfer), M_DEVBUF, 1294 ((flags & WDC_NOSLEEP) != 0 ? M_NOWAIT : M_WAITOK)); 1295 if (xfer == NULL) 1296 return 0; 1297 #ifdef DIAGNOSTIC 1298 xfer->c_flags &= ~C_INUSE; 1299 #endif 1300 #ifdef WDCDEBUG 1301 wdc_nxfer++; 1302 #endif 1303 } 1304 #ifdef DIAGNOSTIC 1305 if ((xfer->c_flags & C_INUSE) != 0) 1306 panic("wdc_get_xfer: xfer already in use\n"); 1307 #endif 1308 memset(xfer, 0, sizeof(struct wdc_xfer)); 1309 xfer->c_flags = C_INUSE; 1310 return xfer; 1311 } 1312 1313 void 1314 wdc_free_xfer(chp, xfer) 1315 struct channel_softc *chp; 1316 struct wdc_xfer *xfer; 1317 { 1318 struct wdc_softc *wdc = chp->wdc; 1319 int s; 1320 1321 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1322 (*wdc->free_hw)(chp); 1323 s = splbio(); 1324 chp->ch_flags &= ~WDCF_ACTIVE; 1325 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1326 xfer->c_flags &= ~C_INUSE; 1327 LIST_INSERT_HEAD(&xfer_free_list, xfer, free_list); 1328 splx(s); 1329 } 1330 1331 static void 1332 __wdcerror(chp, msg) 1333 struct channel_softc *chp; 1334 char *msg; 1335 { 1336 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1337 if (xfer == NULL) 1338 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1339 msg); 1340 else 1341 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1342 chp->channel, xfer->drive, msg); 1343 } 1344 1345 /* 1346 * the bit bucket 1347 */ 1348 void 1349 wdcbit_bucket(chp, size) 1350 struct channel_softc *chp; 1351 int size; 1352 { 1353 1354 for (; size >= 2; size -= 2) 1355 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1356 if (size) 1357 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1358 } 1359 1360 int 1361 wdc_addref(chp) 1362 struct channel_softc *chp; 1363 { 1364 struct wdc_softc *wdc = chp->wdc; 1365 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1366 int s, error = 0; 1367 1368 s = splbio(); 1369 if (adapter->scsipi_refcnt++ == 0 && 1370 adapter->scsipi_enable != NULL) { 1371 error = (*adapter->scsipi_enable)(wdc, 1); 1372 if (error) 1373 adapter->scsipi_refcnt--; 1374 } 1375 splx(s); 1376 return (error); 1377 } 1378 1379 void 1380 wdc_delref(chp) 1381 struct channel_softc *chp; 1382 { 1383 struct wdc_softc *wdc = chp->wdc; 1384 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1385 int s; 1386 1387 s = splbio(); 1388 if (adapter->scsipi_refcnt-- == 1 && 1389 adapter->scsipi_enable != NULL) 1390 (void) (*adapter->scsipi_enable)(wdc, 0); 1391 splx(s); 1392 } 1393
Indexes created Tue Sep 23 07:09:52 GMT 2025