wdc.c revision 1.72
1 /* $NetBSD: wdc.c,v 1.72 1999/08/25 17:08:20 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 124 125 #define DEBUG_INTR 0x01 126 #define DEBUG_XFERS 0x02 127 #define DEBUG_STATUS 0x04 128 #define DEBUG_FUNCS 0x08 129 #define DEBUG_PROBE 0x10 130 #ifdef WDCDEBUG 131 int wdcdebug_mask = 0; 132 int wdc_nxfer = 0; 133 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 134 #else 135 #define WDCDEBUG_PRINT(args, level) 136 #endif 137 138 int 139 wdprint(aux, pnp) 140 void *aux; 141 const char *pnp; 142 { 143 struct ata_atapi_attach *aa_link = aux; 144 if (pnp) 145 printf("drive at %s", pnp); 146 printf(" channel %d drive %d", aa_link->aa_channel, 147 aa_link->aa_drv_data->drive); 148 return (UNCONF); 149 } 150 151 int 152 atapi_print(aux, pnp) 153 void *aux; 154 const char *pnp; 155 { 156 struct ata_atapi_attach *aa_link = aux; 157 if (pnp) 158 printf("atapibus at %s", pnp); 159 printf(" channel %d", aa_link->aa_channel); 160 return (UNCONF); 161 } 162 163 /* Test to see controller with at last one attached drive is there. 164 * Returns a bit for each possible drive found (0x01 for drive 0, 165 * 0x02 for drive 1). 166 * Logic: 167 * - If a status register is at 0xff, assume there is no drive here 168 * (ISA has pull-up resistors). If no drive at all -> return. 169 * - reset the controller, wait for it to complete (may take up to 31s !). 170 * If timeout -> return. 171 * - test ATA/ATAPI signatures. If at last one drive found -> return. 172 * - try an ATA command on the master. 173 */ 174 175 int 176 wdcprobe(chp) 177 struct channel_softc *chp; 178 { 179 u_int8_t st0, st1, sc, sn, cl, ch; 180 u_int8_t ret_value = 0x03; 181 u_int8_t drive; 182 183 /* 184 * Sanity check to see if the wdc channel responds at all. 185 */ 186 187 if (chp->wdc == NULL || 188 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 189 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 190 WDSD_IBM); 191 delay(10); 192 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 193 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 194 WDSD_IBM | 0x10); 195 delay(10); 196 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 197 198 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 199 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 200 chp->channel, st0, st1), DEBUG_PROBE); 201 202 if (st0 == 0xff) 203 ret_value &= ~0x01; 204 if (st1 == 0xff) 205 ret_value &= ~0x02; 206 if (ret_value == 0) 207 return 0; 208 } 209 210 /* assert SRST, wait for reset to complete */ 211 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 212 WDSD_IBM); 213 delay(10); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_RST | WDCTL_IDS); 216 DELAY(1000); 217 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 218 WDCTL_IDS); 219 delay(1000); 220 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 221 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 222 delay(10); 223 224 ret_value = __wdcwait_reset(chp, ret_value); 225 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 226 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 227 ret_value), DEBUG_PROBE); 228 229 /* if reset failed, there's nothing here */ 230 if (ret_value == 0) 231 return 0; 232 233 /* 234 * Test presence of drives. First test register signatures looking for 235 * ATAPI devices. If it's not an ATAPI and reset said there may be 236 * something here assume it's ATA or OLD. Ghost will be killed later in 237 * attach routine. 238 */ 239 for (drive = 0; drive < 2; drive++) { 240 if ((ret_value & (0x01 << drive)) == 0) 241 continue; 242 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 243 WDSD_IBM | (drive << 4)); 244 delay(10); 245 /* Save registers contents */ 246 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 247 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 248 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 249 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 250 251 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 252 "cl=0x%x ch=0x%x\n", 253 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 254 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 255 /* 256 * sc is supposted to be 0x1 for ATAPI but at last one drive 257 * set it to 0x0 - or maybe it's the controller. 258 */ 259 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 260 cl == 0x14 && ch == 0xeb) { 261 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 262 } else { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 264 if (chp->wdc == NULL || 265 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 266 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 267 } 268 } 269 return (ret_value); 270 } 271 272 void 273 wdcattach(chp) 274 struct channel_softc *chp; 275 { 276 int channel_flags, ctrl_flags, i, error; 277 struct ata_atapi_attach aa_link; 278 struct ataparams params; 279 static int inited = 0; 280 281 if ((error = wdc_addref(chp)) != 0) { 282 printf("%s: unable to enable controller\n", 283 chp->wdc->sc_dev.dv_xname); 284 return; 285 } 286 287 if (wdcprobe(chp) == 0) { 288 /* If no drives, abort attach here. */ 289 wdc_delref(chp); 290 return; 291 } 292 293 /* initialise global data */ 294 if (inited == 0) { 295 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* If controller can't do 16bit flag the drives as 32bit */ 307 if ((chp->wdc->cap & 308 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 309 WDC_CAPABILITY_DATA32) 310 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 311 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 312 continue; 313 314 /* Issue a IDENTIFY command, to try to detect slave ghost */ 315 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) == 316 CMD_OK) { 317 /* If IDENTIFY succeded, this is not an OLD ctrl */ 318 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 319 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 320 } else { 321 chp->ch_drive[i].drive_flags &= 322 ~(DRIVE_ATA | DRIVE_ATAPI); 323 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 324 chp->wdc->sc_dev.dv_xname, 325 chp->channel, i), DEBUG_PROBE); 326 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 327 continue; 328 /* 329 * Pre-ATA drive ? 330 * Test registers writability (Error register not 331 * writable, but cyllo is), then try an ATA command. 332 */ 333 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 334 WDSD_IBM | (i << 4)); 335 delay(10); 336 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 337 wd_error, 0x58); 338 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 339 wd_cyl_lo, 0xa5); 340 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 341 wd_error == 0x58) || 342 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 343 wd_cyl_lo) != 0xa5) { 344 WDCDEBUG_PRINT(("%s:%d:%d: register " 345 "writability failed\n", 346 chp->wdc->sc_dev.dv_xname, 347 chp->channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 } 350 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 351 WDSD_IBM | (i << 4)); 352 delay(100); 353 if (wait_for_ready(chp, 10000) != 0) { 354 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 355 chp->wdc->sc_dev.dv_xname, 356 chp->channel, i), DEBUG_PROBE); 357 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 358 continue; 359 } 360 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 361 wd_command, WDCC_RECAL); 362 if (wait_for_ready(chp, 10000) != 0) { 363 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 364 chp->wdc->sc_dev.dv_xname, 365 chp->channel, i), DEBUG_PROBE); 366 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 367 } 368 } 369 } 370 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 371 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 372 373 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 374 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 375 DEBUG_PROBE); 376 377 /* If no drives, abort here */ 378 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 379 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 380 return; 381 382 /* 383 * Attach an ATAPI bus, if needed. 384 */ 385 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 386 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 387 #if NATAPIBUS > 0 388 wdc_atapibus_attach(chp); 389 #else 390 /* 391 * Fills in a fake aa_link and call config_found, so that 392 * the config machinery will print 393 * "atapibus at xxx not configured" 394 */ 395 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 396 aa_link.aa_type = T_ATAPI; 397 aa_link.aa_channel = chp->channel; 398 aa_link.aa_openings = 1; 399 aa_link.aa_drv_data = 0; 400 aa_link.aa_bus_private = NULL; 401 (void)config_found(&chp->wdc->sc_dev, (void *)&aa_link, 402 atapi_print); 403 #endif 404 } 405 406 for (i = 0; i < 2; i++) { 407 if ((chp->ch_drive[i].drive_flags & 408 (DRIVE_ATA | DRIVE_OLD)) == 0) { 409 continue; 410 } 411 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 412 aa_link.aa_type = T_ATA; 413 aa_link.aa_channel = chp->channel; 414 aa_link.aa_openings = 1; 415 aa_link.aa_drv_data = &chp->ch_drive[i]; 416 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 417 wdc_probe_caps(&chp->ch_drive[i]); 418 } 419 420 /* 421 * reset drive_flags for unnatached devices, reset state for attached 422 * ones 423 */ 424 for (i = 0; i < 2; i++) { 425 if (chp->ch_drive[i].drv_softc == NULL) 426 chp->ch_drive[i].drive_flags = 0; 427 else 428 chp->ch_drive[i].state = 0; 429 } 430 431 /* 432 * Reset channel. The probe, with some combinations of ATA/ATAPI 433 * devices keep it in a mostly working, but strange state (with busy 434 * led on) 435 */ 436 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 437 wdcreset(chp, VERBOSE); 438 /* 439 * Read status registers to avoid spurious interrupts. 440 */ 441 for (i = 1; i >= 0; i--) { 442 if (chp->ch_drive[i].drive_flags & DRIVE) { 443 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 444 wd_sdh, WDSD_IBM | (i << 4)); 445 if (wait_for_unbusy(chp, 10000) < 0) 446 printf("%s:%d:%d: device busy\n", 447 chp->wdc->sc_dev.dv_xname, 448 chp->channel, i); 449 } 450 } 451 } 452 wdc_delref(chp); 453 } 454 455 /* 456 * Start I/O on a controller, for the given channel. 457 * The first xfer may be not for our channel if the channel queues 458 * are shared. 459 */ 460 void 461 wdcstart(chp) 462 struct channel_softc *chp; 463 { 464 struct wdc_xfer *xfer; 465 466 #ifdef WDC_DIAGNOSTIC 467 int spl1, spl2; 468 469 spl1 = splbio(); 470 spl2 = splbio(); 471 if (spl2 != spl1) { 472 printf("wdcstart: not at splbio()\n"); 473 panic("wdcstart"); 474 } 475 splx(spl2); 476 splx(spl1); 477 #endif /* WDC_DIAGNOSTIC */ 478 479 /* is there a xfer ? */ 480 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 481 return; 482 483 /* adjust chp, in case we have a shared queue */ 484 chp = xfer->chp; 485 486 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 487 return; /* channel aleady active */ 488 } 489 #ifdef DIAGNOSTIC 490 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 491 panic("wdcstart: channel waiting for irq\n"); 492 #endif 493 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 494 if (!(*chp->wdc->claim_hw)(chp, 0)) 495 return; 496 497 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 498 chp->channel, xfer->drive), DEBUG_XFERS); 499 chp->ch_flags |= WDCF_ACTIVE; 500 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 501 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 502 chp->ch_drive[xfer->drive].state = 0; 503 } 504 xfer->c_start(chp, xfer); 505 } 506 507 /* restart an interrupted I/O */ 508 void 509 wdcrestart(v) 510 void *v; 511 { 512 struct channel_softc *chp = v; 513 int s; 514 515 s = splbio(); 516 wdcstart(chp); 517 splx(s); 518 } 519 520 521 /* 522 * Interrupt routine for the controller. Acknowledge the interrupt, check for 523 * errors on the current operation, mark it done if necessary, and start the 524 * next request. Also check for a partially done transfer, and continue with 525 * the next chunk if so. 526 */ 527 int 528 wdcintr(arg) 529 void *arg; 530 { 531 struct channel_softc *chp = arg; 532 struct wdc_xfer *xfer; 533 534 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 535 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 536 return 0; 537 } 538 539 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 540 chp->ch_flags &= ~WDCF_IRQ_WAIT; 541 xfer = chp->ch_queue->sc_xfer.tqh_first; 542 return xfer->c_intr(chp, xfer, 1); 543 } 544 545 /* Put all disk in RESET state */ 546 void wdc_reset_channel(drvp) 547 struct ata_drive_datas *drvp; 548 { 549 struct channel_softc *chp = drvp->chnl_softc; 550 int drive; 551 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 552 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 553 DEBUG_FUNCS); 554 (void) wdcreset(chp, VERBOSE); 555 for (drive = 0; drive < 2; drive++) { 556 chp->ch_drive[drive].state = 0; 557 } 558 } 559 560 int 561 wdcreset(chp, verb) 562 struct channel_softc *chp; 563 int verb; 564 { 565 int drv_mask1, drv_mask2; 566 567 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 568 WDSD_IBM); /* master */ 569 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 570 WDCTL_RST | WDCTL_IDS); 571 delay(1000); 572 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 573 WDCTL_IDS); 574 delay(1000); 575 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 576 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 577 WDCTL_4BIT); 578 579 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 580 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 581 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 582 if (verb && drv_mask2 != drv_mask1) { 583 printf("%s channel %d: reset failed for", 584 chp->wdc->sc_dev.dv_xname, chp->channel); 585 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 586 printf(" drive 0"); 587 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 588 printf(" drive 1"); 589 printf("\n"); 590 } 591 return (drv_mask1 != drv_mask2) ? 1 : 0; 592 } 593 594 static int 595 __wdcwait_reset(chp, drv_mask) 596 struct channel_softc *chp; 597 int drv_mask; 598 { 599 int timeout; 600 u_int8_t st0, st1; 601 #ifdef WDCDEBUG 602 u_int8_t sc0, sn0, cl0, ch0; 603 u_int8_t sc1, sn1, cl1, ch1; 604 #endif 605 /* wait for BSY to deassert */ 606 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 607 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 608 WDSD_IBM); /* master */ 609 delay(10); 610 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 611 #ifdef WDCDEBUG 612 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 613 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 614 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 615 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 616 #endif 617 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 618 WDSD_IBM | 0x10); /* slave */ 619 delay(10); 620 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 621 #ifdef WDCDEBUG 622 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 623 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 624 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 625 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 626 #endif 627 628 if ((drv_mask & 0x01) == 0) { 629 /* no master */ 630 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 631 /* No master, slave is ready, it's done */ 632 goto end; 633 } 634 } else if ((drv_mask & 0x02) == 0) { 635 /* no slave */ 636 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 637 /* No slave, master is ready, it's done */ 638 goto end; 639 } 640 } else { 641 /* Wait for both master and slave to be ready */ 642 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 643 goto end; 644 } 645 } 646 delay(WDCDELAY); 647 } 648 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 649 if (st0 & WDCS_BSY) 650 drv_mask &= ~0x01; 651 if (st1 & WDCS_BSY) 652 drv_mask &= ~0x02; 653 end: 654 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 655 "cl=0x%x ch=0x%x\n", 656 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 657 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 658 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 659 "cl=0x%x ch=0x%x\n", 660 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 661 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 662 663 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 664 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 665 st0, st1), DEBUG_PROBE); 666 667 return drv_mask; 668 } 669 670 /* 671 * Wait for a drive to be !BSY, and have mask in its status register. 672 * return -1 for a timeout after "timeout" ms. 673 */ 674 int 675 wdcwait(chp, mask, bits, timeout) 676 struct channel_softc *chp; 677 int mask, bits, timeout; 678 { 679 u_char status; 680 int time = 0; 681 #ifdef WDCNDELAY_DEBUG 682 extern int cold; 683 #endif 684 685 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 686 :"none", chp->channel), DEBUG_STATUS); 687 chp->ch_error = 0; 688 689 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 690 691 for (;;) { 692 chp->ch_status = status = 693 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 694 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 695 break; 696 if (++time > timeout) { 697 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 698 "error %x\n", status, 699 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 700 wd_error)), 701 DEBUG_STATUS); 702 return -1; 703 } 704 delay(WDCDELAY); 705 } 706 if (status & WDCS_ERR) 707 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 708 wd_error); 709 #ifdef WDCNDELAY_DEBUG 710 /* After autoconfig, there should be no long delays. */ 711 if (!cold && time > WDCNDELAY_DEBUG) { 712 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 713 if (xfer == NULL) 714 printf("%s channel %d: warning: busy-wait took %dus\n", 715 chp->wdc->sc_dev.dv_xname, chp->channel, 716 WDCDELAY * time); 717 else 718 printf("%s:%d:%d: warning: busy-wait took %dus\n", 719 chp->wdc->sc_dev.dv_xname, chp->channel, 720 xfer->drive, 721 WDCDELAY * time); 722 } 723 #endif 724 return 0; 725 } 726 727 void 728 wdctimeout(arg) 729 void *arg; 730 { 731 struct channel_softc *chp = (struct channel_softc *)arg; 732 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 733 int s; 734 735 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 736 737 s = splbio(); 738 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 739 __wdcerror(chp, "lost interrupt"); 740 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 741 "atapi":"ata"); 742 printf("\tc_bcount: %d\n", xfer->c_bcount); 743 printf("\tc_skip: %d\n", xfer->c_skip); 744 /* 745 * Call the interrupt routine. If we just missed and interrupt, 746 * it will do what's needed. Else, it will take the needed 747 * action (reset the device). 748 * Before that we need to reinstall the timeout callback, 749 * in case it will miss another irq while in this transfer 750 * We arbitray chose it to be 1s 751 */ 752 timeout(wdctimeout, chp, hz); 753 xfer->c_flags |= C_TIMEOU; 754 chp->ch_flags &= ~WDCF_IRQ_WAIT; 755 xfer->c_intr(chp, xfer, 1); 756 } else 757 __wdcerror(chp, "missing untimeout"); 758 splx(s); 759 } 760 761 /* 762 * Probe drive's capabilites, for use by the controller later 763 * Assumes drvp points to an existing drive. 764 * XXX this should be a controller-indep function 765 */ 766 void 767 wdc_probe_caps(drvp) 768 struct ata_drive_datas *drvp; 769 { 770 struct ataparams params, params2; 771 struct channel_softc *chp = drvp->chnl_softc; 772 struct device *drv_dev = drvp->drv_softc; 773 struct wdc_softc *wdc = chp->wdc; 774 int i, printed; 775 char *sep = ""; 776 int cf_flags; 777 778 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 779 /* IDENTIFY failed. Can't tell more about the device */ 780 return; 781 } 782 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 783 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 784 /* 785 * Controller claims 16 and 32 bit transfers. 786 * Re-do an IDENTIFY with 32-bit transfers, 787 * and compare results. 788 */ 789 drvp->drive_flags |= DRIVE_CAP32; 790 ata_get_params(drvp, AT_POLL, ¶ms2); 791 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 792 /* Not good. fall back to 16bits */ 793 drvp->drive_flags &= ~DRIVE_CAP32; 794 } else { 795 printf("%s: 32-bits data port", drv_dev->dv_xname); 796 } 797 } 798 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 799 if (params.atap_ata_major > 0x01 && 800 params.atap_ata_major != 0xffff) { 801 for (i = 14; i > 0; i--) { 802 if (params.atap_ata_major & (1 << i)) { 803 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 804 printf("%s: ", drv_dev->dv_xname); 805 else 806 printf(", "); 807 printf("ATA version %d\n", i); 808 drvp->ata_vers = i; 809 break; 810 } 811 } 812 } else 813 #endif 814 if (drvp->drive_flags & DRIVE_CAP32) 815 printf("\n"); 816 817 /* An ATAPI device is at last PIO mode 3 */ 818 if (drvp->drive_flags & DRIVE_ATAPI) 819 drvp->PIO_mode = 3; 820 821 /* 822 * It's not in the specs, but it seems that some drive 823 * returns 0xffff in atap_extensions when this field is invalid 824 */ 825 if (params.atap_extensions != 0xffff && 826 (params.atap_extensions & WDC_EXT_MODES)) { 827 printed = 0; 828 /* 829 * XXX some drives report something wrong here (they claim to 830 * support PIO mode 8 !). As mode is coded on 3 bits in 831 * SET FEATURE, limit it to 7 (so limit i to 4). 832 * If higther mode than 7 is found, abort. 833 */ 834 for (i = 7; i >= 0; i--) { 835 if ((params.atap_piomode_supp & (1 << i)) == 0) 836 continue; 837 if (i > 4) 838 return; 839 /* 840 * See if mode is accepted. 841 * If the controller can't set its PIO mode, 842 * assume the defaults are good, so don't try 843 * to set it 844 */ 845 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 846 if (ata_set_mode(drvp, 0x08 | (i + 3), 847 AT_POLL) != CMD_OK) 848 continue; 849 if (!printed) { 850 printf("%s: drive supports PIO mode %d", 851 drv_dev->dv_xname, i + 3); 852 sep = ","; 853 printed = 1; 854 } 855 /* 856 * If controller's driver can't set its PIO mode, 857 * get the highter one for the drive. 858 */ 859 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 860 wdc->PIO_cap >= i + 3) { 861 drvp->PIO_mode = i + 3; 862 drvp->PIO_cap = i + 3; 863 break; 864 } 865 } 866 if (!printed) { 867 /* 868 * We didn't find a valid PIO mode. 869 * Assume the values returned for DMA are buggy too 870 */ 871 return; 872 } 873 drvp->drive_flags |= DRIVE_MODE; 874 printed = 0; 875 for (i = 7; i >= 0; i--) { 876 if ((params.atap_dmamode_supp & (1 << i)) == 0) 877 continue; 878 if ((wdc->cap & WDC_CAPABILITY_DMA) && 879 (wdc->cap & WDC_CAPABILITY_MODE)) 880 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 881 != CMD_OK) 882 continue; 883 if (!printed) { 884 printf("%s DMA mode %d", sep, i); 885 sep = ","; 886 printed = 1; 887 } 888 if (wdc->cap & WDC_CAPABILITY_DMA) { 889 if ((wdc->cap & WDC_CAPABILITY_MODE) && 890 wdc->DMA_cap < i) 891 continue; 892 drvp->DMA_mode = i; 893 drvp->DMA_cap = i; 894 drvp->drive_flags |= DRIVE_DMA; 895 } 896 break; 897 } 898 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 899 printed = 0; 900 for (i = 7; i >= 0; i--) { 901 if ((params.atap_udmamode_supp & (1 << i)) 902 == 0) 903 continue; 904 if ((wdc->cap & WDC_CAPABILITY_MODE) && 905 (wdc->cap & WDC_CAPABILITY_UDMA)) 906 if (ata_set_mode(drvp, 0x40 | i, 907 AT_POLL) != CMD_OK) 908 continue; 909 if (!printed) { 910 printf("%s Ultra-DMA mode %d", sep, i); 911 sep = ","; 912 printed = 1; 913 } 914 if (wdc->cap & WDC_CAPABILITY_UDMA) { 915 if ((wdc->cap & WDC_CAPABILITY_MODE) && 916 wdc->UDMA_cap < i) 917 continue; 918 drvp->UDMA_mode = i; 919 drvp->UDMA_cap = i; 920 drvp->drive_flags |= DRIVE_UDMA; 921 } 922 break; 923 } 924 } 925 printf("\n"); 926 } 927 928 /* Try to guess ATA version here, if it didn't get reported */ 929 if (drvp->ata_vers == 0) { 930 if (drvp->drive_flags & DRIVE_UDMA) 931 drvp->ata_vers = 4; /* should be at last ATA-4 */ 932 else if (drvp->PIO_cap > 2) 933 drvp->ata_vers = 2; /* should be at last ATA-2 */ 934 } 935 cf_flags = drv_dev->dv_cfdata->cf_flags; 936 if (cf_flags & ATA_CONFIG_PIO_SET) { 937 drvp->PIO_mode = 938 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 939 drvp->drive_flags |= DRIVE_MODE; 940 } 941 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 942 /* don't care about DMA modes */ 943 return; 944 } 945 if (cf_flags & ATA_CONFIG_DMA_SET) { 946 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 947 ATA_CONFIG_DMA_DISABLE) { 948 drvp->drive_flags &= ~DRIVE_DMA; 949 } else { 950 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 951 ATA_CONFIG_DMA_OFF; 952 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 953 } 954 } 955 if (cf_flags & ATA_CONFIG_UDMA_SET) { 956 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 957 ATA_CONFIG_UDMA_DISABLE) { 958 drvp->drive_flags &= ~DRIVE_UDMA; 959 } else { 960 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 961 ATA_CONFIG_UDMA_OFF; 962 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 963 } 964 } 965 } 966 967 /* 968 * downgrade the transfer mode of a drive after an error. return 1 if 969 * downgrade was possible, 0 otherwise. 970 */ 971 int 972 wdc_downgrade_mode(drvp) 973 struct ata_drive_datas *drvp; 974 { 975 struct channel_softc *chp = drvp->chnl_softc; 976 struct device *drv_dev = drvp->drv_softc; 977 struct wdc_softc *wdc = chp->wdc; 978 int cf_flags = drv_dev->dv_cfdata->cf_flags; 979 980 /* if drive or controller don't know its mode, we can't do much */ 981 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 982 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 983 return 0; 984 /* current drive mode was set by a config flag, let it this way */ 985 if ((cf_flags & ATA_CONFIG_PIO_SET) || 986 (cf_flags & ATA_CONFIG_DMA_SET) || 987 (cf_flags & ATA_CONFIG_UDMA_SET)) 988 return 0; 989 990 /* 991 * If we were using ultra-DMA, don't downgrade to multiword DMA 992 * if we noticed a CRC error. It has been noticed that CRC errors 993 * in ultra-DMA lead to silent data corruption in multiword DMA. 994 * Data corruption is less likely to occur in PIO mode. 995 */ 996 997 if ((drvp->drive_flags & DRIVE_UDMA) && 998 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 999 drvp->drive_flags &= ~DRIVE_UDMA; 1000 drvp->drive_flags |= DRIVE_DMA; 1001 drvp->DMA_mode = drvp->DMA_cap; 1002 printf("%s: transfer error, downgrading to DMA mode %d\n", 1003 drv_dev->dv_xname, drvp->DMA_mode); 1004 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1005 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1006 drvp->PIO_mode = drvp->PIO_cap; 1007 printf("%s: transfer error, downgrading to PIO mode %d\n", 1008 drv_dev->dv_xname, drvp->PIO_mode); 1009 } else /* already using PIO, can't downgrade */ 1010 return 0; 1011 1012 wdc->set_modes(chp); 1013 /* reset the channel, which will shedule all drives for setup */ 1014 wdc_reset_channel(drvp); 1015 return 1; 1016 } 1017 1018 int 1019 wdc_exec_command(drvp, wdc_c) 1020 struct ata_drive_datas *drvp; 1021 struct wdc_command *wdc_c; 1022 { 1023 struct channel_softc *chp = drvp->chnl_softc; 1024 struct wdc_xfer *xfer; 1025 int s, ret; 1026 1027 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1028 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1029 DEBUG_FUNCS); 1030 1031 /* set up an xfer and queue. Wait for completion */ 1032 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1033 WDC_NOSLEEP); 1034 if (xfer == NULL) { 1035 return WDC_TRY_AGAIN; 1036 } 1037 1038 if (wdc_c->flags & AT_POLL) 1039 xfer->c_flags |= C_POLL; 1040 xfer->drive = drvp->drive; 1041 xfer->databuf = wdc_c->data; 1042 xfer->c_bcount = wdc_c->bcount; 1043 xfer->cmd = wdc_c; 1044 xfer->c_start = __wdccommand_start; 1045 xfer->c_intr = __wdccommand_intr; 1046 1047 s = splbio(); 1048 wdc_exec_xfer(chp, xfer); 1049 #ifdef DIAGNOSTIC 1050 if ((wdc_c->flags & AT_POLL) != 0 && 1051 (wdc_c->flags & AT_DONE) == 0) 1052 panic("wdc_exec_command: polled command not done\n"); 1053 #endif 1054 if (wdc_c->flags & AT_DONE) { 1055 ret = WDC_COMPLETE; 1056 } else { 1057 if (wdc_c->flags & AT_WAIT) { 1058 while ((wdc_c->flags & AT_DONE) == 0) { 1059 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1060 } 1061 ret = WDC_COMPLETE; 1062 } else { 1063 ret = WDC_QUEUED; 1064 } 1065 } 1066 splx(s); 1067 return ret; 1068 } 1069 1070 void 1071 __wdccommand_start(chp, xfer) 1072 struct channel_softc *chp; 1073 struct wdc_xfer *xfer; 1074 { 1075 int drive = xfer->drive; 1076 struct wdc_command *wdc_c = xfer->cmd; 1077 1078 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1079 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1080 DEBUG_FUNCS); 1081 1082 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1083 WDSD_IBM | (drive << 4)); 1084 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1085 wdc_c->timeout) != 0) { 1086 wdc_c->flags |= AT_TIMEOU; 1087 __wdccommand_done(chp, xfer); 1088 return; 1089 } 1090 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1091 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1092 if ((wdc_c->flags & AT_POLL) == 0) { 1093 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1094 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1095 return; 1096 } 1097 /* 1098 * Polled command. Wait for drive ready or drq. Done in intr(). 1099 * Wait for at last 400ns for status bit to be valid. 1100 */ 1101 delay(10); 1102 __wdccommand_intr(chp, xfer, 0); 1103 } 1104 1105 int 1106 __wdccommand_intr(chp, xfer, irq) 1107 struct channel_softc *chp; 1108 struct wdc_xfer *xfer; 1109 int irq; 1110 { 1111 struct wdc_command *wdc_c = xfer->cmd; 1112 int bcount = wdc_c->bcount; 1113 char *data = wdc_c->data; 1114 1115 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1116 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1117 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1118 (irq == 0) ? wdc_c->timeout : 0)) { 1119 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1120 return 0; /* IRQ was not for us */ 1121 wdc_c->flags |= AT_TIMEOU; 1122 __wdccommand_done(chp, xfer); 1123 return 1; 1124 } 1125 if (wdc_c->flags & AT_READ) { 1126 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1127 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1128 0, (u_int32_t*)data, bcount >> 2); 1129 data += bcount & 0xfffffffc; 1130 bcount = bcount & 0x03; 1131 } 1132 if (bcount > 0) 1133 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1134 wd_data, (u_int16_t *)data, bcount >> 1); 1135 } else if (wdc_c->flags & AT_WRITE) { 1136 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1137 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1138 0, (u_int32_t*)data, bcount >> 2); 1139 data += bcount & 0xfffffffc; 1140 bcount = bcount & 0x03; 1141 } 1142 if (bcount > 0) 1143 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1144 wd_data, (u_int16_t *)data, bcount >> 1); 1145 } 1146 __wdccommand_done(chp, xfer); 1147 return 1; 1148 } 1149 1150 void 1151 __wdccommand_done(chp, xfer) 1152 struct channel_softc *chp; 1153 struct wdc_xfer *xfer; 1154 { 1155 struct wdc_command *wdc_c = xfer->cmd; 1156 1157 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1158 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1159 1160 untimeout(wdctimeout, chp); 1161 1162 if (chp->ch_status & WDCS_DWF) 1163 wdc_c->flags |= AT_DF; 1164 if (chp->ch_status & WDCS_ERR) { 1165 wdc_c->flags |= AT_ERROR; 1166 wdc_c->r_error = chp->ch_error; 1167 } 1168 wdc_c->flags |= AT_DONE; 1169 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1170 == 0) { 1171 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1172 wd_sdh); 1173 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1174 wd_cyl_hi) << 8; 1175 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1176 wd_cyl_lo); 1177 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1178 wd_sector); 1179 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1180 wd_seccnt); 1181 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1182 wd_error); 1183 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1184 wd_precomp); 1185 } 1186 wdc_free_xfer(chp, xfer); 1187 if (wdc_c->flags & AT_WAIT) 1188 wakeup(wdc_c); 1189 else if (wdc_c->callback) 1190 wdc_c->callback(wdc_c->callback_arg); 1191 wdcstart(chp); 1192 return; 1193 } 1194 1195 /* 1196 * Send a command. The drive should be ready. 1197 * Assumes interrupts are blocked. 1198 */ 1199 void 1200 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1201 struct channel_softc *chp; 1202 u_int8_t drive; 1203 u_int8_t command; 1204 u_int16_t cylin; 1205 u_int8_t head, sector, count, precomp; 1206 { 1207 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1208 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1209 chp->channel, drive, command, cylin, head, sector, count, precomp), 1210 DEBUG_FUNCS); 1211 1212 /* Select drive, head, and addressing mode. */ 1213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1214 WDSD_IBM | (drive << 4) | head); 1215 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1216 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1217 precomp); 1218 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1219 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1220 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1221 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1222 1223 /* Send command. */ 1224 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1225 return; 1226 } 1227 1228 /* 1229 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1230 * tested by the caller. 1231 */ 1232 void 1233 wdccommandshort(chp, drive, command) 1234 struct channel_softc *chp; 1235 int drive; 1236 int command; 1237 { 1238 1239 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1240 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1241 DEBUG_FUNCS); 1242 1243 /* Select drive. */ 1244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1245 WDSD_IBM | (drive << 4)); 1246 1247 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1248 } 1249 1250 /* Add a command to the queue and start controller. Must be called at splbio */ 1251 1252 void 1253 wdc_exec_xfer(chp, xfer) 1254 struct channel_softc *chp; 1255 struct wdc_xfer *xfer; 1256 { 1257 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1258 chp->channel, xfer->drive), DEBUG_XFERS); 1259 1260 /* complete xfer setup */ 1261 xfer->chp = chp; 1262 1263 /* 1264 * If we are a polled command, and the list is not empty, 1265 * we are doing a dump. Drop the list to allow the polled command 1266 * to complete, we're going to reboot soon anyway. 1267 */ 1268 if ((xfer->c_flags & C_POLL) != 0 && 1269 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1270 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1271 } 1272 /* insert at the end of command list */ 1273 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1274 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1275 chp->ch_flags), DEBUG_XFERS); 1276 wdcstart(chp); 1277 } 1278 1279 struct wdc_xfer * 1280 wdc_get_xfer(flags) 1281 int flags; 1282 { 1283 struct wdc_xfer *xfer; 1284 int s; 1285 1286 s = splbio(); 1287 xfer = pool_get(&wdc_xfer_pool, 1288 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1289 splx(s); 1290 memset(xfer, 0, sizeof(struct wdc_xfer)); 1291 return xfer; 1292 } 1293 1294 void 1295 wdc_free_xfer(chp, xfer) 1296 struct channel_softc *chp; 1297 struct wdc_xfer *xfer; 1298 { 1299 struct wdc_softc *wdc = chp->wdc; 1300 int s; 1301 1302 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1303 (*wdc->free_hw)(chp); 1304 s = splbio(); 1305 chp->ch_flags &= ~WDCF_ACTIVE; 1306 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1307 pool_put(&wdc_xfer_pool, xfer); 1308 splx(s); 1309 } 1310 1311 static void 1312 __wdcerror(chp, msg) 1313 struct channel_softc *chp; 1314 char *msg; 1315 { 1316 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1317 if (xfer == NULL) 1318 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1319 msg); 1320 else 1321 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1322 chp->channel, xfer->drive, msg); 1323 } 1324 1325 /* 1326 * the bit bucket 1327 */ 1328 void 1329 wdcbit_bucket(chp, size) 1330 struct channel_softc *chp; 1331 int size; 1332 { 1333 1334 for (; size >= 2; size -= 2) 1335 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1336 if (size) 1337 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1338 } 1339 1340 int 1341 wdc_addref(chp) 1342 struct channel_softc *chp; 1343 { 1344 struct wdc_softc *wdc = chp->wdc; 1345 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1346 int s, error = 0; 1347 1348 s = splbio(); 1349 if (adapter->scsipi_refcnt++ == 0 && 1350 adapter->scsipi_enable != NULL) { 1351 error = (*adapter->scsipi_enable)(wdc, 1); 1352 if (error) 1353 adapter->scsipi_refcnt--; 1354 } 1355 splx(s); 1356 return (error); 1357 } 1358 1359 void 1360 wdc_delref(chp) 1361 struct channel_softc *chp; 1362 { 1363 struct wdc_softc *wdc = chp->wdc; 1364 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1365 int s; 1366 1367 s = splbio(); 1368 if (adapter->scsipi_refcnt-- == 1 && 1369 adapter->scsipi_enable != NULL) 1370 (void) (*adapter->scsipi_enable)(wdc, 0); 1371 splx(s); 1372 } 1373
Indexes created Tue Sep 23 14:10:03 GMT 2025