wdc.c revision 1.74
1 /* $NetBSD: wdc.c,v 1.74 1999/09/23 11:04:32 enami Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 124 125 #define DEBUG_INTR 0x01 126 #define DEBUG_XFERS 0x02 127 #define DEBUG_STATUS 0x04 128 #define DEBUG_FUNCS 0x08 129 #define DEBUG_PROBE 0x10 130 #define DEBUG_DETACH 0x20 131 #ifdef WDCDEBUG 132 int wdcdebug_mask = 0; 133 int wdc_nxfer = 0; 134 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 135 #else 136 #define WDCDEBUG_PRINT(args, level) 137 #endif 138 139 int 140 wdprint(aux, pnp) 141 void *aux; 142 const char *pnp; 143 { 144 struct ata_atapi_attach *aa_link = aux; 145 if (pnp) 146 printf("drive at %s", pnp); 147 printf(" channel %d drive %d", aa_link->aa_channel, 148 aa_link->aa_drv_data->drive); 149 return (UNCONF); 150 } 151 152 int 153 atapi_print(aux, pnp) 154 void *aux; 155 const char *pnp; 156 { 157 struct ata_atapi_attach *aa_link = aux; 158 if (pnp) 159 printf("atapibus at %s", pnp); 160 printf(" channel %d", aa_link->aa_channel); 161 return (UNCONF); 162 } 163 164 /* Test to see controller with at last one attached drive is there. 165 * Returns a bit for each possible drive found (0x01 for drive 0, 166 * 0x02 for drive 1). 167 * Logic: 168 * - If a status register is at 0xff, assume there is no drive here 169 * (ISA has pull-up resistors). If no drive at all -> return. 170 * - reset the controller, wait for it to complete (may take up to 31s !). 171 * If timeout -> return. 172 * - test ATA/ATAPI signatures. If at last one drive found -> return. 173 * - try an ATA command on the master. 174 */ 175 176 int 177 wdcprobe(chp) 178 struct channel_softc *chp; 179 { 180 u_int8_t st0, st1, sc, sn, cl, ch; 181 u_int8_t ret_value = 0x03; 182 u_int8_t drive; 183 184 /* 185 * Sanity check to see if the wdc channel responds at all. 186 */ 187 188 if (chp->wdc == NULL || 189 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM); 192 delay(10); 193 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 195 WDSD_IBM | 0x10); 196 delay(10); 197 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 198 199 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 200 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 201 chp->channel, st0, st1), DEBUG_PROBE); 202 203 if (st0 == 0xff) 204 ret_value &= ~0x01; 205 if (st1 == 0xff) 206 ret_value &= ~0x02; 207 if (ret_value == 0) 208 return 0; 209 } 210 211 /* assert SRST, wait for reset to complete */ 212 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 213 WDSD_IBM); 214 delay(10); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 216 WDCTL_RST | WDCTL_IDS); 217 DELAY(1000); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 219 WDCTL_IDS); 220 delay(1000); 221 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 222 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 223 delay(10); 224 225 ret_value = __wdcwait_reset(chp, ret_value); 226 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 227 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 228 ret_value), DEBUG_PROBE); 229 230 /* if reset failed, there's nothing here */ 231 if (ret_value == 0) 232 return 0; 233 234 /* 235 * Test presence of drives. First test register signatures looking for 236 * ATAPI devices. If it's not an ATAPI and reset said there may be 237 * something here assume it's ATA or OLD. Ghost will be killed later in 238 * attach routine. 239 */ 240 for (drive = 0; drive < 2; drive++) { 241 if ((ret_value & (0x01 << drive)) == 0) 242 continue; 243 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 244 WDSD_IBM | (drive << 4)); 245 delay(10); 246 /* Save registers contents */ 247 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 248 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 249 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 250 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 251 252 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 253 "cl=0x%x ch=0x%x\n", 254 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 255 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 256 /* 257 * sc is supposted to be 0x1 for ATAPI but at last one drive 258 * set it to 0x0 - or maybe it's the controller. 259 */ 260 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 261 cl == 0x14 && ch == 0xeb) { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 263 } else { 264 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 265 if (chp->wdc == NULL || 266 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 267 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 268 } 269 } 270 return (ret_value); 271 } 272 273 void 274 wdcattach(chp) 275 struct channel_softc *chp; 276 { 277 int channel_flags, ctrl_flags, i, error; 278 struct ata_atapi_attach aa_link; 279 struct ataparams params; 280 static int inited = 0; 281 282 if ((error = wdc_addref(chp)) != 0) { 283 printf("%s: unable to enable controller\n", 284 chp->wdc->sc_dev.dv_xname); 285 return; 286 } 287 288 if (wdcprobe(chp) == 0) 289 /* If no drives, abort attach here. */ 290 goto out; 291 292 /* initialise global data */ 293 if (inited == 0) { 294 295 /* Initialize the wdc_xfer pool. */ 296 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 297 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 298 inited++; 299 } 300 TAILQ_INIT(&chp->ch_queue->sc_xfer); 301 302 for (i = 0; i < 2; i++) { 303 chp->ch_drive[i].chnl_softc = chp; 304 chp->ch_drive[i].drive = i; 305 /* If controller can't do 16bit flag the drives as 32bit */ 306 if ((chp->wdc->cap & 307 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 308 WDC_CAPABILITY_DATA32) 309 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 310 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 311 continue; 312 313 /* Issue a IDENTIFY command, to try to detect slave ghost */ 314 if (ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms) == 315 CMD_OK) { 316 /* If IDENTIFY succeded, this is not an OLD ctrl */ 317 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 318 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 319 } else { 320 chp->ch_drive[i].drive_flags &= 321 ~(DRIVE_ATA | DRIVE_ATAPI); 322 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 323 chp->wdc->sc_dev.dv_xname, 324 chp->channel, i), DEBUG_PROBE); 325 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 326 continue; 327 /* 328 * Pre-ATA drive ? 329 * Test registers writability (Error register not 330 * writable, but cyllo is), then try an ATA command. 331 */ 332 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 333 WDSD_IBM | (i << 4)); 334 delay(10); 335 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 336 wd_error, 0x58); 337 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 338 wd_cyl_lo, 0xa5); 339 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 340 wd_error == 0x58) || 341 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 342 wd_cyl_lo) != 0xa5) { 343 WDCDEBUG_PRINT(("%s:%d:%d: register " 344 "writability failed\n", 345 chp->wdc->sc_dev.dv_xname, 346 chp->channel, i), DEBUG_PROBE); 347 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 348 } 349 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 350 WDSD_IBM | (i << 4)); 351 delay(100); 352 if (wait_for_ready(chp, 10000) != 0) { 353 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 354 chp->wdc->sc_dev.dv_xname, 355 chp->channel, i), DEBUG_PROBE); 356 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 357 continue; 358 } 359 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 360 wd_command, WDCC_RECAL); 361 if (wait_for_ready(chp, 10000) != 0) { 362 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 363 chp->wdc->sc_dev.dv_xname, 364 chp->channel, i), DEBUG_PROBE); 365 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 366 } 367 } 368 } 369 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 370 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 371 372 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 373 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 374 DEBUG_PROBE); 375 376 /* If no drives, abort here */ 377 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 378 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 379 goto out; 380 381 /* 382 * Attach an ATAPI bus, if needed. 383 */ 384 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 385 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 386 #if NATAPIBUS > 0 387 wdc_atapibus_attach(chp); 388 #else 389 /* 390 * Fills in a fake aa_link and call config_found, so that 391 * the config machinery will print 392 * "atapibus at xxx not configured" 393 */ 394 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 395 aa_link.aa_type = T_ATAPI; 396 aa_link.aa_channel = chp->channel; 397 aa_link.aa_openings = 1; 398 aa_link.aa_drv_data = 0; 399 aa_link.aa_bus_private = NULL; 400 chp->atapibus = config_found(&chp->wdc->sc_dev, 401 (void *)&aa_link, atapi_print); 402 #endif 403 } 404 405 for (i = 0; i < 2; i++) { 406 if ((chp->ch_drive[i].drive_flags & 407 (DRIVE_ATA | DRIVE_OLD)) == 0) { 408 continue; 409 } 410 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 411 aa_link.aa_type = T_ATA; 412 aa_link.aa_channel = chp->channel; 413 aa_link.aa_openings = 1; 414 aa_link.aa_drv_data = &chp->ch_drive[i]; 415 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 416 wdc_probe_caps(&chp->ch_drive[i]); 417 } 418 419 /* 420 * reset drive_flags for unnatached devices, reset state for attached 421 * ones 422 */ 423 for (i = 0; i < 2; i++) { 424 if (chp->ch_drive[i].drv_softc == NULL) 425 chp->ch_drive[i].drive_flags = 0; 426 else 427 chp->ch_drive[i].state = 0; 428 } 429 430 /* 431 * Reset channel. The probe, with some combinations of ATA/ATAPI 432 * devices keep it in a mostly working, but strange state (with busy 433 * led on) 434 */ 435 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 436 wdcreset(chp, VERBOSE); 437 /* 438 * Read status registers to avoid spurious interrupts. 439 */ 440 for (i = 1; i >= 0; i--) { 441 if (chp->ch_drive[i].drive_flags & DRIVE) { 442 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 443 wd_sdh, WDSD_IBM | (i << 4)); 444 if (wait_for_unbusy(chp, 10000) < 0) 445 printf("%s:%d:%d: device busy\n", 446 chp->wdc->sc_dev.dv_xname, 447 chp->channel, i); 448 } 449 } 450 } 451 452 out: 453 wdc_delref(chp); 454 } 455 456 /* 457 * Call activate routine of underlying devices. 458 */ 459 int 460 wdcactivate(self, act) 461 struct device *self; 462 enum devact act; 463 { 464 struct wdc_softc *wdc = (struct wdc_softc *)self; 465 struct channel_softc *chp; 466 struct device *sc; 467 int s, i, j, error = 0; 468 469 s = splbio(); 470 switch (act) { 471 case DVACT_ACTIVATE: 472 error = EOPNOTSUPP; 473 break; 474 475 case DVACT_DEACTIVATE: 476 for (i = 0; i < wdc->nchannels; i++) { 477 chp = wdc->channels[i]; 478 479 /* 480 * We might call deactivate routine for 481 * the children of atapibus twice (once via 482 * atapibus, once directly), but since 483 * config_deactivate maintains DVF_ACTIVE flag, 484 * it's safe. 485 */ 486 sc = chp->atapibus; 487 if (sc != NULL) { 488 error = config_deactivate(sc); 489 if (error != 0) 490 goto out; 491 } 492 493 for (j = 0; j < 2; j++) { 494 sc = chp->ch_drive[j].drv_softc; 495 WDCDEBUG_PRINT(("wdcactivate: %s:" 496 " deactivating %s\n", wdc->sc_dev.dv_xname, 497 sc == NULL ? "nodrv" : sc->dv_xname), 498 DEBUG_DETACH); 499 if (sc != NULL) { 500 error = config_deactivate(sc); 501 if (error != 0) 502 goto out; 503 } 504 } 505 } 506 break; 507 } 508 509 out: 510 splx(s); 511 512 #ifdef WDCDEBUG 513 if (error != 0) 514 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 515 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 516 #endif 517 return (error); 518 } 519 520 int 521 wdcdetach(self, flags) 522 struct device *self; 523 int flags; 524 { 525 struct wdc_softc *wdc = (struct wdc_softc *)self; 526 struct channel_softc *chp; 527 struct device *sc; 528 int i, j, error = 0; 529 530 for (i = 0; i < wdc->nchannels; i++) { 531 chp = wdc->channels[i]; 532 533 /* 534 * Detach atapibus and its children. 535 */ 536 sc = chp->atapibus; 537 if (sc != NULL) { 538 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 539 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 540 error = config_detach(sc, flags); 541 if (error != 0) 542 goto out; 543 } 544 545 /* 546 * Detach our other children. 547 */ 548 for (j = 0; j < 2; j++) { 549 sc = chp->ch_drive[j].drv_softc; 550 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 551 wdc->sc_dev.dv_xname, 552 sc == NULL ? "nodrv" : sc->dv_xname), 553 DEBUG_DETACH); 554 if (sc != NULL) { 555 error = config_detach(sc, flags); 556 if (error != 0) 557 goto out; 558 } 559 } 560 } 561 562 out: 563 #ifdef WDCDEBUG 564 if (error != 0) 565 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 566 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 567 #endif 568 return (error); 569 } 570 571 /* 572 * Start I/O on a controller, for the given channel. 573 * The first xfer may be not for our channel if the channel queues 574 * are shared. 575 */ 576 void 577 wdcstart(chp) 578 struct channel_softc *chp; 579 { 580 struct wdc_xfer *xfer; 581 582 #ifdef WDC_DIAGNOSTIC 583 int spl1, spl2; 584 585 spl1 = splbio(); 586 spl2 = splbio(); 587 if (spl2 != spl1) { 588 printf("wdcstart: not at splbio()\n"); 589 panic("wdcstart"); 590 } 591 splx(spl2); 592 splx(spl1); 593 #endif /* WDC_DIAGNOSTIC */ 594 595 /* is there a xfer ? */ 596 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 597 return; 598 599 /* adjust chp, in case we have a shared queue */ 600 chp = xfer->chp; 601 602 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 603 return; /* channel aleady active */ 604 } 605 #ifdef DIAGNOSTIC 606 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 607 panic("wdcstart: channel waiting for irq\n"); 608 #endif 609 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 610 if (!(*chp->wdc->claim_hw)(chp, 0)) 611 return; 612 613 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 614 chp->channel, xfer->drive), DEBUG_XFERS); 615 chp->ch_flags |= WDCF_ACTIVE; 616 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 617 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 618 chp->ch_drive[xfer->drive].state = 0; 619 } 620 xfer->c_start(chp, xfer); 621 } 622 623 /* restart an interrupted I/O */ 624 void 625 wdcrestart(v) 626 void *v; 627 { 628 struct channel_softc *chp = v; 629 int s; 630 631 s = splbio(); 632 wdcstart(chp); 633 splx(s); 634 } 635 636 637 /* 638 * Interrupt routine for the controller. Acknowledge the interrupt, check for 639 * errors on the current operation, mark it done if necessary, and start the 640 * next request. Also check for a partially done transfer, and continue with 641 * the next chunk if so. 642 */ 643 int 644 wdcintr(arg) 645 void *arg; 646 { 647 struct channel_softc *chp = arg; 648 struct wdc_xfer *xfer; 649 650 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 651 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 652 return 0; 653 } 654 655 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 656 chp->ch_flags &= ~WDCF_IRQ_WAIT; 657 xfer = chp->ch_queue->sc_xfer.tqh_first; 658 return xfer->c_intr(chp, xfer, 1); 659 } 660 661 /* Put all disk in RESET state */ 662 void wdc_reset_channel(drvp) 663 struct ata_drive_datas *drvp; 664 { 665 struct channel_softc *chp = drvp->chnl_softc; 666 int drive; 667 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 668 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 669 DEBUG_FUNCS); 670 (void) wdcreset(chp, VERBOSE); 671 for (drive = 0; drive < 2; drive++) { 672 chp->ch_drive[drive].state = 0; 673 } 674 } 675 676 int 677 wdcreset(chp, verb) 678 struct channel_softc *chp; 679 int verb; 680 { 681 int drv_mask1, drv_mask2; 682 683 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 684 WDSD_IBM); /* master */ 685 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 686 WDCTL_RST | WDCTL_IDS); 687 delay(1000); 688 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 689 WDCTL_IDS); 690 delay(1000); 691 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 692 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 693 WDCTL_4BIT); 694 695 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 696 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 697 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 698 if (verb && drv_mask2 != drv_mask1) { 699 printf("%s channel %d: reset failed for", 700 chp->wdc->sc_dev.dv_xname, chp->channel); 701 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 702 printf(" drive 0"); 703 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 704 printf(" drive 1"); 705 printf("\n"); 706 } 707 return (drv_mask1 != drv_mask2) ? 1 : 0; 708 } 709 710 static int 711 __wdcwait_reset(chp, drv_mask) 712 struct channel_softc *chp; 713 int drv_mask; 714 { 715 int timeout; 716 u_int8_t st0, st1; 717 #ifdef WDCDEBUG 718 u_int8_t sc0, sn0, cl0, ch0; 719 u_int8_t sc1, sn1, cl1, ch1; 720 #endif 721 /* wait for BSY to deassert */ 722 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 723 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 724 WDSD_IBM); /* master */ 725 delay(10); 726 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 727 #ifdef WDCDEBUG 728 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 729 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 730 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 731 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 732 #endif 733 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 734 WDSD_IBM | 0x10); /* slave */ 735 delay(10); 736 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 737 #ifdef WDCDEBUG 738 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 739 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 740 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 741 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 742 #endif 743 744 if ((drv_mask & 0x01) == 0) { 745 /* no master */ 746 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 747 /* No master, slave is ready, it's done */ 748 goto end; 749 } 750 } else if ((drv_mask & 0x02) == 0) { 751 /* no slave */ 752 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 753 /* No slave, master is ready, it's done */ 754 goto end; 755 } 756 } else { 757 /* Wait for both master and slave to be ready */ 758 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 759 goto end; 760 } 761 } 762 delay(WDCDELAY); 763 } 764 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 765 if (st0 & WDCS_BSY) 766 drv_mask &= ~0x01; 767 if (st1 & WDCS_BSY) 768 drv_mask &= ~0x02; 769 end: 770 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 771 "cl=0x%x ch=0x%x\n", 772 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 773 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 774 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 775 "cl=0x%x ch=0x%x\n", 776 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 777 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 778 779 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 780 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 781 st0, st1), DEBUG_PROBE); 782 783 return drv_mask; 784 } 785 786 /* 787 * Wait for a drive to be !BSY, and have mask in its status register. 788 * return -1 for a timeout after "timeout" ms. 789 */ 790 int 791 wdcwait(chp, mask, bits, timeout) 792 struct channel_softc *chp; 793 int mask, bits, timeout; 794 { 795 u_char status; 796 int time = 0; 797 #ifdef WDCNDELAY_DEBUG 798 extern int cold; 799 #endif 800 801 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 802 :"none", chp->channel), DEBUG_STATUS); 803 chp->ch_error = 0; 804 805 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 806 807 for (;;) { 808 chp->ch_status = status = 809 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 810 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 811 break; 812 if (++time > timeout) { 813 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 814 "error %x\n", status, 815 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 816 wd_error)), 817 DEBUG_STATUS); 818 return -1; 819 } 820 delay(WDCDELAY); 821 } 822 if (status & WDCS_ERR) 823 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 824 wd_error); 825 #ifdef WDCNDELAY_DEBUG 826 /* After autoconfig, there should be no long delays. */ 827 if (!cold && time > WDCNDELAY_DEBUG) { 828 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 829 if (xfer == NULL) 830 printf("%s channel %d: warning: busy-wait took %dus\n", 831 chp->wdc->sc_dev.dv_xname, chp->channel, 832 WDCDELAY * time); 833 else 834 printf("%s:%d:%d: warning: busy-wait took %dus\n", 835 chp->wdc->sc_dev.dv_xname, chp->channel, 836 xfer->drive, 837 WDCDELAY * time); 838 } 839 #endif 840 return 0; 841 } 842 843 void 844 wdctimeout(arg) 845 void *arg; 846 { 847 struct channel_softc *chp = (struct channel_softc *)arg; 848 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 849 int s; 850 851 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 852 853 s = splbio(); 854 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 855 __wdcerror(chp, "lost interrupt"); 856 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 857 "atapi":"ata"); 858 printf("\tc_bcount: %d\n", xfer->c_bcount); 859 printf("\tc_skip: %d\n", xfer->c_skip); 860 /* 861 * Call the interrupt routine. If we just missed and interrupt, 862 * it will do what's needed. Else, it will take the needed 863 * action (reset the device). 864 * Before that we need to reinstall the timeout callback, 865 * in case it will miss another irq while in this transfer 866 * We arbitray chose it to be 1s 867 */ 868 timeout(wdctimeout, chp, hz); 869 xfer->c_flags |= C_TIMEOU; 870 chp->ch_flags &= ~WDCF_IRQ_WAIT; 871 xfer->c_intr(chp, xfer, 1); 872 } else 873 __wdcerror(chp, "missing untimeout"); 874 splx(s); 875 } 876 877 /* 878 * Probe drive's capabilites, for use by the controller later 879 * Assumes drvp points to an existing drive. 880 * XXX this should be a controller-indep function 881 */ 882 void 883 wdc_probe_caps(drvp) 884 struct ata_drive_datas *drvp; 885 { 886 struct ataparams params, params2; 887 struct channel_softc *chp = drvp->chnl_softc; 888 struct device *drv_dev = drvp->drv_softc; 889 struct wdc_softc *wdc = chp->wdc; 890 int i, printed; 891 char *sep = ""; 892 int cf_flags; 893 894 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 895 /* IDENTIFY failed. Can't tell more about the device */ 896 return; 897 } 898 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 899 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 900 /* 901 * Controller claims 16 and 32 bit transfers. 902 * Re-do an IDENTIFY with 32-bit transfers, 903 * and compare results. 904 */ 905 drvp->drive_flags |= DRIVE_CAP32; 906 ata_get_params(drvp, AT_POLL, ¶ms2); 907 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 908 /* Not good. fall back to 16bits */ 909 drvp->drive_flags &= ~DRIVE_CAP32; 910 } else { 911 printf("%s: 32-bits data port", drv_dev->dv_xname); 912 } 913 } 914 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 915 if (params.atap_ata_major > 0x01 && 916 params.atap_ata_major != 0xffff) { 917 for (i = 14; i > 0; i--) { 918 if (params.atap_ata_major & (1 << i)) { 919 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 920 printf("%s: ", drv_dev->dv_xname); 921 else 922 printf(", "); 923 printf("ATA version %d\n", i); 924 drvp->ata_vers = i; 925 break; 926 } 927 } 928 } else 929 #endif 930 if (drvp->drive_flags & DRIVE_CAP32) 931 printf("\n"); 932 933 /* An ATAPI device is at last PIO mode 3 */ 934 if (drvp->drive_flags & DRIVE_ATAPI) 935 drvp->PIO_mode = 3; 936 937 /* 938 * It's not in the specs, but it seems that some drive 939 * returns 0xffff in atap_extensions when this field is invalid 940 */ 941 if (params.atap_extensions != 0xffff && 942 (params.atap_extensions & WDC_EXT_MODES)) { 943 printed = 0; 944 /* 945 * XXX some drives report something wrong here (they claim to 946 * support PIO mode 8 !). As mode is coded on 3 bits in 947 * SET FEATURE, limit it to 7 (so limit i to 4). 948 * If higther mode than 7 is found, abort. 949 */ 950 for (i = 7; i >= 0; i--) { 951 if ((params.atap_piomode_supp & (1 << i)) == 0) 952 continue; 953 if (i > 4) 954 return; 955 /* 956 * See if mode is accepted. 957 * If the controller can't set its PIO mode, 958 * assume the defaults are good, so don't try 959 * to set it 960 */ 961 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 962 if (ata_set_mode(drvp, 0x08 | (i + 3), 963 AT_POLL) != CMD_OK) 964 continue; 965 if (!printed) { 966 printf("%s: drive supports PIO mode %d", 967 drv_dev->dv_xname, i + 3); 968 sep = ","; 969 printed = 1; 970 } 971 /* 972 * If controller's driver can't set its PIO mode, 973 * get the highter one for the drive. 974 */ 975 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 976 wdc->PIO_cap >= i + 3) { 977 drvp->PIO_mode = i + 3; 978 drvp->PIO_cap = i + 3; 979 break; 980 } 981 } 982 if (!printed) { 983 /* 984 * We didn't find a valid PIO mode. 985 * Assume the values returned for DMA are buggy too 986 */ 987 return; 988 } 989 drvp->drive_flags |= DRIVE_MODE; 990 printed = 0; 991 for (i = 7; i >= 0; i--) { 992 if ((params.atap_dmamode_supp & (1 << i)) == 0) 993 continue; 994 if ((wdc->cap & WDC_CAPABILITY_DMA) && 995 (wdc->cap & WDC_CAPABILITY_MODE)) 996 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 997 != CMD_OK) 998 continue; 999 if (!printed) { 1000 printf("%s DMA mode %d", sep, i); 1001 sep = ","; 1002 printed = 1; 1003 } 1004 if (wdc->cap & WDC_CAPABILITY_DMA) { 1005 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1006 wdc->DMA_cap < i) 1007 continue; 1008 drvp->DMA_mode = i; 1009 drvp->DMA_cap = i; 1010 drvp->drive_flags |= DRIVE_DMA; 1011 } 1012 break; 1013 } 1014 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1015 printed = 0; 1016 for (i = 7; i >= 0; i--) { 1017 if ((params.atap_udmamode_supp & (1 << i)) 1018 == 0) 1019 continue; 1020 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1021 (wdc->cap & WDC_CAPABILITY_UDMA)) 1022 if (ata_set_mode(drvp, 0x40 | i, 1023 AT_POLL) != CMD_OK) 1024 continue; 1025 if (!printed) { 1026 printf("%s Ultra-DMA mode %d", sep, i); 1027 sep = ","; 1028 printed = 1; 1029 } 1030 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1031 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1032 wdc->UDMA_cap < i) 1033 continue; 1034 drvp->UDMA_mode = i; 1035 drvp->UDMA_cap = i; 1036 drvp->drive_flags |= DRIVE_UDMA; 1037 } 1038 break; 1039 } 1040 } 1041 printf("\n"); 1042 } 1043 1044 /* Try to guess ATA version here, if it didn't get reported */ 1045 if (drvp->ata_vers == 0) { 1046 if (drvp->drive_flags & DRIVE_UDMA) 1047 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1048 else if (drvp->PIO_cap > 2) 1049 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1050 } 1051 cf_flags = drv_dev->dv_cfdata->cf_flags; 1052 if (cf_flags & ATA_CONFIG_PIO_SET) { 1053 drvp->PIO_mode = 1054 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1055 drvp->drive_flags |= DRIVE_MODE; 1056 } 1057 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1058 /* don't care about DMA modes */ 1059 return; 1060 } 1061 if (cf_flags & ATA_CONFIG_DMA_SET) { 1062 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1063 ATA_CONFIG_DMA_DISABLE) { 1064 drvp->drive_flags &= ~DRIVE_DMA; 1065 } else { 1066 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1067 ATA_CONFIG_DMA_OFF; 1068 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1069 } 1070 } 1071 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1072 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1073 ATA_CONFIG_UDMA_DISABLE) { 1074 drvp->drive_flags &= ~DRIVE_UDMA; 1075 } else { 1076 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1077 ATA_CONFIG_UDMA_OFF; 1078 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1079 } 1080 } 1081 } 1082 1083 /* 1084 * downgrade the transfer mode of a drive after an error. return 1 if 1085 * downgrade was possible, 0 otherwise. 1086 */ 1087 int 1088 wdc_downgrade_mode(drvp) 1089 struct ata_drive_datas *drvp; 1090 { 1091 struct channel_softc *chp = drvp->chnl_softc; 1092 struct device *drv_dev = drvp->drv_softc; 1093 struct wdc_softc *wdc = chp->wdc; 1094 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1095 1096 /* if drive or controller don't know its mode, we can't do much */ 1097 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1098 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1099 return 0; 1100 /* current drive mode was set by a config flag, let it this way */ 1101 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1102 (cf_flags & ATA_CONFIG_DMA_SET) || 1103 (cf_flags & ATA_CONFIG_UDMA_SET)) 1104 return 0; 1105 1106 /* 1107 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1108 * Maybe we didn't properly notice the cable type 1109 */ 1110 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 2) { 1111 drvp->UDMA_mode = 2; 1112 printf("%s: transfer error, downgrading to DMA mode %d\n", 1113 drv_dev->dv_xname, drvp->UDMA_mode); 1114 } 1115 1116 /* 1117 * If we were using ultra-DMA, don't downgrade to multiword DMA 1118 * if we noticed a CRC error. It has been noticed that CRC errors 1119 * in ultra-DMA lead to silent data corruption in multiword DMA. 1120 * Data corruption is less likely to occur in PIO mode. 1121 */ 1122 1123 else if ((drvp->drive_flags & DRIVE_UDMA) && 1124 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1125 drvp->drive_flags &= ~DRIVE_UDMA; 1126 drvp->drive_flags |= DRIVE_DMA; 1127 drvp->DMA_mode = drvp->DMA_cap; 1128 printf("%s: transfer error, downgrading to DMA mode %d\n", 1129 drv_dev->dv_xname, drvp->DMA_mode); 1130 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1131 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1132 drvp->PIO_mode = drvp->PIO_cap; 1133 printf("%s: transfer error, downgrading to PIO mode %d\n", 1134 drv_dev->dv_xname, drvp->PIO_mode); 1135 } else /* already using PIO, can't downgrade */ 1136 return 0; 1137 1138 wdc->set_modes(chp); 1139 /* reset the channel, which will shedule all drives for setup */ 1140 wdc_reset_channel(drvp); 1141 return 1; 1142 } 1143 1144 int 1145 wdc_exec_command(drvp, wdc_c) 1146 struct ata_drive_datas *drvp; 1147 struct wdc_command *wdc_c; 1148 { 1149 struct channel_softc *chp = drvp->chnl_softc; 1150 struct wdc_xfer *xfer; 1151 int s, ret; 1152 1153 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1154 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1155 DEBUG_FUNCS); 1156 1157 /* set up an xfer and queue. Wait for completion */ 1158 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1159 WDC_NOSLEEP); 1160 if (xfer == NULL) { 1161 return WDC_TRY_AGAIN; 1162 } 1163 1164 if (wdc_c->flags & AT_POLL) 1165 xfer->c_flags |= C_POLL; 1166 xfer->drive = drvp->drive; 1167 xfer->databuf = wdc_c->data; 1168 xfer->c_bcount = wdc_c->bcount; 1169 xfer->cmd = wdc_c; 1170 xfer->c_start = __wdccommand_start; 1171 xfer->c_intr = __wdccommand_intr; 1172 1173 s = splbio(); 1174 wdc_exec_xfer(chp, xfer); 1175 #ifdef DIAGNOSTIC 1176 if ((wdc_c->flags & AT_POLL) != 0 && 1177 (wdc_c->flags & AT_DONE) == 0) 1178 panic("wdc_exec_command: polled command not done\n"); 1179 #endif 1180 if (wdc_c->flags & AT_DONE) { 1181 ret = WDC_COMPLETE; 1182 } else { 1183 if (wdc_c->flags & AT_WAIT) { 1184 while ((wdc_c->flags & AT_DONE) == 0) { 1185 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1186 } 1187 ret = WDC_COMPLETE; 1188 } else { 1189 ret = WDC_QUEUED; 1190 } 1191 } 1192 splx(s); 1193 return ret; 1194 } 1195 1196 void 1197 __wdccommand_start(chp, xfer) 1198 struct channel_softc *chp; 1199 struct wdc_xfer *xfer; 1200 { 1201 int drive = xfer->drive; 1202 struct wdc_command *wdc_c = xfer->cmd; 1203 1204 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1205 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1206 DEBUG_FUNCS); 1207 1208 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1209 WDSD_IBM | (drive << 4)); 1210 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1211 wdc_c->timeout) != 0) { 1212 wdc_c->flags |= AT_TIMEOU; 1213 __wdccommand_done(chp, xfer); 1214 return; 1215 } 1216 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1217 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1218 if ((wdc_c->flags & AT_POLL) == 0) { 1219 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1220 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1221 return; 1222 } 1223 /* 1224 * Polled command. Wait for drive ready or drq. Done in intr(). 1225 * Wait for at last 400ns for status bit to be valid. 1226 */ 1227 delay(10); 1228 __wdccommand_intr(chp, xfer, 0); 1229 } 1230 1231 int 1232 __wdccommand_intr(chp, xfer, irq) 1233 struct channel_softc *chp; 1234 struct wdc_xfer *xfer; 1235 int irq; 1236 { 1237 struct wdc_command *wdc_c = xfer->cmd; 1238 int bcount = wdc_c->bcount; 1239 char *data = wdc_c->data; 1240 1241 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1242 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1243 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1244 (irq == 0) ? wdc_c->timeout : 0)) { 1245 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1246 return 0; /* IRQ was not for us */ 1247 wdc_c->flags |= AT_TIMEOU; 1248 __wdccommand_done(chp, xfer); 1249 return 1; 1250 } 1251 if (wdc_c->flags & AT_READ) { 1252 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1253 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1254 0, (u_int32_t*)data, bcount >> 2); 1255 data += bcount & 0xfffffffc; 1256 bcount = bcount & 0x03; 1257 } 1258 if (bcount > 0) 1259 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1260 wd_data, (u_int16_t *)data, bcount >> 1); 1261 } else if (wdc_c->flags & AT_WRITE) { 1262 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1263 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1264 0, (u_int32_t*)data, bcount >> 2); 1265 data += bcount & 0xfffffffc; 1266 bcount = bcount & 0x03; 1267 } 1268 if (bcount > 0) 1269 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1270 wd_data, (u_int16_t *)data, bcount >> 1); 1271 } 1272 __wdccommand_done(chp, xfer); 1273 return 1; 1274 } 1275 1276 void 1277 __wdccommand_done(chp, xfer) 1278 struct channel_softc *chp; 1279 struct wdc_xfer *xfer; 1280 { 1281 struct wdc_command *wdc_c = xfer->cmd; 1282 1283 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1284 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1285 1286 untimeout(wdctimeout, chp); 1287 1288 if (chp->ch_status & WDCS_DWF) 1289 wdc_c->flags |= AT_DF; 1290 if (chp->ch_status & WDCS_ERR) { 1291 wdc_c->flags |= AT_ERROR; 1292 wdc_c->r_error = chp->ch_error; 1293 } 1294 wdc_c->flags |= AT_DONE; 1295 if (wdc_c->flags & AT_READREG && (wdc_c->flags & (AT_ERROR | AT_DF)) 1296 == 0) { 1297 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1298 wd_sdh); 1299 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1300 wd_cyl_hi) << 8; 1301 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1302 wd_cyl_lo); 1303 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1304 wd_sector); 1305 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1306 wd_seccnt); 1307 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1308 wd_error); 1309 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1310 wd_precomp); 1311 } 1312 wdc_free_xfer(chp, xfer); 1313 if (wdc_c->flags & AT_WAIT) 1314 wakeup(wdc_c); 1315 else if (wdc_c->callback) 1316 wdc_c->callback(wdc_c->callback_arg); 1317 wdcstart(chp); 1318 return; 1319 } 1320 1321 /* 1322 * Send a command. The drive should be ready. 1323 * Assumes interrupts are blocked. 1324 */ 1325 void 1326 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1327 struct channel_softc *chp; 1328 u_int8_t drive; 1329 u_int8_t command; 1330 u_int16_t cylin; 1331 u_int8_t head, sector, count, precomp; 1332 { 1333 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1334 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1335 chp->channel, drive, command, cylin, head, sector, count, precomp), 1336 DEBUG_FUNCS); 1337 1338 /* Select drive, head, and addressing mode. */ 1339 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1340 WDSD_IBM | (drive << 4) | head); 1341 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1342 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1343 precomp); 1344 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1345 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1347 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1348 1349 /* Send command. */ 1350 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1351 return; 1352 } 1353 1354 /* 1355 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1356 * tested by the caller. 1357 */ 1358 void 1359 wdccommandshort(chp, drive, command) 1360 struct channel_softc *chp; 1361 int drive; 1362 int command; 1363 { 1364 1365 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1366 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1367 DEBUG_FUNCS); 1368 1369 /* Select drive. */ 1370 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1371 WDSD_IBM | (drive << 4)); 1372 1373 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1374 } 1375 1376 /* Add a command to the queue and start controller. Must be called at splbio */ 1377 1378 void 1379 wdc_exec_xfer(chp, xfer) 1380 struct channel_softc *chp; 1381 struct wdc_xfer *xfer; 1382 { 1383 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1384 chp->channel, xfer->drive), DEBUG_XFERS); 1385 1386 /* complete xfer setup */ 1387 xfer->chp = chp; 1388 1389 /* 1390 * If we are a polled command, and the list is not empty, 1391 * we are doing a dump. Drop the list to allow the polled command 1392 * to complete, we're going to reboot soon anyway. 1393 */ 1394 if ((xfer->c_flags & C_POLL) != 0 && 1395 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1396 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1397 } 1398 /* insert at the end of command list */ 1399 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1400 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1401 chp->ch_flags), DEBUG_XFERS); 1402 wdcstart(chp); 1403 } 1404 1405 struct wdc_xfer * 1406 wdc_get_xfer(flags) 1407 int flags; 1408 { 1409 struct wdc_xfer *xfer; 1410 int s; 1411 1412 s = splbio(); 1413 xfer = pool_get(&wdc_xfer_pool, 1414 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1415 splx(s); 1416 memset(xfer, 0, sizeof(struct wdc_xfer)); 1417 return xfer; 1418 } 1419 1420 void 1421 wdc_free_xfer(chp, xfer) 1422 struct channel_softc *chp; 1423 struct wdc_xfer *xfer; 1424 { 1425 struct wdc_softc *wdc = chp->wdc; 1426 int s; 1427 1428 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1429 (*wdc->free_hw)(chp); 1430 s = splbio(); 1431 chp->ch_flags &= ~WDCF_ACTIVE; 1432 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1433 pool_put(&wdc_xfer_pool, xfer); 1434 splx(s); 1435 } 1436 1437 static void 1438 __wdcerror(chp, msg) 1439 struct channel_softc *chp; 1440 char *msg; 1441 { 1442 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1443 if (xfer == NULL) 1444 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1445 msg); 1446 else 1447 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1448 chp->channel, xfer->drive, msg); 1449 } 1450 1451 /* 1452 * the bit bucket 1453 */ 1454 void 1455 wdcbit_bucket(chp, size) 1456 struct channel_softc *chp; 1457 int size; 1458 { 1459 1460 for (; size >= 2; size -= 2) 1461 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1462 if (size) 1463 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1464 } 1465 1466 int 1467 wdc_addref(chp) 1468 struct channel_softc *chp; 1469 { 1470 struct wdc_softc *wdc = chp->wdc; 1471 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1472 int s, error = 0; 1473 1474 s = splbio(); 1475 if (adapter->scsipi_refcnt++ == 0 && 1476 adapter->scsipi_enable != NULL) { 1477 error = (*adapter->scsipi_enable)(wdc, 1); 1478 if (error) 1479 adapter->scsipi_refcnt--; 1480 } 1481 splx(s); 1482 return (error); 1483 } 1484 1485 void 1486 wdc_delref(chp) 1487 struct channel_softc *chp; 1488 { 1489 struct wdc_softc *wdc = chp->wdc; 1490 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1491 int s; 1492 1493 s = splbio(); 1494 if (adapter->scsipi_refcnt-- == 1 && 1495 adapter->scsipi_enable != NULL) 1496 (void) (*adapter->scsipi_enable)(wdc, 0); 1497 splx(s); 1498 } 1499
Indexes created Wed Sep 24 05:09:52 GMT 2025