wdc.c revision 1.77
1 /* $NetBSD: wdc.c,v 1.77 1999/11/28 20:04:22 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 void wdc_kill_pending __P((struct channel_softc *)); 124 125 126 #define DEBUG_INTR 0x01 127 #define DEBUG_XFERS 0x02 128 #define DEBUG_STATUS 0x04 129 #define DEBUG_FUNCS 0x08 130 #define DEBUG_PROBE 0x10 131 #define DEBUG_DETACH 0x20 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc is supposted to be 0x1 for ATAPI but at last one drive 259 * set it to 0x0 - or maybe it's the controller. 260 */ 261 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 262 cl == 0x14 && ch == 0xeb) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 264 } else { 265 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 266 if (chp->wdc == NULL || 267 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 268 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 269 } 270 } 271 return (ret_value); 272 } 273 274 void 275 wdcattach(chp) 276 struct channel_softc *chp; 277 { 278 int channel_flags, ctrl_flags, i, error; 279 struct ata_atapi_attach aa_link; 280 struct ataparams params; 281 static int inited = 0; 282 283 if ((error = wdc_addref(chp)) != 0) { 284 printf("%s: unable to enable controller\n", 285 chp->wdc->sc_dev.dv_xname); 286 return; 287 } 288 289 if (wdcprobe(chp) == 0) 290 /* If no drives, abort attach here. */ 291 goto out; 292 293 /* initialise global data */ 294 if (inited == 0) { 295 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* If controller can't do 16bit flag the drives as 32bit */ 307 if ((chp->wdc->cap & 308 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 309 WDC_CAPABILITY_DATA32) 310 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 311 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 312 continue; 313 314 /* Issue a IDENTIFY command, to try to detect slave ghost */ 315 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 316 if (error == CMD_OK) { 317 /* If IDENTIFY succeded, this is not an OLD ctrl */ 318 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 319 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 320 } else { 321 chp->ch_drive[i].drive_flags &= 322 ~(DRIVE_ATA | DRIVE_ATAPI); 323 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 324 chp->wdc->sc_dev.dv_xname, 325 chp->channel, i, error), DEBUG_PROBE); 326 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 327 continue; 328 /* 329 * Pre-ATA drive ? 330 * Test registers writability (Error register not 331 * writable, but cyllo is), then try an ATA command. 332 */ 333 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 334 WDSD_IBM | (i << 4)); 335 delay(10); 336 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 337 wd_error, 0x58); 338 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 339 wd_cyl_lo, 0xa5); 340 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 341 wd_error == 0x58) || 342 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 343 wd_cyl_lo) != 0xa5) { 344 WDCDEBUG_PRINT(("%s:%d:%d: register " 345 "writability failed\n", 346 chp->wdc->sc_dev.dv_xname, 347 chp->channel, i), DEBUG_PROBE); 348 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 349 } 350 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 351 WDSD_IBM | (i << 4)); 352 delay(100); 353 if (wait_for_ready(chp, 10000) != 0) { 354 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 355 chp->wdc->sc_dev.dv_xname, 356 chp->channel, i), DEBUG_PROBE); 357 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 358 continue; 359 } 360 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 361 wd_command, WDCC_RECAL); 362 if (wait_for_ready(chp, 10000) != 0) { 363 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 364 chp->wdc->sc_dev.dv_xname, 365 chp->channel, i), DEBUG_PROBE); 366 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 367 } 368 } 369 } 370 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 371 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 372 373 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 374 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 375 DEBUG_PROBE); 376 377 /* If no drives, abort here */ 378 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 379 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 380 goto out; 381 382 /* 383 * Attach an ATAPI bus, if needed. 384 */ 385 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 386 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 387 #if NATAPIBUS > 0 388 wdc_atapibus_attach(chp); 389 #else 390 /* 391 * Fills in a fake aa_link and call config_found, so that 392 * the config machinery will print 393 * "atapibus at xxx not configured" 394 */ 395 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 396 aa_link.aa_type = T_ATAPI; 397 aa_link.aa_channel = chp->channel; 398 aa_link.aa_openings = 1; 399 aa_link.aa_drv_data = 0; 400 aa_link.aa_bus_private = NULL; 401 chp->atapibus = config_found(&chp->wdc->sc_dev, 402 (void *)&aa_link, atapi_print); 403 #endif 404 } 405 406 for (i = 0; i < 2; i++) { 407 if ((chp->ch_drive[i].drive_flags & 408 (DRIVE_ATA | DRIVE_OLD)) == 0) { 409 continue; 410 } 411 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 412 aa_link.aa_type = T_ATA; 413 aa_link.aa_channel = chp->channel; 414 aa_link.aa_openings = 1; 415 aa_link.aa_drv_data = &chp->ch_drive[i]; 416 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 417 wdc_probe_caps(&chp->ch_drive[i]); 418 } 419 420 /* 421 * reset drive_flags for unnatached devices, reset state for attached 422 * ones 423 */ 424 for (i = 0; i < 2; i++) { 425 if (chp->ch_drive[i].drv_softc == NULL) 426 chp->ch_drive[i].drive_flags = 0; 427 else 428 chp->ch_drive[i].state = 0; 429 } 430 431 /* 432 * Reset channel. The probe, with some combinations of ATA/ATAPI 433 * devices keep it in a mostly working, but strange state (with busy 434 * led on) 435 */ 436 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 437 wdcreset(chp, VERBOSE); 438 /* 439 * Read status registers to avoid spurious interrupts. 440 */ 441 for (i = 1; i >= 0; i--) { 442 if (chp->ch_drive[i].drive_flags & DRIVE) { 443 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 444 wd_sdh, WDSD_IBM | (i << 4)); 445 if (wait_for_unbusy(chp, 10000) < 0) 446 printf("%s:%d:%d: device busy\n", 447 chp->wdc->sc_dev.dv_xname, 448 chp->channel, i); 449 } 450 } 451 } 452 453 out: 454 wdc_delref(chp); 455 } 456 457 /* 458 * Call activate routine of underlying devices. 459 */ 460 int 461 wdcactivate(self, act) 462 struct device *self; 463 enum devact act; 464 { 465 struct wdc_softc *wdc = (struct wdc_softc *)self; 466 struct channel_softc *chp; 467 struct device *sc; 468 int s, i, j, error = 0; 469 470 s = splbio(); 471 switch (act) { 472 case DVACT_ACTIVATE: 473 error = EOPNOTSUPP; 474 break; 475 476 case DVACT_DEACTIVATE: 477 if (wdc->sc_dying != 0) 478 goto out; 479 for (i = 0; i < wdc->nchannels; i++) { 480 chp = wdc->channels[i]; 481 482 /* 483 * We might call deactivate routine for 484 * the children of atapibus twice (once via 485 * atapibus, once directly), but since 486 * config_deactivate maintains DVF_ACTIVE flag, 487 * it's safe. 488 */ 489 sc = chp->atapibus; 490 if (sc != NULL) { 491 error = config_deactivate(sc); 492 if (error != 0) 493 goto out; 494 } 495 496 for (j = 0; j < 2; j++) { 497 sc = chp->ch_drive[j].drv_softc; 498 WDCDEBUG_PRINT(("wdcactivate: %s:" 499 " deactivating %s\n", wdc->sc_dev.dv_xname, 500 sc == NULL ? "nodrv" : sc->dv_xname), 501 DEBUG_DETACH); 502 if (sc != NULL) { 503 error = config_deactivate(sc); 504 if (error != 0) 505 goto out; 506 } 507 } 508 } 509 wdc->sc_dying = 1; 510 break; 511 } 512 513 out: 514 splx(s); 515 516 #ifdef WDCDEBUG 517 if (error != 0) 518 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 519 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 520 #endif 521 return (error); 522 } 523 524 int 525 wdcdetach(self, flags) 526 struct device *self; 527 int flags; 528 { 529 struct wdc_softc *wdc = (struct wdc_softc *)self; 530 struct channel_softc *chp; 531 struct device *sc; 532 int i, j, error = 0; 533 534 for (i = 0; i < wdc->nchannels; i++) { 535 chp = wdc->channels[i]; 536 537 /* 538 * Detach atapibus and its children. 539 */ 540 sc = chp->atapibus; 541 if (sc != NULL) { 542 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 543 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 544 error = config_detach(sc, flags); 545 if (error != 0) 546 goto out; 547 } 548 549 /* 550 * Detach our other children. 551 */ 552 for (j = 0; j < 2; j++) { 553 sc = chp->ch_drive[j].drv_softc; 554 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 555 wdc->sc_dev.dv_xname, 556 sc == NULL ? "nodrv" : sc->dv_xname), 557 DEBUG_DETACH); 558 if (sc != NULL) { 559 error = config_detach(sc, flags); 560 if (error != 0) 561 goto out; 562 } 563 } 564 565 wdc_kill_pending(chp); 566 } 567 568 out: 569 #ifdef WDCDEBUG 570 if (error != 0) 571 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 572 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 573 #endif 574 return (error); 575 } 576 577 /* 578 * Start I/O on a controller, for the given channel. 579 * The first xfer may be not for our channel if the channel queues 580 * are shared. 581 */ 582 void 583 wdcstart(chp) 584 struct channel_softc *chp; 585 { 586 struct wdc_xfer *xfer; 587 588 #ifdef WDC_DIAGNOSTIC 589 int spl1, spl2; 590 591 spl1 = splbio(); 592 spl2 = splbio(); 593 if (spl2 != spl1) { 594 printf("wdcstart: not at splbio()\n"); 595 panic("wdcstart"); 596 } 597 splx(spl2); 598 splx(spl1); 599 #endif /* WDC_DIAGNOSTIC */ 600 601 /* is there a xfer ? */ 602 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 603 return; 604 605 /* adjust chp, in case we have a shared queue */ 606 chp = xfer->chp; 607 608 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 609 return; /* channel aleady active */ 610 } 611 #ifdef DIAGNOSTIC 612 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 613 panic("wdcstart: channel waiting for irq\n"); 614 #endif 615 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 616 if (!(*chp->wdc->claim_hw)(chp, 0)) 617 return; 618 619 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 620 chp->channel, xfer->drive), DEBUG_XFERS); 621 chp->ch_flags |= WDCF_ACTIVE; 622 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 623 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 624 chp->ch_drive[xfer->drive].state = 0; 625 } 626 xfer->c_start(chp, xfer); 627 } 628 629 /* restart an interrupted I/O */ 630 void 631 wdcrestart(v) 632 void *v; 633 { 634 struct channel_softc *chp = v; 635 int s; 636 637 s = splbio(); 638 wdcstart(chp); 639 splx(s); 640 } 641 642 643 /* 644 * Interrupt routine for the controller. Acknowledge the interrupt, check for 645 * errors on the current operation, mark it done if necessary, and start the 646 * next request. Also check for a partially done transfer, and continue with 647 * the next chunk if so. 648 */ 649 int 650 wdcintr(arg) 651 void *arg; 652 { 653 struct channel_softc *chp = arg; 654 struct wdc_xfer *xfer; 655 int ret; 656 657 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 658 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 659 return 0; 660 } 661 662 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 663 chp->ch_flags &= ~WDCF_IRQ_WAIT; 664 xfer = chp->ch_queue->sc_xfer.tqh_first; 665 ret = xfer->c_intr(chp, xfer, 1); 666 if (ret == 0) /* irq was not for us, still waiting for irq */ 667 chp->ch_flags |= WDCF_IRQ_WAIT; 668 return (ret); 669 } 670 671 /* Put all disk in RESET state */ 672 void wdc_reset_channel(drvp) 673 struct ata_drive_datas *drvp; 674 { 675 struct channel_softc *chp = drvp->chnl_softc; 676 int drive; 677 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 678 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 679 DEBUG_FUNCS); 680 (void) wdcreset(chp, VERBOSE); 681 for (drive = 0; drive < 2; drive++) { 682 chp->ch_drive[drive].state = 0; 683 } 684 } 685 686 int 687 wdcreset(chp, verb) 688 struct channel_softc *chp; 689 int verb; 690 { 691 int drv_mask1, drv_mask2; 692 693 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 694 WDSD_IBM); /* master */ 695 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 696 WDCTL_RST | WDCTL_IDS); 697 delay(1000); 698 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 699 WDCTL_IDS); 700 delay(1000); 701 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 702 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 703 WDCTL_4BIT); 704 705 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 706 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 707 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 708 if (verb && drv_mask2 != drv_mask1) { 709 printf("%s channel %d: reset failed for", 710 chp->wdc->sc_dev.dv_xname, chp->channel); 711 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 712 printf(" drive 0"); 713 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 714 printf(" drive 1"); 715 printf("\n"); 716 } 717 return (drv_mask1 != drv_mask2) ? 1 : 0; 718 } 719 720 static int 721 __wdcwait_reset(chp, drv_mask) 722 struct channel_softc *chp; 723 int drv_mask; 724 { 725 int timeout; 726 u_int8_t st0, st1; 727 #ifdef WDCDEBUG 728 u_int8_t sc0, sn0, cl0, ch0; 729 u_int8_t sc1, sn1, cl1, ch1; 730 #endif 731 /* wait for BSY to deassert */ 732 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 733 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 734 WDSD_IBM); /* master */ 735 delay(10); 736 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 737 #ifdef WDCDEBUG 738 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 739 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 740 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 741 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 742 #endif 743 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 744 WDSD_IBM | 0x10); /* slave */ 745 delay(10); 746 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 747 #ifdef WDCDEBUG 748 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 749 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 750 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 751 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 752 #endif 753 754 if ((drv_mask & 0x01) == 0) { 755 /* no master */ 756 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 757 /* No master, slave is ready, it's done */ 758 goto end; 759 } 760 } else if ((drv_mask & 0x02) == 0) { 761 /* no slave */ 762 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 763 /* No slave, master is ready, it's done */ 764 goto end; 765 } 766 } else { 767 /* Wait for both master and slave to be ready */ 768 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 769 goto end; 770 } 771 } 772 delay(WDCDELAY); 773 } 774 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 775 if (st0 & WDCS_BSY) 776 drv_mask &= ~0x01; 777 if (st1 & WDCS_BSY) 778 drv_mask &= ~0x02; 779 end: 780 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 781 "cl=0x%x ch=0x%x\n", 782 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 783 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 784 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 785 "cl=0x%x ch=0x%x\n", 786 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 787 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 788 789 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 790 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 791 st0, st1), DEBUG_PROBE); 792 793 return drv_mask; 794 } 795 796 /* 797 * Wait for a drive to be !BSY, and have mask in its status register. 798 * return -1 for a timeout after "timeout" ms. 799 */ 800 int 801 wdcwait(chp, mask, bits, timeout) 802 struct channel_softc *chp; 803 int mask, bits, timeout; 804 { 805 u_char status; 806 int time = 0; 807 #ifdef WDCNDELAY_DEBUG 808 extern int cold; 809 #endif 810 811 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 812 :"none", chp->channel), DEBUG_STATUS); 813 chp->ch_error = 0; 814 815 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 816 817 for (;;) { 818 chp->ch_status = status = 819 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 820 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 821 break; 822 if (++time > timeout) { 823 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 824 "error %x (mask 0x%x bits 0x%x)\n", status, 825 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 826 wd_error), mask, bits), 827 DEBUG_STATUS | DEBUG_PROBE); 828 return -1; 829 } 830 delay(WDCDELAY); 831 } 832 if (status & WDCS_ERR) 833 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 834 wd_error); 835 #ifdef WDCNDELAY_DEBUG 836 /* After autoconfig, there should be no long delays. */ 837 if (!cold && time > WDCNDELAY_DEBUG) { 838 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 839 if (xfer == NULL) 840 printf("%s channel %d: warning: busy-wait took %dus\n", 841 chp->wdc->sc_dev.dv_xname, chp->channel, 842 WDCDELAY * time); 843 else 844 printf("%s:%d:%d: warning: busy-wait took %dus\n", 845 chp->wdc->sc_dev.dv_xname, chp->channel, 846 xfer->drive, 847 WDCDELAY * time); 848 } 849 #endif 850 return 0; 851 } 852 853 void 854 wdctimeout(arg) 855 void *arg; 856 { 857 struct channel_softc *chp = (struct channel_softc *)arg; 858 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 859 int s; 860 861 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 862 863 s = splbio(); 864 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 865 __wdcerror(chp, "lost interrupt"); 866 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 867 "atapi":"ata"); 868 printf("\tc_bcount: %d\n", xfer->c_bcount); 869 printf("\tc_skip: %d\n", xfer->c_skip); 870 /* 871 * Call the interrupt routine. If we just missed and interrupt, 872 * it will do what's needed. Else, it will take the needed 873 * action (reset the device). 874 * Before that we need to reinstall the timeout callback, 875 * in case it will miss another irq while in this transfer 876 * We arbitray chose it to be 1s 877 */ 878 timeout(wdctimeout, chp, hz); 879 xfer->c_flags |= C_TIMEOU; 880 chp->ch_flags &= ~WDCF_IRQ_WAIT; 881 xfer->c_intr(chp, xfer, 1); 882 } else 883 __wdcerror(chp, "missing untimeout"); 884 splx(s); 885 } 886 887 /* 888 * Probe drive's capabilites, for use by the controller later 889 * Assumes drvp points to an existing drive. 890 * XXX this should be a controller-indep function 891 */ 892 void 893 wdc_probe_caps(drvp) 894 struct ata_drive_datas *drvp; 895 { 896 struct ataparams params, params2; 897 struct channel_softc *chp = drvp->chnl_softc; 898 struct device *drv_dev = drvp->drv_softc; 899 struct wdc_softc *wdc = chp->wdc; 900 int i, printed; 901 char *sep = ""; 902 int cf_flags; 903 904 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 905 /* IDENTIFY failed. Can't tell more about the device */ 906 return; 907 } 908 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 909 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 910 /* 911 * Controller claims 16 and 32 bit transfers. 912 * Re-do an IDENTIFY with 32-bit transfers, 913 * and compare results. 914 */ 915 drvp->drive_flags |= DRIVE_CAP32; 916 ata_get_params(drvp, AT_POLL, ¶ms2); 917 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 918 /* Not good. fall back to 16bits */ 919 drvp->drive_flags &= ~DRIVE_CAP32; 920 } else { 921 printf("%s: 32-bits data port", drv_dev->dv_xname); 922 } 923 } 924 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 925 if (params.atap_ata_major > 0x01 && 926 params.atap_ata_major != 0xffff) { 927 for (i = 14; i > 0; i--) { 928 if (params.atap_ata_major & (1 << i)) { 929 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 930 printf("%s: ", drv_dev->dv_xname); 931 else 932 printf(", "); 933 printf("ATA version %d\n", i); 934 drvp->ata_vers = i; 935 break; 936 } 937 } 938 } else 939 #endif 940 if (drvp->drive_flags & DRIVE_CAP32) 941 printf("\n"); 942 943 /* An ATAPI device is at last PIO mode 3 */ 944 if (drvp->drive_flags & DRIVE_ATAPI) 945 drvp->PIO_mode = 3; 946 947 /* 948 * It's not in the specs, but it seems that some drive 949 * returns 0xffff in atap_extensions when this field is invalid 950 */ 951 if (params.atap_extensions != 0xffff && 952 (params.atap_extensions & WDC_EXT_MODES)) { 953 printed = 0; 954 /* 955 * XXX some drives report something wrong here (they claim to 956 * support PIO mode 8 !). As mode is coded on 3 bits in 957 * SET FEATURE, limit it to 7 (so limit i to 4). 958 * If higther mode than 7 is found, abort. 959 */ 960 for (i = 7; i >= 0; i--) { 961 if ((params.atap_piomode_supp & (1 << i)) == 0) 962 continue; 963 if (i > 4) 964 return; 965 /* 966 * See if mode is accepted. 967 * If the controller can't set its PIO mode, 968 * assume the defaults are good, so don't try 969 * to set it 970 */ 971 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 972 if (ata_set_mode(drvp, 0x08 | (i + 3), 973 AT_POLL) != CMD_OK) 974 continue; 975 if (!printed) { 976 printf("%s: drive supports PIO mode %d", 977 drv_dev->dv_xname, i + 3); 978 sep = ","; 979 printed = 1; 980 } 981 /* 982 * If controller's driver can't set its PIO mode, 983 * get the highter one for the drive. 984 */ 985 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 986 wdc->PIO_cap >= i + 3) { 987 drvp->PIO_mode = i + 3; 988 drvp->PIO_cap = i + 3; 989 break; 990 } 991 } 992 if (!printed) { 993 /* 994 * We didn't find a valid PIO mode. 995 * Assume the values returned for DMA are buggy too 996 */ 997 return; 998 } 999 drvp->drive_flags |= DRIVE_MODE; 1000 printed = 0; 1001 for (i = 7; i >= 0; i--) { 1002 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1003 continue; 1004 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1005 (wdc->cap & WDC_CAPABILITY_MODE)) 1006 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1007 != CMD_OK) 1008 continue; 1009 if (!printed) { 1010 printf("%s DMA mode %d", sep, i); 1011 sep = ","; 1012 printed = 1; 1013 } 1014 if (wdc->cap & WDC_CAPABILITY_DMA) { 1015 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1016 wdc->DMA_cap < i) 1017 continue; 1018 drvp->DMA_mode = i; 1019 drvp->DMA_cap = i; 1020 drvp->drive_flags |= DRIVE_DMA; 1021 } 1022 break; 1023 } 1024 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1025 printed = 0; 1026 for (i = 7; i >= 0; i--) { 1027 if ((params.atap_udmamode_supp & (1 << i)) 1028 == 0) 1029 continue; 1030 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1031 (wdc->cap & WDC_CAPABILITY_UDMA)) 1032 if (ata_set_mode(drvp, 0x40 | i, 1033 AT_POLL) != CMD_OK) 1034 continue; 1035 if (!printed) { 1036 printf("%s Ultra-DMA mode %d", sep, i); 1037 sep = ","; 1038 printed = 1; 1039 } 1040 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1041 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1042 wdc->UDMA_cap < i) 1043 continue; 1044 drvp->UDMA_mode = i; 1045 drvp->UDMA_cap = i; 1046 drvp->drive_flags |= DRIVE_UDMA; 1047 } 1048 break; 1049 } 1050 } 1051 printf("\n"); 1052 } 1053 1054 /* Try to guess ATA version here, if it didn't get reported */ 1055 if (drvp->ata_vers == 0) { 1056 if (drvp->drive_flags & DRIVE_UDMA) 1057 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1058 else if (drvp->PIO_cap > 2) 1059 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1060 } 1061 cf_flags = drv_dev->dv_cfdata->cf_flags; 1062 if (cf_flags & ATA_CONFIG_PIO_SET) { 1063 drvp->PIO_mode = 1064 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1065 drvp->drive_flags |= DRIVE_MODE; 1066 } 1067 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1068 /* don't care about DMA modes */ 1069 return; 1070 } 1071 if (cf_flags & ATA_CONFIG_DMA_SET) { 1072 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1073 ATA_CONFIG_DMA_DISABLE) { 1074 drvp->drive_flags &= ~DRIVE_DMA; 1075 } else { 1076 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1077 ATA_CONFIG_DMA_OFF; 1078 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1079 } 1080 } 1081 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1082 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1083 ATA_CONFIG_UDMA_DISABLE) { 1084 drvp->drive_flags &= ~DRIVE_UDMA; 1085 } else { 1086 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1087 ATA_CONFIG_UDMA_OFF; 1088 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1089 } 1090 } 1091 } 1092 1093 /* 1094 * downgrade the transfer mode of a drive after an error. return 1 if 1095 * downgrade was possible, 0 otherwise. 1096 */ 1097 int 1098 wdc_downgrade_mode(drvp) 1099 struct ata_drive_datas *drvp; 1100 { 1101 struct channel_softc *chp = drvp->chnl_softc; 1102 struct device *drv_dev = drvp->drv_softc; 1103 struct wdc_softc *wdc = chp->wdc; 1104 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1105 1106 /* if drive or controller don't know its mode, we can't do much */ 1107 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1108 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1109 return 0; 1110 /* current drive mode was set by a config flag, let it this way */ 1111 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1112 (cf_flags & ATA_CONFIG_DMA_SET) || 1113 (cf_flags & ATA_CONFIG_UDMA_SET)) 1114 return 0; 1115 1116 /* 1117 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1118 * Maybe we didn't properly notice the cable type 1119 */ 1120 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 2) { 1121 drvp->UDMA_mode = 2; 1122 printf("%s: transfer error, downgrading to DMA mode %d\n", 1123 drv_dev->dv_xname, drvp->UDMA_mode); 1124 } 1125 1126 /* 1127 * If we were using ultra-DMA, don't downgrade to multiword DMA 1128 * if we noticed a CRC error. It has been noticed that CRC errors 1129 * in ultra-DMA lead to silent data corruption in multiword DMA. 1130 * Data corruption is less likely to occur in PIO mode. 1131 */ 1132 1133 else if ((drvp->drive_flags & DRIVE_UDMA) && 1134 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1135 drvp->drive_flags &= ~DRIVE_UDMA; 1136 drvp->drive_flags |= DRIVE_DMA; 1137 drvp->DMA_mode = drvp->DMA_cap; 1138 printf("%s: transfer error, downgrading to DMA mode %d\n", 1139 drv_dev->dv_xname, drvp->DMA_mode); 1140 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1141 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1142 drvp->PIO_mode = drvp->PIO_cap; 1143 printf("%s: transfer error, downgrading to PIO mode %d\n", 1144 drv_dev->dv_xname, drvp->PIO_mode); 1145 } else /* already using PIO, can't downgrade */ 1146 return 0; 1147 1148 wdc->set_modes(chp); 1149 /* reset the channel, which will shedule all drives for setup */ 1150 wdc_reset_channel(drvp); 1151 return 1; 1152 } 1153 1154 int 1155 wdc_exec_command(drvp, wdc_c) 1156 struct ata_drive_datas *drvp; 1157 struct wdc_command *wdc_c; 1158 { 1159 struct channel_softc *chp = drvp->chnl_softc; 1160 struct wdc_xfer *xfer; 1161 int s, ret; 1162 1163 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1164 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1165 DEBUG_FUNCS); 1166 1167 /* set up an xfer and queue. Wait for completion */ 1168 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1169 WDC_NOSLEEP); 1170 if (xfer == NULL) { 1171 return WDC_TRY_AGAIN; 1172 } 1173 1174 if (wdc_c->flags & AT_POLL) 1175 xfer->c_flags |= C_POLL; 1176 xfer->drive = drvp->drive; 1177 xfer->databuf = wdc_c->data; 1178 xfer->c_bcount = wdc_c->bcount; 1179 xfer->cmd = wdc_c; 1180 xfer->c_start = __wdccommand_start; 1181 xfer->c_intr = __wdccommand_intr; 1182 xfer->c_kill_xfer = __wdccommand_done; 1183 1184 s = splbio(); 1185 wdc_exec_xfer(chp, xfer); 1186 #ifdef DIAGNOSTIC 1187 if ((wdc_c->flags & AT_POLL) != 0 && 1188 (wdc_c->flags & AT_DONE) == 0) 1189 panic("wdc_exec_command: polled command not done\n"); 1190 #endif 1191 if (wdc_c->flags & AT_DONE) { 1192 ret = WDC_COMPLETE; 1193 } else { 1194 if (wdc_c->flags & AT_WAIT) { 1195 while ((wdc_c->flags & AT_DONE) == 0) { 1196 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1197 } 1198 ret = WDC_COMPLETE; 1199 } else { 1200 ret = WDC_QUEUED; 1201 } 1202 } 1203 splx(s); 1204 return ret; 1205 } 1206 1207 void 1208 __wdccommand_start(chp, xfer) 1209 struct channel_softc *chp; 1210 struct wdc_xfer *xfer; 1211 { 1212 int drive = xfer->drive; 1213 struct wdc_command *wdc_c = xfer->cmd; 1214 1215 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1216 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1217 DEBUG_FUNCS); 1218 1219 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1220 WDSD_IBM | (drive << 4)); 1221 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1222 wdc_c->timeout) != 0) { 1223 wdc_c->flags |= AT_TIMEOU; 1224 __wdccommand_done(chp, xfer); 1225 return; 1226 } 1227 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1228 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1229 if ((wdc_c->flags & AT_POLL) == 0) { 1230 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1231 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1232 return; 1233 } 1234 /* 1235 * Polled command. Wait for drive ready or drq. Done in intr(). 1236 * Wait for at last 400ns for status bit to be valid. 1237 */ 1238 delay(10); 1239 __wdccommand_intr(chp, xfer, 0); 1240 } 1241 1242 int 1243 __wdccommand_intr(chp, xfer, irq) 1244 struct channel_softc *chp; 1245 struct wdc_xfer *xfer; 1246 int irq; 1247 { 1248 struct wdc_command *wdc_c = xfer->cmd; 1249 int bcount = wdc_c->bcount; 1250 char *data = wdc_c->data; 1251 1252 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1253 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1254 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1255 (irq == 0) ? wdc_c->timeout : 0)) { 1256 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1257 return 0; /* IRQ was not for us */ 1258 wdc_c->flags |= AT_TIMEOU; 1259 __wdccommand_done(chp, xfer); 1260 return 1; 1261 } 1262 if (wdc_c->flags & AT_READ) { 1263 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1264 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1265 0, (u_int32_t*)data, bcount >> 2); 1266 data += bcount & 0xfffffffc; 1267 bcount = bcount & 0x03; 1268 } 1269 if (bcount > 0) 1270 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1271 wd_data, (u_int16_t *)data, bcount >> 1); 1272 } else if (wdc_c->flags & AT_WRITE) { 1273 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1274 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1275 0, (u_int32_t*)data, bcount >> 2); 1276 data += bcount & 0xfffffffc; 1277 bcount = bcount & 0x03; 1278 } 1279 if (bcount > 0) 1280 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1281 wd_data, (u_int16_t *)data, bcount >> 1); 1282 } 1283 __wdccommand_done(chp, xfer); 1284 return 1; 1285 } 1286 1287 void 1288 __wdccommand_done(chp, xfer) 1289 struct channel_softc *chp; 1290 struct wdc_xfer *xfer; 1291 { 1292 struct wdc_command *wdc_c = xfer->cmd; 1293 1294 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1295 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1296 1297 untimeout(wdctimeout, chp); 1298 1299 if (chp->ch_status & WDCS_DWF) 1300 wdc_c->flags |= AT_DF; 1301 if (chp->ch_status & WDCS_ERR) { 1302 wdc_c->flags |= AT_ERROR; 1303 wdc_c->r_error = chp->ch_error; 1304 } 1305 wdc_c->flags |= AT_DONE; 1306 if ((wdc_c->flags & AT_READREG) != 0 && chp->wdc->sc_dying != 0 && 1307 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1308 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1309 wd_sdh); 1310 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1311 wd_cyl_hi) << 8; 1312 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1313 wd_cyl_lo); 1314 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1315 wd_sector); 1316 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1317 wd_seccnt); 1318 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1319 wd_error); 1320 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1321 wd_precomp); 1322 } 1323 wdc_free_xfer(chp, xfer); 1324 if (wdc_c->flags & AT_WAIT) 1325 wakeup(wdc_c); 1326 else if (wdc_c->callback) 1327 wdc_c->callback(wdc_c->callback_arg); 1328 wdcstart(chp); 1329 return; 1330 } 1331 1332 /* 1333 * Send a command. The drive should be ready. 1334 * Assumes interrupts are blocked. 1335 */ 1336 void 1337 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1338 struct channel_softc *chp; 1339 u_int8_t drive; 1340 u_int8_t command; 1341 u_int16_t cylin; 1342 u_int8_t head, sector, count, precomp; 1343 { 1344 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1345 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1346 chp->channel, drive, command, cylin, head, sector, count, precomp), 1347 DEBUG_FUNCS); 1348 1349 /* Select drive, head, and addressing mode. */ 1350 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1351 WDSD_IBM | (drive << 4) | head); 1352 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1353 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1354 precomp); 1355 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1356 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1357 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1358 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1359 1360 /* Send command. */ 1361 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1362 return; 1363 } 1364 1365 /* 1366 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1367 * tested by the caller. 1368 */ 1369 void 1370 wdccommandshort(chp, drive, command) 1371 struct channel_softc *chp; 1372 int drive; 1373 int command; 1374 { 1375 1376 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1377 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1378 DEBUG_FUNCS); 1379 1380 /* Select drive. */ 1381 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1382 WDSD_IBM | (drive << 4)); 1383 1384 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1385 } 1386 1387 /* Add a command to the queue and start controller. Must be called at splbio */ 1388 1389 void 1390 wdc_exec_xfer(chp, xfer) 1391 struct channel_softc *chp; 1392 struct wdc_xfer *xfer; 1393 { 1394 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1395 chp->channel, xfer->drive), DEBUG_XFERS); 1396 1397 /* complete xfer setup */ 1398 xfer->chp = chp; 1399 1400 /* 1401 * If we are a polled command, and the list is not empty, 1402 * we are doing a dump. Drop the list to allow the polled command 1403 * to complete, we're going to reboot soon anyway. 1404 */ 1405 if ((xfer->c_flags & C_POLL) != 0 && 1406 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1407 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1408 } 1409 /* insert at the end of command list */ 1410 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1411 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1412 chp->ch_flags), DEBUG_XFERS); 1413 wdcstart(chp); 1414 } 1415 1416 struct wdc_xfer * 1417 wdc_get_xfer(flags) 1418 int flags; 1419 { 1420 struct wdc_xfer *xfer; 1421 int s; 1422 1423 s = splbio(); 1424 xfer = pool_get(&wdc_xfer_pool, 1425 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1426 splx(s); 1427 memset(xfer, 0, sizeof(struct wdc_xfer)); 1428 return xfer; 1429 } 1430 1431 void 1432 wdc_free_xfer(chp, xfer) 1433 struct channel_softc *chp; 1434 struct wdc_xfer *xfer; 1435 { 1436 struct wdc_softc *wdc = chp->wdc; 1437 int s; 1438 1439 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1440 (*wdc->free_hw)(chp); 1441 s = splbio(); 1442 chp->ch_flags &= ~WDCF_ACTIVE; 1443 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1444 pool_put(&wdc_xfer_pool, xfer); 1445 splx(s); 1446 } 1447 1448 /* 1449 * Kill off all pending xfers for a channel_softc. 1450 * 1451 * Must be called at splbio(). 1452 */ 1453 void 1454 wdc_kill_pending(chp) 1455 struct channel_softc *chp; 1456 { 1457 struct wdc_xfer *xfer; 1458 1459 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1460 chp = xfer->chp; 1461 (*xfer->c_kill_xfer)(chp, xfer); 1462 } 1463 } 1464 1465 static void 1466 __wdcerror(chp, msg) 1467 struct channel_softc *chp; 1468 char *msg; 1469 { 1470 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1471 if (xfer == NULL) 1472 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1473 msg); 1474 else 1475 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1476 chp->channel, xfer->drive, msg); 1477 } 1478 1479 /* 1480 * the bit bucket 1481 */ 1482 void 1483 wdcbit_bucket(chp, size) 1484 struct channel_softc *chp; 1485 int size; 1486 { 1487 1488 for (; size >= 2; size -= 2) 1489 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1490 if (size) 1491 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1492 } 1493 1494 int 1495 wdc_addref(chp) 1496 struct channel_softc *chp; 1497 { 1498 struct wdc_softc *wdc = chp->wdc; 1499 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1500 int s, error = 0; 1501 1502 s = splbio(); 1503 if (adapter->scsipi_refcnt++ == 0 && 1504 adapter->scsipi_enable != NULL) { 1505 error = (*adapter->scsipi_enable)(wdc, 1); 1506 if (error) 1507 adapter->scsipi_refcnt--; 1508 } 1509 splx(s); 1510 return (error); 1511 } 1512 1513 void 1514 wdc_delref(chp) 1515 struct channel_softc *chp; 1516 { 1517 struct wdc_softc *wdc = chp->wdc; 1518 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1519 int s; 1520 1521 s = splbio(); 1522 if (adapter->scsipi_refcnt-- == 1 && 1523 adapter->scsipi_enable != NULL) 1524 (void) (*adapter->scsipi_enable)(wdc, 0); 1525 splx(s); 1526 } 1527
Indexes created Tue Sep 23 23:09:58 GMT 2025