wdc.c revision 1.78
1 /* $NetBSD: wdc.c,v 1.78 2000/01/17 00:01:01 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 void wdc_kill_pending __P((struct channel_softc *)); 124 125 126 #define DEBUG_INTR 0x01 127 #define DEBUG_XFERS 0x02 128 #define DEBUG_STATUS 0x04 129 #define DEBUG_FUNCS 0x08 130 #define DEBUG_PROBE 0x10 131 #define DEBUG_DETACH 0x20 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc is supposted to be 0x1 for ATAPI but at last one drive 259 * set it to 0x0 - or maybe it's the controller. 260 */ 261 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 262 cl == 0x14 && ch == 0xeb) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 264 } else { 265 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 266 if (chp->wdc == NULL || 267 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 268 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 269 } 270 } 271 return (ret_value); 272 } 273 274 void 275 wdcattach(chp) 276 struct channel_softc *chp; 277 { 278 int channel_flags, ctrl_flags, i, error; 279 struct ata_atapi_attach aa_link; 280 struct ataparams params; 281 static int inited = 0; 282 283 if ((error = wdc_addref(chp)) != 0) { 284 printf("%s: unable to enable controller\n", 285 chp->wdc->sc_dev.dv_xname); 286 return; 287 } 288 289 if (wdcprobe(chp) == 0) 290 /* If no drives, abort attach here. */ 291 goto out; 292 293 /* initialise global data */ 294 if (inited == 0) { 295 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* 307 * Init error counter so that an error withing the first xfers 308 * will trigger a downgrade 309 */ 310 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 311 312 /* If controller can't do 16bit flag the drives as 32bit */ 313 if ((chp->wdc->cap & 314 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 315 WDC_CAPABILITY_DATA32) 316 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 317 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 318 continue; 319 320 /* Issue a IDENTIFY command, to try to detect slave ghost */ 321 ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 322 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 323 if (error == CMD_OK) { 324 /* If IDENTIFY succeded, this is not an OLD ctrl */ 325 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 326 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 327 } else { 328 chp->ch_drive[i].drive_flags &= 329 ~(DRIVE_ATA | DRIVE_ATAPI); 330 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 331 chp->wdc->sc_dev.dv_xname, 332 chp->channel, i, error), DEBUG_PROBE); 333 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 334 continue; 335 /* 336 * Pre-ATA drive ? 337 * Test registers writability (Error register not 338 * writable, but cyllo is), then try an ATA command. 339 */ 340 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 341 WDSD_IBM | (i << 4)); 342 delay(10); 343 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 344 wd_error, 0x58); 345 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 346 wd_cyl_lo, 0xa5); 347 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 348 wd_error == 0x58) || 349 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 350 wd_cyl_lo) != 0xa5) { 351 WDCDEBUG_PRINT(("%s:%d:%d: register " 352 "writability failed\n", 353 chp->wdc->sc_dev.dv_xname, 354 chp->channel, i), DEBUG_PROBE); 355 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 356 } 357 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 358 WDSD_IBM | (i << 4)); 359 delay(100); 360 if (wait_for_ready(chp, 10000) != 0) { 361 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 362 chp->wdc->sc_dev.dv_xname, 363 chp->channel, i), DEBUG_PROBE); 364 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 365 continue; 366 } 367 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 368 wd_command, WDCC_RECAL); 369 if (wait_for_ready(chp, 10000) != 0) { 370 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 371 chp->wdc->sc_dev.dv_xname, 372 chp->channel, i), DEBUG_PROBE); 373 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 374 } 375 } 376 } 377 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 378 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 379 380 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 381 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 382 DEBUG_PROBE); 383 384 /* If no drives, abort here */ 385 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 386 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 387 goto out; 388 389 /* 390 * Attach an ATAPI bus, if needed. 391 */ 392 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 393 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 394 #if NATAPIBUS > 0 395 wdc_atapibus_attach(chp); 396 #else 397 /* 398 * Fills in a fake aa_link and call config_found, so that 399 * the config machinery will print 400 * "atapibus at xxx not configured" 401 */ 402 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 403 aa_link.aa_type = T_ATAPI; 404 aa_link.aa_channel = chp->channel; 405 aa_link.aa_openings = 1; 406 aa_link.aa_drv_data = 0; 407 aa_link.aa_bus_private = NULL; 408 chp->atapibus = config_found(&chp->wdc->sc_dev, 409 (void *)&aa_link, atapi_print); 410 #endif 411 } 412 413 for (i = 0; i < 2; i++) { 414 if ((chp->ch_drive[i].drive_flags & 415 (DRIVE_ATA | DRIVE_OLD)) == 0) { 416 continue; 417 } 418 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 419 aa_link.aa_type = T_ATA; 420 aa_link.aa_channel = chp->channel; 421 aa_link.aa_openings = 1; 422 aa_link.aa_drv_data = &chp->ch_drive[i]; 423 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 424 wdc_probe_caps(&chp->ch_drive[i]); 425 } 426 427 /* 428 * reset drive_flags for unnatached devices, reset state for attached 429 * ones 430 */ 431 for (i = 0; i < 2; i++) { 432 if (chp->ch_drive[i].drv_softc == NULL) 433 chp->ch_drive[i].drive_flags = 0; 434 else 435 chp->ch_drive[i].state = 0; 436 } 437 438 /* 439 * Reset channel. The probe, with some combinations of ATA/ATAPI 440 * devices keep it in a mostly working, but strange state (with busy 441 * led on) 442 */ 443 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 444 wdcreset(chp, VERBOSE); 445 /* 446 * Read status registers to avoid spurious interrupts. 447 */ 448 for (i = 1; i >= 0; i--) { 449 if (chp->ch_drive[i].drive_flags & DRIVE) { 450 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 451 wd_sdh, WDSD_IBM | (i << 4)); 452 if (wait_for_unbusy(chp, 10000) < 0) 453 printf("%s:%d:%d: device busy\n", 454 chp->wdc->sc_dev.dv_xname, 455 chp->channel, i); 456 } 457 } 458 } 459 460 out: 461 wdc_delref(chp); 462 } 463 464 /* 465 * Call activate routine of underlying devices. 466 */ 467 int 468 wdcactivate(self, act) 469 struct device *self; 470 enum devact act; 471 { 472 struct wdc_softc *wdc = (struct wdc_softc *)self; 473 struct channel_softc *chp; 474 struct device *sc; 475 int s, i, j, error = 0; 476 477 s = splbio(); 478 switch (act) { 479 case DVACT_ACTIVATE: 480 error = EOPNOTSUPP; 481 break; 482 483 case DVACT_DEACTIVATE: 484 if (wdc->sc_dying != 0) 485 goto out; 486 for (i = 0; i < wdc->nchannels; i++) { 487 chp = wdc->channels[i]; 488 489 /* 490 * We might call deactivate routine for 491 * the children of atapibus twice (once via 492 * atapibus, once directly), but since 493 * config_deactivate maintains DVF_ACTIVE flag, 494 * it's safe. 495 */ 496 sc = chp->atapibus; 497 if (sc != NULL) { 498 error = config_deactivate(sc); 499 if (error != 0) 500 goto out; 501 } 502 503 for (j = 0; j < 2; j++) { 504 sc = chp->ch_drive[j].drv_softc; 505 WDCDEBUG_PRINT(("wdcactivate: %s:" 506 " deactivating %s\n", wdc->sc_dev.dv_xname, 507 sc == NULL ? "nodrv" : sc->dv_xname), 508 DEBUG_DETACH); 509 if (sc != NULL) { 510 error = config_deactivate(sc); 511 if (error != 0) 512 goto out; 513 } 514 } 515 } 516 wdc->sc_dying = 1; 517 break; 518 } 519 520 out: 521 splx(s); 522 523 #ifdef WDCDEBUG 524 if (error != 0) 525 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 526 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 527 #endif 528 return (error); 529 } 530 531 int 532 wdcdetach(self, flags) 533 struct device *self; 534 int flags; 535 { 536 struct wdc_softc *wdc = (struct wdc_softc *)self; 537 struct channel_softc *chp; 538 struct device *sc; 539 int i, j, error = 0; 540 541 for (i = 0; i < wdc->nchannels; i++) { 542 chp = wdc->channels[i]; 543 544 /* 545 * Detach atapibus and its children. 546 */ 547 sc = chp->atapibus; 548 if (sc != NULL) { 549 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 550 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 551 error = config_detach(sc, flags); 552 if (error != 0) 553 goto out; 554 } 555 556 /* 557 * Detach our other children. 558 */ 559 for (j = 0; j < 2; j++) { 560 sc = chp->ch_drive[j].drv_softc; 561 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 562 wdc->sc_dev.dv_xname, 563 sc == NULL ? "nodrv" : sc->dv_xname), 564 DEBUG_DETACH); 565 if (sc != NULL) { 566 error = config_detach(sc, flags); 567 if (error != 0) 568 goto out; 569 } 570 } 571 572 wdc_kill_pending(chp); 573 } 574 575 out: 576 #ifdef WDCDEBUG 577 if (error != 0) 578 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 579 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 580 #endif 581 return (error); 582 } 583 584 /* 585 * Start I/O on a controller, for the given channel. 586 * The first xfer may be not for our channel if the channel queues 587 * are shared. 588 */ 589 void 590 wdcstart(chp) 591 struct channel_softc *chp; 592 { 593 struct wdc_xfer *xfer; 594 595 #ifdef WDC_DIAGNOSTIC 596 int spl1, spl2; 597 598 spl1 = splbio(); 599 spl2 = splbio(); 600 if (spl2 != spl1) { 601 printf("wdcstart: not at splbio()\n"); 602 panic("wdcstart"); 603 } 604 splx(spl2); 605 splx(spl1); 606 #endif /* WDC_DIAGNOSTIC */ 607 608 /* is there a xfer ? */ 609 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 610 return; 611 612 /* adjust chp, in case we have a shared queue */ 613 chp = xfer->chp; 614 615 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 616 return; /* channel aleady active */ 617 } 618 #ifdef DIAGNOSTIC 619 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 620 panic("wdcstart: channel waiting for irq\n"); 621 #endif 622 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 623 if (!(*chp->wdc->claim_hw)(chp, 0)) 624 return; 625 626 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 627 chp->channel, xfer->drive), DEBUG_XFERS); 628 chp->ch_flags |= WDCF_ACTIVE; 629 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 630 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 631 chp->ch_drive[xfer->drive].state = 0; 632 } 633 xfer->c_start(chp, xfer); 634 } 635 636 /* restart an interrupted I/O */ 637 void 638 wdcrestart(v) 639 void *v; 640 { 641 struct channel_softc *chp = v; 642 int s; 643 644 s = splbio(); 645 wdcstart(chp); 646 splx(s); 647 } 648 649 650 /* 651 * Interrupt routine for the controller. Acknowledge the interrupt, check for 652 * errors on the current operation, mark it done if necessary, and start the 653 * next request. Also check for a partially done transfer, and continue with 654 * the next chunk if so. 655 */ 656 int 657 wdcintr(arg) 658 void *arg; 659 { 660 struct channel_softc *chp = arg; 661 struct wdc_xfer *xfer; 662 int ret; 663 664 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 665 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 666 return 0; 667 } 668 669 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 670 chp->ch_flags &= ~WDCF_IRQ_WAIT; 671 xfer = chp->ch_queue->sc_xfer.tqh_first; 672 ret = xfer->c_intr(chp, xfer, 1); 673 if (ret == 0) /* irq was not for us, still waiting for irq */ 674 chp->ch_flags |= WDCF_IRQ_WAIT; 675 return (ret); 676 } 677 678 /* Put all disk in RESET state */ 679 void wdc_reset_channel(drvp) 680 struct ata_drive_datas *drvp; 681 { 682 struct channel_softc *chp = drvp->chnl_softc; 683 int drive; 684 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 685 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 686 DEBUG_FUNCS); 687 (void) wdcreset(chp, VERBOSE); 688 for (drive = 0; drive < 2; drive++) { 689 chp->ch_drive[drive].state = 0; 690 } 691 } 692 693 int 694 wdcreset(chp, verb) 695 struct channel_softc *chp; 696 int verb; 697 { 698 int drv_mask1, drv_mask2; 699 700 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 701 WDSD_IBM); /* master */ 702 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 703 WDCTL_RST | WDCTL_IDS); 704 delay(1000); 705 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 706 WDCTL_IDS); 707 delay(1000); 708 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 709 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 710 WDCTL_4BIT); 711 712 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 713 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 714 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 715 if (verb && drv_mask2 != drv_mask1) { 716 printf("%s channel %d: reset failed for", 717 chp->wdc->sc_dev.dv_xname, chp->channel); 718 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 719 printf(" drive 0"); 720 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 721 printf(" drive 1"); 722 printf("\n"); 723 } 724 return (drv_mask1 != drv_mask2) ? 1 : 0; 725 } 726 727 static int 728 __wdcwait_reset(chp, drv_mask) 729 struct channel_softc *chp; 730 int drv_mask; 731 { 732 int timeout; 733 u_int8_t st0, st1; 734 #ifdef WDCDEBUG 735 u_int8_t sc0, sn0, cl0, ch0; 736 u_int8_t sc1, sn1, cl1, ch1; 737 #endif 738 /* wait for BSY to deassert */ 739 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 740 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 741 WDSD_IBM); /* master */ 742 delay(10); 743 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 744 #ifdef WDCDEBUG 745 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 746 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 747 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 748 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 749 #endif 750 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 751 WDSD_IBM | 0x10); /* slave */ 752 delay(10); 753 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 754 #ifdef WDCDEBUG 755 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 756 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 757 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 758 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 759 #endif 760 761 if ((drv_mask & 0x01) == 0) { 762 /* no master */ 763 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 764 /* No master, slave is ready, it's done */ 765 goto end; 766 } 767 } else if ((drv_mask & 0x02) == 0) { 768 /* no slave */ 769 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 770 /* No slave, master is ready, it's done */ 771 goto end; 772 } 773 } else { 774 /* Wait for both master and slave to be ready */ 775 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 776 goto end; 777 } 778 } 779 delay(WDCDELAY); 780 } 781 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 782 if (st0 & WDCS_BSY) 783 drv_mask &= ~0x01; 784 if (st1 & WDCS_BSY) 785 drv_mask &= ~0x02; 786 end: 787 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 788 "cl=0x%x ch=0x%x\n", 789 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 790 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 791 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 792 "cl=0x%x ch=0x%x\n", 793 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 794 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 795 796 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 797 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 798 st0, st1), DEBUG_PROBE); 799 800 return drv_mask; 801 } 802 803 /* 804 * Wait for a drive to be !BSY, and have mask in its status register. 805 * return -1 for a timeout after "timeout" ms. 806 */ 807 int 808 wdcwait(chp, mask, bits, timeout) 809 struct channel_softc *chp; 810 int mask, bits, timeout; 811 { 812 u_char status; 813 int time = 0; 814 #ifdef WDCNDELAY_DEBUG 815 extern int cold; 816 #endif 817 818 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 819 :"none", chp->channel), DEBUG_STATUS); 820 chp->ch_error = 0; 821 822 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 823 824 for (;;) { 825 chp->ch_status = status = 826 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 827 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 828 break; 829 if (++time > timeout) { 830 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 831 "error %x (mask 0x%x bits 0x%x)\n", status, 832 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 833 wd_error), mask, bits), 834 DEBUG_STATUS | DEBUG_PROBE); 835 return -1; 836 } 837 delay(WDCDELAY); 838 } 839 if (status & WDCS_ERR) 840 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 841 wd_error); 842 #ifdef WDCNDELAY_DEBUG 843 /* After autoconfig, there should be no long delays. */ 844 if (!cold && time > WDCNDELAY_DEBUG) { 845 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 846 if (xfer == NULL) 847 printf("%s channel %d: warning: busy-wait took %dus\n", 848 chp->wdc->sc_dev.dv_xname, chp->channel, 849 WDCDELAY * time); 850 else 851 printf("%s:%d:%d: warning: busy-wait took %dus\n", 852 chp->wdc->sc_dev.dv_xname, chp->channel, 853 xfer->drive, 854 WDCDELAY * time); 855 } 856 #endif 857 return 0; 858 } 859 860 void 861 wdctimeout(arg) 862 void *arg; 863 { 864 struct channel_softc *chp = (struct channel_softc *)arg; 865 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 866 int s; 867 868 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 869 870 s = splbio(); 871 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 872 __wdcerror(chp, "lost interrupt"); 873 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 874 "atapi":"ata"); 875 printf("\tc_bcount: %d\n", xfer->c_bcount); 876 printf("\tc_skip: %d\n", xfer->c_skip); 877 /* 878 * Call the interrupt routine. If we just missed and interrupt, 879 * it will do what's needed. Else, it will take the needed 880 * action (reset the device). 881 * Before that we need to reinstall the timeout callback, 882 * in case it will miss another irq while in this transfer 883 * We arbitray chose it to be 1s 884 */ 885 timeout(wdctimeout, chp, hz); 886 xfer->c_flags |= C_TIMEOU; 887 chp->ch_flags &= ~WDCF_IRQ_WAIT; 888 xfer->c_intr(chp, xfer, 1); 889 } else 890 __wdcerror(chp, "missing untimeout"); 891 splx(s); 892 } 893 894 /* 895 * Probe drive's capabilites, for use by the controller later 896 * Assumes drvp points to an existing drive. 897 * XXX this should be a controller-indep function 898 */ 899 void 900 wdc_probe_caps(drvp) 901 struct ata_drive_datas *drvp; 902 { 903 struct ataparams params, params2; 904 struct channel_softc *chp = drvp->chnl_softc; 905 struct device *drv_dev = drvp->drv_softc; 906 struct wdc_softc *wdc = chp->wdc; 907 int i, printed; 908 char *sep = ""; 909 int cf_flags; 910 911 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 912 /* IDENTIFY failed. Can't tell more about the device */ 913 return; 914 } 915 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 916 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 917 /* 918 * Controller claims 16 and 32 bit transfers. 919 * Re-do an IDENTIFY with 32-bit transfers, 920 * and compare results. 921 */ 922 drvp->drive_flags |= DRIVE_CAP32; 923 ata_get_params(drvp, AT_POLL, ¶ms2); 924 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 925 /* Not good. fall back to 16bits */ 926 drvp->drive_flags &= ~DRIVE_CAP32; 927 } else { 928 printf("%s: 32-bits data port", drv_dev->dv_xname); 929 } 930 } 931 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 932 if (params.atap_ata_major > 0x01 && 933 params.atap_ata_major != 0xffff) { 934 for (i = 14; i > 0; i--) { 935 if (params.atap_ata_major & (1 << i)) { 936 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 937 printf("%s: ", drv_dev->dv_xname); 938 else 939 printf(", "); 940 printf("ATA version %d\n", i); 941 drvp->ata_vers = i; 942 break; 943 } 944 } 945 } else 946 #endif 947 if (drvp->drive_flags & DRIVE_CAP32) 948 printf("\n"); 949 950 /* An ATAPI device is at last PIO mode 3 */ 951 if (drvp->drive_flags & DRIVE_ATAPI) 952 drvp->PIO_mode = 3; 953 954 /* 955 * It's not in the specs, but it seems that some drive 956 * returns 0xffff in atap_extensions when this field is invalid 957 */ 958 if (params.atap_extensions != 0xffff && 959 (params.atap_extensions & WDC_EXT_MODES)) { 960 printed = 0; 961 /* 962 * XXX some drives report something wrong here (they claim to 963 * support PIO mode 8 !). As mode is coded on 3 bits in 964 * SET FEATURE, limit it to 7 (so limit i to 4). 965 * If higther mode than 7 is found, abort. 966 */ 967 for (i = 7; i >= 0; i--) { 968 if ((params.atap_piomode_supp & (1 << i)) == 0) 969 continue; 970 if (i > 4) 971 return; 972 /* 973 * See if mode is accepted. 974 * If the controller can't set its PIO mode, 975 * assume the defaults are good, so don't try 976 * to set it 977 */ 978 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 979 if (ata_set_mode(drvp, 0x08 | (i + 3), 980 AT_POLL) != CMD_OK) 981 continue; 982 if (!printed) { 983 printf("%s: drive supports PIO mode %d", 984 drv_dev->dv_xname, i + 3); 985 sep = ","; 986 printed = 1; 987 } 988 /* 989 * If controller's driver can't set its PIO mode, 990 * get the highter one for the drive. 991 */ 992 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 993 wdc->PIO_cap >= i + 3) { 994 drvp->PIO_mode = i + 3; 995 drvp->PIO_cap = i + 3; 996 break; 997 } 998 } 999 if (!printed) { 1000 /* 1001 * We didn't find a valid PIO mode. 1002 * Assume the values returned for DMA are buggy too 1003 */ 1004 return; 1005 } 1006 drvp->drive_flags |= DRIVE_MODE; 1007 printed = 0; 1008 for (i = 7; i >= 0; i--) { 1009 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1010 continue; 1011 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1012 (wdc->cap & WDC_CAPABILITY_MODE)) 1013 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1014 != CMD_OK) 1015 continue; 1016 if (!printed) { 1017 printf("%s DMA mode %d", sep, i); 1018 sep = ","; 1019 printed = 1; 1020 } 1021 if (wdc->cap & WDC_CAPABILITY_DMA) { 1022 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1023 wdc->DMA_cap < i) 1024 continue; 1025 drvp->DMA_mode = i; 1026 drvp->DMA_cap = i; 1027 drvp->drive_flags |= DRIVE_DMA; 1028 } 1029 break; 1030 } 1031 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1032 printed = 0; 1033 for (i = 7; i >= 0; i--) { 1034 if ((params.atap_udmamode_supp & (1 << i)) 1035 == 0) 1036 continue; 1037 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1038 (wdc->cap & WDC_CAPABILITY_UDMA)) 1039 if (ata_set_mode(drvp, 0x40 | i, 1040 AT_POLL) != CMD_OK) 1041 continue; 1042 if (!printed) { 1043 printf("%s Ultra-DMA mode %d", sep, i); 1044 sep = ","; 1045 printed = 1; 1046 } 1047 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1048 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1049 wdc->UDMA_cap < i) 1050 continue; 1051 drvp->UDMA_mode = i; 1052 drvp->UDMA_cap = i; 1053 drvp->drive_flags |= DRIVE_UDMA; 1054 } 1055 break; 1056 } 1057 } 1058 printf("\n"); 1059 } 1060 1061 /* Try to guess ATA version here, if it didn't get reported */ 1062 if (drvp->ata_vers == 0) { 1063 if (drvp->drive_flags & DRIVE_UDMA) 1064 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1065 else if (drvp->PIO_cap > 2) 1066 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1067 } 1068 cf_flags = drv_dev->dv_cfdata->cf_flags; 1069 if (cf_flags & ATA_CONFIG_PIO_SET) { 1070 drvp->PIO_mode = 1071 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1072 drvp->drive_flags |= DRIVE_MODE; 1073 } 1074 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1075 /* don't care about DMA modes */ 1076 return; 1077 } 1078 if (cf_flags & ATA_CONFIG_DMA_SET) { 1079 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1080 ATA_CONFIG_DMA_DISABLE) { 1081 drvp->drive_flags &= ~DRIVE_DMA; 1082 } else { 1083 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1084 ATA_CONFIG_DMA_OFF; 1085 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1086 } 1087 } 1088 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1089 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1090 ATA_CONFIG_UDMA_DISABLE) { 1091 drvp->drive_flags &= ~DRIVE_UDMA; 1092 } else { 1093 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1094 ATA_CONFIG_UDMA_OFF; 1095 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1096 } 1097 } 1098 } 1099 1100 /* 1101 * downgrade the transfer mode of a drive after an error. return 1 if 1102 * downgrade was possible, 0 otherwise. 1103 */ 1104 int 1105 wdc_downgrade_mode(drvp) 1106 struct ata_drive_datas *drvp; 1107 { 1108 struct channel_softc *chp = drvp->chnl_softc; 1109 struct device *drv_dev = drvp->drv_softc; 1110 struct wdc_softc *wdc = chp->wdc; 1111 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1112 1113 /* if drive or controller don't know its mode, we can't do much */ 1114 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1115 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1116 return 0; 1117 /* current drive mode was set by a config flag, let it this way */ 1118 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1119 (cf_flags & ATA_CONFIG_DMA_SET) || 1120 (cf_flags & ATA_CONFIG_UDMA_SET)) 1121 return 0; 1122 1123 /* 1124 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1125 * Maybe we didn't properly notice the cable type 1126 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1127 * It helps in some cases. 1128 */ 1129 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1130 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1131 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1132 drv_dev->dv_xname, drvp->UDMA_mode); 1133 } 1134 1135 /* 1136 * If we were using ultra-DMA, don't downgrade to multiword DMA 1137 * if we noticed a CRC error. It has been noticed that CRC errors 1138 * in ultra-DMA lead to silent data corruption in multiword DMA. 1139 * Data corruption is less likely to occur in PIO mode. 1140 */ 1141 else if ((drvp->drive_flags & DRIVE_UDMA) && 1142 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1143 drvp->drive_flags &= ~DRIVE_UDMA; 1144 drvp->drive_flags |= DRIVE_DMA; 1145 drvp->DMA_mode = drvp->DMA_cap; 1146 printf("%s: transfer error, downgrading to DMA mode %d\n", 1147 drv_dev->dv_xname, drvp->DMA_mode); 1148 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1149 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1150 drvp->PIO_mode = drvp->PIO_cap; 1151 printf("%s: transfer error, downgrading to PIO mode %d\n", 1152 drv_dev->dv_xname, drvp->PIO_mode); 1153 } else /* already using PIO, can't downgrade */ 1154 return 0; 1155 1156 wdc->set_modes(chp); 1157 /* reset the channel, which will shedule all drives for setup */ 1158 wdc_reset_channel(drvp); 1159 return 1; 1160 } 1161 1162 int 1163 wdc_exec_command(drvp, wdc_c) 1164 struct ata_drive_datas *drvp; 1165 struct wdc_command *wdc_c; 1166 { 1167 struct channel_softc *chp = drvp->chnl_softc; 1168 struct wdc_xfer *xfer; 1169 int s, ret; 1170 1171 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1172 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1173 DEBUG_FUNCS); 1174 1175 /* set up an xfer and queue. Wait for completion */ 1176 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1177 WDC_NOSLEEP); 1178 if (xfer == NULL) { 1179 return WDC_TRY_AGAIN; 1180 } 1181 1182 if (wdc_c->flags & AT_POLL) 1183 xfer->c_flags |= C_POLL; 1184 xfer->drive = drvp->drive; 1185 xfer->databuf = wdc_c->data; 1186 xfer->c_bcount = wdc_c->bcount; 1187 xfer->cmd = wdc_c; 1188 xfer->c_start = __wdccommand_start; 1189 xfer->c_intr = __wdccommand_intr; 1190 xfer->c_kill_xfer = __wdccommand_done; 1191 1192 s = splbio(); 1193 wdc_exec_xfer(chp, xfer); 1194 #ifdef DIAGNOSTIC 1195 if ((wdc_c->flags & AT_POLL) != 0 && 1196 (wdc_c->flags & AT_DONE) == 0) 1197 panic("wdc_exec_command: polled command not done\n"); 1198 #endif 1199 if (wdc_c->flags & AT_DONE) { 1200 ret = WDC_COMPLETE; 1201 } else { 1202 if (wdc_c->flags & AT_WAIT) { 1203 while ((wdc_c->flags & AT_DONE) == 0) { 1204 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1205 } 1206 ret = WDC_COMPLETE; 1207 } else { 1208 ret = WDC_QUEUED; 1209 } 1210 } 1211 splx(s); 1212 return ret; 1213 } 1214 1215 void 1216 __wdccommand_start(chp, xfer) 1217 struct channel_softc *chp; 1218 struct wdc_xfer *xfer; 1219 { 1220 int drive = xfer->drive; 1221 struct wdc_command *wdc_c = xfer->cmd; 1222 1223 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1224 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1225 DEBUG_FUNCS); 1226 1227 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1228 WDSD_IBM | (drive << 4)); 1229 if (wdcwait(chp, wdc_c->r_st_bmask, wdc_c->r_st_bmask, 1230 wdc_c->timeout) != 0) { 1231 wdc_c->flags |= AT_TIMEOU; 1232 __wdccommand_done(chp, xfer); 1233 return; 1234 } 1235 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1236 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1237 if ((wdc_c->flags & AT_POLL) == 0) { 1238 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1239 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1240 return; 1241 } 1242 /* 1243 * Polled command. Wait for drive ready or drq. Done in intr(). 1244 * Wait for at last 400ns for status bit to be valid. 1245 */ 1246 delay(10); 1247 __wdccommand_intr(chp, xfer, 0); 1248 } 1249 1250 int 1251 __wdccommand_intr(chp, xfer, irq) 1252 struct channel_softc *chp; 1253 struct wdc_xfer *xfer; 1254 int irq; 1255 { 1256 struct wdc_command *wdc_c = xfer->cmd; 1257 int bcount = wdc_c->bcount; 1258 char *data = wdc_c->data; 1259 1260 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1261 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1262 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1263 (irq == 0) ? wdc_c->timeout : 0)) { 1264 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1265 return 0; /* IRQ was not for us */ 1266 wdc_c->flags |= AT_TIMEOU; 1267 __wdccommand_done(chp, xfer); 1268 return 1; 1269 } 1270 if (wdc_c->flags & AT_READ) { 1271 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1272 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1273 0, (u_int32_t*)data, bcount >> 2); 1274 data += bcount & 0xfffffffc; 1275 bcount = bcount & 0x03; 1276 } 1277 if (bcount > 0) 1278 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1279 wd_data, (u_int16_t *)data, bcount >> 1); 1280 } else if (wdc_c->flags & AT_WRITE) { 1281 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1282 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1283 0, (u_int32_t*)data, bcount >> 2); 1284 data += bcount & 0xfffffffc; 1285 bcount = bcount & 0x03; 1286 } 1287 if (bcount > 0) 1288 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1289 wd_data, (u_int16_t *)data, bcount >> 1); 1290 } 1291 __wdccommand_done(chp, xfer); 1292 return 1; 1293 } 1294 1295 void 1296 __wdccommand_done(chp, xfer) 1297 struct channel_softc *chp; 1298 struct wdc_xfer *xfer; 1299 { 1300 struct wdc_command *wdc_c = xfer->cmd; 1301 1302 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1303 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1304 1305 untimeout(wdctimeout, chp); 1306 1307 if (chp->ch_status & WDCS_DWF) 1308 wdc_c->flags |= AT_DF; 1309 if (chp->ch_status & WDCS_ERR) { 1310 wdc_c->flags |= AT_ERROR; 1311 wdc_c->r_error = chp->ch_error; 1312 } 1313 wdc_c->flags |= AT_DONE; 1314 if ((wdc_c->flags & AT_READREG) != 0 && chp->wdc->sc_dying != 0 && 1315 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1316 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1317 wd_sdh); 1318 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1319 wd_cyl_hi) << 8; 1320 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1321 wd_cyl_lo); 1322 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1323 wd_sector); 1324 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1325 wd_seccnt); 1326 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1327 wd_error); 1328 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1329 wd_precomp); 1330 } 1331 wdc_free_xfer(chp, xfer); 1332 if (wdc_c->flags & AT_WAIT) 1333 wakeup(wdc_c); 1334 else if (wdc_c->callback) 1335 wdc_c->callback(wdc_c->callback_arg); 1336 wdcstart(chp); 1337 return; 1338 } 1339 1340 /* 1341 * Send a command. The drive should be ready. 1342 * Assumes interrupts are blocked. 1343 */ 1344 void 1345 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1346 struct channel_softc *chp; 1347 u_int8_t drive; 1348 u_int8_t command; 1349 u_int16_t cylin; 1350 u_int8_t head, sector, count, precomp; 1351 { 1352 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1353 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1354 chp->channel, drive, command, cylin, head, sector, count, precomp), 1355 DEBUG_FUNCS); 1356 1357 /* Select drive, head, and addressing mode. */ 1358 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1359 WDSD_IBM | (drive << 4) | head); 1360 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1361 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1362 precomp); 1363 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1364 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1365 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1366 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1367 1368 /* Send command. */ 1369 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1370 return; 1371 } 1372 1373 /* 1374 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1375 * tested by the caller. 1376 */ 1377 void 1378 wdccommandshort(chp, drive, command) 1379 struct channel_softc *chp; 1380 int drive; 1381 int command; 1382 { 1383 1384 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1385 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1386 DEBUG_FUNCS); 1387 1388 /* Select drive. */ 1389 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1390 WDSD_IBM | (drive << 4)); 1391 1392 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1393 } 1394 1395 /* Add a command to the queue and start controller. Must be called at splbio */ 1396 1397 void 1398 wdc_exec_xfer(chp, xfer) 1399 struct channel_softc *chp; 1400 struct wdc_xfer *xfer; 1401 { 1402 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1403 chp->channel, xfer->drive), DEBUG_XFERS); 1404 1405 /* complete xfer setup */ 1406 xfer->chp = chp; 1407 1408 /* 1409 * If we are a polled command, and the list is not empty, 1410 * we are doing a dump. Drop the list to allow the polled command 1411 * to complete, we're going to reboot soon anyway. 1412 */ 1413 if ((xfer->c_flags & C_POLL) != 0 && 1414 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1415 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1416 } 1417 /* insert at the end of command list */ 1418 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1419 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1420 chp->ch_flags), DEBUG_XFERS); 1421 wdcstart(chp); 1422 } 1423 1424 struct wdc_xfer * 1425 wdc_get_xfer(flags) 1426 int flags; 1427 { 1428 struct wdc_xfer *xfer; 1429 int s; 1430 1431 s = splbio(); 1432 xfer = pool_get(&wdc_xfer_pool, 1433 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1434 splx(s); 1435 memset(xfer, 0, sizeof(struct wdc_xfer)); 1436 return xfer; 1437 } 1438 1439 void 1440 wdc_free_xfer(chp, xfer) 1441 struct channel_softc *chp; 1442 struct wdc_xfer *xfer; 1443 { 1444 struct wdc_softc *wdc = chp->wdc; 1445 int s; 1446 1447 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1448 (*wdc->free_hw)(chp); 1449 s = splbio(); 1450 chp->ch_flags &= ~WDCF_ACTIVE; 1451 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1452 pool_put(&wdc_xfer_pool, xfer); 1453 splx(s); 1454 } 1455 1456 /* 1457 * Kill off all pending xfers for a channel_softc. 1458 * 1459 * Must be called at splbio(). 1460 */ 1461 void 1462 wdc_kill_pending(chp) 1463 struct channel_softc *chp; 1464 { 1465 struct wdc_xfer *xfer; 1466 1467 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1468 chp = xfer->chp; 1469 (*xfer->c_kill_xfer)(chp, xfer); 1470 } 1471 } 1472 1473 static void 1474 __wdcerror(chp, msg) 1475 struct channel_softc *chp; 1476 char *msg; 1477 { 1478 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1479 if (xfer == NULL) 1480 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1481 msg); 1482 else 1483 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1484 chp->channel, xfer->drive, msg); 1485 } 1486 1487 /* 1488 * the bit bucket 1489 */ 1490 void 1491 wdcbit_bucket(chp, size) 1492 struct channel_softc *chp; 1493 int size; 1494 { 1495 1496 for (; size >= 2; size -= 2) 1497 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1498 if (size) 1499 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1500 } 1501 1502 int 1503 wdc_addref(chp) 1504 struct channel_softc *chp; 1505 { 1506 struct wdc_softc *wdc = chp->wdc; 1507 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1508 int s, error = 0; 1509 1510 s = splbio(); 1511 if (adapter->scsipi_refcnt++ == 0 && 1512 adapter->scsipi_enable != NULL) { 1513 error = (*adapter->scsipi_enable)(wdc, 1); 1514 if (error) 1515 adapter->scsipi_refcnt--; 1516 } 1517 splx(s); 1518 return (error); 1519 } 1520 1521 void 1522 wdc_delref(chp) 1523 struct channel_softc *chp; 1524 { 1525 struct wdc_softc *wdc = chp->wdc; 1526 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1527 int s; 1528 1529 s = splbio(); 1530 if (adapter->scsipi_refcnt-- == 1 && 1531 adapter->scsipi_enable != NULL) 1532 (void) (*adapter->scsipi_enable)(wdc, 0); 1533 splx(s); 1534 } 1535
Indexes created Wed Sep 24 05:09:52 GMT 2025