wdc.c revision 1.79
1 /* $NetBSD: wdc.c,v 1.79 2000/02/14 12:37:35 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 void wdc_kill_pending __P((struct channel_softc *)); 124 125 126 #define DEBUG_INTR 0x01 127 #define DEBUG_XFERS 0x02 128 #define DEBUG_STATUS 0x04 129 #define DEBUG_FUNCS 0x08 130 #define DEBUG_PROBE 0x10 131 #define DEBUG_DETACH 0x20 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc is supposted to be 0x1 for ATAPI but at last one drive 259 * set it to 0x0 - or maybe it's the controller. 260 */ 261 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 262 cl == 0x14 && ch == 0xeb) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 264 } else { 265 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 266 if (chp->wdc == NULL || 267 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 268 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 269 } 270 } 271 return (ret_value); 272 } 273 274 void 275 wdcattach(chp) 276 struct channel_softc *chp; 277 { 278 int channel_flags, ctrl_flags, i, error; 279 struct ata_atapi_attach aa_link; 280 struct ataparams params; 281 static int inited = 0; 282 283 if ((error = wdc_addref(chp)) != 0) { 284 printf("%s: unable to enable controller\n", 285 chp->wdc->sc_dev.dv_xname); 286 return; 287 } 288 289 if (wdcprobe(chp) == 0) 290 /* If no drives, abort attach here. */ 291 goto out; 292 293 /* initialise global data */ 294 if (inited == 0) { 295 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* 307 * Init error counter so that an error withing the first xfers 308 * will trigger a downgrade 309 */ 310 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 311 312 /* If controller can't do 16bit flag the drives as 32bit */ 313 if ((chp->wdc->cap & 314 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 315 WDC_CAPABILITY_DATA32) 316 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 317 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 318 continue; 319 320 /* 321 * Wait a bit, some devices are weird just after a reset. 322 * Then issue a IDENTIFY command, to try to detect slave ghost 323 */ 324 delay(100); 325 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 326 if (error == CMD_OK) { 327 /* If IDENTIFY succeded, this is not an OLD ctrl */ 328 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 329 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 330 } else { 331 chp->ch_drive[i].drive_flags &= 332 ~(DRIVE_ATA | DRIVE_ATAPI); 333 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 334 chp->wdc->sc_dev.dv_xname, 335 chp->channel, i, error), DEBUG_PROBE); 336 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 337 continue; 338 /* 339 * Pre-ATA drive ? 340 * Test registers writability (Error register not 341 * writable, but cyllo is), then try an ATA command. 342 */ 343 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 344 WDSD_IBM | (i << 4)); 345 delay(10); 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 347 wd_error, 0x58); 348 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 349 wd_cyl_lo, 0xa5); 350 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 351 wd_error == 0x58) || 352 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 353 wd_cyl_lo) != 0xa5) { 354 WDCDEBUG_PRINT(("%s:%d:%d: register " 355 "writability failed\n", 356 chp->wdc->sc_dev.dv_xname, 357 chp->channel, i), DEBUG_PROBE); 358 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 359 } 360 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 361 WDSD_IBM | (i << 4)); 362 delay(100); 363 if (wait_for_ready(chp, 10000) != 0) { 364 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 365 chp->wdc->sc_dev.dv_xname, 366 chp->channel, i), DEBUG_PROBE); 367 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 368 continue; 369 } 370 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 371 wd_command, WDCC_RECAL); 372 if (wait_for_ready(chp, 10000) != 0) { 373 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 374 chp->wdc->sc_dev.dv_xname, 375 chp->channel, i), DEBUG_PROBE); 376 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 377 } 378 } 379 } 380 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 381 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 382 383 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 384 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 385 DEBUG_PROBE); 386 387 /* If no drives, abort here */ 388 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 389 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 390 goto out; 391 392 /* 393 * Attach an ATAPI bus, if needed. 394 */ 395 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 396 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 397 #if NATAPIBUS > 0 398 wdc_atapibus_attach(chp); 399 #else 400 /* 401 * Fills in a fake aa_link and call config_found, so that 402 * the config machinery will print 403 * "atapibus at xxx not configured" 404 */ 405 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 406 aa_link.aa_type = T_ATAPI; 407 aa_link.aa_channel = chp->channel; 408 aa_link.aa_openings = 1; 409 aa_link.aa_drv_data = 0; 410 aa_link.aa_bus_private = NULL; 411 chp->atapibus = config_found(&chp->wdc->sc_dev, 412 (void *)&aa_link, atapi_print); 413 #endif 414 } 415 416 for (i = 0; i < 2; i++) { 417 if ((chp->ch_drive[i].drive_flags & 418 (DRIVE_ATA | DRIVE_OLD)) == 0) { 419 continue; 420 } 421 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 422 aa_link.aa_type = T_ATA; 423 aa_link.aa_channel = chp->channel; 424 aa_link.aa_openings = 1; 425 aa_link.aa_drv_data = &chp->ch_drive[i]; 426 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 427 wdc_probe_caps(&chp->ch_drive[i]); 428 } 429 430 /* 431 * reset drive_flags for unnatached devices, reset state for attached 432 * ones 433 */ 434 for (i = 0; i < 2; i++) { 435 if (chp->ch_drive[i].drv_softc == NULL) 436 chp->ch_drive[i].drive_flags = 0; 437 else 438 chp->ch_drive[i].state = 0; 439 } 440 441 /* 442 * Reset channel. The probe, with some combinations of ATA/ATAPI 443 * devices keep it in a mostly working, but strange state (with busy 444 * led on) 445 */ 446 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 447 wdcreset(chp, VERBOSE); 448 /* 449 * Read status registers to avoid spurious interrupts. 450 */ 451 for (i = 1; i >= 0; i--) { 452 if (chp->ch_drive[i].drive_flags & DRIVE) { 453 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 454 wd_sdh, WDSD_IBM | (i << 4)); 455 if (wait_for_unbusy(chp, 10000) < 0) 456 printf("%s:%d:%d: device busy\n", 457 chp->wdc->sc_dev.dv_xname, 458 chp->channel, i); 459 } 460 } 461 } 462 463 out: 464 wdc_delref(chp); 465 } 466 467 /* 468 * Call activate routine of underlying devices. 469 */ 470 int 471 wdcactivate(self, act) 472 struct device *self; 473 enum devact act; 474 { 475 struct wdc_softc *wdc = (struct wdc_softc *)self; 476 struct channel_softc *chp; 477 struct device *sc; 478 int s, i, j, error = 0; 479 480 s = splbio(); 481 switch (act) { 482 case DVACT_ACTIVATE: 483 error = EOPNOTSUPP; 484 break; 485 486 case DVACT_DEACTIVATE: 487 if (wdc->sc_dying != 0) 488 goto out; 489 for (i = 0; i < wdc->nchannels; i++) { 490 chp = wdc->channels[i]; 491 492 /* 493 * We might call deactivate routine for 494 * the children of atapibus twice (once via 495 * atapibus, once directly), but since 496 * config_deactivate maintains DVF_ACTIVE flag, 497 * it's safe. 498 */ 499 sc = chp->atapibus; 500 if (sc != NULL) { 501 error = config_deactivate(sc); 502 if (error != 0) 503 goto out; 504 } 505 506 for (j = 0; j < 2; j++) { 507 sc = chp->ch_drive[j].drv_softc; 508 WDCDEBUG_PRINT(("wdcactivate: %s:" 509 " deactivating %s\n", wdc->sc_dev.dv_xname, 510 sc == NULL ? "nodrv" : sc->dv_xname), 511 DEBUG_DETACH); 512 if (sc != NULL) { 513 error = config_deactivate(sc); 514 if (error != 0) 515 goto out; 516 } 517 } 518 } 519 wdc->sc_dying = 1; 520 break; 521 } 522 523 out: 524 splx(s); 525 526 #ifdef WDCDEBUG 527 if (error != 0) 528 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 529 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 530 #endif 531 return (error); 532 } 533 534 int 535 wdcdetach(self, flags) 536 struct device *self; 537 int flags; 538 { 539 struct wdc_softc *wdc = (struct wdc_softc *)self; 540 struct channel_softc *chp; 541 struct device *sc; 542 int i, j, error = 0; 543 544 for (i = 0; i < wdc->nchannels; i++) { 545 chp = wdc->channels[i]; 546 547 /* 548 * Detach atapibus and its children. 549 */ 550 sc = chp->atapibus; 551 if (sc != NULL) { 552 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 553 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 554 error = config_detach(sc, flags); 555 if (error != 0) 556 goto out; 557 } 558 559 /* 560 * Detach our other children. 561 */ 562 for (j = 0; j < 2; j++) { 563 sc = chp->ch_drive[j].drv_softc; 564 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 565 wdc->sc_dev.dv_xname, 566 sc == NULL ? "nodrv" : sc->dv_xname), 567 DEBUG_DETACH); 568 if (sc != NULL) { 569 error = config_detach(sc, flags); 570 if (error != 0) 571 goto out; 572 } 573 } 574 575 wdc_kill_pending(chp); 576 } 577 578 out: 579 #ifdef WDCDEBUG 580 if (error != 0) 581 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 582 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 583 #endif 584 return (error); 585 } 586 587 /* 588 * Start I/O on a controller, for the given channel. 589 * The first xfer may be not for our channel if the channel queues 590 * are shared. 591 */ 592 void 593 wdcstart(chp) 594 struct channel_softc *chp; 595 { 596 struct wdc_xfer *xfer; 597 598 #ifdef WDC_DIAGNOSTIC 599 int spl1, spl2; 600 601 spl1 = splbio(); 602 spl2 = splbio(); 603 if (spl2 != spl1) { 604 printf("wdcstart: not at splbio()\n"); 605 panic("wdcstart"); 606 } 607 splx(spl2); 608 splx(spl1); 609 #endif /* WDC_DIAGNOSTIC */ 610 611 /* is there a xfer ? */ 612 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 613 return; 614 615 /* adjust chp, in case we have a shared queue */ 616 chp = xfer->chp; 617 618 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 619 return; /* channel aleady active */ 620 } 621 #ifdef DIAGNOSTIC 622 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 623 panic("wdcstart: channel waiting for irq\n"); 624 #endif 625 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 626 if (!(*chp->wdc->claim_hw)(chp, 0)) 627 return; 628 629 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 630 chp->channel, xfer->drive), DEBUG_XFERS); 631 chp->ch_flags |= WDCF_ACTIVE; 632 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 633 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 634 chp->ch_drive[xfer->drive].state = 0; 635 } 636 xfer->c_start(chp, xfer); 637 } 638 639 /* restart an interrupted I/O */ 640 void 641 wdcrestart(v) 642 void *v; 643 { 644 struct channel_softc *chp = v; 645 int s; 646 647 s = splbio(); 648 wdcstart(chp); 649 splx(s); 650 } 651 652 653 /* 654 * Interrupt routine for the controller. Acknowledge the interrupt, check for 655 * errors on the current operation, mark it done if necessary, and start the 656 * next request. Also check for a partially done transfer, and continue with 657 * the next chunk if so. 658 */ 659 int 660 wdcintr(arg) 661 void *arg; 662 { 663 struct channel_softc *chp = arg; 664 struct wdc_xfer *xfer; 665 int ret; 666 667 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 668 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 669 return 0; 670 } 671 672 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 673 chp->ch_flags &= ~WDCF_IRQ_WAIT; 674 xfer = chp->ch_queue->sc_xfer.tqh_first; 675 ret = xfer->c_intr(chp, xfer, 1); 676 if (ret == 0) /* irq was not for us, still waiting for irq */ 677 chp->ch_flags |= WDCF_IRQ_WAIT; 678 return (ret); 679 } 680 681 /* Put all disk in RESET state */ 682 void wdc_reset_channel(drvp) 683 struct ata_drive_datas *drvp; 684 { 685 struct channel_softc *chp = drvp->chnl_softc; 686 int drive; 687 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 688 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 689 DEBUG_FUNCS); 690 (void) wdcreset(chp, VERBOSE); 691 for (drive = 0; drive < 2; drive++) { 692 chp->ch_drive[drive].state = 0; 693 } 694 } 695 696 int 697 wdcreset(chp, verb) 698 struct channel_softc *chp; 699 int verb; 700 { 701 int drv_mask1, drv_mask2; 702 703 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 704 WDSD_IBM); /* master */ 705 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 706 WDCTL_RST | WDCTL_IDS); 707 delay(1000); 708 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 709 WDCTL_IDS); 710 delay(1000); 711 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 712 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 713 WDCTL_4BIT); 714 715 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 716 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 717 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 718 if (verb && drv_mask2 != drv_mask1) { 719 printf("%s channel %d: reset failed for", 720 chp->wdc->sc_dev.dv_xname, chp->channel); 721 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 722 printf(" drive 0"); 723 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 724 printf(" drive 1"); 725 printf("\n"); 726 } 727 return (drv_mask1 != drv_mask2) ? 1 : 0; 728 } 729 730 static int 731 __wdcwait_reset(chp, drv_mask) 732 struct channel_softc *chp; 733 int drv_mask; 734 { 735 int timeout; 736 u_int8_t st0, st1; 737 #ifdef WDCDEBUG 738 u_int8_t sc0, sn0, cl0, ch0; 739 u_int8_t sc1, sn1, cl1, ch1; 740 #endif 741 /* wait for BSY to deassert */ 742 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 743 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 744 WDSD_IBM); /* master */ 745 delay(10); 746 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 747 #ifdef WDCDEBUG 748 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 749 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 750 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 751 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 752 #endif 753 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 754 WDSD_IBM | 0x10); /* slave */ 755 delay(10); 756 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 757 #ifdef WDCDEBUG 758 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 759 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 760 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 761 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 762 #endif 763 764 if ((drv_mask & 0x01) == 0) { 765 /* no master */ 766 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 767 /* No master, slave is ready, it's done */ 768 goto end; 769 } 770 } else if ((drv_mask & 0x02) == 0) { 771 /* no slave */ 772 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 773 /* No slave, master is ready, it's done */ 774 goto end; 775 } 776 } else { 777 /* Wait for both master and slave to be ready */ 778 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 779 goto end; 780 } 781 } 782 delay(WDCDELAY); 783 } 784 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 785 if (st0 & WDCS_BSY) 786 drv_mask &= ~0x01; 787 if (st1 & WDCS_BSY) 788 drv_mask &= ~0x02; 789 end: 790 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 791 "cl=0x%x ch=0x%x\n", 792 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 793 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 794 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 795 "cl=0x%x ch=0x%x\n", 796 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 797 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 798 799 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 800 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 801 st0, st1), DEBUG_PROBE); 802 803 return drv_mask; 804 } 805 806 /* 807 * Wait for a drive to be !BSY, and have mask in its status register. 808 * return -1 for a timeout after "timeout" ms. 809 */ 810 int 811 wdcwait(chp, mask, bits, timeout) 812 struct channel_softc *chp; 813 int mask, bits, timeout; 814 { 815 u_char status; 816 int time = 0; 817 #ifdef WDCNDELAY_DEBUG 818 extern int cold; 819 #endif 820 821 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 822 :"none", chp->channel), DEBUG_STATUS); 823 chp->ch_error = 0; 824 825 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 826 827 for (;;) { 828 chp->ch_status = status = 829 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 830 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 831 break; 832 if (++time > timeout) { 833 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 834 "error %x (mask 0x%x bits 0x%x)\n", status, 835 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 836 wd_error), mask, bits), 837 DEBUG_STATUS | DEBUG_PROBE); 838 return -1; 839 } 840 delay(WDCDELAY); 841 } 842 if (status & WDCS_ERR) 843 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 844 wd_error); 845 #ifdef WDCNDELAY_DEBUG 846 /* After autoconfig, there should be no long delays. */ 847 if (!cold && time > WDCNDELAY_DEBUG) { 848 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 849 if (xfer == NULL) 850 printf("%s channel %d: warning: busy-wait took %dus\n", 851 chp->wdc->sc_dev.dv_xname, chp->channel, 852 WDCDELAY * time); 853 else 854 printf("%s:%d:%d: warning: busy-wait took %dus\n", 855 chp->wdc->sc_dev.dv_xname, chp->channel, 856 xfer->drive, 857 WDCDELAY * time); 858 } 859 #endif 860 return 0; 861 } 862 863 void 864 wdctimeout(arg) 865 void *arg; 866 { 867 struct channel_softc *chp = (struct channel_softc *)arg; 868 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 869 int s; 870 871 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 872 873 s = splbio(); 874 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 875 __wdcerror(chp, "lost interrupt"); 876 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 877 "atapi":"ata"); 878 printf("\tc_bcount: %d\n", xfer->c_bcount); 879 printf("\tc_skip: %d\n", xfer->c_skip); 880 /* 881 * Call the interrupt routine. If we just missed and interrupt, 882 * it will do what's needed. Else, it will take the needed 883 * action (reset the device). 884 * Before that we need to reinstall the timeout callback, 885 * in case it will miss another irq while in this transfer 886 * We arbitray chose it to be 1s 887 */ 888 timeout(wdctimeout, chp, hz); 889 xfer->c_flags |= C_TIMEOU; 890 chp->ch_flags &= ~WDCF_IRQ_WAIT; 891 xfer->c_intr(chp, xfer, 1); 892 } else 893 __wdcerror(chp, "missing untimeout"); 894 splx(s); 895 } 896 897 /* 898 * Probe drive's capabilites, for use by the controller later 899 * Assumes drvp points to an existing drive. 900 * XXX this should be a controller-indep function 901 */ 902 void 903 wdc_probe_caps(drvp) 904 struct ata_drive_datas *drvp; 905 { 906 struct ataparams params, params2; 907 struct channel_softc *chp = drvp->chnl_softc; 908 struct device *drv_dev = drvp->drv_softc; 909 struct wdc_softc *wdc = chp->wdc; 910 int i, printed; 911 char *sep = ""; 912 int cf_flags; 913 914 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 915 /* IDENTIFY failed. Can't tell more about the device */ 916 return; 917 } 918 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 919 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 920 /* 921 * Controller claims 16 and 32 bit transfers. 922 * Re-do an IDENTIFY with 32-bit transfers, 923 * and compare results. 924 */ 925 drvp->drive_flags |= DRIVE_CAP32; 926 ata_get_params(drvp, AT_POLL, ¶ms2); 927 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 928 /* Not good. fall back to 16bits */ 929 drvp->drive_flags &= ~DRIVE_CAP32; 930 } else { 931 printf("%s: 32-bits data port", drv_dev->dv_xname); 932 } 933 } 934 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 935 if (params.atap_ata_major > 0x01 && 936 params.atap_ata_major != 0xffff) { 937 for (i = 14; i > 0; i--) { 938 if (params.atap_ata_major & (1 << i)) { 939 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 940 printf("%s: ", drv_dev->dv_xname); 941 else 942 printf(", "); 943 printf("ATA version %d\n", i); 944 drvp->ata_vers = i; 945 break; 946 } 947 } 948 } else 949 #endif 950 if (drvp->drive_flags & DRIVE_CAP32) 951 printf("\n"); 952 953 /* An ATAPI device is at last PIO mode 3 */ 954 if (drvp->drive_flags & DRIVE_ATAPI) 955 drvp->PIO_mode = 3; 956 957 /* 958 * It's not in the specs, but it seems that some drive 959 * returns 0xffff in atap_extensions when this field is invalid 960 */ 961 if (params.atap_extensions != 0xffff && 962 (params.atap_extensions & WDC_EXT_MODES)) { 963 printed = 0; 964 /* 965 * XXX some drives report something wrong here (they claim to 966 * support PIO mode 8 !). As mode is coded on 3 bits in 967 * SET FEATURE, limit it to 7 (so limit i to 4). 968 * If higther mode than 7 is found, abort. 969 */ 970 for (i = 7; i >= 0; i--) { 971 if ((params.atap_piomode_supp & (1 << i)) == 0) 972 continue; 973 if (i > 4) 974 return; 975 /* 976 * See if mode is accepted. 977 * If the controller can't set its PIO mode, 978 * assume the defaults are good, so don't try 979 * to set it 980 */ 981 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 982 if (ata_set_mode(drvp, 0x08 | (i + 3), 983 AT_POLL) != CMD_OK) 984 continue; 985 if (!printed) { 986 printf("%s: drive supports PIO mode %d", 987 drv_dev->dv_xname, i + 3); 988 sep = ","; 989 printed = 1; 990 } 991 /* 992 * If controller's driver can't set its PIO mode, 993 * get the highter one for the drive. 994 */ 995 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 996 wdc->PIO_cap >= i + 3) { 997 drvp->PIO_mode = i + 3; 998 drvp->PIO_cap = i + 3; 999 break; 1000 } 1001 } 1002 if (!printed) { 1003 /* 1004 * We didn't find a valid PIO mode. 1005 * Assume the values returned for DMA are buggy too 1006 */ 1007 return; 1008 } 1009 drvp->drive_flags |= DRIVE_MODE; 1010 printed = 0; 1011 for (i = 7; i >= 0; i--) { 1012 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1013 continue; 1014 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1015 (wdc->cap & WDC_CAPABILITY_MODE)) 1016 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1017 != CMD_OK) 1018 continue; 1019 if (!printed) { 1020 printf("%s DMA mode %d", sep, i); 1021 sep = ","; 1022 printed = 1; 1023 } 1024 if (wdc->cap & WDC_CAPABILITY_DMA) { 1025 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1026 wdc->DMA_cap < i) 1027 continue; 1028 drvp->DMA_mode = i; 1029 drvp->DMA_cap = i; 1030 drvp->drive_flags |= DRIVE_DMA; 1031 } 1032 break; 1033 } 1034 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1035 printed = 0; 1036 for (i = 7; i >= 0; i--) { 1037 if ((params.atap_udmamode_supp & (1 << i)) 1038 == 0) 1039 continue; 1040 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1041 (wdc->cap & WDC_CAPABILITY_UDMA)) 1042 if (ata_set_mode(drvp, 0x40 | i, 1043 AT_POLL) != CMD_OK) 1044 continue; 1045 if (!printed) { 1046 printf("%s Ultra-DMA mode %d", sep, i); 1047 sep = ","; 1048 printed = 1; 1049 } 1050 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1051 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1052 wdc->UDMA_cap < i) 1053 continue; 1054 drvp->UDMA_mode = i; 1055 drvp->UDMA_cap = i; 1056 drvp->drive_flags |= DRIVE_UDMA; 1057 } 1058 break; 1059 } 1060 } 1061 printf("\n"); 1062 } 1063 1064 /* Try to guess ATA version here, if it didn't get reported */ 1065 if (drvp->ata_vers == 0) { 1066 if (drvp->drive_flags & DRIVE_UDMA) 1067 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1068 else if (drvp->PIO_cap > 2) 1069 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1070 } 1071 cf_flags = drv_dev->dv_cfdata->cf_flags; 1072 if (cf_flags & ATA_CONFIG_PIO_SET) { 1073 drvp->PIO_mode = 1074 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1075 drvp->drive_flags |= DRIVE_MODE; 1076 } 1077 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1078 /* don't care about DMA modes */ 1079 return; 1080 } 1081 if (cf_flags & ATA_CONFIG_DMA_SET) { 1082 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1083 ATA_CONFIG_DMA_DISABLE) { 1084 drvp->drive_flags &= ~DRIVE_DMA; 1085 } else { 1086 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1087 ATA_CONFIG_DMA_OFF; 1088 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1089 } 1090 } 1091 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1092 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1093 ATA_CONFIG_UDMA_DISABLE) { 1094 drvp->drive_flags &= ~DRIVE_UDMA; 1095 } else { 1096 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1097 ATA_CONFIG_UDMA_OFF; 1098 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1099 } 1100 } 1101 } 1102 1103 /* 1104 * downgrade the transfer mode of a drive after an error. return 1 if 1105 * downgrade was possible, 0 otherwise. 1106 */ 1107 int 1108 wdc_downgrade_mode(drvp) 1109 struct ata_drive_datas *drvp; 1110 { 1111 struct channel_softc *chp = drvp->chnl_softc; 1112 struct device *drv_dev = drvp->drv_softc; 1113 struct wdc_softc *wdc = chp->wdc; 1114 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1115 1116 /* if drive or controller don't know its mode, we can't do much */ 1117 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1118 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1119 return 0; 1120 /* current drive mode was set by a config flag, let it this way */ 1121 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1122 (cf_flags & ATA_CONFIG_DMA_SET) || 1123 (cf_flags & ATA_CONFIG_UDMA_SET)) 1124 return 0; 1125 1126 /* 1127 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1128 * Maybe we didn't properly notice the cable type 1129 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1130 * It helps in some cases. 1131 */ 1132 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1133 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1134 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1135 drv_dev->dv_xname, drvp->UDMA_mode); 1136 } 1137 1138 /* 1139 * If we were using ultra-DMA, don't downgrade to multiword DMA 1140 * if we noticed a CRC error. It has been noticed that CRC errors 1141 * in ultra-DMA lead to silent data corruption in multiword DMA. 1142 * Data corruption is less likely to occur in PIO mode. 1143 */ 1144 else if ((drvp->drive_flags & DRIVE_UDMA) && 1145 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1146 drvp->drive_flags &= ~DRIVE_UDMA; 1147 drvp->drive_flags |= DRIVE_DMA; 1148 drvp->DMA_mode = drvp->DMA_cap; 1149 printf("%s: transfer error, downgrading to DMA mode %d\n", 1150 drv_dev->dv_xname, drvp->DMA_mode); 1151 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1152 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1153 drvp->PIO_mode = drvp->PIO_cap; 1154 printf("%s: transfer error, downgrading to PIO mode %d\n", 1155 drv_dev->dv_xname, drvp->PIO_mode); 1156 } else /* already using PIO, can't downgrade */ 1157 return 0; 1158 1159 wdc->set_modes(chp); 1160 /* reset the channel, which will shedule all drives for setup */ 1161 wdc_reset_channel(drvp); 1162 return 1; 1163 } 1164 1165 int 1166 wdc_exec_command(drvp, wdc_c) 1167 struct ata_drive_datas *drvp; 1168 struct wdc_command *wdc_c; 1169 { 1170 struct channel_softc *chp = drvp->chnl_softc; 1171 struct wdc_xfer *xfer; 1172 int s, ret; 1173 1174 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1175 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1176 DEBUG_FUNCS); 1177 1178 /* set up an xfer and queue. Wait for completion */ 1179 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1180 WDC_NOSLEEP); 1181 if (xfer == NULL) { 1182 return WDC_TRY_AGAIN; 1183 } 1184 1185 if (wdc_c->flags & AT_POLL) 1186 xfer->c_flags |= C_POLL; 1187 xfer->drive = drvp->drive; 1188 xfer->databuf = wdc_c->data; 1189 xfer->c_bcount = wdc_c->bcount; 1190 xfer->cmd = wdc_c; 1191 xfer->c_start = __wdccommand_start; 1192 xfer->c_intr = __wdccommand_intr; 1193 xfer->c_kill_xfer = __wdccommand_done; 1194 1195 s = splbio(); 1196 wdc_exec_xfer(chp, xfer); 1197 #ifdef DIAGNOSTIC 1198 if ((wdc_c->flags & AT_POLL) != 0 && 1199 (wdc_c->flags & AT_DONE) == 0) 1200 panic("wdc_exec_command: polled command not done\n"); 1201 #endif 1202 if (wdc_c->flags & AT_DONE) { 1203 ret = WDC_COMPLETE; 1204 } else { 1205 if (wdc_c->flags & AT_WAIT) { 1206 while ((wdc_c->flags & AT_DONE) == 0) { 1207 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1208 } 1209 ret = WDC_COMPLETE; 1210 } else { 1211 ret = WDC_QUEUED; 1212 } 1213 } 1214 splx(s); 1215 return ret; 1216 } 1217 1218 void 1219 __wdccommand_start(chp, xfer) 1220 struct channel_softc *chp; 1221 struct wdc_xfer *xfer; 1222 { 1223 int drive = xfer->drive; 1224 struct wdc_command *wdc_c = xfer->cmd; 1225 1226 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1227 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1228 DEBUG_FUNCS); 1229 1230 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1231 WDSD_IBM | (drive << 4)); 1232 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1233 wdc_c->timeout) != 0) { 1234 wdc_c->flags |= AT_TIMEOU; 1235 __wdccommand_done(chp, xfer); 1236 return; 1237 } 1238 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1239 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1240 if ((wdc_c->flags & AT_POLL) == 0) { 1241 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1242 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1243 return; 1244 } 1245 /* 1246 * Polled command. Wait for drive ready or drq. Done in intr(). 1247 * Wait for at last 400ns for status bit to be valid. 1248 */ 1249 delay(10); 1250 __wdccommand_intr(chp, xfer, 0); 1251 } 1252 1253 int 1254 __wdccommand_intr(chp, xfer, irq) 1255 struct channel_softc *chp; 1256 struct wdc_xfer *xfer; 1257 int irq; 1258 { 1259 struct wdc_command *wdc_c = xfer->cmd; 1260 int bcount = wdc_c->bcount; 1261 char *data = wdc_c->data; 1262 1263 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1264 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1265 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1266 (irq == 0) ? wdc_c->timeout : 0)) { 1267 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1268 return 0; /* IRQ was not for us */ 1269 wdc_c->flags |= AT_TIMEOU; 1270 __wdccommand_done(chp, xfer); 1271 return 1; 1272 } 1273 if (wdc_c->flags & AT_READ) { 1274 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1275 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1276 0, (u_int32_t*)data, bcount >> 2); 1277 data += bcount & 0xfffffffc; 1278 bcount = bcount & 0x03; 1279 } 1280 if (bcount > 0) 1281 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1282 wd_data, (u_int16_t *)data, bcount >> 1); 1283 } else if (wdc_c->flags & AT_WRITE) { 1284 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1285 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1286 0, (u_int32_t*)data, bcount >> 2); 1287 data += bcount & 0xfffffffc; 1288 bcount = bcount & 0x03; 1289 } 1290 if (bcount > 0) 1291 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1292 wd_data, (u_int16_t *)data, bcount >> 1); 1293 } 1294 __wdccommand_done(chp, xfer); 1295 return 1; 1296 } 1297 1298 void 1299 __wdccommand_done(chp, xfer) 1300 struct channel_softc *chp; 1301 struct wdc_xfer *xfer; 1302 { 1303 struct wdc_command *wdc_c = xfer->cmd; 1304 1305 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1306 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1307 1308 untimeout(wdctimeout, chp); 1309 1310 if (chp->ch_status & WDCS_DWF) 1311 wdc_c->flags |= AT_DF; 1312 if (chp->ch_status & WDCS_ERR) { 1313 wdc_c->flags |= AT_ERROR; 1314 wdc_c->r_error = chp->ch_error; 1315 } 1316 wdc_c->flags |= AT_DONE; 1317 if ((wdc_c->flags & AT_READREG) != 0 && chp->wdc->sc_dying != 0 && 1318 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1319 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1320 wd_sdh); 1321 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1322 wd_cyl_hi) << 8; 1323 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1324 wd_cyl_lo); 1325 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1326 wd_sector); 1327 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1328 wd_seccnt); 1329 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1330 wd_error); 1331 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1332 wd_precomp); 1333 } 1334 wdc_free_xfer(chp, xfer); 1335 if (wdc_c->flags & AT_WAIT) 1336 wakeup(wdc_c); 1337 else if (wdc_c->callback) 1338 wdc_c->callback(wdc_c->callback_arg); 1339 wdcstart(chp); 1340 return; 1341 } 1342 1343 /* 1344 * Send a command. The drive should be ready. 1345 * Assumes interrupts are blocked. 1346 */ 1347 void 1348 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1349 struct channel_softc *chp; 1350 u_int8_t drive; 1351 u_int8_t command; 1352 u_int16_t cylin; 1353 u_int8_t head, sector, count, precomp; 1354 { 1355 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1356 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1357 chp->channel, drive, command, cylin, head, sector, count, precomp), 1358 DEBUG_FUNCS); 1359 1360 /* Select drive, head, and addressing mode. */ 1361 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1362 WDSD_IBM | (drive << 4) | head); 1363 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1364 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1365 precomp); 1366 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1367 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1368 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1369 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1370 1371 /* Send command. */ 1372 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1373 return; 1374 } 1375 1376 /* 1377 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1378 * tested by the caller. 1379 */ 1380 void 1381 wdccommandshort(chp, drive, command) 1382 struct channel_softc *chp; 1383 int drive; 1384 int command; 1385 { 1386 1387 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1388 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1389 DEBUG_FUNCS); 1390 1391 /* Select drive. */ 1392 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1393 WDSD_IBM | (drive << 4)); 1394 1395 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1396 } 1397 1398 /* Add a command to the queue and start controller. Must be called at splbio */ 1399 1400 void 1401 wdc_exec_xfer(chp, xfer) 1402 struct channel_softc *chp; 1403 struct wdc_xfer *xfer; 1404 { 1405 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1406 chp->channel, xfer->drive), DEBUG_XFERS); 1407 1408 /* complete xfer setup */ 1409 xfer->chp = chp; 1410 1411 /* 1412 * If we are a polled command, and the list is not empty, 1413 * we are doing a dump. Drop the list to allow the polled command 1414 * to complete, we're going to reboot soon anyway. 1415 */ 1416 if ((xfer->c_flags & C_POLL) != 0 && 1417 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1418 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1419 } 1420 /* insert at the end of command list */ 1421 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1422 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1423 chp->ch_flags), DEBUG_XFERS); 1424 wdcstart(chp); 1425 } 1426 1427 struct wdc_xfer * 1428 wdc_get_xfer(flags) 1429 int flags; 1430 { 1431 struct wdc_xfer *xfer; 1432 int s; 1433 1434 s = splbio(); 1435 xfer = pool_get(&wdc_xfer_pool, 1436 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1437 splx(s); 1438 memset(xfer, 0, sizeof(struct wdc_xfer)); 1439 return xfer; 1440 } 1441 1442 void 1443 wdc_free_xfer(chp, xfer) 1444 struct channel_softc *chp; 1445 struct wdc_xfer *xfer; 1446 { 1447 struct wdc_softc *wdc = chp->wdc; 1448 int s; 1449 1450 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1451 (*wdc->free_hw)(chp); 1452 s = splbio(); 1453 chp->ch_flags &= ~WDCF_ACTIVE; 1454 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1455 pool_put(&wdc_xfer_pool, xfer); 1456 splx(s); 1457 } 1458 1459 /* 1460 * Kill off all pending xfers for a channel_softc. 1461 * 1462 * Must be called at splbio(). 1463 */ 1464 void 1465 wdc_kill_pending(chp) 1466 struct channel_softc *chp; 1467 { 1468 struct wdc_xfer *xfer; 1469 1470 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1471 chp = xfer->chp; 1472 (*xfer->c_kill_xfer)(chp, xfer); 1473 } 1474 } 1475 1476 static void 1477 __wdcerror(chp, msg) 1478 struct channel_softc *chp; 1479 char *msg; 1480 { 1481 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1482 if (xfer == NULL) 1483 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1484 msg); 1485 else 1486 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1487 chp->channel, xfer->drive, msg); 1488 } 1489 1490 /* 1491 * the bit bucket 1492 */ 1493 void 1494 wdcbit_bucket(chp, size) 1495 struct channel_softc *chp; 1496 int size; 1497 { 1498 1499 for (; size >= 2; size -= 2) 1500 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1501 if (size) 1502 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1503 } 1504 1505 int 1506 wdc_addref(chp) 1507 struct channel_softc *chp; 1508 { 1509 struct wdc_softc *wdc = chp->wdc; 1510 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1511 int s, error = 0; 1512 1513 s = splbio(); 1514 if (adapter->scsipi_refcnt++ == 0 && 1515 adapter->scsipi_enable != NULL) { 1516 error = (*adapter->scsipi_enable)(wdc, 1); 1517 if (error) 1518 adapter->scsipi_refcnt--; 1519 } 1520 splx(s); 1521 return (error); 1522 } 1523 1524 void 1525 wdc_delref(chp) 1526 struct channel_softc *chp; 1527 { 1528 struct wdc_softc *wdc = chp->wdc; 1529 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1530 int s; 1531 1532 s = splbio(); 1533 if (adapter->scsipi_refcnt-- == 1 && 1534 adapter->scsipi_enable != NULL) 1535 (void) (*adapter->scsipi_enable)(wdc, 0); 1536 splx(s); 1537 } 1538
Indexes created Tue Sep 23 21:09:50 GMT 2025