wdc.c revision 1.80
1 /* $NetBSD: wdc.c,v 1.80 2000/03/20 22:53:36 enami Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 void wdc_kill_pending __P((struct channel_softc *)); 124 125 126 #define DEBUG_INTR 0x01 127 #define DEBUG_XFERS 0x02 128 #define DEBUG_STATUS 0x04 129 #define DEBUG_FUNCS 0x08 130 #define DEBUG_PROBE 0x10 131 #define DEBUG_DETACH 0x20 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc is supposted to be 0x1 for ATAPI but at last one drive 259 * set it to 0x0 - or maybe it's the controller. 260 */ 261 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 262 cl == 0x14 && ch == 0xeb) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 264 } else { 265 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 266 if (chp->wdc == NULL || 267 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 268 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 269 } 270 } 271 return (ret_value); 272 } 273 274 void 275 wdcattach(chp) 276 struct channel_softc *chp; 277 { 278 int channel_flags, ctrl_flags, i, error; 279 struct ata_atapi_attach aa_link; 280 struct ataparams params; 281 static int inited = 0; 282 283 if ((error = wdc_addref(chp)) != 0) { 284 printf("%s: unable to enable controller\n", 285 chp->wdc->sc_dev.dv_xname); 286 return; 287 } 288 289 if (wdcprobe(chp) == 0) 290 /* If no drives, abort attach here. */ 291 goto out; 292 293 /* initialise global data */ 294 if (inited == 0) { 295 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* 307 * Init error counter so that an error withing the first xfers 308 * will trigger a downgrade 309 */ 310 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 311 312 /* If controller can't do 16bit flag the drives as 32bit */ 313 if ((chp->wdc->cap & 314 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 315 WDC_CAPABILITY_DATA32) 316 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 317 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 318 continue; 319 320 /* 321 * Wait a bit, some devices are weird just after a reset. 322 * Then issue a IDENTIFY command, to try to detect slave ghost 323 */ 324 delay(100); 325 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 326 if (error == CMD_OK) { 327 /* If IDENTIFY succeded, this is not an OLD ctrl */ 328 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 329 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 330 } else { 331 chp->ch_drive[i].drive_flags &= 332 ~(DRIVE_ATA | DRIVE_ATAPI); 333 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 334 chp->wdc->sc_dev.dv_xname, 335 chp->channel, i, error), DEBUG_PROBE); 336 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 337 continue; 338 /* 339 * Pre-ATA drive ? 340 * Test registers writability (Error register not 341 * writable, but cyllo is), then try an ATA command. 342 */ 343 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 344 WDSD_IBM | (i << 4)); 345 delay(10); 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 347 wd_error, 0x58); 348 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 349 wd_cyl_lo, 0xa5); 350 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 351 wd_error == 0x58) || 352 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 353 wd_cyl_lo) != 0xa5) { 354 WDCDEBUG_PRINT(("%s:%d:%d: register " 355 "writability failed\n", 356 chp->wdc->sc_dev.dv_xname, 357 chp->channel, i), DEBUG_PROBE); 358 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 359 } 360 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 361 WDSD_IBM | (i << 4)); 362 delay(100); 363 if (wait_for_ready(chp, 10000) != 0) { 364 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 365 chp->wdc->sc_dev.dv_xname, 366 chp->channel, i), DEBUG_PROBE); 367 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 368 continue; 369 } 370 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 371 wd_command, WDCC_RECAL); 372 if (wait_for_ready(chp, 10000) != 0) { 373 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 374 chp->wdc->sc_dev.dv_xname, 375 chp->channel, i), DEBUG_PROBE); 376 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 377 } 378 } 379 } 380 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 381 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 382 383 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 384 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 385 DEBUG_PROBE); 386 387 /* If no drives, abort here */ 388 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 389 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 390 goto out; 391 392 /* 393 * Attach an ATAPI bus, if needed. 394 */ 395 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 396 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 397 #if NATAPIBUS > 0 398 wdc_atapibus_attach(chp); 399 #else 400 /* 401 * Fills in a fake aa_link and call config_found, so that 402 * the config machinery will print 403 * "atapibus at xxx not configured" 404 */ 405 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 406 aa_link.aa_type = T_ATAPI; 407 aa_link.aa_channel = chp->channel; 408 aa_link.aa_openings = 1; 409 aa_link.aa_drv_data = 0; 410 aa_link.aa_bus_private = NULL; 411 chp->atapibus = config_found(&chp->wdc->sc_dev, 412 (void *)&aa_link, atapi_print); 413 #endif 414 } 415 416 for (i = 0; i < 2; i++) { 417 if ((chp->ch_drive[i].drive_flags & 418 (DRIVE_ATA | DRIVE_OLD)) == 0) { 419 continue; 420 } 421 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 422 aa_link.aa_type = T_ATA; 423 aa_link.aa_channel = chp->channel; 424 aa_link.aa_openings = 1; 425 aa_link.aa_drv_data = &chp->ch_drive[i]; 426 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 427 wdc_probe_caps(&chp->ch_drive[i]); 428 } 429 430 /* 431 * reset drive_flags for unnatached devices, reset state for attached 432 * ones 433 */ 434 for (i = 0; i < 2; i++) { 435 if (chp->ch_drive[i].drv_softc == NULL) 436 chp->ch_drive[i].drive_flags = 0; 437 else 438 chp->ch_drive[i].state = 0; 439 } 440 441 /* 442 * Reset channel. The probe, with some combinations of ATA/ATAPI 443 * devices keep it in a mostly working, but strange state (with busy 444 * led on) 445 */ 446 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 447 wdcreset(chp, VERBOSE); 448 /* 449 * Read status registers to avoid spurious interrupts. 450 */ 451 for (i = 1; i >= 0; i--) { 452 if (chp->ch_drive[i].drive_flags & DRIVE) { 453 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 454 wd_sdh, WDSD_IBM | (i << 4)); 455 if (wait_for_unbusy(chp, 10000) < 0) 456 printf("%s:%d:%d: device busy\n", 457 chp->wdc->sc_dev.dv_xname, 458 chp->channel, i); 459 } 460 } 461 } 462 463 out: 464 wdc_delref(chp); 465 } 466 467 /* 468 * Call activate routine of underlying devices. 469 */ 470 int 471 wdcactivate(self, act) 472 struct device *self; 473 enum devact act; 474 { 475 struct wdc_softc *wdc = (struct wdc_softc *)self; 476 struct channel_softc *chp; 477 struct device *sc; 478 int s, i, j, error = 0; 479 480 s = splbio(); 481 switch (act) { 482 case DVACT_ACTIVATE: 483 error = EOPNOTSUPP; 484 break; 485 486 case DVACT_DEACTIVATE: 487 for (i = 0; i < wdc->nchannels; i++) { 488 chp = wdc->channels[i]; 489 490 /* 491 * We might call deactivate routine for 492 * the children of atapibus twice (once via 493 * atapibus, once directly), but since 494 * config_deactivate maintains DVF_ACTIVE flag, 495 * it's safe. 496 */ 497 sc = chp->atapibus; 498 if (sc != NULL) { 499 error = config_deactivate(sc); 500 if (error != 0) 501 goto out; 502 } 503 504 for (j = 0; j < 2; j++) { 505 sc = chp->ch_drive[j].drv_softc; 506 WDCDEBUG_PRINT(("wdcactivate: %s:" 507 " deactivating %s\n", wdc->sc_dev.dv_xname, 508 sc == NULL ? "nodrv" : sc->dv_xname), 509 DEBUG_DETACH); 510 if (sc != NULL) { 511 error = config_deactivate(sc); 512 if (error != 0) 513 goto out; 514 } 515 } 516 } 517 break; 518 } 519 520 out: 521 splx(s); 522 523 #ifdef WDCDEBUG 524 if (error != 0) 525 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 526 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 527 #endif 528 return (error); 529 } 530 531 int 532 wdcdetach(self, flags) 533 struct device *self; 534 int flags; 535 { 536 struct wdc_softc *wdc = (struct wdc_softc *)self; 537 struct channel_softc *chp; 538 struct device *sc; 539 int i, j, error = 0; 540 541 for (i = 0; i < wdc->nchannels; i++) { 542 chp = wdc->channels[i]; 543 544 /* 545 * Detach atapibus and its children. 546 */ 547 sc = chp->atapibus; 548 if (sc != NULL) { 549 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 550 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 551 error = config_detach(sc, flags); 552 if (error != 0) 553 goto out; 554 } 555 556 /* 557 * Detach our other children. 558 */ 559 for (j = 0; j < 2; j++) { 560 sc = chp->ch_drive[j].drv_softc; 561 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 562 wdc->sc_dev.dv_xname, 563 sc == NULL ? "nodrv" : sc->dv_xname), 564 DEBUG_DETACH); 565 if (sc != NULL) { 566 error = config_detach(sc, flags); 567 if (error != 0) 568 goto out; 569 } 570 } 571 572 wdc_kill_pending(chp); 573 } 574 575 out: 576 #ifdef WDCDEBUG 577 if (error != 0) 578 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 579 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 580 #endif 581 return (error); 582 } 583 584 /* 585 * Start I/O on a controller, for the given channel. 586 * The first xfer may be not for our channel if the channel queues 587 * are shared. 588 */ 589 void 590 wdcstart(chp) 591 struct channel_softc *chp; 592 { 593 struct wdc_xfer *xfer; 594 595 #ifdef WDC_DIAGNOSTIC 596 int spl1, spl2; 597 598 spl1 = splbio(); 599 spl2 = splbio(); 600 if (spl2 != spl1) { 601 printf("wdcstart: not at splbio()\n"); 602 panic("wdcstart"); 603 } 604 splx(spl2); 605 splx(spl1); 606 #endif /* WDC_DIAGNOSTIC */ 607 608 /* is there a xfer ? */ 609 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 610 return; 611 612 /* adjust chp, in case we have a shared queue */ 613 chp = xfer->chp; 614 615 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 616 return; /* channel aleady active */ 617 } 618 #ifdef DIAGNOSTIC 619 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 620 panic("wdcstart: channel waiting for irq\n"); 621 #endif 622 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 623 if (!(*chp->wdc->claim_hw)(chp, 0)) 624 return; 625 626 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 627 chp->channel, xfer->drive), DEBUG_XFERS); 628 chp->ch_flags |= WDCF_ACTIVE; 629 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 630 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 631 chp->ch_drive[xfer->drive].state = 0; 632 } 633 xfer->c_start(chp, xfer); 634 } 635 636 /* restart an interrupted I/O */ 637 void 638 wdcrestart(v) 639 void *v; 640 { 641 struct channel_softc *chp = v; 642 int s; 643 644 s = splbio(); 645 wdcstart(chp); 646 splx(s); 647 } 648 649 650 /* 651 * Interrupt routine for the controller. Acknowledge the interrupt, check for 652 * errors on the current operation, mark it done if necessary, and start the 653 * next request. Also check for a partially done transfer, and continue with 654 * the next chunk if so. 655 */ 656 int 657 wdcintr(arg) 658 void *arg; 659 { 660 struct channel_softc *chp = arg; 661 struct wdc_xfer *xfer; 662 int ret; 663 664 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 665 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 666 DEBUG_INTR); 667 return (0); 668 } 669 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 670 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 671 return (0); 672 } 673 674 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 675 chp->ch_flags &= ~WDCF_IRQ_WAIT; 676 xfer = chp->ch_queue->sc_xfer.tqh_first; 677 ret = xfer->c_intr(chp, xfer, 1); 678 if (ret == 0) /* irq was not for us, still waiting for irq */ 679 chp->ch_flags |= WDCF_IRQ_WAIT; 680 return (ret); 681 } 682 683 /* Put all disk in RESET state */ 684 void wdc_reset_channel(drvp) 685 struct ata_drive_datas *drvp; 686 { 687 struct channel_softc *chp = drvp->chnl_softc; 688 int drive; 689 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 690 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 691 DEBUG_FUNCS); 692 (void) wdcreset(chp, VERBOSE); 693 for (drive = 0; drive < 2; drive++) { 694 chp->ch_drive[drive].state = 0; 695 } 696 } 697 698 int 699 wdcreset(chp, verb) 700 struct channel_softc *chp; 701 int verb; 702 { 703 int drv_mask1, drv_mask2; 704 705 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 706 WDSD_IBM); /* master */ 707 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 708 WDCTL_RST | WDCTL_IDS); 709 delay(1000); 710 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 711 WDCTL_IDS); 712 delay(1000); 713 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 714 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 715 WDCTL_4BIT); 716 717 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 718 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 719 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 720 if (verb && drv_mask2 != drv_mask1) { 721 printf("%s channel %d: reset failed for", 722 chp->wdc->sc_dev.dv_xname, chp->channel); 723 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 724 printf(" drive 0"); 725 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 726 printf(" drive 1"); 727 printf("\n"); 728 } 729 return (drv_mask1 != drv_mask2) ? 1 : 0; 730 } 731 732 static int 733 __wdcwait_reset(chp, drv_mask) 734 struct channel_softc *chp; 735 int drv_mask; 736 { 737 int timeout; 738 u_int8_t st0, st1; 739 #ifdef WDCDEBUG 740 u_int8_t sc0, sn0, cl0, ch0; 741 u_int8_t sc1, sn1, cl1, ch1; 742 #endif 743 /* wait for BSY to deassert */ 744 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 745 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 746 WDSD_IBM); /* master */ 747 delay(10); 748 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 749 #ifdef WDCDEBUG 750 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 751 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 752 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 753 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 754 #endif 755 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 756 WDSD_IBM | 0x10); /* slave */ 757 delay(10); 758 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 759 #ifdef WDCDEBUG 760 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 761 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 762 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 763 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 764 #endif 765 766 if ((drv_mask & 0x01) == 0) { 767 /* no master */ 768 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 769 /* No master, slave is ready, it's done */ 770 goto end; 771 } 772 } else if ((drv_mask & 0x02) == 0) { 773 /* no slave */ 774 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 775 /* No slave, master is ready, it's done */ 776 goto end; 777 } 778 } else { 779 /* Wait for both master and slave to be ready */ 780 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 781 goto end; 782 } 783 } 784 delay(WDCDELAY); 785 } 786 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 787 if (st0 & WDCS_BSY) 788 drv_mask &= ~0x01; 789 if (st1 & WDCS_BSY) 790 drv_mask &= ~0x02; 791 end: 792 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 793 "cl=0x%x ch=0x%x\n", 794 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 795 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 796 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 797 "cl=0x%x ch=0x%x\n", 798 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 799 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 800 801 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 802 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 803 st0, st1), DEBUG_PROBE); 804 805 return drv_mask; 806 } 807 808 /* 809 * Wait for a drive to be !BSY, and have mask in its status register. 810 * return -1 for a timeout after "timeout" ms. 811 */ 812 int 813 wdcwait(chp, mask, bits, timeout) 814 struct channel_softc *chp; 815 int mask, bits, timeout; 816 { 817 u_char status; 818 int time = 0; 819 #ifdef WDCNDELAY_DEBUG 820 extern int cold; 821 #endif 822 823 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 824 :"none", chp->channel), DEBUG_STATUS); 825 chp->ch_error = 0; 826 827 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 828 829 for (;;) { 830 chp->ch_status = status = 831 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 832 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 833 break; 834 if (++time > timeout) { 835 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 836 "error %x (mask 0x%x bits 0x%x)\n", status, 837 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 838 wd_error), mask, bits), 839 DEBUG_STATUS | DEBUG_PROBE); 840 return -1; 841 } 842 delay(WDCDELAY); 843 } 844 if (status & WDCS_ERR) 845 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 846 wd_error); 847 #ifdef WDCNDELAY_DEBUG 848 /* After autoconfig, there should be no long delays. */ 849 if (!cold && time > WDCNDELAY_DEBUG) { 850 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 851 if (xfer == NULL) 852 printf("%s channel %d: warning: busy-wait took %dus\n", 853 chp->wdc->sc_dev.dv_xname, chp->channel, 854 WDCDELAY * time); 855 else 856 printf("%s:%d:%d: warning: busy-wait took %dus\n", 857 chp->wdc->sc_dev.dv_xname, chp->channel, 858 xfer->drive, 859 WDCDELAY * time); 860 } 861 #endif 862 return 0; 863 } 864 865 void 866 wdctimeout(arg) 867 void *arg; 868 { 869 struct channel_softc *chp = (struct channel_softc *)arg; 870 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 871 int s; 872 873 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 874 875 s = splbio(); 876 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 877 __wdcerror(chp, "lost interrupt"); 878 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 879 "atapi":"ata"); 880 printf("\tc_bcount: %d\n", xfer->c_bcount); 881 printf("\tc_skip: %d\n", xfer->c_skip); 882 /* 883 * Call the interrupt routine. If we just missed and interrupt, 884 * it will do what's needed. Else, it will take the needed 885 * action (reset the device). 886 * Before that we need to reinstall the timeout callback, 887 * in case it will miss another irq while in this transfer 888 * We arbitray chose it to be 1s 889 */ 890 timeout(wdctimeout, chp, hz); 891 xfer->c_flags |= C_TIMEOU; 892 chp->ch_flags &= ~WDCF_IRQ_WAIT; 893 xfer->c_intr(chp, xfer, 1); 894 } else 895 __wdcerror(chp, "missing untimeout"); 896 splx(s); 897 } 898 899 /* 900 * Probe drive's capabilites, for use by the controller later 901 * Assumes drvp points to an existing drive. 902 * XXX this should be a controller-indep function 903 */ 904 void 905 wdc_probe_caps(drvp) 906 struct ata_drive_datas *drvp; 907 { 908 struct ataparams params, params2; 909 struct channel_softc *chp = drvp->chnl_softc; 910 struct device *drv_dev = drvp->drv_softc; 911 struct wdc_softc *wdc = chp->wdc; 912 int i, printed; 913 char *sep = ""; 914 int cf_flags; 915 916 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 917 /* IDENTIFY failed. Can't tell more about the device */ 918 return; 919 } 920 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 921 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 922 /* 923 * Controller claims 16 and 32 bit transfers. 924 * Re-do an IDENTIFY with 32-bit transfers, 925 * and compare results. 926 */ 927 drvp->drive_flags |= DRIVE_CAP32; 928 ata_get_params(drvp, AT_POLL, ¶ms2); 929 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 930 /* Not good. fall back to 16bits */ 931 drvp->drive_flags &= ~DRIVE_CAP32; 932 } else { 933 printf("%s: 32-bits data port", drv_dev->dv_xname); 934 } 935 } 936 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 937 if (params.atap_ata_major > 0x01 && 938 params.atap_ata_major != 0xffff) { 939 for (i = 14; i > 0; i--) { 940 if (params.atap_ata_major & (1 << i)) { 941 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 942 printf("%s: ", drv_dev->dv_xname); 943 else 944 printf(", "); 945 printf("ATA version %d\n", i); 946 drvp->ata_vers = i; 947 break; 948 } 949 } 950 } else 951 #endif 952 if (drvp->drive_flags & DRIVE_CAP32) 953 printf("\n"); 954 955 /* An ATAPI device is at last PIO mode 3 */ 956 if (drvp->drive_flags & DRIVE_ATAPI) 957 drvp->PIO_mode = 3; 958 959 /* 960 * It's not in the specs, but it seems that some drive 961 * returns 0xffff in atap_extensions when this field is invalid 962 */ 963 if (params.atap_extensions != 0xffff && 964 (params.atap_extensions & WDC_EXT_MODES)) { 965 printed = 0; 966 /* 967 * XXX some drives report something wrong here (they claim to 968 * support PIO mode 8 !). As mode is coded on 3 bits in 969 * SET FEATURE, limit it to 7 (so limit i to 4). 970 * If higther mode than 7 is found, abort. 971 */ 972 for (i = 7; i >= 0; i--) { 973 if ((params.atap_piomode_supp & (1 << i)) == 0) 974 continue; 975 if (i > 4) 976 return; 977 /* 978 * See if mode is accepted. 979 * If the controller can't set its PIO mode, 980 * assume the defaults are good, so don't try 981 * to set it 982 */ 983 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 984 if (ata_set_mode(drvp, 0x08 | (i + 3), 985 AT_POLL) != CMD_OK) 986 continue; 987 if (!printed) { 988 printf("%s: drive supports PIO mode %d", 989 drv_dev->dv_xname, i + 3); 990 sep = ","; 991 printed = 1; 992 } 993 /* 994 * If controller's driver can't set its PIO mode, 995 * get the highter one for the drive. 996 */ 997 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 998 wdc->PIO_cap >= i + 3) { 999 drvp->PIO_mode = i + 3; 1000 drvp->PIO_cap = i + 3; 1001 break; 1002 } 1003 } 1004 if (!printed) { 1005 /* 1006 * We didn't find a valid PIO mode. 1007 * Assume the values returned for DMA are buggy too 1008 */ 1009 return; 1010 } 1011 drvp->drive_flags |= DRIVE_MODE; 1012 printed = 0; 1013 for (i = 7; i >= 0; i--) { 1014 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1015 continue; 1016 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1017 (wdc->cap & WDC_CAPABILITY_MODE)) 1018 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1019 != CMD_OK) 1020 continue; 1021 if (!printed) { 1022 printf("%s DMA mode %d", sep, i); 1023 sep = ","; 1024 printed = 1; 1025 } 1026 if (wdc->cap & WDC_CAPABILITY_DMA) { 1027 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1028 wdc->DMA_cap < i) 1029 continue; 1030 drvp->DMA_mode = i; 1031 drvp->DMA_cap = i; 1032 drvp->drive_flags |= DRIVE_DMA; 1033 } 1034 break; 1035 } 1036 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1037 printed = 0; 1038 for (i = 7; i >= 0; i--) { 1039 if ((params.atap_udmamode_supp & (1 << i)) 1040 == 0) 1041 continue; 1042 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1043 (wdc->cap & WDC_CAPABILITY_UDMA)) 1044 if (ata_set_mode(drvp, 0x40 | i, 1045 AT_POLL) != CMD_OK) 1046 continue; 1047 if (!printed) { 1048 printf("%s Ultra-DMA mode %d", sep, i); 1049 sep = ","; 1050 printed = 1; 1051 } 1052 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1053 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1054 wdc->UDMA_cap < i) 1055 continue; 1056 drvp->UDMA_mode = i; 1057 drvp->UDMA_cap = i; 1058 drvp->drive_flags |= DRIVE_UDMA; 1059 } 1060 break; 1061 } 1062 } 1063 printf("\n"); 1064 } 1065 1066 /* Try to guess ATA version here, if it didn't get reported */ 1067 if (drvp->ata_vers == 0) { 1068 if (drvp->drive_flags & DRIVE_UDMA) 1069 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1070 else if (drvp->PIO_cap > 2) 1071 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1072 } 1073 cf_flags = drv_dev->dv_cfdata->cf_flags; 1074 if (cf_flags & ATA_CONFIG_PIO_SET) { 1075 drvp->PIO_mode = 1076 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1077 drvp->drive_flags |= DRIVE_MODE; 1078 } 1079 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1080 /* don't care about DMA modes */ 1081 return; 1082 } 1083 if (cf_flags & ATA_CONFIG_DMA_SET) { 1084 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1085 ATA_CONFIG_DMA_DISABLE) { 1086 drvp->drive_flags &= ~DRIVE_DMA; 1087 } else { 1088 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1089 ATA_CONFIG_DMA_OFF; 1090 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1091 } 1092 } 1093 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1094 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1095 ATA_CONFIG_UDMA_DISABLE) { 1096 drvp->drive_flags &= ~DRIVE_UDMA; 1097 } else { 1098 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1099 ATA_CONFIG_UDMA_OFF; 1100 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1101 } 1102 } 1103 } 1104 1105 /* 1106 * downgrade the transfer mode of a drive after an error. return 1 if 1107 * downgrade was possible, 0 otherwise. 1108 */ 1109 int 1110 wdc_downgrade_mode(drvp) 1111 struct ata_drive_datas *drvp; 1112 { 1113 struct channel_softc *chp = drvp->chnl_softc; 1114 struct device *drv_dev = drvp->drv_softc; 1115 struct wdc_softc *wdc = chp->wdc; 1116 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1117 1118 /* if drive or controller don't know its mode, we can't do much */ 1119 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1120 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1121 return 0; 1122 /* current drive mode was set by a config flag, let it this way */ 1123 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1124 (cf_flags & ATA_CONFIG_DMA_SET) || 1125 (cf_flags & ATA_CONFIG_UDMA_SET)) 1126 return 0; 1127 1128 /* 1129 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1130 * Maybe we didn't properly notice the cable type 1131 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1132 * It helps in some cases. 1133 */ 1134 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1135 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1136 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1137 drv_dev->dv_xname, drvp->UDMA_mode); 1138 } 1139 1140 /* 1141 * If we were using ultra-DMA, don't downgrade to multiword DMA 1142 * if we noticed a CRC error. It has been noticed that CRC errors 1143 * in ultra-DMA lead to silent data corruption in multiword DMA. 1144 * Data corruption is less likely to occur in PIO mode. 1145 */ 1146 else if ((drvp->drive_flags & DRIVE_UDMA) && 1147 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1148 drvp->drive_flags &= ~DRIVE_UDMA; 1149 drvp->drive_flags |= DRIVE_DMA; 1150 drvp->DMA_mode = drvp->DMA_cap; 1151 printf("%s: transfer error, downgrading to DMA mode %d\n", 1152 drv_dev->dv_xname, drvp->DMA_mode); 1153 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1154 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1155 drvp->PIO_mode = drvp->PIO_cap; 1156 printf("%s: transfer error, downgrading to PIO mode %d\n", 1157 drv_dev->dv_xname, drvp->PIO_mode); 1158 } else /* already using PIO, can't downgrade */ 1159 return 0; 1160 1161 wdc->set_modes(chp); 1162 /* reset the channel, which will shedule all drives for setup */ 1163 wdc_reset_channel(drvp); 1164 return 1; 1165 } 1166 1167 int 1168 wdc_exec_command(drvp, wdc_c) 1169 struct ata_drive_datas *drvp; 1170 struct wdc_command *wdc_c; 1171 { 1172 struct channel_softc *chp = drvp->chnl_softc; 1173 struct wdc_xfer *xfer; 1174 int s, ret; 1175 1176 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1177 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1178 DEBUG_FUNCS); 1179 1180 /* set up an xfer and queue. Wait for completion */ 1181 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1182 WDC_NOSLEEP); 1183 if (xfer == NULL) { 1184 return WDC_TRY_AGAIN; 1185 } 1186 1187 if (wdc_c->flags & AT_POLL) 1188 xfer->c_flags |= C_POLL; 1189 xfer->drive = drvp->drive; 1190 xfer->databuf = wdc_c->data; 1191 xfer->c_bcount = wdc_c->bcount; 1192 xfer->cmd = wdc_c; 1193 xfer->c_start = __wdccommand_start; 1194 xfer->c_intr = __wdccommand_intr; 1195 xfer->c_kill_xfer = __wdccommand_done; 1196 1197 s = splbio(); 1198 wdc_exec_xfer(chp, xfer); 1199 #ifdef DIAGNOSTIC 1200 if ((wdc_c->flags & AT_POLL) != 0 && 1201 (wdc_c->flags & AT_DONE) == 0) 1202 panic("wdc_exec_command: polled command not done\n"); 1203 #endif 1204 if (wdc_c->flags & AT_DONE) { 1205 ret = WDC_COMPLETE; 1206 } else { 1207 if (wdc_c->flags & AT_WAIT) { 1208 while ((wdc_c->flags & AT_DONE) == 0) { 1209 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1210 } 1211 ret = WDC_COMPLETE; 1212 } else { 1213 ret = WDC_QUEUED; 1214 } 1215 } 1216 splx(s); 1217 return ret; 1218 } 1219 1220 void 1221 __wdccommand_start(chp, xfer) 1222 struct channel_softc *chp; 1223 struct wdc_xfer *xfer; 1224 { 1225 int drive = xfer->drive; 1226 struct wdc_command *wdc_c = xfer->cmd; 1227 1228 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1229 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1230 DEBUG_FUNCS); 1231 1232 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1233 WDSD_IBM | (drive << 4)); 1234 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1235 wdc_c->timeout) != 0) { 1236 wdc_c->flags |= AT_TIMEOU; 1237 __wdccommand_done(chp, xfer); 1238 return; 1239 } 1240 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1241 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1242 if ((wdc_c->flags & AT_POLL) == 0) { 1243 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1244 timeout(wdctimeout, chp, wdc_c->timeout / 1000 * hz); 1245 return; 1246 } 1247 /* 1248 * Polled command. Wait for drive ready or drq. Done in intr(). 1249 * Wait for at last 400ns for status bit to be valid. 1250 */ 1251 delay(10); 1252 __wdccommand_intr(chp, xfer, 0); 1253 } 1254 1255 int 1256 __wdccommand_intr(chp, xfer, irq) 1257 struct channel_softc *chp; 1258 struct wdc_xfer *xfer; 1259 int irq; 1260 { 1261 struct wdc_command *wdc_c = xfer->cmd; 1262 int bcount = wdc_c->bcount; 1263 char *data = wdc_c->data; 1264 1265 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1266 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1267 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1268 (irq == 0) ? wdc_c->timeout : 0)) { 1269 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1270 return 0; /* IRQ was not for us */ 1271 wdc_c->flags |= AT_TIMEOU; 1272 __wdccommand_done(chp, xfer); 1273 return 1; 1274 } 1275 if (wdc_c->flags & AT_READ) { 1276 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1277 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1278 0, (u_int32_t*)data, bcount >> 2); 1279 data += bcount & 0xfffffffc; 1280 bcount = bcount & 0x03; 1281 } 1282 if (bcount > 0) 1283 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1284 wd_data, (u_int16_t *)data, bcount >> 1); 1285 } else if (wdc_c->flags & AT_WRITE) { 1286 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1287 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1288 0, (u_int32_t*)data, bcount >> 2); 1289 data += bcount & 0xfffffffc; 1290 bcount = bcount & 0x03; 1291 } 1292 if (bcount > 0) 1293 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1294 wd_data, (u_int16_t *)data, bcount >> 1); 1295 } 1296 __wdccommand_done(chp, xfer); 1297 return 1; 1298 } 1299 1300 void 1301 __wdccommand_done(chp, xfer) 1302 struct channel_softc *chp; 1303 struct wdc_xfer *xfer; 1304 { 1305 struct wdc_command *wdc_c = xfer->cmd; 1306 1307 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1308 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1309 1310 untimeout(wdctimeout, chp); 1311 1312 if (chp->ch_status & WDCS_DWF) 1313 wdc_c->flags |= AT_DF; 1314 if (chp->ch_status & WDCS_ERR) { 1315 wdc_c->flags |= AT_ERROR; 1316 wdc_c->r_error = chp->ch_error; 1317 } 1318 wdc_c->flags |= AT_DONE; 1319 if ((wdc_c->flags & AT_READREG) != 0 && 1320 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1321 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1322 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1323 wd_sdh); 1324 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1325 wd_cyl_hi) << 8; 1326 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1327 wd_cyl_lo); 1328 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1329 wd_sector); 1330 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1331 wd_seccnt); 1332 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1333 wd_error); 1334 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1335 wd_precomp); 1336 } 1337 wdc_free_xfer(chp, xfer); 1338 if (wdc_c->flags & AT_WAIT) 1339 wakeup(wdc_c); 1340 else if (wdc_c->callback) 1341 wdc_c->callback(wdc_c->callback_arg); 1342 wdcstart(chp); 1343 return; 1344 } 1345 1346 /* 1347 * Send a command. The drive should be ready. 1348 * Assumes interrupts are blocked. 1349 */ 1350 void 1351 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1352 struct channel_softc *chp; 1353 u_int8_t drive; 1354 u_int8_t command; 1355 u_int16_t cylin; 1356 u_int8_t head, sector, count, precomp; 1357 { 1358 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1359 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1360 chp->channel, drive, command, cylin, head, sector, count, precomp), 1361 DEBUG_FUNCS); 1362 1363 /* Select drive, head, and addressing mode. */ 1364 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1365 WDSD_IBM | (drive << 4) | head); 1366 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1367 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1368 precomp); 1369 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1370 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1371 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1372 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1373 1374 /* Send command. */ 1375 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1376 return; 1377 } 1378 1379 /* 1380 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1381 * tested by the caller. 1382 */ 1383 void 1384 wdccommandshort(chp, drive, command) 1385 struct channel_softc *chp; 1386 int drive; 1387 int command; 1388 { 1389 1390 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1391 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1392 DEBUG_FUNCS); 1393 1394 /* Select drive. */ 1395 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1396 WDSD_IBM | (drive << 4)); 1397 1398 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1399 } 1400 1401 /* Add a command to the queue and start controller. Must be called at splbio */ 1402 1403 void 1404 wdc_exec_xfer(chp, xfer) 1405 struct channel_softc *chp; 1406 struct wdc_xfer *xfer; 1407 { 1408 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1409 chp->channel, xfer->drive), DEBUG_XFERS); 1410 1411 /* complete xfer setup */ 1412 xfer->chp = chp; 1413 1414 /* 1415 * If we are a polled command, and the list is not empty, 1416 * we are doing a dump. Drop the list to allow the polled command 1417 * to complete, we're going to reboot soon anyway. 1418 */ 1419 if ((xfer->c_flags & C_POLL) != 0 && 1420 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1421 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1422 } 1423 /* insert at the end of command list */ 1424 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1425 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1426 chp->ch_flags), DEBUG_XFERS); 1427 wdcstart(chp); 1428 } 1429 1430 struct wdc_xfer * 1431 wdc_get_xfer(flags) 1432 int flags; 1433 { 1434 struct wdc_xfer *xfer; 1435 int s; 1436 1437 s = splbio(); 1438 xfer = pool_get(&wdc_xfer_pool, 1439 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1440 splx(s); 1441 memset(xfer, 0, sizeof(struct wdc_xfer)); 1442 return xfer; 1443 } 1444 1445 void 1446 wdc_free_xfer(chp, xfer) 1447 struct channel_softc *chp; 1448 struct wdc_xfer *xfer; 1449 { 1450 struct wdc_softc *wdc = chp->wdc; 1451 int s; 1452 1453 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1454 (*wdc->free_hw)(chp); 1455 s = splbio(); 1456 chp->ch_flags &= ~WDCF_ACTIVE; 1457 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1458 pool_put(&wdc_xfer_pool, xfer); 1459 splx(s); 1460 } 1461 1462 /* 1463 * Kill off all pending xfers for a channel_softc. 1464 * 1465 * Must be called at splbio(). 1466 */ 1467 void 1468 wdc_kill_pending(chp) 1469 struct channel_softc *chp; 1470 { 1471 struct wdc_xfer *xfer; 1472 1473 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1474 chp = xfer->chp; 1475 (*xfer->c_kill_xfer)(chp, xfer); 1476 } 1477 } 1478 1479 static void 1480 __wdcerror(chp, msg) 1481 struct channel_softc *chp; 1482 char *msg; 1483 { 1484 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1485 if (xfer == NULL) 1486 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1487 msg); 1488 else 1489 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1490 chp->channel, xfer->drive, msg); 1491 } 1492 1493 /* 1494 * the bit bucket 1495 */ 1496 void 1497 wdcbit_bucket(chp, size) 1498 struct channel_softc *chp; 1499 int size; 1500 { 1501 1502 for (; size >= 2; size -= 2) 1503 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1504 if (size) 1505 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1506 } 1507 1508 int 1509 wdc_addref(chp) 1510 struct channel_softc *chp; 1511 { 1512 struct wdc_softc *wdc = chp->wdc; 1513 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1514 int s, error = 0; 1515 1516 s = splbio(); 1517 if (adapter->scsipi_refcnt++ == 0 && 1518 adapter->scsipi_enable != NULL) { 1519 error = (*adapter->scsipi_enable)(wdc, 1); 1520 if (error) 1521 adapter->scsipi_refcnt--; 1522 } 1523 splx(s); 1524 return (error); 1525 } 1526 1527 void 1528 wdc_delref(chp) 1529 struct channel_softc *chp; 1530 { 1531 struct wdc_softc *wdc = chp->wdc; 1532 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1533 int s; 1534 1535 s = splbio(); 1536 if (adapter->scsipi_refcnt-- == 1 && 1537 adapter->scsipi_enable != NULL) 1538 (void) (*adapter->scsipi_enable)(wdc, 0); 1539 splx(s); 1540 } 1541
Indexes created Sun Sep 21 20:09:37 GMT 2025