wdc.c revision 1.82
1 /* $NetBSD: wdc.c,v 1.82 2000/03/23 15:04:49 soren Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 void wdc_kill_pending __P((struct channel_softc *)); 124 125 126 #define DEBUG_INTR 0x01 127 #define DEBUG_XFERS 0x02 128 #define DEBUG_STATUS 0x04 129 #define DEBUG_FUNCS 0x08 130 #define DEBUG_PROBE 0x10 131 #define DEBUG_DETACH 0x20 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc is supposted to be 0x1 for ATAPI but at last one drive 259 * set it to 0x0 - or maybe it's the controller. 260 */ 261 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 262 cl == 0x14 && ch == 0xeb) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 264 } else { 265 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 266 if (chp->wdc == NULL || 267 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 268 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 269 } 270 } 271 return (ret_value); 272 } 273 274 void 275 wdcattach(chp) 276 struct channel_softc *chp; 277 { 278 int channel_flags, ctrl_flags, i, error; 279 struct ata_atapi_attach aa_link; 280 struct ataparams params; 281 static int inited = 0; 282 283 callout_init(&chp->ch_callout); 284 285 if ((error = wdc_addref(chp)) != 0) { 286 printf("%s: unable to enable controller\n", 287 chp->wdc->sc_dev.dv_xname); 288 return; 289 } 290 291 if (wdcprobe(chp) == 0) 292 /* If no drives, abort attach here. */ 293 goto out; 294 295 /* initialise global data */ 296 if (inited == 0) { 297 /* Initialize the wdc_xfer pool. */ 298 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 299 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 300 inited++; 301 } 302 TAILQ_INIT(&chp->ch_queue->sc_xfer); 303 304 for (i = 0; i < 2; i++) { 305 chp->ch_drive[i].chnl_softc = chp; 306 chp->ch_drive[i].drive = i; 307 /* 308 * Init error counter so that an error withing the first xfers 309 * will trigger a downgrade 310 */ 311 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 312 313 /* If controller can't do 16bit flag the drives as 32bit */ 314 if ((chp->wdc->cap & 315 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 316 WDC_CAPABILITY_DATA32) 317 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 318 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 319 continue; 320 321 /* 322 * Wait a bit, some devices are weird just after a reset. 323 * Then issue a IDENTIFY command, to try to detect slave ghost 324 */ 325 delay(100); 326 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 327 if (error == CMD_OK) { 328 /* If IDENTIFY succeded, this is not an OLD ctrl */ 329 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 330 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 331 } else { 332 chp->ch_drive[i].drive_flags &= 333 ~(DRIVE_ATA | DRIVE_ATAPI); 334 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 335 chp->wdc->sc_dev.dv_xname, 336 chp->channel, i, error), DEBUG_PROBE); 337 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 338 continue; 339 /* 340 * Pre-ATA drive ? 341 * Test registers writability (Error register not 342 * writable, but cyllo is), then try an ATA command. 343 */ 344 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 345 WDSD_IBM | (i << 4)); 346 delay(10); 347 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 348 wd_error, 0x58); 349 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 350 wd_cyl_lo, 0xa5); 351 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 352 wd_error == 0x58) || 353 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 354 wd_cyl_lo) != 0xa5) { 355 WDCDEBUG_PRINT(("%s:%d:%d: register " 356 "writability failed\n", 357 chp->wdc->sc_dev.dv_xname, 358 chp->channel, i), DEBUG_PROBE); 359 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 360 } 361 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 362 WDSD_IBM | (i << 4)); 363 delay(100); 364 if (wait_for_ready(chp, 10000) != 0) { 365 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 366 chp->wdc->sc_dev.dv_xname, 367 chp->channel, i), DEBUG_PROBE); 368 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 369 continue; 370 } 371 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 372 wd_command, WDCC_RECAL); 373 if (wait_for_ready(chp, 10000) != 0) { 374 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 375 chp->wdc->sc_dev.dv_xname, 376 chp->channel, i), DEBUG_PROBE); 377 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 378 } 379 } 380 } 381 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 382 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 383 384 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 385 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 386 DEBUG_PROBE); 387 388 /* If no drives, abort here */ 389 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 390 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 391 goto out; 392 393 /* 394 * Attach an ATAPI bus, if needed. 395 */ 396 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 397 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 398 #if NATAPIBUS > 0 399 wdc_atapibus_attach(chp); 400 #else 401 /* 402 * Fills in a fake aa_link and call config_found, so that 403 * the config machinery will print 404 * "atapibus at xxx not configured" 405 */ 406 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 407 aa_link.aa_type = T_ATAPI; 408 aa_link.aa_channel = chp->channel; 409 aa_link.aa_openings = 1; 410 aa_link.aa_drv_data = 0; 411 aa_link.aa_bus_private = NULL; 412 chp->atapibus = config_found(&chp->wdc->sc_dev, 413 (void *)&aa_link, atapi_print); 414 #endif 415 } 416 417 for (i = 0; i < 2; i++) { 418 if ((chp->ch_drive[i].drive_flags & 419 (DRIVE_ATA | DRIVE_OLD)) == 0) { 420 continue; 421 } 422 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 423 aa_link.aa_type = T_ATA; 424 aa_link.aa_channel = chp->channel; 425 aa_link.aa_openings = 1; 426 aa_link.aa_drv_data = &chp->ch_drive[i]; 427 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 428 wdc_probe_caps(&chp->ch_drive[i]); 429 } 430 431 /* 432 * reset drive_flags for unnatached devices, reset state for attached 433 * ones 434 */ 435 for (i = 0; i < 2; i++) { 436 if (chp->ch_drive[i].drv_softc == NULL) 437 chp->ch_drive[i].drive_flags = 0; 438 else 439 chp->ch_drive[i].state = 0; 440 } 441 442 /* 443 * Reset channel. The probe, with some combinations of ATA/ATAPI 444 * devices keep it in a mostly working, but strange state (with busy 445 * led on) 446 */ 447 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 448 wdcreset(chp, VERBOSE); 449 /* 450 * Read status registers to avoid spurious interrupts. 451 */ 452 for (i = 1; i >= 0; i--) { 453 if (chp->ch_drive[i].drive_flags & DRIVE) { 454 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 455 wd_sdh, WDSD_IBM | (i << 4)); 456 if (wait_for_unbusy(chp, 10000) < 0) 457 printf("%s:%d:%d: device busy\n", 458 chp->wdc->sc_dev.dv_xname, 459 chp->channel, i); 460 } 461 } 462 } 463 464 out: 465 wdc_delref(chp); 466 } 467 468 /* 469 * Call activate routine of underlying devices. 470 */ 471 int 472 wdcactivate(self, act) 473 struct device *self; 474 enum devact act; 475 { 476 struct wdc_softc *wdc = (struct wdc_softc *)self; 477 struct channel_softc *chp; 478 struct device *sc; 479 int s, i, j, error = 0; 480 481 s = splbio(); 482 switch (act) { 483 case DVACT_ACTIVATE: 484 error = EOPNOTSUPP; 485 break; 486 487 case DVACT_DEACTIVATE: 488 for (i = 0; i < wdc->nchannels; i++) { 489 chp = wdc->channels[i]; 490 491 /* 492 * We might call deactivate routine for 493 * the children of atapibus twice (once via 494 * atapibus, once directly), but since 495 * config_deactivate maintains DVF_ACTIVE flag, 496 * it's safe. 497 */ 498 sc = chp->atapibus; 499 if (sc != NULL) { 500 error = config_deactivate(sc); 501 if (error != 0) 502 goto out; 503 } 504 505 for (j = 0; j < 2; j++) { 506 sc = chp->ch_drive[j].drv_softc; 507 WDCDEBUG_PRINT(("wdcactivate: %s:" 508 " deactivating %s\n", wdc->sc_dev.dv_xname, 509 sc == NULL ? "nodrv" : sc->dv_xname), 510 DEBUG_DETACH); 511 if (sc != NULL) { 512 error = config_deactivate(sc); 513 if (error != 0) 514 goto out; 515 } 516 } 517 } 518 break; 519 } 520 521 out: 522 splx(s); 523 524 #ifdef WDCDEBUG 525 if (error != 0) 526 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 527 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 528 #endif 529 return (error); 530 } 531 532 int 533 wdcdetach(self, flags) 534 struct device *self; 535 int flags; 536 { 537 struct wdc_softc *wdc = (struct wdc_softc *)self; 538 struct channel_softc *chp; 539 struct device *sc; 540 int i, j, error = 0; 541 542 for (i = 0; i < wdc->nchannels; i++) { 543 chp = wdc->channels[i]; 544 545 /* 546 * Detach atapibus and its children. 547 */ 548 sc = chp->atapibus; 549 if (sc != NULL) { 550 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 551 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 552 error = config_detach(sc, flags); 553 if (error != 0) 554 goto out; 555 } 556 557 /* 558 * Detach our other children. 559 */ 560 for (j = 0; j < 2; j++) { 561 sc = chp->ch_drive[j].drv_softc; 562 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 563 wdc->sc_dev.dv_xname, 564 sc == NULL ? "nodrv" : sc->dv_xname), 565 DEBUG_DETACH); 566 if (sc != NULL) { 567 error = config_detach(sc, flags); 568 if (error != 0) 569 goto out; 570 } 571 } 572 573 wdc_kill_pending(chp); 574 } 575 576 out: 577 #ifdef WDCDEBUG 578 if (error != 0) 579 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 580 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 581 #endif 582 return (error); 583 } 584 585 /* 586 * Start I/O on a controller, for the given channel. 587 * The first xfer may be not for our channel if the channel queues 588 * are shared. 589 */ 590 void 591 wdcstart(chp) 592 struct channel_softc *chp; 593 { 594 struct wdc_xfer *xfer; 595 596 #ifdef WDC_DIAGNOSTIC 597 int spl1, spl2; 598 599 spl1 = splbio(); 600 spl2 = splbio(); 601 if (spl2 != spl1) { 602 printf("wdcstart: not at splbio()\n"); 603 panic("wdcstart"); 604 } 605 splx(spl2); 606 splx(spl1); 607 #endif /* WDC_DIAGNOSTIC */ 608 609 /* is there a xfer ? */ 610 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 611 return; 612 613 /* adjust chp, in case we have a shared queue */ 614 chp = xfer->chp; 615 616 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 617 return; /* channel aleady active */ 618 } 619 #ifdef DIAGNOSTIC 620 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 621 panic("wdcstart: channel waiting for irq\n"); 622 #endif 623 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 624 if (!(*chp->wdc->claim_hw)(chp, 0)) 625 return; 626 627 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 628 chp->channel, xfer->drive), DEBUG_XFERS); 629 chp->ch_flags |= WDCF_ACTIVE; 630 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 631 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 632 chp->ch_drive[xfer->drive].state = 0; 633 } 634 xfer->c_start(chp, xfer); 635 } 636 637 /* restart an interrupted I/O */ 638 void 639 wdcrestart(v) 640 void *v; 641 { 642 struct channel_softc *chp = v; 643 int s; 644 645 s = splbio(); 646 wdcstart(chp); 647 splx(s); 648 } 649 650 651 /* 652 * Interrupt routine for the controller. Acknowledge the interrupt, check for 653 * errors on the current operation, mark it done if necessary, and start the 654 * next request. Also check for a partially done transfer, and continue with 655 * the next chunk if so. 656 */ 657 int 658 wdcintr(arg) 659 void *arg; 660 { 661 struct channel_softc *chp = arg; 662 struct wdc_xfer *xfer; 663 int ret; 664 665 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 666 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 667 DEBUG_INTR); 668 return (0); 669 } 670 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 671 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 672 return (0); 673 } 674 675 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 676 chp->ch_flags &= ~WDCF_IRQ_WAIT; 677 xfer = chp->ch_queue->sc_xfer.tqh_first; 678 ret = xfer->c_intr(chp, xfer, 1); 679 if (ret == 0) /* irq was not for us, still waiting for irq */ 680 chp->ch_flags |= WDCF_IRQ_WAIT; 681 return (ret); 682 } 683 684 /* Put all disk in RESET state */ 685 void wdc_reset_channel(drvp) 686 struct ata_drive_datas *drvp; 687 { 688 struct channel_softc *chp = drvp->chnl_softc; 689 int drive; 690 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 691 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 692 DEBUG_FUNCS); 693 (void) wdcreset(chp, VERBOSE); 694 for (drive = 0; drive < 2; drive++) { 695 chp->ch_drive[drive].state = 0; 696 } 697 } 698 699 int 700 wdcreset(chp, verb) 701 struct channel_softc *chp; 702 int verb; 703 { 704 int drv_mask1, drv_mask2; 705 706 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 707 WDSD_IBM); /* master */ 708 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 709 WDCTL_RST | WDCTL_IDS); 710 delay(1000); 711 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 712 WDCTL_IDS); 713 delay(1000); 714 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 715 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 716 WDCTL_4BIT); 717 718 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 719 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 720 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 721 if (verb && drv_mask2 != drv_mask1) { 722 printf("%s channel %d: reset failed for", 723 chp->wdc->sc_dev.dv_xname, chp->channel); 724 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 725 printf(" drive 0"); 726 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 727 printf(" drive 1"); 728 printf("\n"); 729 } 730 return (drv_mask1 != drv_mask2) ? 1 : 0; 731 } 732 733 static int 734 __wdcwait_reset(chp, drv_mask) 735 struct channel_softc *chp; 736 int drv_mask; 737 { 738 int timeout; 739 u_int8_t st0, st1; 740 #ifdef WDCDEBUG 741 u_int8_t sc0, sn0, cl0, ch0; 742 u_int8_t sc1, sn1, cl1, ch1; 743 #endif 744 /* wait for BSY to deassert */ 745 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 746 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 747 WDSD_IBM); /* master */ 748 delay(10); 749 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 750 #ifdef WDCDEBUG 751 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 752 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 753 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 754 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 755 #endif 756 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 757 WDSD_IBM | 0x10); /* slave */ 758 delay(10); 759 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 760 #ifdef WDCDEBUG 761 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 762 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 763 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 764 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 765 #endif 766 767 if ((drv_mask & 0x01) == 0) { 768 /* no master */ 769 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 770 /* No master, slave is ready, it's done */ 771 goto end; 772 } 773 } else if ((drv_mask & 0x02) == 0) { 774 /* no slave */ 775 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 776 /* No slave, master is ready, it's done */ 777 goto end; 778 } 779 } else { 780 /* Wait for both master and slave to be ready */ 781 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 782 goto end; 783 } 784 } 785 delay(WDCDELAY); 786 } 787 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 788 if (st0 & WDCS_BSY) 789 drv_mask &= ~0x01; 790 if (st1 & WDCS_BSY) 791 drv_mask &= ~0x02; 792 end: 793 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 794 "cl=0x%x ch=0x%x\n", 795 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 796 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 797 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 798 "cl=0x%x ch=0x%x\n", 799 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 800 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 801 802 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 803 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 804 st0, st1), DEBUG_PROBE); 805 806 return drv_mask; 807 } 808 809 /* 810 * Wait for a drive to be !BSY, and have mask in its status register. 811 * return -1 for a timeout after "timeout" ms. 812 */ 813 int 814 wdcwait(chp, mask, bits, timeout) 815 struct channel_softc *chp; 816 int mask, bits, timeout; 817 { 818 u_char status; 819 int time = 0; 820 #ifdef WDCNDELAY_DEBUG 821 extern int cold; 822 #endif 823 824 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 825 :"none", chp->channel), DEBUG_STATUS); 826 chp->ch_error = 0; 827 828 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 829 830 for (;;) { 831 chp->ch_status = status = 832 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 833 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 834 break; 835 if (++time > timeout) { 836 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 837 "error %x (mask 0x%x bits 0x%x)\n", status, 838 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 839 wd_error), mask, bits), 840 DEBUG_STATUS | DEBUG_PROBE); 841 return -1; 842 } 843 delay(WDCDELAY); 844 } 845 if (status & WDCS_ERR) 846 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 847 wd_error); 848 #ifdef WDCNDELAY_DEBUG 849 /* After autoconfig, there should be no long delays. */ 850 if (!cold && time > WDCNDELAY_DEBUG) { 851 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 852 if (xfer == NULL) 853 printf("%s channel %d: warning: busy-wait took %dus\n", 854 chp->wdc->sc_dev.dv_xname, chp->channel, 855 WDCDELAY * time); 856 else 857 printf("%s:%d:%d: warning: busy-wait took %dus\n", 858 chp->wdc->sc_dev.dv_xname, chp->channel, 859 xfer->drive, 860 WDCDELAY * time); 861 } 862 #endif 863 return 0; 864 } 865 866 void 867 wdctimeout(arg) 868 void *arg; 869 { 870 struct channel_softc *chp = (struct channel_softc *)arg; 871 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 872 int s; 873 874 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 875 876 s = splbio(); 877 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 878 __wdcerror(chp, "lost interrupt"); 879 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 880 "atapi":"ata"); 881 printf("\tc_bcount: %d\n", xfer->c_bcount); 882 printf("\tc_skip: %d\n", xfer->c_skip); 883 /* 884 * Call the interrupt routine. If we just missed and interrupt, 885 * it will do what's needed. Else, it will take the needed 886 * action (reset the device). 887 * Before that we need to reinstall the timeout callback, 888 * in case it will miss another irq while in this transfer 889 * We arbitray chose it to be 1s 890 */ 891 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 892 xfer->c_flags |= C_TIMEOU; 893 chp->ch_flags &= ~WDCF_IRQ_WAIT; 894 xfer->c_intr(chp, xfer, 1); 895 } else 896 __wdcerror(chp, "missing untimeout"); 897 splx(s); 898 } 899 900 /* 901 * Probe drive's capabilites, for use by the controller later 902 * Assumes drvp points to an existing drive. 903 * XXX this should be a controller-indep function 904 */ 905 void 906 wdc_probe_caps(drvp) 907 struct ata_drive_datas *drvp; 908 { 909 struct ataparams params, params2; 910 struct channel_softc *chp = drvp->chnl_softc; 911 struct device *drv_dev = drvp->drv_softc; 912 struct wdc_softc *wdc = chp->wdc; 913 int i, printed; 914 char *sep = ""; 915 int cf_flags; 916 917 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 918 /* IDENTIFY failed. Can't tell more about the device */ 919 return; 920 } 921 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 922 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 923 /* 924 * Controller claims 16 and 32 bit transfers. 925 * Re-do an IDENTIFY with 32-bit transfers, 926 * and compare results. 927 */ 928 drvp->drive_flags |= DRIVE_CAP32; 929 ata_get_params(drvp, AT_POLL, ¶ms2); 930 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 931 /* Not good. fall back to 16bits */ 932 drvp->drive_flags &= ~DRIVE_CAP32; 933 } else { 934 printf("%s: 32-bit data port", drv_dev->dv_xname); 935 } 936 } 937 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 938 if (params.atap_ata_major > 0x01 && 939 params.atap_ata_major != 0xffff) { 940 for (i = 14; i > 0; i--) { 941 if (params.atap_ata_major & (1 << i)) { 942 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 943 printf("%s: ", drv_dev->dv_xname); 944 else 945 printf(", "); 946 printf("ATA version %d\n", i); 947 drvp->ata_vers = i; 948 break; 949 } 950 } 951 } else 952 #endif 953 if (drvp->drive_flags & DRIVE_CAP32) 954 printf("\n"); 955 956 /* An ATAPI device is at last PIO mode 3 */ 957 if (drvp->drive_flags & DRIVE_ATAPI) 958 drvp->PIO_mode = 3; 959 960 /* 961 * It's not in the specs, but it seems that some drive 962 * returns 0xffff in atap_extensions when this field is invalid 963 */ 964 if (params.atap_extensions != 0xffff && 965 (params.atap_extensions & WDC_EXT_MODES)) { 966 printed = 0; 967 /* 968 * XXX some drives report something wrong here (they claim to 969 * support PIO mode 8 !). As mode is coded on 3 bits in 970 * SET FEATURE, limit it to 7 (so limit i to 4). 971 * If higther mode than 7 is found, abort. 972 */ 973 for (i = 7; i >= 0; i--) { 974 if ((params.atap_piomode_supp & (1 << i)) == 0) 975 continue; 976 if (i > 4) 977 return; 978 /* 979 * See if mode is accepted. 980 * If the controller can't set its PIO mode, 981 * assume the defaults are good, so don't try 982 * to set it 983 */ 984 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 985 if (ata_set_mode(drvp, 0x08 | (i + 3), 986 AT_POLL) != CMD_OK) 987 continue; 988 if (!printed) { 989 printf("%s: drive supports PIO mode %d", 990 drv_dev->dv_xname, i + 3); 991 sep = ","; 992 printed = 1; 993 } 994 /* 995 * If controller's driver can't set its PIO mode, 996 * get the highter one for the drive. 997 */ 998 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 999 wdc->PIO_cap >= i + 3) { 1000 drvp->PIO_mode = i + 3; 1001 drvp->PIO_cap = i + 3; 1002 break; 1003 } 1004 } 1005 if (!printed) { 1006 /* 1007 * We didn't find a valid PIO mode. 1008 * Assume the values returned for DMA are buggy too 1009 */ 1010 return; 1011 } 1012 drvp->drive_flags |= DRIVE_MODE; 1013 printed = 0; 1014 for (i = 7; i >= 0; i--) { 1015 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1016 continue; 1017 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1018 (wdc->cap & WDC_CAPABILITY_MODE)) 1019 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1020 != CMD_OK) 1021 continue; 1022 if (!printed) { 1023 printf("%s DMA mode %d", sep, i); 1024 sep = ","; 1025 printed = 1; 1026 } 1027 if (wdc->cap & WDC_CAPABILITY_DMA) { 1028 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1029 wdc->DMA_cap < i) 1030 continue; 1031 drvp->DMA_mode = i; 1032 drvp->DMA_cap = i; 1033 drvp->drive_flags |= DRIVE_DMA; 1034 } 1035 break; 1036 } 1037 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1038 printed = 0; 1039 for (i = 7; i >= 0; i--) { 1040 if ((params.atap_udmamode_supp & (1 << i)) 1041 == 0) 1042 continue; 1043 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1044 (wdc->cap & WDC_CAPABILITY_UDMA)) 1045 if (ata_set_mode(drvp, 0x40 | i, 1046 AT_POLL) != CMD_OK) 1047 continue; 1048 if (!printed) { 1049 printf("%s Ultra-DMA mode %d", sep, i); 1050 sep = ","; 1051 printed = 1; 1052 } 1053 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1054 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1055 wdc->UDMA_cap < i) 1056 continue; 1057 drvp->UDMA_mode = i; 1058 drvp->UDMA_cap = i; 1059 drvp->drive_flags |= DRIVE_UDMA; 1060 } 1061 break; 1062 } 1063 } 1064 printf("\n"); 1065 } 1066 1067 /* Try to guess ATA version here, if it didn't get reported */ 1068 if (drvp->ata_vers == 0) { 1069 if (drvp->drive_flags & DRIVE_UDMA) 1070 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1071 else if (drvp->PIO_cap > 2) 1072 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1073 } 1074 cf_flags = drv_dev->dv_cfdata->cf_flags; 1075 if (cf_flags & ATA_CONFIG_PIO_SET) { 1076 drvp->PIO_mode = 1077 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1078 drvp->drive_flags |= DRIVE_MODE; 1079 } 1080 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1081 /* don't care about DMA modes */ 1082 return; 1083 } 1084 if (cf_flags & ATA_CONFIG_DMA_SET) { 1085 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1086 ATA_CONFIG_DMA_DISABLE) { 1087 drvp->drive_flags &= ~DRIVE_DMA; 1088 } else { 1089 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1090 ATA_CONFIG_DMA_OFF; 1091 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1092 } 1093 } 1094 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1095 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1096 ATA_CONFIG_UDMA_DISABLE) { 1097 drvp->drive_flags &= ~DRIVE_UDMA; 1098 } else { 1099 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1100 ATA_CONFIG_UDMA_OFF; 1101 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1102 } 1103 } 1104 } 1105 1106 /* 1107 * downgrade the transfer mode of a drive after an error. return 1 if 1108 * downgrade was possible, 0 otherwise. 1109 */ 1110 int 1111 wdc_downgrade_mode(drvp) 1112 struct ata_drive_datas *drvp; 1113 { 1114 struct channel_softc *chp = drvp->chnl_softc; 1115 struct device *drv_dev = drvp->drv_softc; 1116 struct wdc_softc *wdc = chp->wdc; 1117 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1118 1119 /* if drive or controller don't know its mode, we can't do much */ 1120 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1121 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1122 return 0; 1123 /* current drive mode was set by a config flag, let it this way */ 1124 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1125 (cf_flags & ATA_CONFIG_DMA_SET) || 1126 (cf_flags & ATA_CONFIG_UDMA_SET)) 1127 return 0; 1128 1129 /* 1130 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1131 * Maybe we didn't properly notice the cable type 1132 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1133 * It helps in some cases. 1134 */ 1135 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1136 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1137 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1138 drv_dev->dv_xname, drvp->UDMA_mode); 1139 } 1140 1141 /* 1142 * If we were using ultra-DMA, don't downgrade to multiword DMA 1143 * if we noticed a CRC error. It has been noticed that CRC errors 1144 * in ultra-DMA lead to silent data corruption in multiword DMA. 1145 * Data corruption is less likely to occur in PIO mode. 1146 */ 1147 else if ((drvp->drive_flags & DRIVE_UDMA) && 1148 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1149 drvp->drive_flags &= ~DRIVE_UDMA; 1150 drvp->drive_flags |= DRIVE_DMA; 1151 drvp->DMA_mode = drvp->DMA_cap; 1152 printf("%s: transfer error, downgrading to DMA mode %d\n", 1153 drv_dev->dv_xname, drvp->DMA_mode); 1154 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1155 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1156 drvp->PIO_mode = drvp->PIO_cap; 1157 printf("%s: transfer error, downgrading to PIO mode %d\n", 1158 drv_dev->dv_xname, drvp->PIO_mode); 1159 } else /* already using PIO, can't downgrade */ 1160 return 0; 1161 1162 wdc->set_modes(chp); 1163 /* reset the channel, which will shedule all drives for setup */ 1164 wdc_reset_channel(drvp); 1165 return 1; 1166 } 1167 1168 int 1169 wdc_exec_command(drvp, wdc_c) 1170 struct ata_drive_datas *drvp; 1171 struct wdc_command *wdc_c; 1172 { 1173 struct channel_softc *chp = drvp->chnl_softc; 1174 struct wdc_xfer *xfer; 1175 int s, ret; 1176 1177 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1178 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1179 DEBUG_FUNCS); 1180 1181 /* set up an xfer and queue. Wait for completion */ 1182 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1183 WDC_NOSLEEP); 1184 if (xfer == NULL) { 1185 return WDC_TRY_AGAIN; 1186 } 1187 1188 if (wdc_c->flags & AT_POLL) 1189 xfer->c_flags |= C_POLL; 1190 xfer->drive = drvp->drive; 1191 xfer->databuf = wdc_c->data; 1192 xfer->c_bcount = wdc_c->bcount; 1193 xfer->cmd = wdc_c; 1194 xfer->c_start = __wdccommand_start; 1195 xfer->c_intr = __wdccommand_intr; 1196 xfer->c_kill_xfer = __wdccommand_done; 1197 1198 s = splbio(); 1199 wdc_exec_xfer(chp, xfer); 1200 #ifdef DIAGNOSTIC 1201 if ((wdc_c->flags & AT_POLL) != 0 && 1202 (wdc_c->flags & AT_DONE) == 0) 1203 panic("wdc_exec_command: polled command not done\n"); 1204 #endif 1205 if (wdc_c->flags & AT_DONE) { 1206 ret = WDC_COMPLETE; 1207 } else { 1208 if (wdc_c->flags & AT_WAIT) { 1209 while ((wdc_c->flags & AT_DONE) == 0) { 1210 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1211 } 1212 ret = WDC_COMPLETE; 1213 } else { 1214 ret = WDC_QUEUED; 1215 } 1216 } 1217 splx(s); 1218 return ret; 1219 } 1220 1221 void 1222 __wdccommand_start(chp, xfer) 1223 struct channel_softc *chp; 1224 struct wdc_xfer *xfer; 1225 { 1226 int drive = xfer->drive; 1227 struct wdc_command *wdc_c = xfer->cmd; 1228 1229 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1230 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1231 DEBUG_FUNCS); 1232 1233 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1234 WDSD_IBM | (drive << 4)); 1235 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1236 wdc_c->timeout) != 0) { 1237 wdc_c->flags |= AT_TIMEOU; 1238 __wdccommand_done(chp, xfer); 1239 return; 1240 } 1241 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1242 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1243 if ((wdc_c->flags & AT_POLL) == 0) { 1244 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1245 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1246 wdctimeout, chp); 1247 return; 1248 } 1249 /* 1250 * Polled command. Wait for drive ready or drq. Done in intr(). 1251 * Wait for at last 400ns for status bit to be valid. 1252 */ 1253 delay(10); 1254 __wdccommand_intr(chp, xfer, 0); 1255 } 1256 1257 int 1258 __wdccommand_intr(chp, xfer, irq) 1259 struct channel_softc *chp; 1260 struct wdc_xfer *xfer; 1261 int irq; 1262 { 1263 struct wdc_command *wdc_c = xfer->cmd; 1264 int bcount = wdc_c->bcount; 1265 char *data = wdc_c->data; 1266 1267 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1268 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1269 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1270 (irq == 0) ? wdc_c->timeout : 0)) { 1271 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1272 return 0; /* IRQ was not for us */ 1273 wdc_c->flags |= AT_TIMEOU; 1274 __wdccommand_done(chp, xfer); 1275 return 1; 1276 } 1277 if (wdc_c->flags & AT_READ) { 1278 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1279 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1280 0, (u_int32_t*)data, bcount >> 2); 1281 data += bcount & 0xfffffffc; 1282 bcount = bcount & 0x03; 1283 } 1284 if (bcount > 0) 1285 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1286 wd_data, (u_int16_t *)data, bcount >> 1); 1287 } else if (wdc_c->flags & AT_WRITE) { 1288 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1289 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1290 0, (u_int32_t*)data, bcount >> 2); 1291 data += bcount & 0xfffffffc; 1292 bcount = bcount & 0x03; 1293 } 1294 if (bcount > 0) 1295 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1296 wd_data, (u_int16_t *)data, bcount >> 1); 1297 } 1298 __wdccommand_done(chp, xfer); 1299 return 1; 1300 } 1301 1302 void 1303 __wdccommand_done(chp, xfer) 1304 struct channel_softc *chp; 1305 struct wdc_xfer *xfer; 1306 { 1307 struct wdc_command *wdc_c = xfer->cmd; 1308 1309 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1310 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1311 1312 callout_stop(&chp->ch_callout); 1313 1314 if (chp->ch_status & WDCS_DWF) 1315 wdc_c->flags |= AT_DF; 1316 if (chp->ch_status & WDCS_ERR) { 1317 wdc_c->flags |= AT_ERROR; 1318 wdc_c->r_error = chp->ch_error; 1319 } 1320 wdc_c->flags |= AT_DONE; 1321 if ((wdc_c->flags & AT_READREG) != 0 && 1322 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1323 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1324 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1325 wd_sdh); 1326 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1327 wd_cyl_hi) << 8; 1328 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1329 wd_cyl_lo); 1330 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1331 wd_sector); 1332 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1333 wd_seccnt); 1334 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1335 wd_error); 1336 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1337 wd_precomp); 1338 } 1339 wdc_free_xfer(chp, xfer); 1340 if (wdc_c->flags & AT_WAIT) 1341 wakeup(wdc_c); 1342 else if (wdc_c->callback) 1343 wdc_c->callback(wdc_c->callback_arg); 1344 wdcstart(chp); 1345 return; 1346 } 1347 1348 /* 1349 * Send a command. The drive should be ready. 1350 * Assumes interrupts are blocked. 1351 */ 1352 void 1353 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1354 struct channel_softc *chp; 1355 u_int8_t drive; 1356 u_int8_t command; 1357 u_int16_t cylin; 1358 u_int8_t head, sector, count, precomp; 1359 { 1360 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1361 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1362 chp->channel, drive, command, cylin, head, sector, count, precomp), 1363 DEBUG_FUNCS); 1364 1365 /* Select drive, head, and addressing mode. */ 1366 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1367 WDSD_IBM | (drive << 4) | head); 1368 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1369 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1370 precomp); 1371 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1372 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1373 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1374 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1375 1376 /* Send command. */ 1377 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1378 return; 1379 } 1380 1381 /* 1382 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1383 * tested by the caller. 1384 */ 1385 void 1386 wdccommandshort(chp, drive, command) 1387 struct channel_softc *chp; 1388 int drive; 1389 int command; 1390 { 1391 1392 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1393 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1394 DEBUG_FUNCS); 1395 1396 /* Select drive. */ 1397 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1398 WDSD_IBM | (drive << 4)); 1399 1400 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1401 } 1402 1403 /* Add a command to the queue and start controller. Must be called at splbio */ 1404 1405 void 1406 wdc_exec_xfer(chp, xfer) 1407 struct channel_softc *chp; 1408 struct wdc_xfer *xfer; 1409 { 1410 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1411 chp->channel, xfer->drive), DEBUG_XFERS); 1412 1413 /* complete xfer setup */ 1414 xfer->chp = chp; 1415 1416 /* 1417 * If we are a polled command, and the list is not empty, 1418 * we are doing a dump. Drop the list to allow the polled command 1419 * to complete, we're going to reboot soon anyway. 1420 */ 1421 if ((xfer->c_flags & C_POLL) != 0 && 1422 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1423 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1424 } 1425 /* insert at the end of command list */ 1426 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1427 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1428 chp->ch_flags), DEBUG_XFERS); 1429 wdcstart(chp); 1430 } 1431 1432 struct wdc_xfer * 1433 wdc_get_xfer(flags) 1434 int flags; 1435 { 1436 struct wdc_xfer *xfer; 1437 int s; 1438 1439 s = splbio(); 1440 xfer = pool_get(&wdc_xfer_pool, 1441 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1442 splx(s); 1443 memset(xfer, 0, sizeof(struct wdc_xfer)); 1444 return xfer; 1445 } 1446 1447 void 1448 wdc_free_xfer(chp, xfer) 1449 struct channel_softc *chp; 1450 struct wdc_xfer *xfer; 1451 { 1452 struct wdc_softc *wdc = chp->wdc; 1453 int s; 1454 1455 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1456 (*wdc->free_hw)(chp); 1457 s = splbio(); 1458 chp->ch_flags &= ~WDCF_ACTIVE; 1459 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1460 pool_put(&wdc_xfer_pool, xfer); 1461 splx(s); 1462 } 1463 1464 /* 1465 * Kill off all pending xfers for a channel_softc. 1466 * 1467 * Must be called at splbio(). 1468 */ 1469 void 1470 wdc_kill_pending(chp) 1471 struct channel_softc *chp; 1472 { 1473 struct wdc_xfer *xfer; 1474 1475 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1476 chp = xfer->chp; 1477 (*xfer->c_kill_xfer)(chp, xfer); 1478 } 1479 } 1480 1481 static void 1482 __wdcerror(chp, msg) 1483 struct channel_softc *chp; 1484 char *msg; 1485 { 1486 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1487 if (xfer == NULL) 1488 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1489 msg); 1490 else 1491 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1492 chp->channel, xfer->drive, msg); 1493 } 1494 1495 /* 1496 * the bit bucket 1497 */ 1498 void 1499 wdcbit_bucket(chp, size) 1500 struct channel_softc *chp; 1501 int size; 1502 { 1503 1504 for (; size >= 2; size -= 2) 1505 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1506 if (size) 1507 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1508 } 1509 1510 int 1511 wdc_addref(chp) 1512 struct channel_softc *chp; 1513 { 1514 struct wdc_softc *wdc = chp->wdc; 1515 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1516 int s, error = 0; 1517 1518 s = splbio(); 1519 if (adapter->scsipi_refcnt++ == 0 && 1520 adapter->scsipi_enable != NULL) { 1521 error = (*adapter->scsipi_enable)(wdc, 1); 1522 if (error) 1523 adapter->scsipi_refcnt--; 1524 } 1525 splx(s); 1526 return (error); 1527 } 1528 1529 void 1530 wdc_delref(chp) 1531 struct channel_softc *chp; 1532 { 1533 struct wdc_softc *wdc = chp->wdc; 1534 struct scsipi_adapter *adapter = &wdc->sc_atapi_adapter; 1535 int s; 1536 1537 s = splbio(); 1538 if (adapter->scsipi_refcnt-- == 1 && 1539 adapter->scsipi_enable != NULL) 1540 (void) (*adapter->scsipi_enable)(wdc, 0); 1541 splx(s); 1542 } 1543
Indexes created Fri Sep 26 08:10:20 GMT 2025