wdc.c revision 1.84
1 /* $NetBSD: wdc.c,v 1.84 2000/04/01 14:32:22 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 124 125 #define DEBUG_INTR 0x01 126 #define DEBUG_XFERS 0x02 127 #define DEBUG_STATUS 0x04 128 #define DEBUG_FUNCS 0x08 129 #define DEBUG_PROBE 0x10 130 #define DEBUG_DETACH 0x20 131 #ifdef WDCDEBUG 132 int wdcdebug_mask = 0; 133 int wdc_nxfer = 0; 134 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 135 #else 136 #define WDCDEBUG_PRINT(args, level) 137 #endif 138 139 int 140 wdprint(aux, pnp) 141 void *aux; 142 const char *pnp; 143 { 144 struct ata_atapi_attach *aa_link = aux; 145 if (pnp) 146 printf("drive at %s", pnp); 147 printf(" channel %d drive %d", aa_link->aa_channel, 148 aa_link->aa_drv_data->drive); 149 return (UNCONF); 150 } 151 152 int 153 atapi_print(aux, pnp) 154 void *aux; 155 const char *pnp; 156 { 157 struct ata_atapi_attach *aa_link = aux; 158 if (pnp) 159 printf("atapibus at %s", pnp); 160 printf(" channel %d", aa_link->aa_channel); 161 return (UNCONF); 162 } 163 164 /* Test to see controller with at last one attached drive is there. 165 * Returns a bit for each possible drive found (0x01 for drive 0, 166 * 0x02 for drive 1). 167 * Logic: 168 * - If a status register is at 0xff, assume there is no drive here 169 * (ISA has pull-up resistors). If no drive at all -> return. 170 * - reset the controller, wait for it to complete (may take up to 31s !). 171 * If timeout -> return. 172 * - test ATA/ATAPI signatures. If at last one drive found -> return. 173 * - try an ATA command on the master. 174 */ 175 176 int 177 wdcprobe(chp) 178 struct channel_softc *chp; 179 { 180 u_int8_t st0, st1, sc, sn, cl, ch; 181 u_int8_t ret_value = 0x03; 182 u_int8_t drive; 183 184 /* 185 * Sanity check to see if the wdc channel responds at all. 186 */ 187 188 if (chp->wdc == NULL || 189 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM); 192 delay(10); 193 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 195 WDSD_IBM | 0x10); 196 delay(10); 197 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 198 199 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 200 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 201 chp->channel, st0, st1), DEBUG_PROBE); 202 203 if (st0 == 0xff) 204 ret_value &= ~0x01; 205 if (st1 == 0xff) 206 ret_value &= ~0x02; 207 if (ret_value == 0) 208 return 0; 209 } 210 211 /* assert SRST, wait for reset to complete */ 212 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 213 WDSD_IBM); 214 delay(10); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 216 WDCTL_RST | WDCTL_IDS); 217 DELAY(1000); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 219 WDCTL_IDS); 220 delay(1000); 221 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 222 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 223 delay(10); 224 225 ret_value = __wdcwait_reset(chp, ret_value); 226 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 227 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 228 ret_value), DEBUG_PROBE); 229 230 /* if reset failed, there's nothing here */ 231 if (ret_value == 0) 232 return 0; 233 234 /* 235 * Test presence of drives. First test register signatures looking for 236 * ATAPI devices. If it's not an ATAPI and reset said there may be 237 * something here assume it's ATA or OLD. Ghost will be killed later in 238 * attach routine. 239 */ 240 for (drive = 0; drive < 2; drive++) { 241 if ((ret_value & (0x01 << drive)) == 0) 242 continue; 243 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 244 WDSD_IBM | (drive << 4)); 245 delay(10); 246 /* Save registers contents */ 247 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 248 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 249 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 250 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 251 252 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 253 "cl=0x%x ch=0x%x\n", 254 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 255 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 256 /* 257 * sc is supposted to be 0x1 for ATAPI but at last one drive 258 * set it to 0x0 - or maybe it's the controller. 259 */ 260 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 261 cl == 0x14 && ch == 0xeb) { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 263 } else { 264 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 265 if (chp->wdc == NULL || 266 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 267 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 268 } 269 } 270 return (ret_value); 271 } 272 273 void 274 wdcattach(chp) 275 struct channel_softc *chp; 276 { 277 int channel_flags, ctrl_flags, i, error; 278 struct ata_atapi_attach aa_link; 279 struct ataparams params; 280 static int inited = 0; 281 282 callout_init(&chp->ch_callout); 283 284 if ((error = wdc_addref(chp)) != 0) { 285 printf("%s: unable to enable controller\n", 286 chp->wdc->sc_dev.dv_xname); 287 return; 288 } 289 290 if (wdcprobe(chp) == 0) 291 /* If no drives, abort attach here. */ 292 goto out; 293 294 /* initialise global data */ 295 if (inited == 0) { 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* 307 * Init error counter so that an error withing the first xfers 308 * will trigger a downgrade 309 */ 310 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 311 312 /* If controller can't do 16bit flag the drives as 32bit */ 313 if ((chp->wdc->cap & 314 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 315 WDC_CAPABILITY_DATA32) 316 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 317 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 318 continue; 319 320 /* 321 * Wait a bit, some devices are weird just after a reset. 322 * Then issue a IDENTIFY command, to try to detect slave ghost 323 */ 324 delay(100); 325 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 326 if (error == CMD_OK) { 327 /* If IDENTIFY succeded, this is not an OLD ctrl */ 328 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 329 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 330 } else { 331 chp->ch_drive[i].drive_flags &= 332 ~(DRIVE_ATA | DRIVE_ATAPI); 333 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 334 chp->wdc->sc_dev.dv_xname, 335 chp->channel, i, error), DEBUG_PROBE); 336 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 337 continue; 338 /* 339 * Pre-ATA drive ? 340 * Test registers writability (Error register not 341 * writable, but cyllo is), then try an ATA command. 342 */ 343 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 344 WDSD_IBM | (i << 4)); 345 delay(10); 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 347 wd_error, 0x58); 348 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 349 wd_cyl_lo, 0xa5); 350 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 351 wd_error == 0x58) || 352 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 353 wd_cyl_lo) != 0xa5) { 354 WDCDEBUG_PRINT(("%s:%d:%d: register " 355 "writability failed\n", 356 chp->wdc->sc_dev.dv_xname, 357 chp->channel, i), DEBUG_PROBE); 358 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 359 } 360 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 361 WDSD_IBM | (i << 4)); 362 delay(100); 363 if (wait_for_ready(chp, 10000) != 0) { 364 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 365 chp->wdc->sc_dev.dv_xname, 366 chp->channel, i), DEBUG_PROBE); 367 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 368 continue; 369 } 370 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 371 wd_command, WDCC_RECAL); 372 if (wait_for_ready(chp, 10000) != 0) { 373 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 374 chp->wdc->sc_dev.dv_xname, 375 chp->channel, i), DEBUG_PROBE); 376 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 377 } 378 } 379 } 380 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 381 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 382 383 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 384 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 385 DEBUG_PROBE); 386 387 /* If no drives, abort here */ 388 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 389 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 390 goto out; 391 392 /* 393 * Attach an ATAPI bus, if needed. 394 */ 395 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 396 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 397 #if NATAPIBUS > 0 398 wdc_atapibus_attach(chp); 399 #else 400 /* 401 * Fills in a fake aa_link and call config_found, so that 402 * the config machinery will print 403 * "atapibus at xxx not configured" 404 */ 405 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 406 aa_link.aa_type = T_ATAPI; 407 aa_link.aa_channel = chp->channel; 408 aa_link.aa_openings = 1; 409 aa_link.aa_drv_data = 0; 410 aa_link.aa_bus_private = NULL; 411 chp->atapibus = config_found(&chp->wdc->sc_dev, 412 (void *)&aa_link, atapi_print); 413 #endif 414 } 415 416 for (i = 0; i < 2; i++) { 417 if ((chp->ch_drive[i].drive_flags & 418 (DRIVE_ATA | DRIVE_OLD)) == 0) { 419 continue; 420 } 421 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 422 aa_link.aa_type = T_ATA; 423 aa_link.aa_channel = chp->channel; 424 aa_link.aa_openings = 1; 425 aa_link.aa_drv_data = &chp->ch_drive[i]; 426 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 427 wdc_probe_caps(&chp->ch_drive[i]); 428 } 429 430 /* 431 * reset drive_flags for unnatached devices, reset state for attached 432 * ones 433 */ 434 for (i = 0; i < 2; i++) { 435 if (chp->ch_drive[i].drv_softc == NULL) 436 chp->ch_drive[i].drive_flags = 0; 437 else 438 chp->ch_drive[i].state = 0; 439 } 440 441 /* 442 * Reset channel. The probe, with some combinations of ATA/ATAPI 443 * devices keep it in a mostly working, but strange state (with busy 444 * led on) 445 */ 446 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 447 wdcreset(chp, VERBOSE); 448 /* 449 * Read status registers to avoid spurious interrupts. 450 */ 451 for (i = 1; i >= 0; i--) { 452 if (chp->ch_drive[i].drive_flags & DRIVE) { 453 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 454 wd_sdh, WDSD_IBM | (i << 4)); 455 if (wait_for_unbusy(chp, 10000) < 0) 456 printf("%s:%d:%d: device busy\n", 457 chp->wdc->sc_dev.dv_xname, 458 chp->channel, i); 459 } 460 } 461 } 462 463 out: 464 wdc_delref(chp); 465 } 466 467 /* 468 * Call activate routine of underlying devices. 469 */ 470 int 471 wdcactivate(self, act) 472 struct device *self; 473 enum devact act; 474 { 475 struct wdc_softc *wdc = (struct wdc_softc *)self; 476 struct channel_softc *chp; 477 struct device *sc; 478 int s, i, j, error = 0; 479 480 s = splbio(); 481 switch (act) { 482 case DVACT_ACTIVATE: 483 error = EOPNOTSUPP; 484 break; 485 486 case DVACT_DEACTIVATE: 487 for (i = 0; i < wdc->nchannels; i++) { 488 chp = wdc->channels[i]; 489 490 /* 491 * We might call deactivate routine for 492 * the children of atapibus twice (once via 493 * atapibus, once directly), but since 494 * config_deactivate maintains DVF_ACTIVE flag, 495 * it's safe. 496 */ 497 sc = chp->atapibus; 498 if (sc != NULL) { 499 error = config_deactivate(sc); 500 if (error != 0) 501 goto out; 502 } 503 504 for (j = 0; j < 2; j++) { 505 sc = chp->ch_drive[j].drv_softc; 506 WDCDEBUG_PRINT(("wdcactivate: %s:" 507 " deactivating %s\n", wdc->sc_dev.dv_xname, 508 sc == NULL ? "nodrv" : sc->dv_xname), 509 DEBUG_DETACH); 510 if (sc != NULL) { 511 error = config_deactivate(sc); 512 if (error != 0) 513 goto out; 514 } 515 } 516 } 517 break; 518 } 519 520 out: 521 splx(s); 522 523 #ifdef WDCDEBUG 524 if (error != 0) 525 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 526 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 527 #endif 528 return (error); 529 } 530 531 int 532 wdcdetach(self, flags) 533 struct device *self; 534 int flags; 535 { 536 struct wdc_softc *wdc = (struct wdc_softc *)self; 537 struct channel_softc *chp; 538 struct device *sc; 539 int i, j, error = 0; 540 541 for (i = 0; i < wdc->nchannels; i++) { 542 chp = wdc->channels[i]; 543 544 /* 545 * Detach atapibus and its children. 546 */ 547 sc = chp->atapibus; 548 if (sc != NULL) { 549 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 550 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 551 error = config_detach(sc, flags); 552 if (error != 0) 553 goto out; 554 } 555 556 /* 557 * Detach our other children. 558 */ 559 for (j = 0; j < 2; j++) { 560 sc = chp->ch_drive[j].drv_softc; 561 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 562 wdc->sc_dev.dv_xname, 563 sc == NULL ? "nodrv" : sc->dv_xname), 564 DEBUG_DETACH); 565 if (sc != NULL) { 566 error = config_detach(sc, flags); 567 if (error != 0) 568 goto out; 569 } 570 } 571 572 wdc_kill_pending(chp); 573 } 574 575 out: 576 #ifdef WDCDEBUG 577 if (error != 0) 578 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 579 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 580 #endif 581 return (error); 582 } 583 584 /* 585 * Start I/O on a controller, for the given channel. 586 * The first xfer may be not for our channel if the channel queues 587 * are shared. 588 */ 589 void 590 wdcstart(chp) 591 struct channel_softc *chp; 592 { 593 struct wdc_xfer *xfer; 594 595 #ifdef WDC_DIAGNOSTIC 596 int spl1, spl2; 597 598 spl1 = splbio(); 599 spl2 = splbio(); 600 if (spl2 != spl1) { 601 printf("wdcstart: not at splbio()\n"); 602 panic("wdcstart"); 603 } 604 splx(spl2); 605 splx(spl1); 606 #endif /* WDC_DIAGNOSTIC */ 607 608 /* is there a xfer ? */ 609 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 610 return; 611 612 /* adjust chp, in case we have a shared queue */ 613 chp = xfer->chp; 614 615 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 616 return; /* channel aleady active */ 617 } 618 #ifdef DIAGNOSTIC 619 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 620 panic("wdcstart: channel waiting for irq\n"); 621 #endif 622 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 623 if (!(*chp->wdc->claim_hw)(chp, 0)) 624 return; 625 626 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 627 chp->channel, xfer->drive), DEBUG_XFERS); 628 chp->ch_flags |= WDCF_ACTIVE; 629 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 630 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 631 chp->ch_drive[xfer->drive].state = 0; 632 } 633 xfer->c_start(chp, xfer); 634 } 635 636 /* restart an interrupted I/O */ 637 void 638 wdcrestart(v) 639 void *v; 640 { 641 struct channel_softc *chp = v; 642 int s; 643 644 s = splbio(); 645 wdcstart(chp); 646 splx(s); 647 } 648 649 650 /* 651 * Interrupt routine for the controller. Acknowledge the interrupt, check for 652 * errors on the current operation, mark it done if necessary, and start the 653 * next request. Also check for a partially done transfer, and continue with 654 * the next chunk if so. 655 */ 656 int 657 wdcintr(arg) 658 void *arg; 659 { 660 struct channel_softc *chp = arg; 661 struct wdc_xfer *xfer; 662 int ret; 663 664 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 665 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 666 DEBUG_INTR); 667 return (0); 668 } 669 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 670 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 671 return (0); 672 } 673 674 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 675 xfer = chp->ch_queue->sc_xfer.tqh_first; 676 if (chp->ch_flags & WDCF_DMA_WAIT) { 677 chp->wdc->dma_status = 678 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 679 xfer->drive, 0); 680 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 681 /* IRQ not for us, not detected by DMA engine */ 682 return 0; 683 } 684 chp->ch_flags &= ~WDCF_DMA_WAIT; 685 } 686 chp->ch_flags &= ~WDCF_IRQ_WAIT; 687 ret = xfer->c_intr(chp, xfer, 1); 688 if (ret == 0) /* irq was not for us, still waiting for irq */ 689 chp->ch_flags |= WDCF_IRQ_WAIT; 690 return (ret); 691 } 692 693 /* Put all disk in RESET state */ 694 void wdc_reset_channel(drvp) 695 struct ata_drive_datas *drvp; 696 { 697 struct channel_softc *chp = drvp->chnl_softc; 698 int drive; 699 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 700 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 701 DEBUG_FUNCS); 702 (void) wdcreset(chp, VERBOSE); 703 for (drive = 0; drive < 2; drive++) { 704 chp->ch_drive[drive].state = 0; 705 } 706 } 707 708 int 709 wdcreset(chp, verb) 710 struct channel_softc *chp; 711 int verb; 712 { 713 int drv_mask1, drv_mask2; 714 715 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 716 WDSD_IBM); /* master */ 717 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 718 WDCTL_RST | WDCTL_IDS); 719 delay(1000); 720 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 721 WDCTL_IDS); 722 delay(1000); 723 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 724 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 725 WDCTL_4BIT); 726 727 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 728 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 729 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 730 if (verb && drv_mask2 != drv_mask1) { 731 printf("%s channel %d: reset failed for", 732 chp->wdc->sc_dev.dv_xname, chp->channel); 733 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 734 printf(" drive 0"); 735 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 736 printf(" drive 1"); 737 printf("\n"); 738 } 739 return (drv_mask1 != drv_mask2) ? 1 : 0; 740 } 741 742 static int 743 __wdcwait_reset(chp, drv_mask) 744 struct channel_softc *chp; 745 int drv_mask; 746 { 747 int timeout; 748 u_int8_t st0, st1; 749 #ifdef WDCDEBUG 750 u_int8_t sc0, sn0, cl0, ch0; 751 u_int8_t sc1, sn1, cl1, ch1; 752 #endif 753 /* wait for BSY to deassert */ 754 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 755 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 756 WDSD_IBM); /* master */ 757 delay(10); 758 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 759 #ifdef WDCDEBUG 760 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 761 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 762 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 763 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 764 #endif 765 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 766 WDSD_IBM | 0x10); /* slave */ 767 delay(10); 768 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 769 #ifdef WDCDEBUG 770 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 771 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 772 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 773 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 774 #endif 775 776 if ((drv_mask & 0x01) == 0) { 777 /* no master */ 778 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 779 /* No master, slave is ready, it's done */ 780 goto end; 781 } 782 } else if ((drv_mask & 0x02) == 0) { 783 /* no slave */ 784 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 785 /* No slave, master is ready, it's done */ 786 goto end; 787 } 788 } else { 789 /* Wait for both master and slave to be ready */ 790 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 791 goto end; 792 } 793 } 794 delay(WDCDELAY); 795 } 796 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 797 if (st0 & WDCS_BSY) 798 drv_mask &= ~0x01; 799 if (st1 & WDCS_BSY) 800 drv_mask &= ~0x02; 801 end: 802 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 803 "cl=0x%x ch=0x%x\n", 804 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 805 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 806 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 807 "cl=0x%x ch=0x%x\n", 808 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 809 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 810 811 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 812 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 813 st0, st1), DEBUG_PROBE); 814 815 return drv_mask; 816 } 817 818 /* 819 * Wait for a drive to be !BSY, and have mask in its status register. 820 * return -1 for a timeout after "timeout" ms. 821 */ 822 int 823 wdcwait(chp, mask, bits, timeout) 824 struct channel_softc *chp; 825 int mask, bits, timeout; 826 { 827 u_char status; 828 int time = 0; 829 #ifdef WDCNDELAY_DEBUG 830 extern int cold; 831 #endif 832 833 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 834 :"none", chp->channel), DEBUG_STATUS); 835 chp->ch_error = 0; 836 837 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 838 839 for (;;) { 840 chp->ch_status = status = 841 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 842 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 843 break; 844 if (++time > timeout) { 845 WDCDEBUG_PRINT(("wdcwait: timeout, status %x " 846 "error %x (mask 0x%x bits 0x%x)\n", status, 847 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 848 wd_error), mask, bits), 849 DEBUG_STATUS | DEBUG_PROBE); 850 return -1; 851 } 852 delay(WDCDELAY); 853 } 854 if (status & WDCS_ERR) 855 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 856 wd_error); 857 #ifdef WDCNDELAY_DEBUG 858 /* After autoconfig, there should be no long delays. */ 859 if (!cold && time > WDCNDELAY_DEBUG) { 860 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 861 if (xfer == NULL) 862 printf("%s channel %d: warning: busy-wait took %dus\n", 863 chp->wdc->sc_dev.dv_xname, chp->channel, 864 WDCDELAY * time); 865 else 866 printf("%s:%d:%d: warning: busy-wait took %dus\n", 867 chp->wdc->sc_dev.dv_xname, chp->channel, 868 xfer->drive, 869 WDCDELAY * time); 870 } 871 #endif 872 return 0; 873 } 874 875 /* 876 * Busy-wait for DMA to complete 877 */ 878 int 879 wdc_dmawait(chp, xfer, timeout) 880 struct channel_softc *chp; 881 struct wdc_xfer *xfer; 882 int timeout; 883 { 884 int time; 885 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 886 chp->wdc->dma_status = 887 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 888 chp->channel, xfer->drive, 0); 889 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 890 return 0; 891 delay(WDCDELAY); 892 } 893 /* timeout, force a DMA halt */ 894 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 895 chp->channel, xfer->drive, 1); 896 return 1; 897 } 898 899 void 900 wdctimeout(arg) 901 void *arg; 902 { 903 struct channel_softc *chp = (struct channel_softc *)arg; 904 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 905 int s; 906 907 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 908 909 s = splbio(); 910 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 911 __wdcerror(chp, "lost interrupt"); 912 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 913 "atapi":"ata"); 914 printf("\tc_bcount: %d\n", xfer->c_bcount); 915 printf("\tc_skip: %d\n", xfer->c_skip); 916 if (chp->ch_flags & WDCF_DMA_WAIT) { 917 chp->wdc->dma_status = 918 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 919 chp->channel, xfer->drive, 1); 920 chp->ch_flags &= ~WDCF_DMA_WAIT; 921 } 922 /* 923 * Call the interrupt routine. If we just missed and interrupt, 924 * it will do what's needed. Else, it will take the needed 925 * action (reset the device). 926 * Before that we need to reinstall the timeout callback, 927 * in case it will miss another irq while in this transfer 928 * We arbitray chose it to be 1s 929 */ 930 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 931 xfer->c_flags |= C_TIMEOU; 932 chp->ch_flags &= ~WDCF_IRQ_WAIT; 933 xfer->c_intr(chp, xfer, 1); 934 } else 935 __wdcerror(chp, "missing untimeout"); 936 splx(s); 937 } 938 939 /* 940 * Probe drive's capabilites, for use by the controller later 941 * Assumes drvp points to an existing drive. 942 * XXX this should be a controller-indep function 943 */ 944 void 945 wdc_probe_caps(drvp) 946 struct ata_drive_datas *drvp; 947 { 948 struct ataparams params, params2; 949 struct channel_softc *chp = drvp->chnl_softc; 950 struct device *drv_dev = drvp->drv_softc; 951 struct wdc_softc *wdc = chp->wdc; 952 int i, printed; 953 char *sep = ""; 954 int cf_flags; 955 956 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 957 /* IDENTIFY failed. Can't tell more about the device */ 958 return; 959 } 960 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 961 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 962 /* 963 * Controller claims 16 and 32 bit transfers. 964 * Re-do an IDENTIFY with 32-bit transfers, 965 * and compare results. 966 */ 967 drvp->drive_flags |= DRIVE_CAP32; 968 ata_get_params(drvp, AT_POLL, ¶ms2); 969 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 970 /* Not good. fall back to 16bits */ 971 drvp->drive_flags &= ~DRIVE_CAP32; 972 } else { 973 printf("%s: 32-bit data port", drv_dev->dv_xname); 974 } 975 } 976 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 977 if (params.atap_ata_major > 0x01 && 978 params.atap_ata_major != 0xffff) { 979 for (i = 14; i > 0; i--) { 980 if (params.atap_ata_major & (1 << i)) { 981 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 982 printf("%s: ", drv_dev->dv_xname); 983 else 984 printf(", "); 985 printf("ATA version %d\n", i); 986 drvp->ata_vers = i; 987 break; 988 } 989 } 990 } else 991 #endif 992 if (drvp->drive_flags & DRIVE_CAP32) 993 printf("\n"); 994 995 /* An ATAPI device is at last PIO mode 3 */ 996 if (drvp->drive_flags & DRIVE_ATAPI) 997 drvp->PIO_mode = 3; 998 999 /* 1000 * It's not in the specs, but it seems that some drive 1001 * returns 0xffff in atap_extensions when this field is invalid 1002 */ 1003 if (params.atap_extensions != 0xffff && 1004 (params.atap_extensions & WDC_EXT_MODES)) { 1005 printed = 0; 1006 /* 1007 * XXX some drives report something wrong here (they claim to 1008 * support PIO mode 8 !). As mode is coded on 3 bits in 1009 * SET FEATURE, limit it to 7 (so limit i to 4). 1010 * If higther mode than 7 is found, abort. 1011 */ 1012 for (i = 7; i >= 0; i--) { 1013 if ((params.atap_piomode_supp & (1 << i)) == 0) 1014 continue; 1015 if (i > 4) 1016 return; 1017 /* 1018 * See if mode is accepted. 1019 * If the controller can't set its PIO mode, 1020 * assume the defaults are good, so don't try 1021 * to set it 1022 */ 1023 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1024 if (ata_set_mode(drvp, 0x08 | (i + 3), 1025 AT_POLL) != CMD_OK) 1026 continue; 1027 if (!printed) { 1028 printf("%s: drive supports PIO mode %d", 1029 drv_dev->dv_xname, i + 3); 1030 sep = ","; 1031 printed = 1; 1032 } 1033 /* 1034 * If controller's driver can't set its PIO mode, 1035 * get the highter one for the drive. 1036 */ 1037 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1038 wdc->PIO_cap >= i + 3) { 1039 drvp->PIO_mode = i + 3; 1040 drvp->PIO_cap = i + 3; 1041 break; 1042 } 1043 } 1044 if (!printed) { 1045 /* 1046 * We didn't find a valid PIO mode. 1047 * Assume the values returned for DMA are buggy too 1048 */ 1049 return; 1050 } 1051 drvp->drive_flags |= DRIVE_MODE; 1052 printed = 0; 1053 for (i = 7; i >= 0; i--) { 1054 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1055 continue; 1056 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1057 (wdc->cap & WDC_CAPABILITY_MODE)) 1058 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1059 != CMD_OK) 1060 continue; 1061 if (!printed) { 1062 printf("%s DMA mode %d", sep, i); 1063 sep = ","; 1064 printed = 1; 1065 } 1066 if (wdc->cap & WDC_CAPABILITY_DMA) { 1067 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1068 wdc->DMA_cap < i) 1069 continue; 1070 drvp->DMA_mode = i; 1071 drvp->DMA_cap = i; 1072 drvp->drive_flags |= DRIVE_DMA; 1073 } 1074 break; 1075 } 1076 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1077 printed = 0; 1078 for (i = 7; i >= 0; i--) { 1079 if ((params.atap_udmamode_supp & (1 << i)) 1080 == 0) 1081 continue; 1082 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1083 (wdc->cap & WDC_CAPABILITY_UDMA)) 1084 if (ata_set_mode(drvp, 0x40 | i, 1085 AT_POLL) != CMD_OK) 1086 continue; 1087 if (!printed) { 1088 printf("%s Ultra-DMA mode %d", sep, i); 1089 sep = ","; 1090 printed = 1; 1091 } 1092 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1093 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1094 wdc->UDMA_cap < i) 1095 continue; 1096 drvp->UDMA_mode = i; 1097 drvp->UDMA_cap = i; 1098 drvp->drive_flags |= DRIVE_UDMA; 1099 } 1100 break; 1101 } 1102 } 1103 printf("\n"); 1104 } 1105 1106 /* Try to guess ATA version here, if it didn't get reported */ 1107 if (drvp->ata_vers == 0) { 1108 if (drvp->drive_flags & DRIVE_UDMA) 1109 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1110 else if (drvp->PIO_cap > 2) 1111 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1112 } 1113 cf_flags = drv_dev->dv_cfdata->cf_flags; 1114 if (cf_flags & ATA_CONFIG_PIO_SET) { 1115 drvp->PIO_mode = 1116 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1117 drvp->drive_flags |= DRIVE_MODE; 1118 } 1119 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1120 /* don't care about DMA modes */ 1121 return; 1122 } 1123 if (cf_flags & ATA_CONFIG_DMA_SET) { 1124 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1125 ATA_CONFIG_DMA_DISABLE) { 1126 drvp->drive_flags &= ~DRIVE_DMA; 1127 } else { 1128 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1129 ATA_CONFIG_DMA_OFF; 1130 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1131 } 1132 } 1133 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1134 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1135 ATA_CONFIG_UDMA_DISABLE) { 1136 drvp->drive_flags &= ~DRIVE_UDMA; 1137 } else { 1138 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1139 ATA_CONFIG_UDMA_OFF; 1140 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1141 } 1142 } 1143 } 1144 1145 /* 1146 * downgrade the transfer mode of a drive after an error. return 1 if 1147 * downgrade was possible, 0 otherwise. 1148 */ 1149 int 1150 wdc_downgrade_mode(drvp) 1151 struct ata_drive_datas *drvp; 1152 { 1153 struct channel_softc *chp = drvp->chnl_softc; 1154 struct device *drv_dev = drvp->drv_softc; 1155 struct wdc_softc *wdc = chp->wdc; 1156 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1157 1158 /* if drive or controller don't know its mode, we can't do much */ 1159 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1160 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1161 return 0; 1162 /* current drive mode was set by a config flag, let it this way */ 1163 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1164 (cf_flags & ATA_CONFIG_DMA_SET) || 1165 (cf_flags & ATA_CONFIG_UDMA_SET)) 1166 return 0; 1167 1168 /* 1169 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1170 * Maybe we didn't properly notice the cable type 1171 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1172 * It helps in some cases. 1173 */ 1174 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1175 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1176 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1177 drv_dev->dv_xname, drvp->UDMA_mode); 1178 } 1179 1180 /* 1181 * If we were using ultra-DMA, don't downgrade to multiword DMA 1182 * if we noticed a CRC error. It has been noticed that CRC errors 1183 * in ultra-DMA lead to silent data corruption in multiword DMA. 1184 * Data corruption is less likely to occur in PIO mode. 1185 */ 1186 else if ((drvp->drive_flags & DRIVE_UDMA) && 1187 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1188 drvp->drive_flags &= ~DRIVE_UDMA; 1189 drvp->drive_flags |= DRIVE_DMA; 1190 drvp->DMA_mode = drvp->DMA_cap; 1191 printf("%s: transfer error, downgrading to DMA mode %d\n", 1192 drv_dev->dv_xname, drvp->DMA_mode); 1193 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1194 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1195 drvp->PIO_mode = drvp->PIO_cap; 1196 printf("%s: transfer error, downgrading to PIO mode %d\n", 1197 drv_dev->dv_xname, drvp->PIO_mode); 1198 } else /* already using PIO, can't downgrade */ 1199 return 0; 1200 1201 wdc->set_modes(chp); 1202 /* reset the channel, which will shedule all drives for setup */ 1203 wdc_reset_channel(drvp); 1204 return 1; 1205 } 1206 1207 int 1208 wdc_exec_command(drvp, wdc_c) 1209 struct ata_drive_datas *drvp; 1210 struct wdc_command *wdc_c; 1211 { 1212 struct channel_softc *chp = drvp->chnl_softc; 1213 struct wdc_xfer *xfer; 1214 int s, ret; 1215 1216 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1217 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1218 DEBUG_FUNCS); 1219 1220 /* set up an xfer and queue. Wait for completion */ 1221 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1222 WDC_NOSLEEP); 1223 if (xfer == NULL) { 1224 return WDC_TRY_AGAIN; 1225 } 1226 1227 if (wdc_c->flags & AT_POLL) 1228 xfer->c_flags |= C_POLL; 1229 xfer->drive = drvp->drive; 1230 xfer->databuf = wdc_c->data; 1231 xfer->c_bcount = wdc_c->bcount; 1232 xfer->cmd = wdc_c; 1233 xfer->c_start = __wdccommand_start; 1234 xfer->c_intr = __wdccommand_intr; 1235 xfer->c_kill_xfer = __wdccommand_done; 1236 1237 s = splbio(); 1238 wdc_exec_xfer(chp, xfer); 1239 #ifdef DIAGNOSTIC 1240 if ((wdc_c->flags & AT_POLL) != 0 && 1241 (wdc_c->flags & AT_DONE) == 0) 1242 panic("wdc_exec_command: polled command not done\n"); 1243 #endif 1244 if (wdc_c->flags & AT_DONE) { 1245 ret = WDC_COMPLETE; 1246 } else { 1247 if (wdc_c->flags & AT_WAIT) { 1248 while ((wdc_c->flags & AT_DONE) == 0) { 1249 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1250 } 1251 ret = WDC_COMPLETE; 1252 } else { 1253 ret = WDC_QUEUED; 1254 } 1255 } 1256 splx(s); 1257 return ret; 1258 } 1259 1260 void 1261 __wdccommand_start(chp, xfer) 1262 struct channel_softc *chp; 1263 struct wdc_xfer *xfer; 1264 { 1265 int drive = xfer->drive; 1266 struct wdc_command *wdc_c = xfer->cmd; 1267 1268 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1269 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1270 DEBUG_FUNCS); 1271 1272 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1273 WDSD_IBM | (drive << 4)); 1274 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1275 wdc_c->timeout) != 0) { 1276 wdc_c->flags |= AT_TIMEOU; 1277 __wdccommand_done(chp, xfer); 1278 return; 1279 } 1280 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1281 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1282 if ((wdc_c->flags & AT_POLL) == 0) { 1283 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1284 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1285 wdctimeout, chp); 1286 return; 1287 } 1288 /* 1289 * Polled command. Wait for drive ready or drq. Done in intr(). 1290 * Wait for at last 400ns for status bit to be valid. 1291 */ 1292 delay(10); 1293 __wdccommand_intr(chp, xfer, 0); 1294 } 1295 1296 int 1297 __wdccommand_intr(chp, xfer, irq) 1298 struct channel_softc *chp; 1299 struct wdc_xfer *xfer; 1300 int irq; 1301 { 1302 struct wdc_command *wdc_c = xfer->cmd; 1303 int bcount = wdc_c->bcount; 1304 char *data = wdc_c->data; 1305 1306 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1307 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1308 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1309 (irq == 0) ? wdc_c->timeout : 0)) { 1310 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1311 return 0; /* IRQ was not for us */ 1312 wdc_c->flags |= AT_TIMEOU; 1313 __wdccommand_done(chp, xfer); 1314 return 1; 1315 } 1316 if (wdc_c->flags & AT_READ) { 1317 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1318 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1319 0, (u_int32_t*)data, bcount >> 2); 1320 data += bcount & 0xfffffffc; 1321 bcount = bcount & 0x03; 1322 } 1323 if (bcount > 0) 1324 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1325 wd_data, (u_int16_t *)data, bcount >> 1); 1326 } else if (wdc_c->flags & AT_WRITE) { 1327 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1328 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1329 0, (u_int32_t*)data, bcount >> 2); 1330 data += bcount & 0xfffffffc; 1331 bcount = bcount & 0x03; 1332 } 1333 if (bcount > 0) 1334 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1335 wd_data, (u_int16_t *)data, bcount >> 1); 1336 } 1337 __wdccommand_done(chp, xfer); 1338 return 1; 1339 } 1340 1341 void 1342 __wdccommand_done(chp, xfer) 1343 struct channel_softc *chp; 1344 struct wdc_xfer *xfer; 1345 { 1346 struct wdc_command *wdc_c = xfer->cmd; 1347 1348 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1349 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1350 1351 callout_stop(&chp->ch_callout); 1352 1353 if (chp->ch_status & WDCS_DWF) 1354 wdc_c->flags |= AT_DF; 1355 if (chp->ch_status & WDCS_ERR) { 1356 wdc_c->flags |= AT_ERROR; 1357 wdc_c->r_error = chp->ch_error; 1358 } 1359 wdc_c->flags |= AT_DONE; 1360 if ((wdc_c->flags & AT_READREG) != 0 && 1361 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1362 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1363 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1364 wd_sdh); 1365 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1366 wd_cyl_hi) << 8; 1367 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1368 wd_cyl_lo); 1369 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1370 wd_sector); 1371 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1372 wd_seccnt); 1373 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1374 wd_error); 1375 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1376 wd_precomp); 1377 } 1378 wdc_free_xfer(chp, xfer); 1379 if (wdc_c->flags & AT_WAIT) 1380 wakeup(wdc_c); 1381 else if (wdc_c->callback) 1382 wdc_c->callback(wdc_c->callback_arg); 1383 wdcstart(chp); 1384 return; 1385 } 1386 1387 /* 1388 * Send a command. The drive should be ready. 1389 * Assumes interrupts are blocked. 1390 */ 1391 void 1392 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1393 struct channel_softc *chp; 1394 u_int8_t drive; 1395 u_int8_t command; 1396 u_int16_t cylin; 1397 u_int8_t head, sector, count, precomp; 1398 { 1399 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1400 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1401 chp->channel, drive, command, cylin, head, sector, count, precomp), 1402 DEBUG_FUNCS); 1403 1404 /* Select drive, head, and addressing mode. */ 1405 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1406 WDSD_IBM | (drive << 4) | head); 1407 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1408 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1409 precomp); 1410 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1411 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1412 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1413 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1414 1415 /* Send command. */ 1416 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1417 return; 1418 } 1419 1420 /* 1421 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1422 * tested by the caller. 1423 */ 1424 void 1425 wdccommandshort(chp, drive, command) 1426 struct channel_softc *chp; 1427 int drive; 1428 int command; 1429 { 1430 1431 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1432 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1433 DEBUG_FUNCS); 1434 1435 /* Select drive. */ 1436 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1437 WDSD_IBM | (drive << 4)); 1438 1439 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1440 } 1441 1442 /* Add a command to the queue and start controller. Must be called at splbio */ 1443 1444 void 1445 wdc_exec_xfer(chp, xfer) 1446 struct channel_softc *chp; 1447 struct wdc_xfer *xfer; 1448 { 1449 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1450 chp->channel, xfer->drive), DEBUG_XFERS); 1451 1452 /* complete xfer setup */ 1453 xfer->chp = chp; 1454 1455 /* 1456 * If we are a polled command, and the list is not empty, 1457 * we are doing a dump. Drop the list to allow the polled command 1458 * to complete, we're going to reboot soon anyway. 1459 */ 1460 if ((xfer->c_flags & C_POLL) != 0 && 1461 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1462 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1463 } 1464 /* insert at the end of command list */ 1465 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1466 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1467 chp->ch_flags), DEBUG_XFERS); 1468 wdcstart(chp); 1469 } 1470 1471 struct wdc_xfer * 1472 wdc_get_xfer(flags) 1473 int flags; 1474 { 1475 struct wdc_xfer *xfer; 1476 int s; 1477 1478 s = splbio(); 1479 xfer = pool_get(&wdc_xfer_pool, 1480 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1481 splx(s); 1482 memset(xfer, 0, sizeof(struct wdc_xfer)); 1483 return xfer; 1484 } 1485 1486 void 1487 wdc_free_xfer(chp, xfer) 1488 struct channel_softc *chp; 1489 struct wdc_xfer *xfer; 1490 { 1491 struct wdc_softc *wdc = chp->wdc; 1492 int s; 1493 1494 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1495 (*wdc->free_hw)(chp); 1496 s = splbio(); 1497 chp->ch_flags &= ~WDCF_ACTIVE; 1498 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1499 pool_put(&wdc_xfer_pool, xfer); 1500 splx(s); 1501 } 1502 1503 /* 1504 * Kill off all pending xfers for a channel_softc. 1505 * 1506 * Must be called at splbio(). 1507 */ 1508 void 1509 wdc_kill_pending(chp) 1510 struct channel_softc *chp; 1511 { 1512 struct wdc_xfer *xfer; 1513 1514 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1515 chp = xfer->chp; 1516 (*xfer->c_kill_xfer)(chp, xfer); 1517 } 1518 } 1519 1520 static void 1521 __wdcerror(chp, msg) 1522 struct channel_softc *chp; 1523 char *msg; 1524 { 1525 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1526 if (xfer == NULL) 1527 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1528 msg); 1529 else 1530 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1531 chp->channel, xfer->drive, msg); 1532 } 1533 1534 /* 1535 * the bit bucket 1536 */ 1537 void 1538 wdcbit_bucket(chp, size) 1539 struct channel_softc *chp; 1540 int size; 1541 { 1542 1543 for (; size >= 2; size -= 2) 1544 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1545 if (size) 1546 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1547 } 1548 1549 int 1550 wdc_addref(chp) 1551 struct channel_softc *chp; 1552 { 1553 struct wdc_softc *wdc = chp->wdc; 1554 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1555 int s, error = 0; 1556 1557 s = splbio(); 1558 if (adapter->_generic.scsipi_refcnt++ == 0 && 1559 adapter->_generic.scsipi_enable != NULL) { 1560 error = (*adapter->_generic.scsipi_enable)(wdc, 1); 1561 if (error) 1562 adapter->_generic.scsipi_refcnt--; 1563 } 1564 splx(s); 1565 return (error); 1566 } 1567 1568 void 1569 wdc_delref(chp) 1570 struct channel_softc *chp; 1571 { 1572 struct wdc_softc *wdc = chp->wdc; 1573 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1574 int s; 1575 1576 s = splbio(); 1577 if (adapter->_generic.scsipi_refcnt-- == 1 && 1578 adapter->_generic.scsipi_enable != NULL) 1579 (void) (*adapter->_generic.scsipi_enable)(wdc, 0); 1580 splx(s); 1581 } 1582
Indexes created Wed Sep 24 05:09:52 GMT 2025