wdc.c revision 1.88
1 /* $NetBSD: wdc.c,v 1.88 2000/04/05 06:27:36 mrg Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 124 125 #define DEBUG_INTR 0x01 126 #define DEBUG_XFERS 0x02 127 #define DEBUG_STATUS 0x04 128 #define DEBUG_FUNCS 0x08 129 #define DEBUG_PROBE 0x10 130 #define DEBUG_DETACH 0x20 131 #define DEBUG_DELAY 0x40 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc is supposted to be 0x1 for ATAPI but at last one drive 259 * set it to 0x0 - or maybe it's the controller. 260 */ 261 if ((sc == 0x00 || sc == 0x01) && sn == 0x01 && 262 cl == 0x14 && ch == 0xeb) { 263 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 264 } else { 265 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 266 if (chp->wdc == NULL || 267 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 268 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 269 } 270 } 271 return (ret_value); 272 } 273 274 void 275 wdcattach(chp) 276 struct channel_softc *chp; 277 { 278 int channel_flags, ctrl_flags, i, error; 279 struct ata_atapi_attach aa_link; 280 struct ataparams params; 281 static int inited = 0; 282 283 callout_init(&chp->ch_callout); 284 285 if ((error = wdc_addref(chp)) != 0) { 286 printf("%s: unable to enable controller\n", 287 chp->wdc->sc_dev.dv_xname); 288 return; 289 } 290 291 if (wdcprobe(chp) == 0) 292 /* If no drives, abort attach here. */ 293 goto out; 294 295 /* initialise global data */ 296 if (inited == 0) { 297 /* Initialize the wdc_xfer pool. */ 298 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 299 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 300 inited++; 301 } 302 TAILQ_INIT(&chp->ch_queue->sc_xfer); 303 304 for (i = 0; i < 2; i++) { 305 chp->ch_drive[i].chnl_softc = chp; 306 chp->ch_drive[i].drive = i; 307 /* 308 * Init error counter so that an error withing the first xfers 309 * will trigger a downgrade 310 */ 311 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 312 313 /* If controller can't do 16bit flag the drives as 32bit */ 314 if ((chp->wdc->cap & 315 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 316 WDC_CAPABILITY_DATA32) 317 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 318 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 319 continue; 320 321 /* 322 * Wait a bit, some devices are weird just after a reset. 323 * Then issue a IDENTIFY command, to try to detect slave ghost 324 */ 325 delay(100); 326 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 327 if (error != CMD_OK) { 328 delay(1000000); 329 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 330 ¶ms); 331 } 332 if (error == CMD_OK) { 333 /* If IDENTIFY succeded, this is not an OLD ctrl */ 334 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 335 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 336 } else { 337 chp->ch_drive[i].drive_flags &= 338 ~(DRIVE_ATA | DRIVE_ATAPI); 339 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 340 chp->wdc->sc_dev.dv_xname, 341 chp->channel, i, error), DEBUG_PROBE); 342 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 343 continue; 344 /* 345 * Pre-ATA drive ? 346 * Test registers writability (Error register not 347 * writable, but cyllo is), then try an ATA command. 348 */ 349 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 350 WDSD_IBM | (i << 4)); 351 delay(10); 352 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 353 wd_error, 0x58); 354 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 355 wd_cyl_lo, 0xa5); 356 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 357 wd_error == 0x58) || 358 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 359 wd_cyl_lo) != 0xa5) { 360 WDCDEBUG_PRINT(("%s:%d:%d: register " 361 "writability failed\n", 362 chp->wdc->sc_dev.dv_xname, 363 chp->channel, i), DEBUG_PROBE); 364 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 365 } 366 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 367 WDSD_IBM | (i << 4)); 368 delay(100); 369 if (wait_for_ready(chp, 10000) != 0) { 370 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 371 chp->wdc->sc_dev.dv_xname, 372 chp->channel, i), DEBUG_PROBE); 373 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 374 continue; 375 } 376 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 377 wd_command, WDCC_RECAL); 378 if (wait_for_ready(chp, 10000) != 0) { 379 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 380 chp->wdc->sc_dev.dv_xname, 381 chp->channel, i), DEBUG_PROBE); 382 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 383 } 384 } 385 } 386 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 387 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 388 389 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 390 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 391 DEBUG_PROBE); 392 393 /* If no drives, abort here */ 394 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 395 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 396 goto out; 397 398 /* 399 * Attach an ATAPI bus, if needed. 400 */ 401 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 402 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 403 #if NATAPIBUS > 0 404 wdc_atapibus_attach(chp); 405 #else 406 /* 407 * Fills in a fake aa_link and call config_found, so that 408 * the config machinery will print 409 * "atapibus at xxx not configured" 410 */ 411 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 412 aa_link.aa_type = T_ATAPI; 413 aa_link.aa_channel = chp->channel; 414 aa_link.aa_openings = 1; 415 aa_link.aa_drv_data = 0; 416 aa_link.aa_bus_private = NULL; 417 chp->atapibus = config_found(&chp->wdc->sc_dev, 418 (void *)&aa_link, atapi_print); 419 #endif 420 } 421 422 for (i = 0; i < 2; i++) { 423 if ((chp->ch_drive[i].drive_flags & 424 (DRIVE_ATA | DRIVE_OLD)) == 0) { 425 continue; 426 } 427 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 428 aa_link.aa_type = T_ATA; 429 aa_link.aa_channel = chp->channel; 430 aa_link.aa_openings = 1; 431 aa_link.aa_drv_data = &chp->ch_drive[i]; 432 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 433 wdc_probe_caps(&chp->ch_drive[i]); 434 } 435 436 /* 437 * reset drive_flags for unnatached devices, reset state for attached 438 * ones 439 */ 440 for (i = 0; i < 2; i++) { 441 if (chp->ch_drive[i].drv_softc == NULL) 442 chp->ch_drive[i].drive_flags = 0; 443 else 444 chp->ch_drive[i].state = 0; 445 } 446 447 /* 448 * Reset channel. The probe, with some combinations of ATA/ATAPI 449 * devices keep it in a mostly working, but strange state (with busy 450 * led on) 451 */ 452 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 453 wdcreset(chp, VERBOSE); 454 /* 455 * Read status registers to avoid spurious interrupts. 456 */ 457 for (i = 1; i >= 0; i--) { 458 if (chp->ch_drive[i].drive_flags & DRIVE) { 459 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 460 wd_sdh, WDSD_IBM | (i << 4)); 461 if (wait_for_unbusy(chp, 10000) < 0) 462 printf("%s:%d:%d: device busy\n", 463 chp->wdc->sc_dev.dv_xname, 464 chp->channel, i); 465 } 466 } 467 } 468 469 out: 470 wdc_delref(chp); 471 } 472 473 /* 474 * Call activate routine of underlying devices. 475 */ 476 int 477 wdcactivate(self, act) 478 struct device *self; 479 enum devact act; 480 { 481 struct wdc_softc *wdc = (struct wdc_softc *)self; 482 struct channel_softc *chp; 483 struct device *sc = 0; 484 int s, i, j, error = 0; 485 486 s = splbio(); 487 switch (act) { 488 case DVACT_ACTIVATE: 489 error = EOPNOTSUPP; 490 break; 491 492 case DVACT_DEACTIVATE: 493 for (i = 0; i < wdc->nchannels; i++) { 494 chp = wdc->channels[i]; 495 496 /* 497 * We might call deactivate routine for 498 * the children of atapibus twice (once via 499 * atapibus, once directly), but since 500 * config_deactivate maintains DVF_ACTIVE flag, 501 * it's safe. 502 */ 503 sc = chp->atapibus; 504 if (sc != NULL) { 505 error = config_deactivate(sc); 506 if (error != 0) 507 goto out; 508 } 509 510 for (j = 0; j < 2; j++) { 511 sc = chp->ch_drive[j].drv_softc; 512 WDCDEBUG_PRINT(("wdcactivate: %s:" 513 " deactivating %s\n", wdc->sc_dev.dv_xname, 514 sc == NULL ? "nodrv" : sc->dv_xname), 515 DEBUG_DETACH); 516 if (sc != NULL) { 517 error = config_deactivate(sc); 518 if (error != 0) 519 goto out; 520 } 521 } 522 } 523 break; 524 } 525 526 out: 527 splx(s); 528 529 #ifdef WDCDEBUG 530 if (sc && error != 0) 531 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 532 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 533 #endif 534 return (error); 535 } 536 537 int 538 wdcdetach(self, flags) 539 struct device *self; 540 int flags; 541 { 542 struct wdc_softc *wdc = (struct wdc_softc *)self; 543 struct channel_softc *chp; 544 struct device *sc = 0; 545 int i, j, error = 0; 546 547 for (i = 0; i < wdc->nchannels; i++) { 548 chp = wdc->channels[i]; 549 550 /* 551 * Detach atapibus and its children. 552 */ 553 sc = chp->atapibus; 554 if (sc != NULL) { 555 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 556 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 557 error = config_detach(sc, flags); 558 if (error != 0) 559 goto out; 560 } 561 562 /* 563 * Detach our other children. 564 */ 565 for (j = 0; j < 2; j++) { 566 sc = chp->ch_drive[j].drv_softc; 567 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 568 wdc->sc_dev.dv_xname, 569 sc == NULL ? "nodrv" : sc->dv_xname), 570 DEBUG_DETACH); 571 if (sc != NULL) { 572 error = config_detach(sc, flags); 573 if (error != 0) 574 goto out; 575 } 576 } 577 578 wdc_kill_pending(chp); 579 } 580 581 out: 582 #ifdef WDCDEBUG 583 if (sc && error != 0) 584 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 585 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 586 #endif 587 return (error); 588 } 589 590 /* 591 * Start I/O on a controller, for the given channel. 592 * The first xfer may be not for our channel if the channel queues 593 * are shared. 594 */ 595 void 596 wdcstart(chp) 597 struct channel_softc *chp; 598 { 599 struct wdc_xfer *xfer; 600 601 #ifdef WDC_DIAGNOSTIC 602 int spl1, spl2; 603 604 spl1 = splbio(); 605 spl2 = splbio(); 606 if (spl2 != spl1) { 607 printf("wdcstart: not at splbio()\n"); 608 panic("wdcstart"); 609 } 610 splx(spl2); 611 splx(spl1); 612 #endif /* WDC_DIAGNOSTIC */ 613 614 /* is there a xfer ? */ 615 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 616 return; 617 618 /* adjust chp, in case we have a shared queue */ 619 chp = xfer->chp; 620 621 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 622 return; /* channel aleady active */ 623 } 624 #ifdef DIAGNOSTIC 625 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 626 panic("wdcstart: channel waiting for irq\n"); 627 #endif 628 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 629 if (!(*chp->wdc->claim_hw)(chp, 0)) 630 return; 631 632 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 633 chp->channel, xfer->drive), DEBUG_XFERS); 634 chp->ch_flags |= WDCF_ACTIVE; 635 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 636 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 637 chp->ch_drive[xfer->drive].state = 0; 638 } 639 xfer->c_start(chp, xfer); 640 } 641 642 /* restart an interrupted I/O */ 643 void 644 wdcrestart(v) 645 void *v; 646 { 647 struct channel_softc *chp = v; 648 int s; 649 650 s = splbio(); 651 wdcstart(chp); 652 splx(s); 653 } 654 655 656 /* 657 * Interrupt routine for the controller. Acknowledge the interrupt, check for 658 * errors on the current operation, mark it done if necessary, and start the 659 * next request. Also check for a partially done transfer, and continue with 660 * the next chunk if so. 661 */ 662 int 663 wdcintr(arg) 664 void *arg; 665 { 666 struct channel_softc *chp = arg; 667 struct wdc_xfer *xfer; 668 int ret; 669 670 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 671 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 672 DEBUG_INTR); 673 return (0); 674 } 675 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 676 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 677 return (0); 678 } 679 680 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 681 xfer = chp->ch_queue->sc_xfer.tqh_first; 682 if (chp->ch_flags & WDCF_DMA_WAIT) { 683 chp->wdc->dma_status = 684 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 685 xfer->drive, 0); 686 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 687 /* IRQ not for us, not detected by DMA engine */ 688 return 0; 689 } 690 chp->ch_flags &= ~WDCF_DMA_WAIT; 691 } 692 chp->ch_flags &= ~WDCF_IRQ_WAIT; 693 ret = xfer->c_intr(chp, xfer, 1); 694 if (ret == 0) /* irq was not for us, still waiting for irq */ 695 chp->ch_flags |= WDCF_IRQ_WAIT; 696 return (ret); 697 } 698 699 /* Put all disk in RESET state */ 700 void wdc_reset_channel(drvp) 701 struct ata_drive_datas *drvp; 702 { 703 struct channel_softc *chp = drvp->chnl_softc; 704 int drive; 705 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 706 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 707 DEBUG_FUNCS); 708 (void) wdcreset(chp, VERBOSE); 709 for (drive = 0; drive < 2; drive++) { 710 chp->ch_drive[drive].state = 0; 711 } 712 } 713 714 int 715 wdcreset(chp, verb) 716 struct channel_softc *chp; 717 int verb; 718 { 719 int drv_mask1, drv_mask2; 720 721 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 722 WDSD_IBM); /* master */ 723 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 724 WDCTL_RST | WDCTL_IDS); 725 delay(1000); 726 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 727 WDCTL_IDS); 728 delay(1000); 729 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 730 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 731 WDCTL_4BIT); 732 733 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 734 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 735 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 736 if (verb && drv_mask2 != drv_mask1) { 737 printf("%s channel %d: reset failed for", 738 chp->wdc->sc_dev.dv_xname, chp->channel); 739 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 740 printf(" drive 0"); 741 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 742 printf(" drive 1"); 743 printf("\n"); 744 } 745 return (drv_mask1 != drv_mask2) ? 1 : 0; 746 } 747 748 static int 749 __wdcwait_reset(chp, drv_mask) 750 struct channel_softc *chp; 751 int drv_mask; 752 { 753 int timeout; 754 u_int8_t st0, st1; 755 #ifdef WDCDEBUG 756 u_int8_t sc0, sn0, cl0, ch0; 757 u_int8_t sc1, sn1, cl1, ch1; 758 #endif 759 /* wait for BSY to deassert */ 760 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 761 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 762 WDSD_IBM); /* master */ 763 delay(10); 764 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 765 #ifdef WDCDEBUG 766 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 767 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 768 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 769 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 770 #endif 771 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 772 WDSD_IBM | 0x10); /* slave */ 773 delay(10); 774 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 775 #ifdef WDCDEBUG 776 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 777 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 778 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 779 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 780 #endif 781 782 if ((drv_mask & 0x01) == 0) { 783 /* no master */ 784 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 785 /* No master, slave is ready, it's done */ 786 goto end; 787 } 788 } else if ((drv_mask & 0x02) == 0) { 789 /* no slave */ 790 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 791 /* No slave, master is ready, it's done */ 792 goto end; 793 } 794 } else { 795 /* Wait for both master and slave to be ready */ 796 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 797 goto end; 798 } 799 } 800 delay(WDCDELAY); 801 } 802 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 803 if (st0 & WDCS_BSY) 804 drv_mask &= ~0x01; 805 if (st1 & WDCS_BSY) 806 drv_mask &= ~0x02; 807 end: 808 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 809 "cl=0x%x ch=0x%x\n", 810 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 811 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 812 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 813 "cl=0x%x ch=0x%x\n", 814 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 815 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 816 817 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 818 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 819 st0, st1), DEBUG_PROBE); 820 821 return drv_mask; 822 } 823 824 /* 825 * Wait for a drive to be !BSY, and have mask in its status register. 826 * return -1 for a timeout after "timeout" ms. 827 */ 828 int 829 wdcwait(chp, mask, bits, timeout) 830 struct channel_softc *chp; 831 int mask, bits, timeout; 832 { 833 u_char status; 834 int time = 0; 835 #ifdef WDCNDELAY_DEBUG 836 extern int cold; 837 #endif 838 839 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 840 :"none", chp->channel), DEBUG_STATUS); 841 chp->ch_error = 0; 842 843 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 844 845 for (;;) { 846 chp->ch_status = status = 847 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 848 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 849 break; 850 if (++time > timeout) { 851 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 852 "status %x error %x (mask 0x%x bits 0x%x)\n", 853 time, status, 854 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 855 wd_error), mask, bits), 856 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 857 return -1; 858 } 859 delay(WDCDELAY); 860 } 861 #ifdef WDCDEBUG 862 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 863 printf("wdcwait: did busy-wait, time=%d\n", time); 864 #endif 865 if (status & WDCS_ERR) 866 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 867 wd_error); 868 #ifdef WDCNDELAY_DEBUG 869 /* After autoconfig, there should be no long delays. */ 870 if (!cold && time > WDCNDELAY_DEBUG) { 871 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 872 if (xfer == NULL) 873 printf("%s channel %d: warning: busy-wait took %dus\n", 874 chp->wdc->sc_dev.dv_xname, chp->channel, 875 WDCDELAY * time); 876 else 877 printf("%s:%d:%d: warning: busy-wait took %dus\n", 878 chp->wdc->sc_dev.dv_xname, chp->channel, 879 xfer->drive, 880 WDCDELAY * time); 881 } 882 #endif 883 return 0; 884 } 885 886 /* 887 * Busy-wait for DMA to complete 888 */ 889 int 890 wdc_dmawait(chp, xfer, timeout) 891 struct channel_softc *chp; 892 struct wdc_xfer *xfer; 893 int timeout; 894 { 895 int time; 896 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 897 chp->wdc->dma_status = 898 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 899 chp->channel, xfer->drive, 0); 900 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 901 return 0; 902 delay(WDCDELAY); 903 } 904 /* timeout, force a DMA halt */ 905 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 906 chp->channel, xfer->drive, 1); 907 return 1; 908 } 909 910 void 911 wdctimeout(arg) 912 void *arg; 913 { 914 struct channel_softc *chp = (struct channel_softc *)arg; 915 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 916 int s; 917 918 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 919 920 s = splbio(); 921 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 922 __wdcerror(chp, "lost interrupt"); 923 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 924 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 925 xfer->c_bcount, 926 xfer->c_skip); 927 if (chp->ch_flags & WDCF_DMA_WAIT) { 928 chp->wdc->dma_status = 929 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 930 chp->channel, xfer->drive, 1); 931 chp->ch_flags &= ~WDCF_DMA_WAIT; 932 } 933 /* 934 * Call the interrupt routine. If we just missed and interrupt, 935 * it will do what's needed. Else, it will take the needed 936 * action (reset the device). 937 * Before that we need to reinstall the timeout callback, 938 * in case it will miss another irq while in this transfer 939 * We arbitray chose it to be 1s 940 */ 941 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 942 xfer->c_flags |= C_TIMEOU; 943 chp->ch_flags &= ~WDCF_IRQ_WAIT; 944 xfer->c_intr(chp, xfer, 1); 945 } else 946 __wdcerror(chp, "missing untimeout"); 947 splx(s); 948 } 949 950 /* 951 * Probe drive's capabilites, for use by the controller later 952 * Assumes drvp points to an existing drive. 953 * XXX this should be a controller-indep function 954 */ 955 void 956 wdc_probe_caps(drvp) 957 struct ata_drive_datas *drvp; 958 { 959 struct ataparams params, params2; 960 struct channel_softc *chp = drvp->chnl_softc; 961 struct device *drv_dev = drvp->drv_softc; 962 struct wdc_softc *wdc = chp->wdc; 963 int i, printed; 964 char *sep = ""; 965 int cf_flags; 966 967 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 968 /* IDENTIFY failed. Can't tell more about the device */ 969 return; 970 } 971 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 972 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 973 /* 974 * Controller claims 16 and 32 bit transfers. 975 * Re-do an IDENTIFY with 32-bit transfers, 976 * and compare results. 977 */ 978 drvp->drive_flags |= DRIVE_CAP32; 979 ata_get_params(drvp, AT_POLL, ¶ms2); 980 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 981 /* Not good. fall back to 16bits */ 982 drvp->drive_flags &= ~DRIVE_CAP32; 983 } else { 984 printf("%s: 32-bit data port", drv_dev->dv_xname); 985 } 986 } 987 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 988 if (params.atap_ata_major > 0x01 && 989 params.atap_ata_major != 0xffff) { 990 for (i = 14; i > 0; i--) { 991 if (params.atap_ata_major & (1 << i)) { 992 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 993 printf("%s: ", drv_dev->dv_xname); 994 else 995 printf(", "); 996 printf("ATA version %d\n", i); 997 drvp->ata_vers = i; 998 break; 999 } 1000 } 1001 } else 1002 #endif 1003 if (drvp->drive_flags & DRIVE_CAP32) 1004 printf("\n"); 1005 1006 /* An ATAPI device is at last PIO mode 3 */ 1007 if (drvp->drive_flags & DRIVE_ATAPI) 1008 drvp->PIO_mode = 3; 1009 1010 /* 1011 * It's not in the specs, but it seems that some drive 1012 * returns 0xffff in atap_extensions when this field is invalid 1013 */ 1014 if (params.atap_extensions != 0xffff && 1015 (params.atap_extensions & WDC_EXT_MODES)) { 1016 printed = 0; 1017 /* 1018 * XXX some drives report something wrong here (they claim to 1019 * support PIO mode 8 !). As mode is coded on 3 bits in 1020 * SET FEATURE, limit it to 7 (so limit i to 4). 1021 * If higther mode than 7 is found, abort. 1022 */ 1023 for (i = 7; i >= 0; i--) { 1024 if ((params.atap_piomode_supp & (1 << i)) == 0) 1025 continue; 1026 if (i > 4) 1027 return; 1028 /* 1029 * See if mode is accepted. 1030 * If the controller can't set its PIO mode, 1031 * assume the defaults are good, so don't try 1032 * to set it 1033 */ 1034 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1035 if (ata_set_mode(drvp, 0x08 | (i + 3), 1036 AT_POLL) != CMD_OK) 1037 continue; 1038 if (!printed) { 1039 printf("%s: drive supports PIO mode %d", 1040 drv_dev->dv_xname, i + 3); 1041 sep = ","; 1042 printed = 1; 1043 } 1044 /* 1045 * If controller's driver can't set its PIO mode, 1046 * get the highter one for the drive. 1047 */ 1048 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1049 wdc->PIO_cap >= i + 3) { 1050 drvp->PIO_mode = i + 3; 1051 drvp->PIO_cap = i + 3; 1052 break; 1053 } 1054 } 1055 if (!printed) { 1056 /* 1057 * We didn't find a valid PIO mode. 1058 * Assume the values returned for DMA are buggy too 1059 */ 1060 return; 1061 } 1062 drvp->drive_flags |= DRIVE_MODE; 1063 printed = 0; 1064 for (i = 7; i >= 0; i--) { 1065 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1066 continue; 1067 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1068 (wdc->cap & WDC_CAPABILITY_MODE)) 1069 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1070 != CMD_OK) 1071 continue; 1072 if (!printed) { 1073 printf("%s DMA mode %d", sep, i); 1074 sep = ","; 1075 printed = 1; 1076 } 1077 if (wdc->cap & WDC_CAPABILITY_DMA) { 1078 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1079 wdc->DMA_cap < i) 1080 continue; 1081 drvp->DMA_mode = i; 1082 drvp->DMA_cap = i; 1083 drvp->drive_flags |= DRIVE_DMA; 1084 } 1085 break; 1086 } 1087 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1088 printed = 0; 1089 for (i = 7; i >= 0; i--) { 1090 if ((params.atap_udmamode_supp & (1 << i)) 1091 == 0) 1092 continue; 1093 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1094 (wdc->cap & WDC_CAPABILITY_UDMA)) 1095 if (ata_set_mode(drvp, 0x40 | i, 1096 AT_POLL) != CMD_OK) 1097 continue; 1098 if (!printed) { 1099 printf("%s Ultra-DMA mode %d", sep, i); 1100 sep = ","; 1101 printed = 1; 1102 } 1103 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1104 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1105 wdc->UDMA_cap < i) 1106 continue; 1107 drvp->UDMA_mode = i; 1108 drvp->UDMA_cap = i; 1109 drvp->drive_flags |= DRIVE_UDMA; 1110 } 1111 break; 1112 } 1113 } 1114 printf("\n"); 1115 } 1116 1117 /* Try to guess ATA version here, if it didn't get reported */ 1118 if (drvp->ata_vers == 0) { 1119 if (drvp->drive_flags & DRIVE_UDMA) 1120 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1121 else if (drvp->PIO_cap > 2) 1122 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1123 } 1124 cf_flags = drv_dev->dv_cfdata->cf_flags; 1125 if (cf_flags & ATA_CONFIG_PIO_SET) { 1126 drvp->PIO_mode = 1127 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1128 drvp->drive_flags |= DRIVE_MODE; 1129 } 1130 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1131 /* don't care about DMA modes */ 1132 return; 1133 } 1134 if (cf_flags & ATA_CONFIG_DMA_SET) { 1135 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1136 ATA_CONFIG_DMA_DISABLE) { 1137 drvp->drive_flags &= ~DRIVE_DMA; 1138 } else { 1139 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1140 ATA_CONFIG_DMA_OFF; 1141 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1142 } 1143 } 1144 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1145 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1146 ATA_CONFIG_UDMA_DISABLE) { 1147 drvp->drive_flags &= ~DRIVE_UDMA; 1148 } else { 1149 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1150 ATA_CONFIG_UDMA_OFF; 1151 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1152 } 1153 } 1154 } 1155 1156 /* 1157 * downgrade the transfer mode of a drive after an error. return 1 if 1158 * downgrade was possible, 0 otherwise. 1159 */ 1160 int 1161 wdc_downgrade_mode(drvp) 1162 struct ata_drive_datas *drvp; 1163 { 1164 struct channel_softc *chp = drvp->chnl_softc; 1165 struct device *drv_dev = drvp->drv_softc; 1166 struct wdc_softc *wdc = chp->wdc; 1167 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1168 1169 /* if drive or controller don't know its mode, we can't do much */ 1170 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1171 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1172 return 0; 1173 /* current drive mode was set by a config flag, let it this way */ 1174 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1175 (cf_flags & ATA_CONFIG_DMA_SET) || 1176 (cf_flags & ATA_CONFIG_UDMA_SET)) 1177 return 0; 1178 1179 /* 1180 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1181 * Maybe we didn't properly notice the cable type 1182 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1183 * It helps in some cases. 1184 */ 1185 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1186 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1187 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1188 drv_dev->dv_xname, drvp->UDMA_mode); 1189 } 1190 1191 /* 1192 * If we were using ultra-DMA, don't downgrade to multiword DMA 1193 * if we noticed a CRC error. It has been noticed that CRC errors 1194 * in ultra-DMA lead to silent data corruption in multiword DMA. 1195 * Data corruption is less likely to occur in PIO mode. 1196 */ 1197 else if ((drvp->drive_flags & DRIVE_UDMA) && 1198 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1199 drvp->drive_flags &= ~DRIVE_UDMA; 1200 drvp->drive_flags |= DRIVE_DMA; 1201 drvp->DMA_mode = drvp->DMA_cap; 1202 printf("%s: transfer error, downgrading to DMA mode %d\n", 1203 drv_dev->dv_xname, drvp->DMA_mode); 1204 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1205 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1206 drvp->PIO_mode = drvp->PIO_cap; 1207 printf("%s: transfer error, downgrading to PIO mode %d\n", 1208 drv_dev->dv_xname, drvp->PIO_mode); 1209 } else /* already using PIO, can't downgrade */ 1210 return 0; 1211 1212 wdc->set_modes(chp); 1213 /* reset the channel, which will shedule all drives for setup */ 1214 wdc_reset_channel(drvp); 1215 return 1; 1216 } 1217 1218 int 1219 wdc_exec_command(drvp, wdc_c) 1220 struct ata_drive_datas *drvp; 1221 struct wdc_command *wdc_c; 1222 { 1223 struct channel_softc *chp = drvp->chnl_softc; 1224 struct wdc_xfer *xfer; 1225 int s, ret; 1226 1227 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1228 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1229 DEBUG_FUNCS); 1230 1231 /* set up an xfer and queue. Wait for completion */ 1232 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1233 WDC_NOSLEEP); 1234 if (xfer == NULL) { 1235 return WDC_TRY_AGAIN; 1236 } 1237 1238 if (wdc_c->flags & AT_POLL) 1239 xfer->c_flags |= C_POLL; 1240 xfer->drive = drvp->drive; 1241 xfer->databuf = wdc_c->data; 1242 xfer->c_bcount = wdc_c->bcount; 1243 xfer->cmd = wdc_c; 1244 xfer->c_start = __wdccommand_start; 1245 xfer->c_intr = __wdccommand_intr; 1246 xfer->c_kill_xfer = __wdccommand_done; 1247 1248 s = splbio(); 1249 wdc_exec_xfer(chp, xfer); 1250 #ifdef DIAGNOSTIC 1251 if ((wdc_c->flags & AT_POLL) != 0 && 1252 (wdc_c->flags & AT_DONE) == 0) 1253 panic("wdc_exec_command: polled command not done\n"); 1254 #endif 1255 if (wdc_c->flags & AT_DONE) { 1256 ret = WDC_COMPLETE; 1257 } else { 1258 if (wdc_c->flags & AT_WAIT) { 1259 while ((wdc_c->flags & AT_DONE) == 0) { 1260 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1261 } 1262 ret = WDC_COMPLETE; 1263 } else { 1264 ret = WDC_QUEUED; 1265 } 1266 } 1267 splx(s); 1268 return ret; 1269 } 1270 1271 void 1272 __wdccommand_start(chp, xfer) 1273 struct channel_softc *chp; 1274 struct wdc_xfer *xfer; 1275 { 1276 int drive = xfer->drive; 1277 struct wdc_command *wdc_c = xfer->cmd; 1278 1279 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1280 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1281 DEBUG_FUNCS); 1282 1283 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1284 WDSD_IBM | (drive << 4)); 1285 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1286 wdc_c->timeout) != 0) { 1287 wdc_c->flags |= AT_TIMEOU; 1288 __wdccommand_done(chp, xfer); 1289 return; 1290 } 1291 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1292 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1293 if ((wdc_c->flags & AT_POLL) == 0) { 1294 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1295 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1296 wdctimeout, chp); 1297 return; 1298 } 1299 /* 1300 * Polled command. Wait for drive ready or drq. Done in intr(). 1301 * Wait for at last 400ns for status bit to be valid. 1302 */ 1303 delay(10); 1304 __wdccommand_intr(chp, xfer, 0); 1305 } 1306 1307 int 1308 __wdccommand_intr(chp, xfer, irq) 1309 struct channel_softc *chp; 1310 struct wdc_xfer *xfer; 1311 int irq; 1312 { 1313 struct wdc_command *wdc_c = xfer->cmd; 1314 int bcount = wdc_c->bcount; 1315 char *data = wdc_c->data; 1316 1317 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1318 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1319 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1320 (irq == 0) ? wdc_c->timeout : 0)) { 1321 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1322 return 0; /* IRQ was not for us */ 1323 wdc_c->flags |= AT_TIMEOU; 1324 __wdccommand_done(chp, xfer); 1325 return 1; 1326 } 1327 if (wdc_c->flags & AT_READ) { 1328 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1329 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1330 0, (u_int32_t*)data, bcount >> 2); 1331 data += bcount & 0xfffffffc; 1332 bcount = bcount & 0x03; 1333 } 1334 if (bcount > 0) 1335 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1336 wd_data, (u_int16_t *)data, bcount >> 1); 1337 } else if (wdc_c->flags & AT_WRITE) { 1338 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1339 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1340 0, (u_int32_t*)data, bcount >> 2); 1341 data += bcount & 0xfffffffc; 1342 bcount = bcount & 0x03; 1343 } 1344 if (bcount > 0) 1345 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1346 wd_data, (u_int16_t *)data, bcount >> 1); 1347 } 1348 __wdccommand_done(chp, xfer); 1349 return 1; 1350 } 1351 1352 void 1353 __wdccommand_done(chp, xfer) 1354 struct channel_softc *chp; 1355 struct wdc_xfer *xfer; 1356 { 1357 struct wdc_command *wdc_c = xfer->cmd; 1358 1359 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1360 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1361 1362 callout_stop(&chp->ch_callout); 1363 1364 if (chp->ch_status & WDCS_DWF) 1365 wdc_c->flags |= AT_DF; 1366 if (chp->ch_status & WDCS_ERR) { 1367 wdc_c->flags |= AT_ERROR; 1368 wdc_c->r_error = chp->ch_error; 1369 } 1370 wdc_c->flags |= AT_DONE; 1371 if ((wdc_c->flags & AT_READREG) != 0 && 1372 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1373 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1374 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1375 wd_sdh); 1376 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1377 wd_cyl_hi) << 8; 1378 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1379 wd_cyl_lo); 1380 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1381 wd_sector); 1382 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1383 wd_seccnt); 1384 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1385 wd_error); 1386 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1387 wd_precomp); 1388 } 1389 wdc_free_xfer(chp, xfer); 1390 if (wdc_c->flags & AT_WAIT) 1391 wakeup(wdc_c); 1392 else if (wdc_c->callback) 1393 wdc_c->callback(wdc_c->callback_arg); 1394 wdcstart(chp); 1395 return; 1396 } 1397 1398 /* 1399 * Send a command. The drive should be ready. 1400 * Assumes interrupts are blocked. 1401 */ 1402 void 1403 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1404 struct channel_softc *chp; 1405 u_int8_t drive; 1406 u_int8_t command; 1407 u_int16_t cylin; 1408 u_int8_t head, sector, count, precomp; 1409 { 1410 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1411 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1412 chp->channel, drive, command, cylin, head, sector, count, precomp), 1413 DEBUG_FUNCS); 1414 1415 /* Select drive, head, and addressing mode. */ 1416 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1417 WDSD_IBM | (drive << 4) | head); 1418 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1419 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1420 precomp); 1421 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1422 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1423 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1424 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1425 1426 /* Send command. */ 1427 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1428 return; 1429 } 1430 1431 /* 1432 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1433 * tested by the caller. 1434 */ 1435 void 1436 wdccommandshort(chp, drive, command) 1437 struct channel_softc *chp; 1438 int drive; 1439 int command; 1440 { 1441 1442 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1443 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1444 DEBUG_FUNCS); 1445 1446 /* Select drive. */ 1447 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1448 WDSD_IBM | (drive << 4)); 1449 1450 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1451 } 1452 1453 /* Add a command to the queue and start controller. Must be called at splbio */ 1454 1455 void 1456 wdc_exec_xfer(chp, xfer) 1457 struct channel_softc *chp; 1458 struct wdc_xfer *xfer; 1459 { 1460 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1461 chp->channel, xfer->drive), DEBUG_XFERS); 1462 1463 /* complete xfer setup */ 1464 xfer->chp = chp; 1465 1466 /* 1467 * If we are a polled command, and the list is not empty, 1468 * we are doing a dump. Drop the list to allow the polled command 1469 * to complete, we're going to reboot soon anyway. 1470 */ 1471 if ((xfer->c_flags & C_POLL) != 0 && 1472 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1473 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1474 } 1475 /* insert at the end of command list */ 1476 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1477 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1478 chp->ch_flags), DEBUG_XFERS); 1479 wdcstart(chp); 1480 } 1481 1482 struct wdc_xfer * 1483 wdc_get_xfer(flags) 1484 int flags; 1485 { 1486 struct wdc_xfer *xfer; 1487 int s; 1488 1489 s = splbio(); 1490 xfer = pool_get(&wdc_xfer_pool, 1491 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1492 splx(s); 1493 memset(xfer, 0, sizeof(struct wdc_xfer)); 1494 return xfer; 1495 } 1496 1497 void 1498 wdc_free_xfer(chp, xfer) 1499 struct channel_softc *chp; 1500 struct wdc_xfer *xfer; 1501 { 1502 struct wdc_softc *wdc = chp->wdc; 1503 int s; 1504 1505 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1506 (*wdc->free_hw)(chp); 1507 s = splbio(); 1508 chp->ch_flags &= ~WDCF_ACTIVE; 1509 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1510 pool_put(&wdc_xfer_pool, xfer); 1511 splx(s); 1512 } 1513 1514 /* 1515 * Kill off all pending xfers for a channel_softc. 1516 * 1517 * Must be called at splbio(). 1518 */ 1519 void 1520 wdc_kill_pending(chp) 1521 struct channel_softc *chp; 1522 { 1523 struct wdc_xfer *xfer; 1524 1525 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1526 chp = xfer->chp; 1527 (*xfer->c_kill_xfer)(chp, xfer); 1528 } 1529 } 1530 1531 static void 1532 __wdcerror(chp, msg) 1533 struct channel_softc *chp; 1534 char *msg; 1535 { 1536 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1537 1538 if (xfer == NULL) 1539 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1540 msg); 1541 else 1542 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1543 chp->channel, xfer->drive, msg); 1544 } 1545 1546 /* 1547 * the bit bucket 1548 */ 1549 void 1550 wdcbit_bucket(chp, size) 1551 struct channel_softc *chp; 1552 int size; 1553 { 1554 1555 for (; size >= 2; size -= 2) 1556 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1557 if (size) 1558 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1559 } 1560 1561 int 1562 wdc_addref(chp) 1563 struct channel_softc *chp; 1564 { 1565 struct wdc_softc *wdc = chp->wdc; 1566 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1567 int s, error = 0; 1568 1569 s = splbio(); 1570 if (adapter->_generic.scsipi_refcnt++ == 0 && 1571 adapter->_generic.scsipi_enable != NULL) { 1572 error = (*adapter->_generic.scsipi_enable)(wdc, 1); 1573 if (error) 1574 adapter->_generic.scsipi_refcnt--; 1575 } 1576 splx(s); 1577 return (error); 1578 } 1579 1580 void 1581 wdc_delref(chp) 1582 struct channel_softc *chp; 1583 { 1584 struct wdc_softc *wdc = chp->wdc; 1585 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1586 int s; 1587 1588 s = splbio(); 1589 if (adapter->_generic.scsipi_refcnt-- == 1 && 1590 adapter->_generic.scsipi_enable != NULL) 1591 (void) (*adapter->_generic.scsipi_enable)(wdc, 0); 1592 splx(s); 1593 } 1594
Indexes created Mon Sep 22 13:09:51 GMT 2025