wdc.c revision 1.90
1 /* $NetBSD: wdc.c,v 1.90 2000/06/11 17:09:34 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <vm/vm.h> 90 91 #include <machine/intr.h> 92 #include <machine/bus.h> 93 94 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 95 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 96 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 97 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 98 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 99 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 100 101 #include <dev/ata/atavar.h> 102 #include <dev/ata/atareg.h> 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ic/wdcvar.h> 105 106 #include "atapibus.h" 107 108 #define WDCDELAY 100 /* 100 microseconds */ 109 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 110 #if 0 111 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 112 #define WDCNDELAY_DEBUG 50 113 #endif 114 115 struct pool wdc_xfer_pool; 116 117 static void __wdcerror __P((struct channel_softc*, char *)); 118 static int __wdcwait_reset __P((struct channel_softc *, int)); 119 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 120 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 121 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 int wdprint __P((void *, const char *)); 123 124 125 #define DEBUG_INTR 0x01 126 #define DEBUG_XFERS 0x02 127 #define DEBUG_STATUS 0x04 128 #define DEBUG_FUNCS 0x08 129 #define DEBUG_PROBE 0x10 130 #define DEBUG_DETACH 0x20 131 #define DEBUG_DELAY 0x40 132 #ifdef WDCDEBUG 133 int wdcdebug_mask = 0; 134 int wdc_nxfer = 0; 135 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 136 #else 137 #define WDCDEBUG_PRINT(args, level) 138 #endif 139 140 int 141 wdprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144 { 145 struct ata_atapi_attach *aa_link = aux; 146 if (pnp) 147 printf("drive at %s", pnp); 148 printf(" channel %d drive %d", aa_link->aa_channel, 149 aa_link->aa_drv_data->drive); 150 return (UNCONF); 151 } 152 153 int 154 atapi_print(aux, pnp) 155 void *aux; 156 const char *pnp; 157 { 158 struct ata_atapi_attach *aa_link = aux; 159 if (pnp) 160 printf("atapibus at %s", pnp); 161 printf(" channel %d", aa_link->aa_channel); 162 return (UNCONF); 163 } 164 165 /* Test to see controller with at last one attached drive is there. 166 * Returns a bit for each possible drive found (0x01 for drive 0, 167 * 0x02 for drive 1). 168 * Logic: 169 * - If a status register is at 0xff, assume there is no drive here 170 * (ISA has pull-up resistors). If no drive at all -> return. 171 * - reset the controller, wait for it to complete (may take up to 31s !). 172 * If timeout -> return. 173 * - test ATA/ATAPI signatures. If at last one drive found -> return. 174 * - try an ATA command on the master. 175 */ 176 177 int 178 wdcprobe(chp) 179 struct channel_softc *chp; 180 { 181 u_int8_t st0, st1, sc, sn, cl, ch; 182 u_int8_t ret_value = 0x03; 183 u_int8_t drive; 184 185 /* 186 * Sanity check to see if the wdc channel responds at all. 187 */ 188 189 if (chp->wdc == NULL || 190 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 191 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 192 WDSD_IBM); 193 delay(10); 194 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 195 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 196 WDSD_IBM | 0x10); 197 delay(10); 198 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 199 200 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 201 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 202 chp->channel, st0, st1), DEBUG_PROBE); 203 204 if (st0 == 0xff) 205 ret_value &= ~0x01; 206 if (st1 == 0xff) 207 ret_value &= ~0x02; 208 if (ret_value == 0) 209 return 0; 210 } 211 212 /* assert SRST, wait for reset to complete */ 213 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 214 WDSD_IBM); 215 delay(10); 216 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 217 WDCTL_RST | WDCTL_IDS); 218 DELAY(1000); 219 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 220 WDCTL_IDS); 221 delay(1000); 222 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 223 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 224 delay(10); 225 226 ret_value = __wdcwait_reset(chp, ret_value); 227 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 228 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 229 ret_value), DEBUG_PROBE); 230 231 /* if reset failed, there's nothing here */ 232 if (ret_value == 0) 233 return 0; 234 235 /* 236 * Test presence of drives. First test register signatures looking for 237 * ATAPI devices. If it's not an ATAPI and reset said there may be 238 * something here assume it's ATA or OLD. Ghost will be killed later in 239 * attach routine. 240 */ 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 245 WDSD_IBM | (drive << 4)); 246 delay(10); 247 /* Save registers contents */ 248 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 249 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 250 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 251 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 252 253 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 254 "cl=0x%x ch=0x%x\n", 255 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 256 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 257 /* 258 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 259 * we get wrong values here, so ignore it. 260 */ 261 if (cl == 0x14 && ch == 0xeb) { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 263 } else { 264 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 265 if (chp->wdc == NULL || 266 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 267 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 268 } 269 } 270 return (ret_value); 271 } 272 273 void 274 wdcattach(chp) 275 struct channel_softc *chp; 276 { 277 int channel_flags, ctrl_flags, i, error; 278 struct ata_atapi_attach aa_link; 279 struct ataparams params; 280 static int inited = 0; 281 282 callout_init(&chp->ch_callout); 283 284 if ((error = wdc_addref(chp)) != 0) { 285 printf("%s: unable to enable controller\n", 286 chp->wdc->sc_dev.dv_xname); 287 return; 288 } 289 290 if (wdcprobe(chp) == 0) 291 /* If no drives, abort attach here. */ 292 goto out; 293 294 /* initialise global data */ 295 if (inited == 0) { 296 /* Initialize the wdc_xfer pool. */ 297 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 298 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 299 inited++; 300 } 301 TAILQ_INIT(&chp->ch_queue->sc_xfer); 302 303 for (i = 0; i < 2; i++) { 304 chp->ch_drive[i].chnl_softc = chp; 305 chp->ch_drive[i].drive = i; 306 /* 307 * Init error counter so that an error withing the first xfers 308 * will trigger a downgrade 309 */ 310 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 311 312 /* If controller can't do 16bit flag the drives as 32bit */ 313 if ((chp->wdc->cap & 314 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 315 WDC_CAPABILITY_DATA32) 316 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 317 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 318 continue; 319 320 /* 321 * Wait a bit, some devices are weird just after a reset. 322 * Then issue a IDENTIFY command, to try to detect slave ghost 323 */ 324 delay(100); 325 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 326 if (error != CMD_OK) { 327 delay(1000000); 328 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 329 ¶ms); 330 } 331 if (error == CMD_OK) { 332 /* If IDENTIFY succeded, this is not an OLD ctrl */ 333 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 334 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 335 } else { 336 chp->ch_drive[i].drive_flags &= 337 ~(DRIVE_ATA | DRIVE_ATAPI); 338 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 339 chp->wdc->sc_dev.dv_xname, 340 chp->channel, i, error), DEBUG_PROBE); 341 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 342 continue; 343 /* 344 * Pre-ATA drive ? 345 * Test registers writability (Error register not 346 * writable, but cyllo is), then try an ATA command. 347 */ 348 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 349 WDSD_IBM | (i << 4)); 350 delay(10); 351 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 352 wd_error, 0x58); 353 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 354 wd_cyl_lo, 0xa5); 355 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 356 wd_error == 0x58) || 357 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 358 wd_cyl_lo) != 0xa5) { 359 WDCDEBUG_PRINT(("%s:%d:%d: register " 360 "writability failed\n", 361 chp->wdc->sc_dev.dv_xname, 362 chp->channel, i), DEBUG_PROBE); 363 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 364 } 365 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 366 WDSD_IBM | (i << 4)); 367 delay(100); 368 if (wait_for_ready(chp, 10000) != 0) { 369 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 370 chp->wdc->sc_dev.dv_xname, 371 chp->channel, i), DEBUG_PROBE); 372 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 373 continue; 374 } 375 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 376 wd_command, WDCC_RECAL); 377 if (wait_for_ready(chp, 10000) != 0) { 378 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 379 chp->wdc->sc_dev.dv_xname, 380 chp->channel, i), DEBUG_PROBE); 381 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 382 } 383 } 384 } 385 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 386 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 387 388 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 389 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 390 DEBUG_PROBE); 391 392 /* If no drives, abort here */ 393 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 394 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 395 goto out; 396 397 /* 398 * Attach an ATAPI bus, if needed. 399 */ 400 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 401 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 402 #if NATAPIBUS > 0 403 wdc_atapibus_attach(chp); 404 #else 405 /* 406 * Fills in a fake aa_link and call config_found, so that 407 * the config machinery will print 408 * "atapibus at xxx not configured" 409 */ 410 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 411 aa_link.aa_type = T_ATAPI; 412 aa_link.aa_channel = chp->channel; 413 aa_link.aa_openings = 1; 414 aa_link.aa_drv_data = 0; 415 aa_link.aa_bus_private = NULL; 416 chp->atapibus = config_found(&chp->wdc->sc_dev, 417 (void *)&aa_link, atapi_print); 418 #endif 419 } 420 421 for (i = 0; i < 2; i++) { 422 if ((chp->ch_drive[i].drive_flags & 423 (DRIVE_ATA | DRIVE_OLD)) == 0) { 424 continue; 425 } 426 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 427 aa_link.aa_type = T_ATA; 428 aa_link.aa_channel = chp->channel; 429 aa_link.aa_openings = 1; 430 aa_link.aa_drv_data = &chp->ch_drive[i]; 431 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 432 wdc_probe_caps(&chp->ch_drive[i]); 433 } 434 435 /* 436 * reset drive_flags for unnatached devices, reset state for attached 437 * ones 438 */ 439 for (i = 0; i < 2; i++) { 440 if (chp->ch_drive[i].drv_softc == NULL) 441 chp->ch_drive[i].drive_flags = 0; 442 else 443 chp->ch_drive[i].state = 0; 444 } 445 446 /* 447 * Reset channel. The probe, with some combinations of ATA/ATAPI 448 * devices keep it in a mostly working, but strange state (with busy 449 * led on) 450 */ 451 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 452 wdcreset(chp, VERBOSE); 453 /* 454 * Read status registers to avoid spurious interrupts. 455 */ 456 for (i = 1; i >= 0; i--) { 457 if (chp->ch_drive[i].drive_flags & DRIVE) { 458 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 459 wd_sdh, WDSD_IBM | (i << 4)); 460 if (wait_for_unbusy(chp, 10000) < 0) 461 printf("%s:%d:%d: device busy\n", 462 chp->wdc->sc_dev.dv_xname, 463 chp->channel, i); 464 } 465 } 466 } 467 468 out: 469 wdc_delref(chp); 470 } 471 472 /* 473 * Call activate routine of underlying devices. 474 */ 475 int 476 wdcactivate(self, act) 477 struct device *self; 478 enum devact act; 479 { 480 struct wdc_softc *wdc = (struct wdc_softc *)self; 481 struct channel_softc *chp; 482 struct device *sc = 0; 483 int s, i, j, error = 0; 484 485 s = splbio(); 486 switch (act) { 487 case DVACT_ACTIVATE: 488 error = EOPNOTSUPP; 489 break; 490 491 case DVACT_DEACTIVATE: 492 for (i = 0; i < wdc->nchannels; i++) { 493 chp = wdc->channels[i]; 494 495 /* 496 * We might call deactivate routine for 497 * the children of atapibus twice (once via 498 * atapibus, once directly), but since 499 * config_deactivate maintains DVF_ACTIVE flag, 500 * it's safe. 501 */ 502 sc = chp->atapibus; 503 if (sc != NULL) { 504 error = config_deactivate(sc); 505 if (error != 0) 506 goto out; 507 } 508 509 for (j = 0; j < 2; j++) { 510 sc = chp->ch_drive[j].drv_softc; 511 WDCDEBUG_PRINT(("wdcactivate: %s:" 512 " deactivating %s\n", wdc->sc_dev.dv_xname, 513 sc == NULL ? "nodrv" : sc->dv_xname), 514 DEBUG_DETACH); 515 if (sc != NULL) { 516 error = config_deactivate(sc); 517 if (error != 0) 518 goto out; 519 } 520 } 521 } 522 break; 523 } 524 525 out: 526 splx(s); 527 528 #ifdef WDCDEBUG 529 if (sc && error != 0) 530 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 531 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 532 #endif 533 return (error); 534 } 535 536 int 537 wdcdetach(self, flags) 538 struct device *self; 539 int flags; 540 { 541 struct wdc_softc *wdc = (struct wdc_softc *)self; 542 struct channel_softc *chp; 543 struct device *sc = 0; 544 int i, j, error = 0; 545 546 for (i = 0; i < wdc->nchannels; i++) { 547 chp = wdc->channels[i]; 548 549 /* 550 * Detach atapibus and its children. 551 */ 552 sc = chp->atapibus; 553 if (sc != NULL) { 554 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 555 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 556 error = config_detach(sc, flags); 557 if (error != 0) 558 goto out; 559 } 560 561 /* 562 * Detach our other children. 563 */ 564 for (j = 0; j < 2; j++) { 565 sc = chp->ch_drive[j].drv_softc; 566 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 567 wdc->sc_dev.dv_xname, 568 sc == NULL ? "nodrv" : sc->dv_xname), 569 DEBUG_DETACH); 570 if (sc != NULL) { 571 error = config_detach(sc, flags); 572 if (error != 0) 573 goto out; 574 } 575 } 576 577 wdc_kill_pending(chp); 578 } 579 580 out: 581 #ifdef WDCDEBUG 582 if (sc && error != 0) 583 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 584 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 585 #endif 586 return (error); 587 } 588 589 /* 590 * Start I/O on a controller, for the given channel. 591 * The first xfer may be not for our channel if the channel queues 592 * are shared. 593 */ 594 void 595 wdcstart(chp) 596 struct channel_softc *chp; 597 { 598 struct wdc_xfer *xfer; 599 600 #ifdef WDC_DIAGNOSTIC 601 int spl1, spl2; 602 603 spl1 = splbio(); 604 spl2 = splbio(); 605 if (spl2 != spl1) { 606 printf("wdcstart: not at splbio()\n"); 607 panic("wdcstart"); 608 } 609 splx(spl2); 610 splx(spl1); 611 #endif /* WDC_DIAGNOSTIC */ 612 613 /* is there a xfer ? */ 614 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 615 return; 616 617 /* adjust chp, in case we have a shared queue */ 618 chp = xfer->chp; 619 620 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 621 return; /* channel aleady active */ 622 } 623 #ifdef DIAGNOSTIC 624 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 625 panic("wdcstart: channel waiting for irq\n"); 626 #endif 627 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 628 if (!(*chp->wdc->claim_hw)(chp, 0)) 629 return; 630 631 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 632 chp->channel, xfer->drive), DEBUG_XFERS); 633 chp->ch_flags |= WDCF_ACTIVE; 634 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 635 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 636 chp->ch_drive[xfer->drive].state = 0; 637 } 638 xfer->c_start(chp, xfer); 639 } 640 641 /* restart an interrupted I/O */ 642 void 643 wdcrestart(v) 644 void *v; 645 { 646 struct channel_softc *chp = v; 647 int s; 648 649 s = splbio(); 650 wdcstart(chp); 651 splx(s); 652 } 653 654 655 /* 656 * Interrupt routine for the controller. Acknowledge the interrupt, check for 657 * errors on the current operation, mark it done if necessary, and start the 658 * next request. Also check for a partially done transfer, and continue with 659 * the next chunk if so. 660 */ 661 int 662 wdcintr(arg) 663 void *arg; 664 { 665 struct channel_softc *chp = arg; 666 struct wdc_xfer *xfer; 667 int ret; 668 669 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 670 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 671 DEBUG_INTR); 672 return (0); 673 } 674 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 675 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 676 return (0); 677 } 678 679 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 680 xfer = chp->ch_queue->sc_xfer.tqh_first; 681 if (chp->ch_flags & WDCF_DMA_WAIT) { 682 chp->wdc->dma_status = 683 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 684 xfer->drive, 0); 685 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 686 /* IRQ not for us, not detected by DMA engine */ 687 return 0; 688 } 689 chp->ch_flags &= ~WDCF_DMA_WAIT; 690 } 691 chp->ch_flags &= ~WDCF_IRQ_WAIT; 692 ret = xfer->c_intr(chp, xfer, 1); 693 if (ret == 0) /* irq was not for us, still waiting for irq */ 694 chp->ch_flags |= WDCF_IRQ_WAIT; 695 return (ret); 696 } 697 698 /* Put all disk in RESET state */ 699 void wdc_reset_channel(drvp) 700 struct ata_drive_datas *drvp; 701 { 702 struct channel_softc *chp = drvp->chnl_softc; 703 int drive; 704 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 705 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 706 DEBUG_FUNCS); 707 (void) wdcreset(chp, VERBOSE); 708 for (drive = 0; drive < 2; drive++) { 709 chp->ch_drive[drive].state = 0; 710 } 711 } 712 713 int 714 wdcreset(chp, verb) 715 struct channel_softc *chp; 716 int verb; 717 { 718 int drv_mask1, drv_mask2; 719 720 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 721 WDSD_IBM); /* master */ 722 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 723 WDCTL_RST | WDCTL_IDS); 724 delay(1000); 725 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 726 WDCTL_IDS); 727 delay(1000); 728 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 729 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 730 WDCTL_4BIT); 731 732 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 733 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 734 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 735 if (verb && drv_mask2 != drv_mask1) { 736 printf("%s channel %d: reset failed for", 737 chp->wdc->sc_dev.dv_xname, chp->channel); 738 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 739 printf(" drive 0"); 740 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 741 printf(" drive 1"); 742 printf("\n"); 743 } 744 return (drv_mask1 != drv_mask2) ? 1 : 0; 745 } 746 747 static int 748 __wdcwait_reset(chp, drv_mask) 749 struct channel_softc *chp; 750 int drv_mask; 751 { 752 int timeout; 753 u_int8_t st0, st1; 754 #ifdef WDCDEBUG 755 u_int8_t sc0, sn0, cl0, ch0; 756 u_int8_t sc1, sn1, cl1, ch1; 757 #endif 758 /* wait for BSY to deassert */ 759 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 760 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 761 WDSD_IBM); /* master */ 762 delay(10); 763 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 764 #ifdef WDCDEBUG 765 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 766 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 767 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 768 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 769 #endif 770 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 771 WDSD_IBM | 0x10); /* slave */ 772 delay(10); 773 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 774 #ifdef WDCDEBUG 775 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 776 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 777 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 778 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 779 #endif 780 781 if ((drv_mask & 0x01) == 0) { 782 /* no master */ 783 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 784 /* No master, slave is ready, it's done */ 785 goto end; 786 } 787 } else if ((drv_mask & 0x02) == 0) { 788 /* no slave */ 789 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 790 /* No slave, master is ready, it's done */ 791 goto end; 792 } 793 } else { 794 /* Wait for both master and slave to be ready */ 795 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 796 goto end; 797 } 798 } 799 delay(WDCDELAY); 800 } 801 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 802 if (st0 & WDCS_BSY) 803 drv_mask &= ~0x01; 804 if (st1 & WDCS_BSY) 805 drv_mask &= ~0x02; 806 end: 807 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 808 "cl=0x%x ch=0x%x\n", 809 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 810 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 811 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 812 "cl=0x%x ch=0x%x\n", 813 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 814 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 815 816 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 817 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 818 st0, st1), DEBUG_PROBE); 819 820 return drv_mask; 821 } 822 823 /* 824 * Wait for a drive to be !BSY, and have mask in its status register. 825 * return -1 for a timeout after "timeout" ms. 826 */ 827 int 828 wdcwait(chp, mask, bits, timeout) 829 struct channel_softc *chp; 830 int mask, bits, timeout; 831 { 832 u_char status; 833 int time = 0; 834 #ifdef WDCNDELAY_DEBUG 835 extern int cold; 836 #endif 837 838 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 839 :"none", chp->channel), DEBUG_STATUS); 840 chp->ch_error = 0; 841 842 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 843 844 for (;;) { 845 chp->ch_status = status = 846 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 847 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 848 break; 849 if (++time > timeout) { 850 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 851 "status %x error %x (mask 0x%x bits 0x%x)\n", 852 time, status, 853 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 854 wd_error), mask, bits), 855 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 856 return -1; 857 } 858 delay(WDCDELAY); 859 } 860 #ifdef WDCDEBUG 861 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 862 printf("wdcwait: did busy-wait, time=%d\n", time); 863 #endif 864 if (status & WDCS_ERR) 865 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 866 wd_error); 867 #ifdef WDCNDELAY_DEBUG 868 /* After autoconfig, there should be no long delays. */ 869 if (!cold && time > WDCNDELAY_DEBUG) { 870 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 871 if (xfer == NULL) 872 printf("%s channel %d: warning: busy-wait took %dus\n", 873 chp->wdc->sc_dev.dv_xname, chp->channel, 874 WDCDELAY * time); 875 else 876 printf("%s:%d:%d: warning: busy-wait took %dus\n", 877 chp->wdc->sc_dev.dv_xname, chp->channel, 878 xfer->drive, 879 WDCDELAY * time); 880 } 881 #endif 882 return 0; 883 } 884 885 /* 886 * Busy-wait for DMA to complete 887 */ 888 int 889 wdc_dmawait(chp, xfer, timeout) 890 struct channel_softc *chp; 891 struct wdc_xfer *xfer; 892 int timeout; 893 { 894 int time; 895 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 896 chp->wdc->dma_status = 897 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 898 chp->channel, xfer->drive, 0); 899 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 900 return 0; 901 delay(WDCDELAY); 902 } 903 /* timeout, force a DMA halt */ 904 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 905 chp->channel, xfer->drive, 1); 906 return 1; 907 } 908 909 void 910 wdctimeout(arg) 911 void *arg; 912 { 913 struct channel_softc *chp = (struct channel_softc *)arg; 914 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 915 int s; 916 917 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 918 919 s = splbio(); 920 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 921 __wdcerror(chp, "lost interrupt"); 922 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 923 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 924 xfer->c_bcount, 925 xfer->c_skip); 926 if (chp->ch_flags & WDCF_DMA_WAIT) { 927 chp->wdc->dma_status = 928 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 929 chp->channel, xfer->drive, 1); 930 chp->ch_flags &= ~WDCF_DMA_WAIT; 931 } 932 /* 933 * Call the interrupt routine. If we just missed and interrupt, 934 * it will do what's needed. Else, it will take the needed 935 * action (reset the device). 936 * Before that we need to reinstall the timeout callback, 937 * in case it will miss another irq while in this transfer 938 * We arbitray chose it to be 1s 939 */ 940 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 941 xfer->c_flags |= C_TIMEOU; 942 chp->ch_flags &= ~WDCF_IRQ_WAIT; 943 xfer->c_intr(chp, xfer, 1); 944 } else 945 __wdcerror(chp, "missing untimeout"); 946 splx(s); 947 } 948 949 /* 950 * Probe drive's capabilites, for use by the controller later 951 * Assumes drvp points to an existing drive. 952 * XXX this should be a controller-indep function 953 */ 954 void 955 wdc_probe_caps(drvp) 956 struct ata_drive_datas *drvp; 957 { 958 struct ataparams params, params2; 959 struct channel_softc *chp = drvp->chnl_softc; 960 struct device *drv_dev = drvp->drv_softc; 961 struct wdc_softc *wdc = chp->wdc; 962 int i, printed; 963 char *sep = ""; 964 int cf_flags; 965 966 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 967 /* IDENTIFY failed. Can't tell more about the device */ 968 return; 969 } 970 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 971 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 972 /* 973 * Controller claims 16 and 32 bit transfers. 974 * Re-do an IDENTIFY with 32-bit transfers, 975 * and compare results. 976 */ 977 drvp->drive_flags |= DRIVE_CAP32; 978 ata_get_params(drvp, AT_POLL, ¶ms2); 979 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 980 /* Not good. fall back to 16bits */ 981 drvp->drive_flags &= ~DRIVE_CAP32; 982 } else { 983 printf("%s: 32-bit data port", drv_dev->dv_xname); 984 } 985 } 986 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 987 if (params.atap_ata_major > 0x01 && 988 params.atap_ata_major != 0xffff) { 989 for (i = 14; i > 0; i--) { 990 if (params.atap_ata_major & (1 << i)) { 991 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 992 printf("%s: ", drv_dev->dv_xname); 993 else 994 printf(", "); 995 printf("ATA version %d\n", i); 996 drvp->ata_vers = i; 997 break; 998 } 999 } 1000 } else 1001 #endif 1002 if (drvp->drive_flags & DRIVE_CAP32) 1003 printf("\n"); 1004 1005 /* An ATAPI device is at last PIO mode 3 */ 1006 if (drvp->drive_flags & DRIVE_ATAPI) 1007 drvp->PIO_mode = 3; 1008 1009 /* 1010 * It's not in the specs, but it seems that some drive 1011 * returns 0xffff in atap_extensions when this field is invalid 1012 */ 1013 if (params.atap_extensions != 0xffff && 1014 (params.atap_extensions & WDC_EXT_MODES)) { 1015 printed = 0; 1016 /* 1017 * XXX some drives report something wrong here (they claim to 1018 * support PIO mode 8 !). As mode is coded on 3 bits in 1019 * SET FEATURE, limit it to 7 (so limit i to 4). 1020 * If higther mode than 7 is found, abort. 1021 */ 1022 for (i = 7; i >= 0; i--) { 1023 if ((params.atap_piomode_supp & (1 << i)) == 0) 1024 continue; 1025 if (i > 4) 1026 return; 1027 /* 1028 * See if mode is accepted. 1029 * If the controller can't set its PIO mode, 1030 * assume the defaults are good, so don't try 1031 * to set it 1032 */ 1033 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1034 if (ata_set_mode(drvp, 0x08 | (i + 3), 1035 AT_POLL) != CMD_OK) 1036 continue; 1037 if (!printed) { 1038 printf("%s: drive supports PIO mode %d", 1039 drv_dev->dv_xname, i + 3); 1040 sep = ","; 1041 printed = 1; 1042 } 1043 /* 1044 * If controller's driver can't set its PIO mode, 1045 * get the highter one for the drive. 1046 */ 1047 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1048 wdc->PIO_cap >= i + 3) { 1049 drvp->PIO_mode = i + 3; 1050 drvp->PIO_cap = i + 3; 1051 break; 1052 } 1053 } 1054 if (!printed) { 1055 /* 1056 * We didn't find a valid PIO mode. 1057 * Assume the values returned for DMA are buggy too 1058 */ 1059 return; 1060 } 1061 drvp->drive_flags |= DRIVE_MODE; 1062 printed = 0; 1063 for (i = 7; i >= 0; i--) { 1064 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1065 continue; 1066 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1067 (wdc->cap & WDC_CAPABILITY_MODE)) 1068 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1069 != CMD_OK) 1070 continue; 1071 if (!printed) { 1072 printf("%s DMA mode %d", sep, i); 1073 sep = ","; 1074 printed = 1; 1075 } 1076 if (wdc->cap & WDC_CAPABILITY_DMA) { 1077 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1078 wdc->DMA_cap < i) 1079 continue; 1080 drvp->DMA_mode = i; 1081 drvp->DMA_cap = i; 1082 drvp->drive_flags |= DRIVE_DMA; 1083 } 1084 break; 1085 } 1086 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1087 printed = 0; 1088 for (i = 7; i >= 0; i--) { 1089 if ((params.atap_udmamode_supp & (1 << i)) 1090 == 0) 1091 continue; 1092 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1093 (wdc->cap & WDC_CAPABILITY_UDMA)) 1094 if (ata_set_mode(drvp, 0x40 | i, 1095 AT_POLL) != CMD_OK) 1096 continue; 1097 if (!printed) { 1098 printf("%s Ultra-DMA mode %d", sep, i); 1099 sep = ","; 1100 printed = 1; 1101 } 1102 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1103 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1104 wdc->UDMA_cap < i) 1105 continue; 1106 drvp->UDMA_mode = i; 1107 drvp->UDMA_cap = i; 1108 drvp->drive_flags |= DRIVE_UDMA; 1109 } 1110 break; 1111 } 1112 } 1113 printf("\n"); 1114 } 1115 1116 /* Try to guess ATA version here, if it didn't get reported */ 1117 if (drvp->ata_vers == 0) { 1118 if (drvp->drive_flags & DRIVE_UDMA) 1119 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1120 else if (drvp->PIO_cap > 2) 1121 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1122 } 1123 cf_flags = drv_dev->dv_cfdata->cf_flags; 1124 if (cf_flags & ATA_CONFIG_PIO_SET) { 1125 drvp->PIO_mode = 1126 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1127 drvp->drive_flags |= DRIVE_MODE; 1128 } 1129 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1130 /* don't care about DMA modes */ 1131 return; 1132 } 1133 if (cf_flags & ATA_CONFIG_DMA_SET) { 1134 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1135 ATA_CONFIG_DMA_DISABLE) { 1136 drvp->drive_flags &= ~DRIVE_DMA; 1137 } else { 1138 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1139 ATA_CONFIG_DMA_OFF; 1140 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1141 } 1142 } 1143 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1144 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1145 ATA_CONFIG_UDMA_DISABLE) { 1146 drvp->drive_flags &= ~DRIVE_UDMA; 1147 } else { 1148 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1149 ATA_CONFIG_UDMA_OFF; 1150 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1151 } 1152 } 1153 } 1154 1155 /* 1156 * downgrade the transfer mode of a drive after an error. return 1 if 1157 * downgrade was possible, 0 otherwise. 1158 */ 1159 int 1160 wdc_downgrade_mode(drvp) 1161 struct ata_drive_datas *drvp; 1162 { 1163 struct channel_softc *chp = drvp->chnl_softc; 1164 struct device *drv_dev = drvp->drv_softc; 1165 struct wdc_softc *wdc = chp->wdc; 1166 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1167 1168 /* if drive or controller don't know its mode, we can't do much */ 1169 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1170 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1171 return 0; 1172 /* current drive mode was set by a config flag, let it this way */ 1173 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1174 (cf_flags & ATA_CONFIG_DMA_SET) || 1175 (cf_flags & ATA_CONFIG_UDMA_SET)) 1176 return 0; 1177 1178 /* 1179 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1180 * Maybe we didn't properly notice the cable type 1181 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1182 * It helps in some cases. 1183 */ 1184 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1185 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1186 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1187 drv_dev->dv_xname, drvp->UDMA_mode); 1188 } 1189 1190 /* 1191 * If we were using ultra-DMA, don't downgrade to multiword DMA 1192 * if we noticed a CRC error. It has been noticed that CRC errors 1193 * in ultra-DMA lead to silent data corruption in multiword DMA. 1194 * Data corruption is less likely to occur in PIO mode. 1195 */ 1196 else if ((drvp->drive_flags & DRIVE_UDMA) && 1197 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1198 drvp->drive_flags &= ~DRIVE_UDMA; 1199 drvp->drive_flags |= DRIVE_DMA; 1200 drvp->DMA_mode = drvp->DMA_cap; 1201 printf("%s: transfer error, downgrading to DMA mode %d\n", 1202 drv_dev->dv_xname, drvp->DMA_mode); 1203 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1204 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1205 drvp->PIO_mode = drvp->PIO_cap; 1206 printf("%s: transfer error, downgrading to PIO mode %d\n", 1207 drv_dev->dv_xname, drvp->PIO_mode); 1208 } else /* already using PIO, can't downgrade */ 1209 return 0; 1210 1211 wdc->set_modes(chp); 1212 /* reset the channel, which will shedule all drives for setup */ 1213 wdc_reset_channel(drvp); 1214 return 1; 1215 } 1216 1217 int 1218 wdc_exec_command(drvp, wdc_c) 1219 struct ata_drive_datas *drvp; 1220 struct wdc_command *wdc_c; 1221 { 1222 struct channel_softc *chp = drvp->chnl_softc; 1223 struct wdc_xfer *xfer; 1224 int s, ret; 1225 1226 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1227 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1228 DEBUG_FUNCS); 1229 1230 /* set up an xfer and queue. Wait for completion */ 1231 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1232 WDC_NOSLEEP); 1233 if (xfer == NULL) { 1234 return WDC_TRY_AGAIN; 1235 } 1236 1237 if (wdc_c->flags & AT_POLL) 1238 xfer->c_flags |= C_POLL; 1239 xfer->drive = drvp->drive; 1240 xfer->databuf = wdc_c->data; 1241 xfer->c_bcount = wdc_c->bcount; 1242 xfer->cmd = wdc_c; 1243 xfer->c_start = __wdccommand_start; 1244 xfer->c_intr = __wdccommand_intr; 1245 xfer->c_kill_xfer = __wdccommand_done; 1246 1247 s = splbio(); 1248 wdc_exec_xfer(chp, xfer); 1249 #ifdef DIAGNOSTIC 1250 if ((wdc_c->flags & AT_POLL) != 0 && 1251 (wdc_c->flags & AT_DONE) == 0) 1252 panic("wdc_exec_command: polled command not done\n"); 1253 #endif 1254 if (wdc_c->flags & AT_DONE) { 1255 ret = WDC_COMPLETE; 1256 } else { 1257 if (wdc_c->flags & AT_WAIT) { 1258 while ((wdc_c->flags & AT_DONE) == 0) { 1259 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1260 } 1261 ret = WDC_COMPLETE; 1262 } else { 1263 ret = WDC_QUEUED; 1264 } 1265 } 1266 splx(s); 1267 return ret; 1268 } 1269 1270 void 1271 __wdccommand_start(chp, xfer) 1272 struct channel_softc *chp; 1273 struct wdc_xfer *xfer; 1274 { 1275 int drive = xfer->drive; 1276 struct wdc_command *wdc_c = xfer->cmd; 1277 1278 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1279 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1280 DEBUG_FUNCS); 1281 1282 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1283 WDSD_IBM | (drive << 4)); 1284 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1285 wdc_c->timeout) != 0) { 1286 wdc_c->flags |= AT_TIMEOU; 1287 __wdccommand_done(chp, xfer); 1288 return; 1289 } 1290 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1291 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1292 if ((wdc_c->flags & AT_POLL) == 0) { 1293 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1294 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1295 wdctimeout, chp); 1296 return; 1297 } 1298 /* 1299 * Polled command. Wait for drive ready or drq. Done in intr(). 1300 * Wait for at last 400ns for status bit to be valid. 1301 */ 1302 delay(10); 1303 __wdccommand_intr(chp, xfer, 0); 1304 } 1305 1306 int 1307 __wdccommand_intr(chp, xfer, irq) 1308 struct channel_softc *chp; 1309 struct wdc_xfer *xfer; 1310 int irq; 1311 { 1312 struct wdc_command *wdc_c = xfer->cmd; 1313 int bcount = wdc_c->bcount; 1314 char *data = wdc_c->data; 1315 1316 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1317 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1318 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1319 (irq == 0) ? wdc_c->timeout : 0)) { 1320 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1321 return 0; /* IRQ was not for us */ 1322 wdc_c->flags |= AT_TIMEOU; 1323 __wdccommand_done(chp, xfer); 1324 return 1; 1325 } 1326 if (wdc_c->flags & AT_READ) { 1327 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1328 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1329 0, (u_int32_t*)data, bcount >> 2); 1330 data += bcount & 0xfffffffc; 1331 bcount = bcount & 0x03; 1332 } 1333 if (bcount > 0) 1334 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1335 wd_data, (u_int16_t *)data, bcount >> 1); 1336 } else if (wdc_c->flags & AT_WRITE) { 1337 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1338 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1339 0, (u_int32_t*)data, bcount >> 2); 1340 data += bcount & 0xfffffffc; 1341 bcount = bcount & 0x03; 1342 } 1343 if (bcount > 0) 1344 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1345 wd_data, (u_int16_t *)data, bcount >> 1); 1346 } 1347 __wdccommand_done(chp, xfer); 1348 return 1; 1349 } 1350 1351 void 1352 __wdccommand_done(chp, xfer) 1353 struct channel_softc *chp; 1354 struct wdc_xfer *xfer; 1355 { 1356 struct wdc_command *wdc_c = xfer->cmd; 1357 1358 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1359 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1360 1361 callout_stop(&chp->ch_callout); 1362 1363 if (chp->ch_status & WDCS_DWF) 1364 wdc_c->flags |= AT_DF; 1365 if (chp->ch_status & WDCS_ERR) { 1366 wdc_c->flags |= AT_ERROR; 1367 wdc_c->r_error = chp->ch_error; 1368 } 1369 wdc_c->flags |= AT_DONE; 1370 if ((wdc_c->flags & AT_READREG) != 0 && 1371 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1372 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1373 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1374 wd_sdh); 1375 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1376 wd_cyl_hi) << 8; 1377 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1378 wd_cyl_lo); 1379 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1380 wd_sector); 1381 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1382 wd_seccnt); 1383 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1384 wd_error); 1385 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1386 wd_precomp); 1387 } 1388 wdc_free_xfer(chp, xfer); 1389 if (wdc_c->flags & AT_WAIT) 1390 wakeup(wdc_c); 1391 else if (wdc_c->callback) 1392 wdc_c->callback(wdc_c->callback_arg); 1393 wdcstart(chp); 1394 return; 1395 } 1396 1397 /* 1398 * Send a command. The drive should be ready. 1399 * Assumes interrupts are blocked. 1400 */ 1401 void 1402 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1403 struct channel_softc *chp; 1404 u_int8_t drive; 1405 u_int8_t command; 1406 u_int16_t cylin; 1407 u_int8_t head, sector, count, precomp; 1408 { 1409 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1410 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1411 chp->channel, drive, command, cylin, head, sector, count, precomp), 1412 DEBUG_FUNCS); 1413 1414 /* Select drive, head, and addressing mode. */ 1415 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1416 WDSD_IBM | (drive << 4) | head); 1417 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1418 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1419 precomp); 1420 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1421 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1422 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1423 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1424 1425 /* Send command. */ 1426 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1427 return; 1428 } 1429 1430 /* 1431 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1432 * tested by the caller. 1433 */ 1434 void 1435 wdccommandshort(chp, drive, command) 1436 struct channel_softc *chp; 1437 int drive; 1438 int command; 1439 { 1440 1441 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1442 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1443 DEBUG_FUNCS); 1444 1445 /* Select drive. */ 1446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1447 WDSD_IBM | (drive << 4)); 1448 1449 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1450 } 1451 1452 /* Add a command to the queue and start controller. Must be called at splbio */ 1453 1454 void 1455 wdc_exec_xfer(chp, xfer) 1456 struct channel_softc *chp; 1457 struct wdc_xfer *xfer; 1458 { 1459 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1460 chp->channel, xfer->drive), DEBUG_XFERS); 1461 1462 /* complete xfer setup */ 1463 xfer->chp = chp; 1464 1465 /* 1466 * If we are a polled command, and the list is not empty, 1467 * we are doing a dump. Drop the list to allow the polled command 1468 * to complete, we're going to reboot soon anyway. 1469 */ 1470 if ((xfer->c_flags & C_POLL) != 0 && 1471 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1472 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1473 } 1474 /* insert at the end of command list */ 1475 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1476 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1477 chp->ch_flags), DEBUG_XFERS); 1478 wdcstart(chp); 1479 } 1480 1481 struct wdc_xfer * 1482 wdc_get_xfer(flags) 1483 int flags; 1484 { 1485 struct wdc_xfer *xfer; 1486 int s; 1487 1488 s = splbio(); 1489 xfer = pool_get(&wdc_xfer_pool, 1490 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1491 splx(s); 1492 memset(xfer, 0, sizeof(struct wdc_xfer)); 1493 return xfer; 1494 } 1495 1496 void 1497 wdc_free_xfer(chp, xfer) 1498 struct channel_softc *chp; 1499 struct wdc_xfer *xfer; 1500 { 1501 struct wdc_softc *wdc = chp->wdc; 1502 int s; 1503 1504 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1505 (*wdc->free_hw)(chp); 1506 s = splbio(); 1507 chp->ch_flags &= ~WDCF_ACTIVE; 1508 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1509 pool_put(&wdc_xfer_pool, xfer); 1510 splx(s); 1511 } 1512 1513 /* 1514 * Kill off all pending xfers for a channel_softc. 1515 * 1516 * Must be called at splbio(). 1517 */ 1518 void 1519 wdc_kill_pending(chp) 1520 struct channel_softc *chp; 1521 { 1522 struct wdc_xfer *xfer; 1523 1524 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1525 chp = xfer->chp; 1526 (*xfer->c_kill_xfer)(chp, xfer); 1527 } 1528 } 1529 1530 static void 1531 __wdcerror(chp, msg) 1532 struct channel_softc *chp; 1533 char *msg; 1534 { 1535 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1536 1537 if (xfer == NULL) 1538 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1539 msg); 1540 else 1541 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1542 chp->channel, xfer->drive, msg); 1543 } 1544 1545 /* 1546 * the bit bucket 1547 */ 1548 void 1549 wdcbit_bucket(chp, size) 1550 struct channel_softc *chp; 1551 int size; 1552 { 1553 1554 for (; size >= 2; size -= 2) 1555 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1556 if (size) 1557 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1558 } 1559 1560 int 1561 wdc_addref(chp) 1562 struct channel_softc *chp; 1563 { 1564 struct wdc_softc *wdc = chp->wdc; 1565 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1566 int s, error = 0; 1567 1568 s = splbio(); 1569 if (adapter->_generic.scsipi_refcnt++ == 0 && 1570 adapter->_generic.scsipi_enable != NULL) { 1571 error = (*adapter->_generic.scsipi_enable)(wdc, 1); 1572 if (error) 1573 adapter->_generic.scsipi_refcnt--; 1574 } 1575 splx(s); 1576 return (error); 1577 } 1578 1579 void 1580 wdc_delref(chp) 1581 struct channel_softc *chp; 1582 { 1583 struct wdc_softc *wdc = chp->wdc; 1584 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1585 int s; 1586 1587 s = splbio(); 1588 if (adapter->_generic.scsipi_refcnt-- == 1 && 1589 adapter->_generic.scsipi_enable != NULL) 1590 (void) (*adapter->_generic.scsipi_enable)(wdc, 0); 1591 splx(s); 1592 } 1593
Indexes created Thu Sep 25 16:09:42 GMT 2025