wdc.c revision 1.94
1 /* $NetBSD: wdc.c,v 1.94 2001/01/06 14:55:49 takemura Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "atapibus.h" 105 106 #define WDCDELAY 100 /* 100 microseconds */ 107 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 108 #if 0 109 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 110 #define WDCNDELAY_DEBUG 50 111 #endif 112 113 struct pool wdc_xfer_pool; 114 115 static void __wdcerror __P((struct channel_softc*, char *)); 116 static int __wdcwait_reset __P((struct channel_softc *, int)); 117 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 118 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 119 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 120 int wdprint __P((void *, const char *)); 121 122 123 #define DEBUG_INTR 0x01 124 #define DEBUG_XFERS 0x02 125 #define DEBUG_STATUS 0x04 126 #define DEBUG_FUNCS 0x08 127 #define DEBUG_PROBE 0x10 128 #define DEBUG_DETACH 0x20 129 #define DEBUG_DELAY 0x40 130 #ifdef WDCDEBUG 131 int wdcdebug_mask = 0; 132 int wdc_nxfer = 0; 133 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 134 #else 135 #define WDCDEBUG_PRINT(args, level) 136 #endif 137 138 int 139 wdprint(aux, pnp) 140 void *aux; 141 const char *pnp; 142 { 143 struct ata_atapi_attach *aa_link = aux; 144 if (pnp) 145 printf("drive at %s", pnp); 146 printf(" channel %d drive %d", aa_link->aa_channel, 147 aa_link->aa_drv_data->drive); 148 return (UNCONF); 149 } 150 151 int 152 atapi_print(aux, pnp) 153 void *aux; 154 const char *pnp; 155 { 156 struct ata_atapi_attach *aa_link = aux; 157 if (pnp) 158 printf("atapibus at %s", pnp); 159 printf(" channel %d", aa_link->aa_channel); 160 return (UNCONF); 161 } 162 163 /* Test to see controller with at last one attached drive is there. 164 * Returns a bit for each possible drive found (0x01 for drive 0, 165 * 0x02 for drive 1). 166 * Logic: 167 * - If a status register is at 0xff, assume there is no drive here 168 * (ISA has pull-up resistors). If no drive at all -> return. 169 * - reset the controller, wait for it to complete (may take up to 31s !). 170 * If timeout -> return. 171 * - test ATA/ATAPI signatures. If at last one drive found -> return. 172 * - try an ATA command on the master. 173 */ 174 175 int 176 wdcprobe(chp) 177 struct channel_softc *chp; 178 { 179 u_int8_t st0, st1, sc, sn, cl, ch; 180 u_int8_t ret_value = 0x03; 181 u_int8_t drive; 182 int found; 183 184 /* 185 * Sanity check to see if the wdc channel responds at all. 186 */ 187 188 if (chp->wdc == NULL || 189 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM); 192 delay(10); 193 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 195 WDSD_IBM | 0x10); 196 delay(10); 197 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 198 199 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 200 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 201 chp->channel, st0, st1), DEBUG_PROBE); 202 203 if (st0 == 0xff) 204 ret_value &= ~0x01; 205 if (st1 == 0xff) 206 ret_value &= ~0x02; 207 if (ret_value == 0) 208 return 0; 209 } 210 211 /* assert SRST, wait for reset to complete */ 212 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 213 WDSD_IBM); 214 delay(10); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 216 WDCTL_RST | WDCTL_IDS); 217 DELAY(1000); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 219 WDCTL_IDS); 220 delay(1000); 221 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 222 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 223 delay(10); 224 225 ret_value = __wdcwait_reset(chp, ret_value); 226 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 227 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 228 ret_value), DEBUG_PROBE); 229 230 /* if reset failed, there's nothing here */ 231 if (ret_value == 0) 232 return 0; 233 234 /* 235 * Test presence of drives. First test register signatures looking for 236 * ATAPI devices. If it's not an ATAPI and reset said there may be 237 * something here assume it's ATA or OLD. Ghost will be killed later in 238 * attach routine. 239 */ 240 found = 0; 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 if (1 < ++found && chp->wdc != NULL && 245 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 246 /* 247 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 248 * is set. 249 * 250 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 251 * doesn't seem to implement drive select command. In 252 * this case, you can't eliminate ghost drive properly. 253 */ 254 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 255 chp->wdc->sc_dev.dv_xname, 256 chp->channel, drive), DEBUG_PROBE); 257 break; 258 } 259 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 260 WDSD_IBM | (drive << 4)); 261 delay(10); 262 /* Save registers contents */ 263 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 264 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 265 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 266 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 267 268 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 269 "cl=0x%x ch=0x%x\n", 270 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 271 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 272 /* 273 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 274 * we get wrong values here, so ignore it. 275 */ 276 if (cl == 0x14 && ch == 0xeb) { 277 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 278 } else { 279 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 280 if (chp->wdc == NULL || 281 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 282 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 283 } 284 } 285 return (ret_value); 286 } 287 288 void 289 wdcattach(chp) 290 struct channel_softc *chp; 291 { 292 int channel_flags, ctrl_flags, i, error; 293 struct ata_atapi_attach aa_link; 294 struct ataparams params; 295 static int inited = 0; 296 297 callout_init(&chp->ch_callout); 298 299 if ((error = wdc_addref(chp)) != 0) { 300 printf("%s: unable to enable controller\n", 301 chp->wdc->sc_dev.dv_xname); 302 return; 303 } 304 305 if (wdcprobe(chp) == 0) 306 /* If no drives, abort attach here. */ 307 goto out; 308 309 /* initialise global data */ 310 if (inited == 0) { 311 /* Initialize the wdc_xfer pool. */ 312 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 313 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 314 inited++; 315 } 316 TAILQ_INIT(&chp->ch_queue->sc_xfer); 317 318 for (i = 0; i < 2; i++) { 319 chp->ch_drive[i].chnl_softc = chp; 320 chp->ch_drive[i].drive = i; 321 /* 322 * Init error counter so that an error withing the first xfers 323 * will trigger a downgrade 324 */ 325 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 326 327 /* If controller can't do 16bit flag the drives as 32bit */ 328 if ((chp->wdc->cap & 329 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 330 WDC_CAPABILITY_DATA32) 331 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 332 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 333 continue; 334 335 /* 336 * Wait a bit, some devices are weird just after a reset. 337 * Then issue a IDENTIFY command, to try to detect slave ghost 338 */ 339 delay(100); 340 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 341 if (error != CMD_OK) { 342 delay(1000000); 343 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 344 ¶ms); 345 } 346 if (error == CMD_OK) { 347 /* If IDENTIFY succeded, this is not an OLD ctrl */ 348 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 349 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 350 } else { 351 chp->ch_drive[i].drive_flags &= 352 ~(DRIVE_ATA | DRIVE_ATAPI); 353 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 354 chp->wdc->sc_dev.dv_xname, 355 chp->channel, i, error), DEBUG_PROBE); 356 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 357 continue; 358 /* 359 * Pre-ATA drive ? 360 * Test registers writability (Error register not 361 * writable, but cyllo is), then try an ATA command. 362 */ 363 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 364 WDSD_IBM | (i << 4)); 365 delay(10); 366 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 367 wd_error, 0x58); 368 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 369 wd_cyl_lo, 0xa5); 370 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 371 wd_error == 0x58) || 372 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 373 wd_cyl_lo) != 0xa5) { 374 WDCDEBUG_PRINT(("%s:%d:%d: register " 375 "writability failed\n", 376 chp->wdc->sc_dev.dv_xname, 377 chp->channel, i), DEBUG_PROBE); 378 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 379 } 380 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 381 WDSD_IBM | (i << 4)); 382 delay(100); 383 if (wait_for_ready(chp, 10000) != 0) { 384 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 385 chp->wdc->sc_dev.dv_xname, 386 chp->channel, i), DEBUG_PROBE); 387 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 388 continue; 389 } 390 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 391 wd_command, WDCC_RECAL); 392 if (wait_for_ready(chp, 10000) != 0) { 393 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 394 chp->wdc->sc_dev.dv_xname, 395 chp->channel, i), DEBUG_PROBE); 396 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 397 } 398 } 399 } 400 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 401 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 402 403 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 404 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 405 DEBUG_PROBE); 406 407 /* If no drives, abort here */ 408 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 409 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 410 goto out; 411 412 /* 413 * Attach an ATAPI bus, if needed. 414 */ 415 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 416 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 417 #if NATAPIBUS > 0 418 wdc_atapibus_attach(chp); 419 #else 420 /* 421 * Fills in a fake aa_link and call config_found, so that 422 * the config machinery will print 423 * "atapibus at xxx not configured" 424 */ 425 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 426 aa_link.aa_type = T_ATAPI; 427 aa_link.aa_channel = chp->channel; 428 aa_link.aa_openings = 1; 429 aa_link.aa_drv_data = 0; 430 aa_link.aa_bus_private = NULL; 431 chp->atapibus = config_found(&chp->wdc->sc_dev, 432 (void *)&aa_link, atapi_print); 433 #endif 434 } 435 436 for (i = 0; i < 2; i++) { 437 if ((chp->ch_drive[i].drive_flags & 438 (DRIVE_ATA | DRIVE_OLD)) == 0) { 439 continue; 440 } 441 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 442 aa_link.aa_type = T_ATA; 443 aa_link.aa_channel = chp->channel; 444 aa_link.aa_openings = 1; 445 aa_link.aa_drv_data = &chp->ch_drive[i]; 446 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 447 wdc_probe_caps(&chp->ch_drive[i]); 448 } 449 450 /* 451 * reset drive_flags for unnatached devices, reset state for attached 452 * ones 453 */ 454 for (i = 0; i < 2; i++) { 455 if (chp->ch_drive[i].drv_softc == NULL) 456 chp->ch_drive[i].drive_flags = 0; 457 else 458 chp->ch_drive[i].state = 0; 459 } 460 461 /* 462 * Reset channel. The probe, with some combinations of ATA/ATAPI 463 * devices keep it in a mostly working, but strange state (with busy 464 * led on) 465 */ 466 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 467 wdcreset(chp, VERBOSE); 468 /* 469 * Read status registers to avoid spurious interrupts. 470 */ 471 for (i = 1; i >= 0; i--) { 472 if (chp->ch_drive[i].drive_flags & DRIVE) { 473 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 474 wd_sdh, WDSD_IBM | (i << 4)); 475 if (wait_for_unbusy(chp, 10000) < 0) 476 printf("%s:%d:%d: device busy\n", 477 chp->wdc->sc_dev.dv_xname, 478 chp->channel, i); 479 } 480 } 481 } 482 483 out: 484 wdc_delref(chp); 485 } 486 487 /* 488 * Call activate routine of underlying devices. 489 */ 490 int 491 wdcactivate(self, act) 492 struct device *self; 493 enum devact act; 494 { 495 struct wdc_softc *wdc = (struct wdc_softc *)self; 496 struct channel_softc *chp; 497 struct device *sc = 0; 498 int s, i, j, error = 0; 499 500 s = splbio(); 501 switch (act) { 502 case DVACT_ACTIVATE: 503 error = EOPNOTSUPP; 504 break; 505 506 case DVACT_DEACTIVATE: 507 for (i = 0; i < wdc->nchannels; i++) { 508 chp = wdc->channels[i]; 509 510 /* 511 * We might call deactivate routine for 512 * the children of atapibus twice (once via 513 * atapibus, once directly), but since 514 * config_deactivate maintains DVF_ACTIVE flag, 515 * it's safe. 516 */ 517 sc = chp->atapibus; 518 if (sc != NULL) { 519 error = config_deactivate(sc); 520 if (error != 0) 521 goto out; 522 } 523 524 for (j = 0; j < 2; j++) { 525 sc = chp->ch_drive[j].drv_softc; 526 WDCDEBUG_PRINT(("wdcactivate: %s:" 527 " deactivating %s\n", wdc->sc_dev.dv_xname, 528 sc == NULL ? "nodrv" : sc->dv_xname), 529 DEBUG_DETACH); 530 if (sc != NULL) { 531 error = config_deactivate(sc); 532 if (error != 0) 533 goto out; 534 } 535 } 536 } 537 break; 538 } 539 540 out: 541 splx(s); 542 543 #ifdef WDCDEBUG 544 if (sc && error != 0) 545 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 546 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 547 #endif 548 return (error); 549 } 550 551 int 552 wdcdetach(self, flags) 553 struct device *self; 554 int flags; 555 { 556 struct wdc_softc *wdc = (struct wdc_softc *)self; 557 struct channel_softc *chp; 558 struct device *sc = 0; 559 int i, j, error = 0; 560 561 for (i = 0; i < wdc->nchannels; i++) { 562 chp = wdc->channels[i]; 563 564 /* 565 * Detach atapibus and its children. 566 */ 567 sc = chp->atapibus; 568 if (sc != NULL) { 569 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 570 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 571 error = config_detach(sc, flags); 572 if (error != 0) 573 goto out; 574 } 575 576 /* 577 * Detach our other children. 578 */ 579 for (j = 0; j < 2; j++) { 580 sc = chp->ch_drive[j].drv_softc; 581 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 582 wdc->sc_dev.dv_xname, 583 sc == NULL ? "nodrv" : sc->dv_xname), 584 DEBUG_DETACH); 585 if (sc != NULL) { 586 error = config_detach(sc, flags); 587 if (error != 0) 588 goto out; 589 } 590 } 591 592 wdc_kill_pending(chp); 593 } 594 595 out: 596 #ifdef WDCDEBUG 597 if (sc && error != 0) 598 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 599 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 600 #endif 601 return (error); 602 } 603 604 /* 605 * Start I/O on a controller, for the given channel. 606 * The first xfer may be not for our channel if the channel queues 607 * are shared. 608 */ 609 void 610 wdcstart(chp) 611 struct channel_softc *chp; 612 { 613 struct wdc_xfer *xfer; 614 615 #ifdef WDC_DIAGNOSTIC 616 int spl1, spl2; 617 618 spl1 = splbio(); 619 spl2 = splbio(); 620 if (spl2 != spl1) { 621 printf("wdcstart: not at splbio()\n"); 622 panic("wdcstart"); 623 } 624 splx(spl2); 625 splx(spl1); 626 #endif /* WDC_DIAGNOSTIC */ 627 628 /* is there a xfer ? */ 629 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 630 return; 631 632 /* adjust chp, in case we have a shared queue */ 633 chp = xfer->chp; 634 635 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 636 return; /* channel aleady active */ 637 } 638 #ifdef DIAGNOSTIC 639 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 640 panic("wdcstart: channel waiting for irq\n"); 641 #endif 642 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 643 if (!(*chp->wdc->claim_hw)(chp, 0)) 644 return; 645 646 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 647 chp->channel, xfer->drive), DEBUG_XFERS); 648 chp->ch_flags |= WDCF_ACTIVE; 649 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 650 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 651 chp->ch_drive[xfer->drive].state = 0; 652 } 653 xfer->c_start(chp, xfer); 654 } 655 656 /* restart an interrupted I/O */ 657 void 658 wdcrestart(v) 659 void *v; 660 { 661 struct channel_softc *chp = v; 662 int s; 663 664 s = splbio(); 665 wdcstart(chp); 666 splx(s); 667 } 668 669 670 /* 671 * Interrupt routine for the controller. Acknowledge the interrupt, check for 672 * errors on the current operation, mark it done if necessary, and start the 673 * next request. Also check for a partially done transfer, and continue with 674 * the next chunk if so. 675 */ 676 int 677 wdcintr(arg) 678 void *arg; 679 { 680 struct channel_softc *chp = arg; 681 struct wdc_xfer *xfer; 682 int ret; 683 684 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 685 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 686 DEBUG_INTR); 687 return (0); 688 } 689 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 690 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 691 return (0); 692 } 693 694 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 695 xfer = chp->ch_queue->sc_xfer.tqh_first; 696 if (chp->ch_flags & WDCF_DMA_WAIT) { 697 chp->wdc->dma_status = 698 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 699 xfer->drive, 0); 700 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 701 /* IRQ not for us, not detected by DMA engine */ 702 return 0; 703 } 704 chp->ch_flags &= ~WDCF_DMA_WAIT; 705 } 706 chp->ch_flags &= ~WDCF_IRQ_WAIT; 707 ret = xfer->c_intr(chp, xfer, 1); 708 if (ret == 0) /* irq was not for us, still waiting for irq */ 709 chp->ch_flags |= WDCF_IRQ_WAIT; 710 return (ret); 711 } 712 713 /* Put all disk in RESET state */ 714 void wdc_reset_channel(drvp) 715 struct ata_drive_datas *drvp; 716 { 717 struct channel_softc *chp = drvp->chnl_softc; 718 int drive; 719 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 720 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 721 DEBUG_FUNCS); 722 (void) wdcreset(chp, VERBOSE); 723 for (drive = 0; drive < 2; drive++) { 724 chp->ch_drive[drive].state = 0; 725 } 726 } 727 728 int 729 wdcreset(chp, verb) 730 struct channel_softc *chp; 731 int verb; 732 { 733 int drv_mask1, drv_mask2; 734 735 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 736 WDSD_IBM); /* master */ 737 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 738 WDCTL_RST | WDCTL_IDS); 739 delay(1000); 740 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 741 WDCTL_IDS); 742 delay(1000); 743 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 744 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 745 WDCTL_4BIT); 746 747 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 748 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 749 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 750 if (verb && drv_mask2 != drv_mask1) { 751 printf("%s channel %d: reset failed for", 752 chp->wdc->sc_dev.dv_xname, chp->channel); 753 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 754 printf(" drive 0"); 755 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 756 printf(" drive 1"); 757 printf("\n"); 758 } 759 return (drv_mask1 != drv_mask2) ? 1 : 0; 760 } 761 762 static int 763 __wdcwait_reset(chp, drv_mask) 764 struct channel_softc *chp; 765 int drv_mask; 766 { 767 int timeout; 768 u_int8_t st0, st1; 769 #ifdef WDCDEBUG 770 u_int8_t sc0, sn0, cl0, ch0; 771 u_int8_t sc1, sn1, cl1, ch1; 772 #endif 773 /* wait for BSY to deassert */ 774 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 775 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 776 WDSD_IBM); /* master */ 777 delay(10); 778 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 779 #ifdef WDCDEBUG 780 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 781 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 782 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 783 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 784 #endif 785 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 786 WDSD_IBM | 0x10); /* slave */ 787 delay(10); 788 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 789 #ifdef WDCDEBUG 790 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 791 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 792 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 793 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 794 #endif 795 796 if ((drv_mask & 0x01) == 0) { 797 /* no master */ 798 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 799 /* No master, slave is ready, it's done */ 800 goto end; 801 } 802 } else if ((drv_mask & 0x02) == 0) { 803 /* no slave */ 804 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 805 /* No slave, master is ready, it's done */ 806 goto end; 807 } 808 } else { 809 /* Wait for both master and slave to be ready */ 810 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 811 goto end; 812 } 813 } 814 delay(WDCDELAY); 815 } 816 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 817 if (st0 & WDCS_BSY) 818 drv_mask &= ~0x01; 819 if (st1 & WDCS_BSY) 820 drv_mask &= ~0x02; 821 end: 822 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 823 "cl=0x%x ch=0x%x\n", 824 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 825 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 826 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 827 "cl=0x%x ch=0x%x\n", 828 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 829 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 830 831 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 832 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 833 st0, st1), DEBUG_PROBE); 834 835 return drv_mask; 836 } 837 838 /* 839 * Wait for a drive to be !BSY, and have mask in its status register. 840 * return -1 for a timeout after "timeout" ms. 841 */ 842 int 843 wdcwait(chp, mask, bits, timeout) 844 struct channel_softc *chp; 845 int mask, bits, timeout; 846 { 847 u_char status; 848 int time = 0; 849 #ifdef WDCNDELAY_DEBUG 850 extern int cold; 851 #endif 852 853 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 854 :"none", chp->channel), DEBUG_STATUS); 855 chp->ch_error = 0; 856 857 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 858 859 for (;;) { 860 chp->ch_status = status = 861 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 862 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 863 break; 864 if (++time > timeout) { 865 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 866 "status %x error %x (mask 0x%x bits 0x%x)\n", 867 time, status, 868 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 869 wd_error), mask, bits), 870 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 871 return -1; 872 } 873 delay(WDCDELAY); 874 } 875 #ifdef WDCDEBUG 876 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 877 printf("wdcwait: did busy-wait, time=%d\n", time); 878 #endif 879 if (status & WDCS_ERR) 880 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 881 wd_error); 882 #ifdef WDCNDELAY_DEBUG 883 /* After autoconfig, there should be no long delays. */ 884 if (!cold && time > WDCNDELAY_DEBUG) { 885 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 886 if (xfer == NULL) 887 printf("%s channel %d: warning: busy-wait took %dus\n", 888 chp->wdc->sc_dev.dv_xname, chp->channel, 889 WDCDELAY * time); 890 else 891 printf("%s:%d:%d: warning: busy-wait took %dus\n", 892 chp->wdc->sc_dev.dv_xname, chp->channel, 893 xfer->drive, 894 WDCDELAY * time); 895 } 896 #endif 897 return 0; 898 } 899 900 /* 901 * Busy-wait for DMA to complete 902 */ 903 int 904 wdc_dmawait(chp, xfer, timeout) 905 struct channel_softc *chp; 906 struct wdc_xfer *xfer; 907 int timeout; 908 { 909 int time; 910 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 911 chp->wdc->dma_status = 912 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 913 chp->channel, xfer->drive, 0); 914 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 915 return 0; 916 delay(WDCDELAY); 917 } 918 /* timeout, force a DMA halt */ 919 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 920 chp->channel, xfer->drive, 1); 921 return 1; 922 } 923 924 void 925 wdctimeout(arg) 926 void *arg; 927 { 928 struct channel_softc *chp = (struct channel_softc *)arg; 929 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 930 int s; 931 932 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 933 934 s = splbio(); 935 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 936 __wdcerror(chp, "lost interrupt"); 937 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 938 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 939 xfer->c_bcount, 940 xfer->c_skip); 941 if (chp->ch_flags & WDCF_DMA_WAIT) { 942 chp->wdc->dma_status = 943 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 944 chp->channel, xfer->drive, 1); 945 chp->ch_flags &= ~WDCF_DMA_WAIT; 946 } 947 /* 948 * Call the interrupt routine. If we just missed and interrupt, 949 * it will do what's needed. Else, it will take the needed 950 * action (reset the device). 951 * Before that we need to reinstall the timeout callback, 952 * in case it will miss another irq while in this transfer 953 * We arbitray chose it to be 1s 954 */ 955 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 956 xfer->c_flags |= C_TIMEOU; 957 chp->ch_flags &= ~WDCF_IRQ_WAIT; 958 xfer->c_intr(chp, xfer, 1); 959 } else 960 __wdcerror(chp, "missing untimeout"); 961 splx(s); 962 } 963 964 /* 965 * Probe drive's capabilites, for use by the controller later 966 * Assumes drvp points to an existing drive. 967 * XXX this should be a controller-indep function 968 */ 969 void 970 wdc_probe_caps(drvp) 971 struct ata_drive_datas *drvp; 972 { 973 struct ataparams params, params2; 974 struct channel_softc *chp = drvp->chnl_softc; 975 struct device *drv_dev = drvp->drv_softc; 976 struct wdc_softc *wdc = chp->wdc; 977 int i, printed; 978 char *sep = ""; 979 int cf_flags; 980 981 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 982 /* IDENTIFY failed. Can't tell more about the device */ 983 return; 984 } 985 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 986 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 987 /* 988 * Controller claims 16 and 32 bit transfers. 989 * Re-do an IDENTIFY with 32-bit transfers, 990 * and compare results. 991 */ 992 drvp->drive_flags |= DRIVE_CAP32; 993 ata_get_params(drvp, AT_POLL, ¶ms2); 994 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 995 /* Not good. fall back to 16bits */ 996 drvp->drive_flags &= ~DRIVE_CAP32; 997 } else { 998 printf("%s: 32-bit data port", drv_dev->dv_xname); 999 } 1000 } 1001 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1002 if (params.atap_ata_major > 0x01 && 1003 params.atap_ata_major != 0xffff) { 1004 for (i = 14; i > 0; i--) { 1005 if (params.atap_ata_major & (1 << i)) { 1006 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1007 printf("%s: ", drv_dev->dv_xname); 1008 else 1009 printf(", "); 1010 printf("ATA version %d\n", i); 1011 drvp->ata_vers = i; 1012 break; 1013 } 1014 } 1015 } else 1016 #endif 1017 if (drvp->drive_flags & DRIVE_CAP32) 1018 printf("\n"); 1019 1020 /* An ATAPI device is at last PIO mode 3 */ 1021 if (drvp->drive_flags & DRIVE_ATAPI) 1022 drvp->PIO_mode = 3; 1023 1024 /* 1025 * It's not in the specs, but it seems that some drive 1026 * returns 0xffff in atap_extensions when this field is invalid 1027 */ 1028 if (params.atap_extensions != 0xffff && 1029 (params.atap_extensions & WDC_EXT_MODES)) { 1030 printed = 0; 1031 /* 1032 * XXX some drives report something wrong here (they claim to 1033 * support PIO mode 8 !). As mode is coded on 3 bits in 1034 * SET FEATURE, limit it to 7 (so limit i to 4). 1035 * If higther mode than 7 is found, abort. 1036 */ 1037 for (i = 7; i >= 0; i--) { 1038 if ((params.atap_piomode_supp & (1 << i)) == 0) 1039 continue; 1040 if (i > 4) 1041 return; 1042 /* 1043 * See if mode is accepted. 1044 * If the controller can't set its PIO mode, 1045 * assume the defaults are good, so don't try 1046 * to set it 1047 */ 1048 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1049 if (ata_set_mode(drvp, 0x08 | (i + 3), 1050 AT_POLL) != CMD_OK) 1051 continue; 1052 if (!printed) { 1053 printf("%s: drive supports PIO mode %d", 1054 drv_dev->dv_xname, i + 3); 1055 sep = ","; 1056 printed = 1; 1057 } 1058 /* 1059 * If controller's driver can't set its PIO mode, 1060 * get the highter one for the drive. 1061 */ 1062 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1063 wdc->PIO_cap >= i + 3) { 1064 drvp->PIO_mode = i + 3; 1065 drvp->PIO_cap = i + 3; 1066 break; 1067 } 1068 } 1069 if (!printed) { 1070 /* 1071 * We didn't find a valid PIO mode. 1072 * Assume the values returned for DMA are buggy too 1073 */ 1074 return; 1075 } 1076 drvp->drive_flags |= DRIVE_MODE; 1077 printed = 0; 1078 for (i = 7; i >= 0; i--) { 1079 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1080 continue; 1081 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1082 (wdc->cap & WDC_CAPABILITY_MODE)) 1083 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1084 != CMD_OK) 1085 continue; 1086 if (!printed) { 1087 printf("%s DMA mode %d", sep, i); 1088 sep = ","; 1089 printed = 1; 1090 } 1091 if (wdc->cap & WDC_CAPABILITY_DMA) { 1092 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1093 wdc->DMA_cap < i) 1094 continue; 1095 drvp->DMA_mode = i; 1096 drvp->DMA_cap = i; 1097 drvp->drive_flags |= DRIVE_DMA; 1098 } 1099 break; 1100 } 1101 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1102 printed = 0; 1103 for (i = 7; i >= 0; i--) { 1104 if ((params.atap_udmamode_supp & (1 << i)) 1105 == 0) 1106 continue; 1107 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1108 (wdc->cap & WDC_CAPABILITY_UDMA)) 1109 if (ata_set_mode(drvp, 0x40 | i, 1110 AT_POLL) != CMD_OK) 1111 continue; 1112 if (!printed) { 1113 printf("%s Ultra-DMA mode %d", sep, i); 1114 if (i == 2) 1115 printf(" (Ultra/33)"); 1116 else if (i == 4) 1117 printf(" (Ultra/66)"); 1118 else if (i == 5) 1119 printf(" (Ultra/100)"); 1120 sep = ","; 1121 printed = 1; 1122 } 1123 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1124 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1125 wdc->UDMA_cap < i) 1126 continue; 1127 drvp->UDMA_mode = i; 1128 drvp->UDMA_cap = i; 1129 drvp->drive_flags |= DRIVE_UDMA; 1130 } 1131 break; 1132 } 1133 } 1134 printf("\n"); 1135 } 1136 1137 /* Try to guess ATA version here, if it didn't get reported */ 1138 if (drvp->ata_vers == 0) { 1139 if (drvp->drive_flags & DRIVE_UDMA) 1140 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1141 else if (drvp->PIO_cap > 2) 1142 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1143 } 1144 cf_flags = drv_dev->dv_cfdata->cf_flags; 1145 if (cf_flags & ATA_CONFIG_PIO_SET) { 1146 drvp->PIO_mode = 1147 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1148 drvp->drive_flags |= DRIVE_MODE; 1149 } 1150 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1151 /* don't care about DMA modes */ 1152 return; 1153 } 1154 if (cf_flags & ATA_CONFIG_DMA_SET) { 1155 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1156 ATA_CONFIG_DMA_DISABLE) { 1157 drvp->drive_flags &= ~DRIVE_DMA; 1158 } else { 1159 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1160 ATA_CONFIG_DMA_OFF; 1161 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1162 } 1163 } 1164 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1165 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1166 ATA_CONFIG_UDMA_DISABLE) { 1167 drvp->drive_flags &= ~DRIVE_UDMA; 1168 } else { 1169 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1170 ATA_CONFIG_UDMA_OFF; 1171 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1172 } 1173 } 1174 } 1175 1176 /* 1177 * downgrade the transfer mode of a drive after an error. return 1 if 1178 * downgrade was possible, 0 otherwise. 1179 */ 1180 int 1181 wdc_downgrade_mode(drvp) 1182 struct ata_drive_datas *drvp; 1183 { 1184 struct channel_softc *chp = drvp->chnl_softc; 1185 struct device *drv_dev = drvp->drv_softc; 1186 struct wdc_softc *wdc = chp->wdc; 1187 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1188 1189 /* if drive or controller don't know its mode, we can't do much */ 1190 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1191 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1192 return 0; 1193 /* current drive mode was set by a config flag, let it this way */ 1194 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1195 (cf_flags & ATA_CONFIG_DMA_SET) || 1196 (cf_flags & ATA_CONFIG_UDMA_SET)) 1197 return 0; 1198 1199 /* 1200 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1201 * Maybe we didn't properly notice the cable type 1202 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1203 * It helps in some cases. 1204 */ 1205 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1206 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1207 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1208 drv_dev->dv_xname, drvp->UDMA_mode); 1209 } 1210 1211 /* 1212 * If we were using ultra-DMA, don't downgrade to multiword DMA 1213 * if we noticed a CRC error. It has been noticed that CRC errors 1214 * in ultra-DMA lead to silent data corruption in multiword DMA. 1215 * Data corruption is less likely to occur in PIO mode. 1216 */ 1217 else if ((drvp->drive_flags & DRIVE_UDMA) && 1218 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1219 drvp->drive_flags &= ~DRIVE_UDMA; 1220 drvp->drive_flags |= DRIVE_DMA; 1221 drvp->DMA_mode = drvp->DMA_cap; 1222 printf("%s: transfer error, downgrading to DMA mode %d\n", 1223 drv_dev->dv_xname, drvp->DMA_mode); 1224 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1225 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1226 drvp->PIO_mode = drvp->PIO_cap; 1227 printf("%s: transfer error, downgrading to PIO mode %d\n", 1228 drv_dev->dv_xname, drvp->PIO_mode); 1229 } else /* already using PIO, can't downgrade */ 1230 return 0; 1231 1232 wdc->set_modes(chp); 1233 /* reset the channel, which will shedule all drives for setup */ 1234 wdc_reset_channel(drvp); 1235 return 1; 1236 } 1237 1238 int 1239 wdc_exec_command(drvp, wdc_c) 1240 struct ata_drive_datas *drvp; 1241 struct wdc_command *wdc_c; 1242 { 1243 struct channel_softc *chp = drvp->chnl_softc; 1244 struct wdc_xfer *xfer; 1245 int s, ret; 1246 1247 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1248 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1249 DEBUG_FUNCS); 1250 1251 /* set up an xfer and queue. Wait for completion */ 1252 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1253 WDC_NOSLEEP); 1254 if (xfer == NULL) { 1255 return WDC_TRY_AGAIN; 1256 } 1257 1258 if (wdc_c->flags & AT_POLL) 1259 xfer->c_flags |= C_POLL; 1260 xfer->drive = drvp->drive; 1261 xfer->databuf = wdc_c->data; 1262 xfer->c_bcount = wdc_c->bcount; 1263 xfer->cmd = wdc_c; 1264 xfer->c_start = __wdccommand_start; 1265 xfer->c_intr = __wdccommand_intr; 1266 xfer->c_kill_xfer = __wdccommand_done; 1267 1268 s = splbio(); 1269 wdc_exec_xfer(chp, xfer); 1270 #ifdef DIAGNOSTIC 1271 if ((wdc_c->flags & AT_POLL) != 0 && 1272 (wdc_c->flags & AT_DONE) == 0) 1273 panic("wdc_exec_command: polled command not done\n"); 1274 #endif 1275 if (wdc_c->flags & AT_DONE) { 1276 ret = WDC_COMPLETE; 1277 } else { 1278 if (wdc_c->flags & AT_WAIT) { 1279 while ((wdc_c->flags & AT_DONE) == 0) { 1280 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1281 } 1282 ret = WDC_COMPLETE; 1283 } else { 1284 ret = WDC_QUEUED; 1285 } 1286 } 1287 splx(s); 1288 return ret; 1289 } 1290 1291 void 1292 __wdccommand_start(chp, xfer) 1293 struct channel_softc *chp; 1294 struct wdc_xfer *xfer; 1295 { 1296 int drive = xfer->drive; 1297 struct wdc_command *wdc_c = xfer->cmd; 1298 1299 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1300 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1301 DEBUG_FUNCS); 1302 1303 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1304 WDSD_IBM | (drive << 4)); 1305 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1306 wdc_c->timeout) != 0) { 1307 wdc_c->flags |= AT_TIMEOU; 1308 __wdccommand_done(chp, xfer); 1309 return; 1310 } 1311 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1312 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1313 if ((wdc_c->flags & AT_POLL) == 0) { 1314 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1315 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1316 wdctimeout, chp); 1317 return; 1318 } 1319 /* 1320 * Polled command. Wait for drive ready or drq. Done in intr(). 1321 * Wait for at last 400ns for status bit to be valid. 1322 */ 1323 delay(10); 1324 __wdccommand_intr(chp, xfer, 0); 1325 } 1326 1327 int 1328 __wdccommand_intr(chp, xfer, irq) 1329 struct channel_softc *chp; 1330 struct wdc_xfer *xfer; 1331 int irq; 1332 { 1333 struct wdc_command *wdc_c = xfer->cmd; 1334 int bcount = wdc_c->bcount; 1335 char *data = wdc_c->data; 1336 1337 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1338 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1339 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1340 (irq == 0) ? wdc_c->timeout : 0)) { 1341 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1342 return 0; /* IRQ was not for us */ 1343 wdc_c->flags |= AT_TIMEOU; 1344 __wdccommand_done(chp, xfer); 1345 return 1; 1346 } 1347 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1348 chp->wdc->irqack(chp); 1349 if (wdc_c->flags & AT_READ) { 1350 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1351 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1352 0, (u_int32_t*)data, bcount >> 2); 1353 data += bcount & 0xfffffffc; 1354 bcount = bcount & 0x03; 1355 } 1356 if (bcount > 0) 1357 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1358 wd_data, (u_int16_t *)data, bcount >> 1); 1359 } else if (wdc_c->flags & AT_WRITE) { 1360 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1361 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1362 0, (u_int32_t*)data, bcount >> 2); 1363 data += bcount & 0xfffffffc; 1364 bcount = bcount & 0x03; 1365 } 1366 if (bcount > 0) 1367 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1368 wd_data, (u_int16_t *)data, bcount >> 1); 1369 } 1370 __wdccommand_done(chp, xfer); 1371 return 1; 1372 } 1373 1374 void 1375 __wdccommand_done(chp, xfer) 1376 struct channel_softc *chp; 1377 struct wdc_xfer *xfer; 1378 { 1379 struct wdc_command *wdc_c = xfer->cmd; 1380 1381 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1382 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1383 1384 callout_stop(&chp->ch_callout); 1385 1386 if (chp->ch_status & WDCS_DWF) 1387 wdc_c->flags |= AT_DF; 1388 if (chp->ch_status & WDCS_ERR) { 1389 wdc_c->flags |= AT_ERROR; 1390 wdc_c->r_error = chp->ch_error; 1391 } 1392 wdc_c->flags |= AT_DONE; 1393 if ((wdc_c->flags & AT_READREG) != 0 && 1394 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1395 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1396 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1397 wd_sdh); 1398 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1399 wd_cyl_hi) << 8; 1400 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1401 wd_cyl_lo); 1402 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1403 wd_sector); 1404 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1405 wd_seccnt); 1406 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1407 wd_error); 1408 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1409 wd_precomp); 1410 } 1411 wdc_free_xfer(chp, xfer); 1412 if (wdc_c->flags & AT_WAIT) 1413 wakeup(wdc_c); 1414 else if (wdc_c->callback) 1415 wdc_c->callback(wdc_c->callback_arg); 1416 wdcstart(chp); 1417 return; 1418 } 1419 1420 /* 1421 * Send a command. The drive should be ready. 1422 * Assumes interrupts are blocked. 1423 */ 1424 void 1425 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1426 struct channel_softc *chp; 1427 u_int8_t drive; 1428 u_int8_t command; 1429 u_int16_t cylin; 1430 u_int8_t head, sector, count, precomp; 1431 { 1432 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1433 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1434 chp->channel, drive, command, cylin, head, sector, count, precomp), 1435 DEBUG_FUNCS); 1436 1437 /* Select drive, head, and addressing mode. */ 1438 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1439 WDSD_IBM | (drive << 4) | head); 1440 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1441 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1442 precomp); 1443 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1444 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1445 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1447 1448 /* Send command. */ 1449 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1450 return; 1451 } 1452 1453 /* 1454 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1455 * tested by the caller. 1456 */ 1457 void 1458 wdccommandshort(chp, drive, command) 1459 struct channel_softc *chp; 1460 int drive; 1461 int command; 1462 { 1463 1464 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1465 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1466 DEBUG_FUNCS); 1467 1468 /* Select drive. */ 1469 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1470 WDSD_IBM | (drive << 4)); 1471 1472 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1473 } 1474 1475 /* Add a command to the queue and start controller. Must be called at splbio */ 1476 1477 void 1478 wdc_exec_xfer(chp, xfer) 1479 struct channel_softc *chp; 1480 struct wdc_xfer *xfer; 1481 { 1482 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1483 chp->channel, xfer->drive), DEBUG_XFERS); 1484 1485 /* complete xfer setup */ 1486 xfer->chp = chp; 1487 1488 /* 1489 * If we are a polled command, and the list is not empty, 1490 * we are doing a dump. Drop the list to allow the polled command 1491 * to complete, we're going to reboot soon anyway. 1492 */ 1493 if ((xfer->c_flags & C_POLL) != 0 && 1494 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1495 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1496 } 1497 /* insert at the end of command list */ 1498 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1499 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1500 chp->ch_flags), DEBUG_XFERS); 1501 wdcstart(chp); 1502 } 1503 1504 struct wdc_xfer * 1505 wdc_get_xfer(flags) 1506 int flags; 1507 { 1508 struct wdc_xfer *xfer; 1509 int s; 1510 1511 s = splbio(); 1512 xfer = pool_get(&wdc_xfer_pool, 1513 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1514 splx(s); 1515 memset(xfer, 0, sizeof(struct wdc_xfer)); 1516 return xfer; 1517 } 1518 1519 void 1520 wdc_free_xfer(chp, xfer) 1521 struct channel_softc *chp; 1522 struct wdc_xfer *xfer; 1523 { 1524 struct wdc_softc *wdc = chp->wdc; 1525 int s; 1526 1527 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1528 (*wdc->free_hw)(chp); 1529 s = splbio(); 1530 chp->ch_flags &= ~WDCF_ACTIVE; 1531 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1532 pool_put(&wdc_xfer_pool, xfer); 1533 splx(s); 1534 } 1535 1536 /* 1537 * Kill off all pending xfers for a channel_softc. 1538 * 1539 * Must be called at splbio(). 1540 */ 1541 void 1542 wdc_kill_pending(chp) 1543 struct channel_softc *chp; 1544 { 1545 struct wdc_xfer *xfer; 1546 1547 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1548 chp = xfer->chp; 1549 (*xfer->c_kill_xfer)(chp, xfer); 1550 } 1551 } 1552 1553 static void 1554 __wdcerror(chp, msg) 1555 struct channel_softc *chp; 1556 char *msg; 1557 { 1558 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1559 1560 if (xfer == NULL) 1561 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1562 msg); 1563 else 1564 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1565 chp->channel, xfer->drive, msg); 1566 } 1567 1568 /* 1569 * the bit bucket 1570 */ 1571 void 1572 wdcbit_bucket(chp, size) 1573 struct channel_softc *chp; 1574 int size; 1575 { 1576 1577 for (; size >= 2; size -= 2) 1578 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1579 if (size) 1580 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1581 } 1582 1583 int 1584 wdc_addref(chp) 1585 struct channel_softc *chp; 1586 { 1587 struct wdc_softc *wdc = chp->wdc; 1588 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1589 int s, error = 0; 1590 1591 s = splbio(); 1592 if (adapter->_generic.scsipi_refcnt++ == 0 && 1593 adapter->_generic.scsipi_enable != NULL) { 1594 error = (*adapter->_generic.scsipi_enable)(wdc, 1); 1595 if (error) 1596 adapter->_generic.scsipi_refcnt--; 1597 } 1598 splx(s); 1599 return (error); 1600 } 1601 1602 void 1603 wdc_delref(chp) 1604 struct channel_softc *chp; 1605 { 1606 struct wdc_softc *wdc = chp->wdc; 1607 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1608 int s; 1609 1610 s = splbio(); 1611 if (adapter->_generic.scsipi_refcnt-- == 1 && 1612 adapter->_generic.scsipi_enable != NULL) 1613 (void) (*adapter->_generic.scsipi_enable)(wdc, 0); 1614 splx(s); 1615 } 1616 1617 void 1618 wdc_print_modes(struct channel_softc *chp) 1619 { 1620 int drive; 1621 struct ata_drive_datas *drvp; 1622 1623 for (drive = 0; drive < 2; drive++) { 1624 drvp = &chp->ch_drive[drive]; 1625 if ((drvp->drive_flags & DRIVE) == 0) 1626 continue; 1627 printf("%s(%s:%d:%d): using PIO mode %d", 1628 drvp->drv_softc->dv_xname, 1629 chp->wdc->sc_dev.dv_xname, 1630 chp->channel, drive, drvp->PIO_mode); 1631 if (drvp->drive_flags & DRIVE_DMA) 1632 printf(", DMA mode %d", drvp->DMA_mode); 1633 if (drvp->drive_flags & DRIVE_UDMA) { 1634 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1635 if (drvp->UDMA_mode == 2) 1636 printf(" (Ultra/33)"); 1637 else if (drvp->UDMA_mode == 4) 1638 printf(" (Ultra/66)"); 1639 else if (drvp->UDMA_mode == 5) 1640 printf(" (Ultra/100)"); 1641 } 1642 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1643 printf(" (using DMA data transfers)"); 1644 printf("\n"); 1645 } 1646 } 1647
Indexes created Tue Sep 23 02:09:52 GMT 2025