wdc.c revision 1.95
1 /* $NetBSD: wdc.c,v 1.95 2001/03/21 08:44:14 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "atapibus.h" 105 106 #define WDCDELAY 100 /* 100 microseconds */ 107 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 108 #if 0 109 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 110 #define WDCNDELAY_DEBUG 50 111 #endif 112 113 struct pool wdc_xfer_pool; 114 115 static void __wdcerror __P((struct channel_softc*, char *)); 116 static int __wdcwait_reset __P((struct channel_softc *, int)); 117 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 118 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 119 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 120 int wdprint __P((void *, const char *)); 121 122 123 #define DEBUG_INTR 0x01 124 #define DEBUG_XFERS 0x02 125 #define DEBUG_STATUS 0x04 126 #define DEBUG_FUNCS 0x08 127 #define DEBUG_PROBE 0x10 128 #define DEBUG_DETACH 0x20 129 #define DEBUG_DELAY 0x40 130 #ifdef WDCDEBUG 131 int wdcdebug_mask = 0; 132 int wdc_nxfer = 0; 133 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 134 #else 135 #define WDCDEBUG_PRINT(args, level) 136 #endif 137 138 int 139 wdprint(aux, pnp) 140 void *aux; 141 const char *pnp; 142 { 143 struct ata_atapi_attach *aa_link = aux; 144 if (pnp) 145 printf("drive at %s", pnp); 146 printf(" channel %d drive %d", aa_link->aa_channel, 147 aa_link->aa_drv_data->drive); 148 return (UNCONF); 149 } 150 151 int 152 atapi_print(aux, pnp) 153 void *aux; 154 const char *pnp; 155 { 156 struct ata_atapi_attach *aa_link = aux; 157 if (pnp) 158 printf("atapibus at %s", pnp); 159 printf(" channel %d", aa_link->aa_channel); 160 return (UNCONF); 161 } 162 163 /* Test to see controller with at last one attached drive is there. 164 * Returns a bit for each possible drive found (0x01 for drive 0, 165 * 0x02 for drive 1). 166 * Logic: 167 * - If a status register is at 0xff, assume there is no drive here 168 * (ISA has pull-up resistors). If no drive at all -> return. 169 * - reset the controller, wait for it to complete (may take up to 31s !). 170 * If timeout -> return. 171 * - test ATA/ATAPI signatures. If at last one drive found -> return. 172 * - try an ATA command on the master. 173 */ 174 175 int 176 wdcprobe(chp) 177 struct channel_softc *chp; 178 { 179 u_int8_t st0, st1, sc, sn, cl, ch; 180 u_int8_t ret_value = 0x03; 181 u_int8_t drive; 182 int found; 183 184 /* 185 * Sanity check to see if the wdc channel responds at all. 186 */ 187 188 if (chp->wdc == NULL || 189 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 190 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 191 WDSD_IBM); 192 delay(10); 193 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 194 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 195 WDSD_IBM | 0x10); 196 delay(10); 197 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 198 199 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 200 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 201 chp->channel, st0, st1), DEBUG_PROBE); 202 203 if (st0 == 0xff) 204 ret_value &= ~0x01; 205 if (st1 == 0xff) 206 ret_value &= ~0x02; 207 if (ret_value == 0) 208 return 0; 209 } 210 211 /* assert SRST, wait for reset to complete */ 212 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 213 WDSD_IBM); 214 delay(10); 215 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 216 WDCTL_RST | WDCTL_IDS); 217 DELAY(1000); 218 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 219 WDCTL_IDS); 220 delay(1000); 221 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 222 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 223 delay(10); 224 225 ret_value = __wdcwait_reset(chp, ret_value); 226 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 227 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 228 ret_value), DEBUG_PROBE); 229 230 /* if reset failed, there's nothing here */ 231 if (ret_value == 0) 232 return 0; 233 234 /* 235 * Test presence of drives. First test register signatures looking for 236 * ATAPI devices. If it's not an ATAPI and reset said there may be 237 * something here assume it's ATA or OLD. Ghost will be killed later in 238 * attach routine. 239 */ 240 found = 0; 241 for (drive = 0; drive < 2; drive++) { 242 if ((ret_value & (0x01 << drive)) == 0) 243 continue; 244 if (1 < ++found && chp->wdc != NULL && 245 (chp->wdc->cap & WDC_CAPABILITY_SINGLE_DRIVE)) { 246 /* 247 * Ignore second drive if WDC_CAPABILITY_SINGLE_DRIVE 248 * is set. 249 * 250 * Some CF Card (for ex. IBM MicroDrive and SanDisk) 251 * doesn't seem to implement drive select command. In 252 * this case, you can't eliminate ghost drive properly. 253 */ 254 WDCDEBUG_PRINT(("%s:%d:%d: ignored.\n", 255 chp->wdc->sc_dev.dv_xname, 256 chp->channel, drive), DEBUG_PROBE); 257 break; 258 } 259 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 260 WDSD_IBM | (drive << 4)); 261 delay(10); 262 /* Save registers contents */ 263 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 264 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 265 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 266 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 267 268 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 269 "cl=0x%x ch=0x%x\n", 270 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 271 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 272 /* 273 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 274 * we get wrong values here, so ignore it. 275 */ 276 if (cl == 0x14 && ch == 0xeb) { 277 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 278 } else { 279 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 280 if (chp->wdc == NULL || 281 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 282 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 283 } 284 } 285 return (ret_value); 286 } 287 288 void 289 wdcattach(chp) 290 struct channel_softc *chp; 291 { 292 int channel_flags, ctrl_flags, i, error; 293 struct ata_atapi_attach aa_link; 294 struct ataparams params; 295 static int inited = 0; 296 297 callout_init(&chp->ch_callout); 298 299 if ((error = wdc_addref(chp)) != 0) { 300 printf("%s: unable to enable controller\n", 301 chp->wdc->sc_dev.dv_xname); 302 return; 303 } 304 305 if (wdcprobe(chp) == 0) 306 /* If no drives, abort attach here. */ 307 goto out; 308 309 /* initialise global data */ 310 if (inited == 0) { 311 /* Initialize the wdc_xfer pool. */ 312 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 313 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 314 inited++; 315 } 316 TAILQ_INIT(&chp->ch_queue->sc_xfer); 317 318 for (i = 0; i < 2; i++) { 319 chp->ch_drive[i].chnl_softc = chp; 320 chp->ch_drive[i].drive = i; 321 /* 322 * Init error counter so that an error withing the first xfers 323 * will trigger a downgrade 324 */ 325 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 326 327 /* If controller can't do 16bit flag the drives as 32bit */ 328 if ((chp->wdc->cap & 329 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 330 WDC_CAPABILITY_DATA32) 331 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 332 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 333 continue; 334 335 /* 336 * Wait a bit, some devices are weird just after a reset. 337 * Then issue a IDENTIFY command, to try to detect slave ghost 338 */ 339 delay(100); 340 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 341 if (error != CMD_OK) { 342 delay(1000000); 343 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 344 ¶ms); 345 } 346 if (error == CMD_OK) { 347 /* If IDENTIFY succeded, this is not an OLD ctrl */ 348 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 349 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 350 } else { 351 chp->ch_drive[i].drive_flags &= 352 ~(DRIVE_ATA | DRIVE_ATAPI); 353 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 354 chp->wdc->sc_dev.dv_xname, 355 chp->channel, i, error), DEBUG_PROBE); 356 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 357 continue; 358 /* 359 * Pre-ATA drive ? 360 * Test registers writability (Error register not 361 * writable, but cyllo is), then try an ATA command. 362 */ 363 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 364 WDSD_IBM | (i << 4)); 365 delay(10); 366 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 367 wd_error, 0x58); 368 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 369 wd_cyl_lo, 0xa5); 370 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 371 wd_error == 0x58) || 372 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 373 wd_cyl_lo) != 0xa5) { 374 WDCDEBUG_PRINT(("%s:%d:%d: register " 375 "writability failed\n", 376 chp->wdc->sc_dev.dv_xname, 377 chp->channel, i), DEBUG_PROBE); 378 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 379 } 380 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 381 WDSD_IBM | (i << 4)); 382 delay(100); 383 if (wait_for_ready(chp, 10000) != 0) { 384 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 385 chp->wdc->sc_dev.dv_xname, 386 chp->channel, i), DEBUG_PROBE); 387 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 388 continue; 389 } 390 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 391 wd_command, WDCC_RECAL); 392 if (wait_for_ready(chp, 10000) != 0) { 393 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 394 chp->wdc->sc_dev.dv_xname, 395 chp->channel, i), DEBUG_PROBE); 396 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 397 } 398 } 399 } 400 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 401 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 402 403 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 404 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 405 DEBUG_PROBE); 406 407 /* If no drives, abort here */ 408 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 409 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 410 goto out; 411 412 /* 413 * Attach an ATAPI bus, if needed. 414 */ 415 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 416 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 417 #if NATAPIBUS > 0 418 wdc_atapibus_attach(chp); 419 #else 420 /* 421 * Fills in a fake aa_link and call config_found, so that 422 * the config machinery will print 423 * "atapibus at xxx not configured" 424 */ 425 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 426 aa_link.aa_type = T_ATAPI; 427 aa_link.aa_channel = chp->channel; 428 aa_link.aa_openings = 1; 429 aa_link.aa_drv_data = 0; 430 aa_link.aa_bus_private = NULL; 431 chp->atapibus = config_found(&chp->wdc->sc_dev, 432 (void *)&aa_link, atapi_print); 433 #endif 434 } 435 436 for (i = 0; i < 2; i++) { 437 if ((chp->ch_drive[i].drive_flags & 438 (DRIVE_ATA | DRIVE_OLD)) == 0) { 439 continue; 440 } 441 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 442 aa_link.aa_type = T_ATA; 443 aa_link.aa_channel = chp->channel; 444 aa_link.aa_openings = 1; 445 aa_link.aa_drv_data = &chp->ch_drive[i]; 446 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 447 wdc_probe_caps(&chp->ch_drive[i]); 448 } 449 450 /* 451 * reset drive_flags for unnatached devices, reset state for attached 452 * ones 453 */ 454 for (i = 0; i < 2; i++) { 455 if (chp->ch_drive[i].drv_softc == NULL) 456 chp->ch_drive[i].drive_flags = 0; 457 else 458 chp->ch_drive[i].state = 0; 459 } 460 461 /* 462 * Reset channel. The probe, with some combinations of ATA/ATAPI 463 * devices keep it in a mostly working, but strange state (with busy 464 * led on) 465 */ 466 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 467 delay(50); 468 wdcreset(chp, VERBOSE); 469 /* 470 * Read status registers to avoid spurious interrupts. 471 */ 472 for (i = 1; i >= 0; i--) { 473 if (chp->ch_drive[i].drive_flags & DRIVE) { 474 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 475 wd_sdh, WDSD_IBM | (i << 4)); 476 if (wait_for_unbusy(chp, 10000) < 0) 477 printf("%s:%d:%d: device busy\n", 478 chp->wdc->sc_dev.dv_xname, 479 chp->channel, i); 480 } 481 } 482 } 483 484 out: 485 wdc_delref(chp); 486 } 487 488 /* 489 * Call activate routine of underlying devices. 490 */ 491 int 492 wdcactivate(self, act) 493 struct device *self; 494 enum devact act; 495 { 496 struct wdc_softc *wdc = (struct wdc_softc *)self; 497 struct channel_softc *chp; 498 struct device *sc = 0; 499 int s, i, j, error = 0; 500 501 s = splbio(); 502 switch (act) { 503 case DVACT_ACTIVATE: 504 error = EOPNOTSUPP; 505 break; 506 507 case DVACT_DEACTIVATE: 508 for (i = 0; i < wdc->nchannels; i++) { 509 chp = wdc->channels[i]; 510 511 /* 512 * We might call deactivate routine for 513 * the children of atapibus twice (once via 514 * atapibus, once directly), but since 515 * config_deactivate maintains DVF_ACTIVE flag, 516 * it's safe. 517 */ 518 sc = chp->atapibus; 519 if (sc != NULL) { 520 error = config_deactivate(sc); 521 if (error != 0) 522 goto out; 523 } 524 525 for (j = 0; j < 2; j++) { 526 sc = chp->ch_drive[j].drv_softc; 527 WDCDEBUG_PRINT(("wdcactivate: %s:" 528 " deactivating %s\n", wdc->sc_dev.dv_xname, 529 sc == NULL ? "nodrv" : sc->dv_xname), 530 DEBUG_DETACH); 531 if (sc != NULL) { 532 error = config_deactivate(sc); 533 if (error != 0) 534 goto out; 535 } 536 } 537 } 538 break; 539 } 540 541 out: 542 splx(s); 543 544 #ifdef WDCDEBUG 545 if (sc && error != 0) 546 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 547 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 548 #endif 549 return (error); 550 } 551 552 int 553 wdcdetach(self, flags) 554 struct device *self; 555 int flags; 556 { 557 struct wdc_softc *wdc = (struct wdc_softc *)self; 558 struct channel_softc *chp; 559 struct device *sc = 0; 560 int i, j, error = 0; 561 562 for (i = 0; i < wdc->nchannels; i++) { 563 chp = wdc->channels[i]; 564 565 /* 566 * Detach atapibus and its children. 567 */ 568 sc = chp->atapibus; 569 if (sc != NULL) { 570 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 571 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 572 error = config_detach(sc, flags); 573 if (error != 0) 574 goto out; 575 } 576 577 /* 578 * Detach our other children. 579 */ 580 for (j = 0; j < 2; j++) { 581 sc = chp->ch_drive[j].drv_softc; 582 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 583 wdc->sc_dev.dv_xname, 584 sc == NULL ? "nodrv" : sc->dv_xname), 585 DEBUG_DETACH); 586 if (sc != NULL) { 587 error = config_detach(sc, flags); 588 if (error != 0) 589 goto out; 590 } 591 } 592 593 wdc_kill_pending(chp); 594 } 595 596 out: 597 #ifdef WDCDEBUG 598 if (sc && error != 0) 599 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 600 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 601 #endif 602 return (error); 603 } 604 605 /* 606 * Start I/O on a controller, for the given channel. 607 * The first xfer may be not for our channel if the channel queues 608 * are shared. 609 */ 610 void 611 wdcstart(chp) 612 struct channel_softc *chp; 613 { 614 struct wdc_xfer *xfer; 615 616 #ifdef WDC_DIAGNOSTIC 617 int spl1, spl2; 618 619 spl1 = splbio(); 620 spl2 = splbio(); 621 if (spl2 != spl1) { 622 printf("wdcstart: not at splbio()\n"); 623 panic("wdcstart"); 624 } 625 splx(spl2); 626 splx(spl1); 627 #endif /* WDC_DIAGNOSTIC */ 628 629 /* is there a xfer ? */ 630 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 631 return; 632 633 /* adjust chp, in case we have a shared queue */ 634 chp = xfer->chp; 635 636 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 637 return; /* channel aleady active */ 638 } 639 #ifdef DIAGNOSTIC 640 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 641 panic("wdcstart: channel waiting for irq\n"); 642 #endif 643 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 644 if (!(*chp->wdc->claim_hw)(chp, 0)) 645 return; 646 647 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 648 chp->channel, xfer->drive), DEBUG_XFERS); 649 chp->ch_flags |= WDCF_ACTIVE; 650 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 651 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 652 chp->ch_drive[xfer->drive].state = 0; 653 } 654 xfer->c_start(chp, xfer); 655 } 656 657 /* restart an interrupted I/O */ 658 void 659 wdcrestart(v) 660 void *v; 661 { 662 struct channel_softc *chp = v; 663 int s; 664 665 s = splbio(); 666 wdcstart(chp); 667 splx(s); 668 } 669 670 671 /* 672 * Interrupt routine for the controller. Acknowledge the interrupt, check for 673 * errors on the current operation, mark it done if necessary, and start the 674 * next request. Also check for a partially done transfer, and continue with 675 * the next chunk if so. 676 */ 677 int 678 wdcintr(arg) 679 void *arg; 680 { 681 struct channel_softc *chp = arg; 682 struct wdc_xfer *xfer; 683 int ret; 684 685 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 686 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 687 DEBUG_INTR); 688 return (0); 689 } 690 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 691 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 692 return (0); 693 } 694 695 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 696 xfer = chp->ch_queue->sc_xfer.tqh_first; 697 if (chp->ch_flags & WDCF_DMA_WAIT) { 698 chp->wdc->dma_status = 699 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 700 xfer->drive, 0); 701 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 702 /* IRQ not for us, not detected by DMA engine */ 703 return 0; 704 } 705 chp->ch_flags &= ~WDCF_DMA_WAIT; 706 } 707 chp->ch_flags &= ~WDCF_IRQ_WAIT; 708 ret = xfer->c_intr(chp, xfer, 1); 709 if (ret == 0) /* irq was not for us, still waiting for irq */ 710 chp->ch_flags |= WDCF_IRQ_WAIT; 711 return (ret); 712 } 713 714 /* Put all disk in RESET state */ 715 void wdc_reset_channel(drvp) 716 struct ata_drive_datas *drvp; 717 { 718 struct channel_softc *chp = drvp->chnl_softc; 719 int drive; 720 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 721 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 722 DEBUG_FUNCS); 723 (void) wdcreset(chp, VERBOSE); 724 for (drive = 0; drive < 2; drive++) { 725 chp->ch_drive[drive].state = 0; 726 } 727 } 728 729 int 730 wdcreset(chp, verb) 731 struct channel_softc *chp; 732 int verb; 733 { 734 int drv_mask1, drv_mask2; 735 736 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 737 WDSD_IBM); /* master */ 738 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 739 WDCTL_RST | WDCTL_IDS); 740 delay(1000); 741 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 742 WDCTL_IDS); 743 delay(1000); 744 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 745 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 746 WDCTL_4BIT); 747 748 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 749 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 750 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 751 if (verb && drv_mask2 != drv_mask1) { 752 printf("%s channel %d: reset failed for", 753 chp->wdc->sc_dev.dv_xname, chp->channel); 754 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 755 printf(" drive 0"); 756 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 757 printf(" drive 1"); 758 printf("\n"); 759 } 760 return (drv_mask1 != drv_mask2) ? 1 : 0; 761 } 762 763 static int 764 __wdcwait_reset(chp, drv_mask) 765 struct channel_softc *chp; 766 int drv_mask; 767 { 768 int timeout; 769 u_int8_t st0, st1; 770 #ifdef WDCDEBUG 771 u_int8_t sc0, sn0, cl0, ch0; 772 u_int8_t sc1, sn1, cl1, ch1; 773 #endif 774 /* wait for BSY to deassert */ 775 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 776 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 777 WDSD_IBM); /* master */ 778 delay(10); 779 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 780 #ifdef WDCDEBUG 781 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 782 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 783 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 784 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 785 #endif 786 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 787 WDSD_IBM | 0x10); /* slave */ 788 delay(10); 789 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 790 #ifdef WDCDEBUG 791 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 792 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 793 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 794 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 795 #endif 796 797 if ((drv_mask & 0x01) == 0) { 798 /* no master */ 799 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 800 /* No master, slave is ready, it's done */ 801 goto end; 802 } 803 } else if ((drv_mask & 0x02) == 0) { 804 /* no slave */ 805 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 806 /* No slave, master is ready, it's done */ 807 goto end; 808 } 809 } else { 810 /* Wait for both master and slave to be ready */ 811 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 812 goto end; 813 } 814 } 815 delay(WDCDELAY); 816 } 817 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 818 if (st0 & WDCS_BSY) 819 drv_mask &= ~0x01; 820 if (st1 & WDCS_BSY) 821 drv_mask &= ~0x02; 822 end: 823 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 824 "cl=0x%x ch=0x%x\n", 825 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 826 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 827 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 828 "cl=0x%x ch=0x%x\n", 829 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 830 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 831 832 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 833 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 834 st0, st1), DEBUG_PROBE); 835 836 return drv_mask; 837 } 838 839 /* 840 * Wait for a drive to be !BSY, and have mask in its status register. 841 * return -1 for a timeout after "timeout" ms. 842 */ 843 int 844 wdcwait(chp, mask, bits, timeout) 845 struct channel_softc *chp; 846 int mask, bits, timeout; 847 { 848 u_char status; 849 int time = 0; 850 #ifdef WDCNDELAY_DEBUG 851 extern int cold; 852 #endif 853 854 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 855 :"none", chp->channel), DEBUG_STATUS); 856 chp->ch_error = 0; 857 858 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 859 860 for (;;) { 861 chp->ch_status = status = 862 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 863 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 864 break; 865 if (++time > timeout) { 866 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 867 "status %x error %x (mask 0x%x bits 0x%x)\n", 868 time, status, 869 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 870 wd_error), mask, bits), 871 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 872 return -1; 873 } 874 delay(WDCDELAY); 875 } 876 #ifdef WDCDEBUG 877 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 878 printf("wdcwait: did busy-wait, time=%d\n", time); 879 #endif 880 if (status & WDCS_ERR) 881 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 882 wd_error); 883 #ifdef WDCNDELAY_DEBUG 884 /* After autoconfig, there should be no long delays. */ 885 if (!cold && time > WDCNDELAY_DEBUG) { 886 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 887 if (xfer == NULL) 888 printf("%s channel %d: warning: busy-wait took %dus\n", 889 chp->wdc->sc_dev.dv_xname, chp->channel, 890 WDCDELAY * time); 891 else 892 printf("%s:%d:%d: warning: busy-wait took %dus\n", 893 chp->wdc->sc_dev.dv_xname, chp->channel, 894 xfer->drive, 895 WDCDELAY * time); 896 } 897 #endif 898 return 0; 899 } 900 901 /* 902 * Busy-wait for DMA to complete 903 */ 904 int 905 wdc_dmawait(chp, xfer, timeout) 906 struct channel_softc *chp; 907 struct wdc_xfer *xfer; 908 int timeout; 909 { 910 int time; 911 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 912 chp->wdc->dma_status = 913 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 914 chp->channel, xfer->drive, 0); 915 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 916 return 0; 917 delay(WDCDELAY); 918 } 919 /* timeout, force a DMA halt */ 920 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 921 chp->channel, xfer->drive, 1); 922 return 1; 923 } 924 925 void 926 wdctimeout(arg) 927 void *arg; 928 { 929 struct channel_softc *chp = (struct channel_softc *)arg; 930 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 931 int s; 932 933 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 934 935 s = splbio(); 936 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 937 __wdcerror(chp, "lost interrupt"); 938 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 939 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 940 xfer->c_bcount, 941 xfer->c_skip); 942 if (chp->ch_flags & WDCF_DMA_WAIT) { 943 chp->wdc->dma_status = 944 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 945 chp->channel, xfer->drive, 1); 946 chp->ch_flags &= ~WDCF_DMA_WAIT; 947 } 948 /* 949 * Call the interrupt routine. If we just missed and interrupt, 950 * it will do what's needed. Else, it will take the needed 951 * action (reset the device). 952 * Before that we need to reinstall the timeout callback, 953 * in case it will miss another irq while in this transfer 954 * We arbitray chose it to be 1s 955 */ 956 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 957 xfer->c_flags |= C_TIMEOU; 958 chp->ch_flags &= ~WDCF_IRQ_WAIT; 959 xfer->c_intr(chp, xfer, 1); 960 } else 961 __wdcerror(chp, "missing untimeout"); 962 splx(s); 963 } 964 965 /* 966 * Probe drive's capabilites, for use by the controller later 967 * Assumes drvp points to an existing drive. 968 * XXX this should be a controller-indep function 969 */ 970 void 971 wdc_probe_caps(drvp) 972 struct ata_drive_datas *drvp; 973 { 974 struct ataparams params, params2; 975 struct channel_softc *chp = drvp->chnl_softc; 976 struct device *drv_dev = drvp->drv_softc; 977 struct wdc_softc *wdc = chp->wdc; 978 int i, printed; 979 char *sep = ""; 980 int cf_flags; 981 982 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 983 /* IDENTIFY failed. Can't tell more about the device */ 984 return; 985 } 986 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 987 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 988 /* 989 * Controller claims 16 and 32 bit transfers. 990 * Re-do an IDENTIFY with 32-bit transfers, 991 * and compare results. 992 */ 993 drvp->drive_flags |= DRIVE_CAP32; 994 ata_get_params(drvp, AT_POLL, ¶ms2); 995 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 996 /* Not good. fall back to 16bits */ 997 drvp->drive_flags &= ~DRIVE_CAP32; 998 } else { 999 printf("%s: 32-bit data port", drv_dev->dv_xname); 1000 } 1001 } 1002 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1003 if (params.atap_ata_major > 0x01 && 1004 params.atap_ata_major != 0xffff) { 1005 for (i = 14; i > 0; i--) { 1006 if (params.atap_ata_major & (1 << i)) { 1007 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 1008 printf("%s: ", drv_dev->dv_xname); 1009 else 1010 printf(", "); 1011 printf("ATA version %d\n", i); 1012 drvp->ata_vers = i; 1013 break; 1014 } 1015 } 1016 } else 1017 #endif 1018 if (drvp->drive_flags & DRIVE_CAP32) 1019 printf("\n"); 1020 1021 /* An ATAPI device is at last PIO mode 3 */ 1022 if (drvp->drive_flags & DRIVE_ATAPI) 1023 drvp->PIO_mode = 3; 1024 1025 /* 1026 * It's not in the specs, but it seems that some drive 1027 * returns 0xffff in atap_extensions when this field is invalid 1028 */ 1029 if (params.atap_extensions != 0xffff && 1030 (params.atap_extensions & WDC_EXT_MODES)) { 1031 printed = 0; 1032 /* 1033 * XXX some drives report something wrong here (they claim to 1034 * support PIO mode 8 !). As mode is coded on 3 bits in 1035 * SET FEATURE, limit it to 7 (so limit i to 4). 1036 * If higther mode than 7 is found, abort. 1037 */ 1038 for (i = 7; i >= 0; i--) { 1039 if ((params.atap_piomode_supp & (1 << i)) == 0) 1040 continue; 1041 if (i > 4) 1042 return; 1043 /* 1044 * See if mode is accepted. 1045 * If the controller can't set its PIO mode, 1046 * assume the defaults are good, so don't try 1047 * to set it 1048 */ 1049 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1050 if (ata_set_mode(drvp, 0x08 | (i + 3), 1051 AT_POLL) != CMD_OK) 1052 continue; 1053 if (!printed) { 1054 printf("%s: drive supports PIO mode %d", 1055 drv_dev->dv_xname, i + 3); 1056 sep = ","; 1057 printed = 1; 1058 } 1059 /* 1060 * If controller's driver can't set its PIO mode, 1061 * get the highter one for the drive. 1062 */ 1063 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1064 wdc->PIO_cap >= i + 3) { 1065 drvp->PIO_mode = i + 3; 1066 drvp->PIO_cap = i + 3; 1067 break; 1068 } 1069 } 1070 if (!printed) { 1071 /* 1072 * We didn't find a valid PIO mode. 1073 * Assume the values returned for DMA are buggy too 1074 */ 1075 return; 1076 } 1077 drvp->drive_flags |= DRIVE_MODE; 1078 printed = 0; 1079 for (i = 7; i >= 0; i--) { 1080 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1081 continue; 1082 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1083 (wdc->cap & WDC_CAPABILITY_MODE)) 1084 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1085 != CMD_OK) 1086 continue; 1087 if (!printed) { 1088 printf("%s DMA mode %d", sep, i); 1089 sep = ","; 1090 printed = 1; 1091 } 1092 if (wdc->cap & WDC_CAPABILITY_DMA) { 1093 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1094 wdc->DMA_cap < i) 1095 continue; 1096 drvp->DMA_mode = i; 1097 drvp->DMA_cap = i; 1098 drvp->drive_flags |= DRIVE_DMA; 1099 } 1100 break; 1101 } 1102 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1103 printed = 0; 1104 for (i = 7; i >= 0; i--) { 1105 if ((params.atap_udmamode_supp & (1 << i)) 1106 == 0) 1107 continue; 1108 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1109 (wdc->cap & WDC_CAPABILITY_UDMA)) 1110 if (ata_set_mode(drvp, 0x40 | i, 1111 AT_POLL) != CMD_OK) 1112 continue; 1113 if (!printed) { 1114 printf("%s Ultra-DMA mode %d", sep, i); 1115 if (i == 2) 1116 printf(" (Ultra/33)"); 1117 else if (i == 4) 1118 printf(" (Ultra/66)"); 1119 else if (i == 5) 1120 printf(" (Ultra/100)"); 1121 sep = ","; 1122 printed = 1; 1123 } 1124 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1125 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1126 wdc->UDMA_cap < i) 1127 continue; 1128 drvp->UDMA_mode = i; 1129 drvp->UDMA_cap = i; 1130 drvp->drive_flags |= DRIVE_UDMA; 1131 } 1132 break; 1133 } 1134 } 1135 printf("\n"); 1136 } 1137 1138 /* Try to guess ATA version here, if it didn't get reported */ 1139 if (drvp->ata_vers == 0) { 1140 if (drvp->drive_flags & DRIVE_UDMA) 1141 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1142 else if (drvp->PIO_cap > 2) 1143 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1144 } 1145 cf_flags = drv_dev->dv_cfdata->cf_flags; 1146 if (cf_flags & ATA_CONFIG_PIO_SET) { 1147 drvp->PIO_mode = 1148 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1149 drvp->drive_flags |= DRIVE_MODE; 1150 } 1151 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1152 /* don't care about DMA modes */ 1153 return; 1154 } 1155 if (cf_flags & ATA_CONFIG_DMA_SET) { 1156 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1157 ATA_CONFIG_DMA_DISABLE) { 1158 drvp->drive_flags &= ~DRIVE_DMA; 1159 } else { 1160 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1161 ATA_CONFIG_DMA_OFF; 1162 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1163 } 1164 } 1165 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1166 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1167 ATA_CONFIG_UDMA_DISABLE) { 1168 drvp->drive_flags &= ~DRIVE_UDMA; 1169 } else { 1170 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1171 ATA_CONFIG_UDMA_OFF; 1172 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1173 } 1174 } 1175 } 1176 1177 /* 1178 * downgrade the transfer mode of a drive after an error. return 1 if 1179 * downgrade was possible, 0 otherwise. 1180 */ 1181 int 1182 wdc_downgrade_mode(drvp) 1183 struct ata_drive_datas *drvp; 1184 { 1185 struct channel_softc *chp = drvp->chnl_softc; 1186 struct device *drv_dev = drvp->drv_softc; 1187 struct wdc_softc *wdc = chp->wdc; 1188 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1189 1190 /* if drive or controller don't know its mode, we can't do much */ 1191 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1192 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1193 return 0; 1194 /* current drive mode was set by a config flag, let it this way */ 1195 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1196 (cf_flags & ATA_CONFIG_DMA_SET) || 1197 (cf_flags & ATA_CONFIG_UDMA_SET)) 1198 return 0; 1199 1200 /* 1201 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1202 * Maybe we didn't properly notice the cable type 1203 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1204 * It helps in some cases. 1205 */ 1206 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1207 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1208 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1209 drv_dev->dv_xname, drvp->UDMA_mode); 1210 } 1211 1212 /* 1213 * If we were using ultra-DMA, don't downgrade to multiword DMA 1214 * if we noticed a CRC error. It has been noticed that CRC errors 1215 * in ultra-DMA lead to silent data corruption in multiword DMA. 1216 * Data corruption is less likely to occur in PIO mode. 1217 */ 1218 else if ((drvp->drive_flags & DRIVE_UDMA) && 1219 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1220 drvp->drive_flags &= ~DRIVE_UDMA; 1221 drvp->drive_flags |= DRIVE_DMA; 1222 drvp->DMA_mode = drvp->DMA_cap; 1223 printf("%s: transfer error, downgrading to DMA mode %d\n", 1224 drv_dev->dv_xname, drvp->DMA_mode); 1225 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1226 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1227 drvp->PIO_mode = drvp->PIO_cap; 1228 printf("%s: transfer error, downgrading to PIO mode %d\n", 1229 drv_dev->dv_xname, drvp->PIO_mode); 1230 } else /* already using PIO, can't downgrade */ 1231 return 0; 1232 1233 wdc->set_modes(chp); 1234 /* reset the channel, which will shedule all drives for setup */ 1235 wdc_reset_channel(drvp); 1236 return 1; 1237 } 1238 1239 int 1240 wdc_exec_command(drvp, wdc_c) 1241 struct ata_drive_datas *drvp; 1242 struct wdc_command *wdc_c; 1243 { 1244 struct channel_softc *chp = drvp->chnl_softc; 1245 struct wdc_xfer *xfer; 1246 int s, ret; 1247 1248 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1249 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1250 DEBUG_FUNCS); 1251 1252 /* set up an xfer and queue. Wait for completion */ 1253 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1254 WDC_NOSLEEP); 1255 if (xfer == NULL) { 1256 return WDC_TRY_AGAIN; 1257 } 1258 1259 if (wdc_c->flags & AT_POLL) 1260 xfer->c_flags |= C_POLL; 1261 xfer->drive = drvp->drive; 1262 xfer->databuf = wdc_c->data; 1263 xfer->c_bcount = wdc_c->bcount; 1264 xfer->cmd = wdc_c; 1265 xfer->c_start = __wdccommand_start; 1266 xfer->c_intr = __wdccommand_intr; 1267 xfer->c_kill_xfer = __wdccommand_done; 1268 1269 s = splbio(); 1270 wdc_exec_xfer(chp, xfer); 1271 #ifdef DIAGNOSTIC 1272 if ((wdc_c->flags & AT_POLL) != 0 && 1273 (wdc_c->flags & AT_DONE) == 0) 1274 panic("wdc_exec_command: polled command not done\n"); 1275 #endif 1276 if (wdc_c->flags & AT_DONE) { 1277 ret = WDC_COMPLETE; 1278 } else { 1279 if (wdc_c->flags & AT_WAIT) { 1280 while ((wdc_c->flags & AT_DONE) == 0) { 1281 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1282 } 1283 ret = WDC_COMPLETE; 1284 } else { 1285 ret = WDC_QUEUED; 1286 } 1287 } 1288 splx(s); 1289 return ret; 1290 } 1291 1292 void 1293 __wdccommand_start(chp, xfer) 1294 struct channel_softc *chp; 1295 struct wdc_xfer *xfer; 1296 { 1297 int drive = xfer->drive; 1298 struct wdc_command *wdc_c = xfer->cmd; 1299 1300 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1301 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1302 DEBUG_FUNCS); 1303 1304 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1305 WDSD_IBM | (drive << 4)); 1306 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1307 wdc_c->timeout) != 0) { 1308 wdc_c->flags |= AT_TIMEOU; 1309 __wdccommand_done(chp, xfer); 1310 return; 1311 } 1312 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1313 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1314 if ((wdc_c->flags & AT_POLL) == 0) { 1315 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1316 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1317 wdctimeout, chp); 1318 return; 1319 } 1320 /* 1321 * Polled command. Wait for drive ready or drq. Done in intr(). 1322 * Wait for at last 400ns for status bit to be valid. 1323 */ 1324 delay(10); 1325 __wdccommand_intr(chp, xfer, 0); 1326 } 1327 1328 int 1329 __wdccommand_intr(chp, xfer, irq) 1330 struct channel_softc *chp; 1331 struct wdc_xfer *xfer; 1332 int irq; 1333 { 1334 struct wdc_command *wdc_c = xfer->cmd; 1335 int bcount = wdc_c->bcount; 1336 char *data = wdc_c->data; 1337 1338 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1339 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1340 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1341 (irq == 0) ? wdc_c->timeout : 0)) { 1342 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1343 return 0; /* IRQ was not for us */ 1344 wdc_c->flags |= AT_TIMEOU; 1345 __wdccommand_done(chp, xfer); 1346 return 1; 1347 } 1348 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1349 chp->wdc->irqack(chp); 1350 if (wdc_c->flags & AT_READ) { 1351 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1352 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1353 0, (u_int32_t*)data, bcount >> 2); 1354 data += bcount & 0xfffffffc; 1355 bcount = bcount & 0x03; 1356 } 1357 if (bcount > 0) 1358 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1359 wd_data, (u_int16_t *)data, bcount >> 1); 1360 } else if (wdc_c->flags & AT_WRITE) { 1361 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1362 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1363 0, (u_int32_t*)data, bcount >> 2); 1364 data += bcount & 0xfffffffc; 1365 bcount = bcount & 0x03; 1366 } 1367 if (bcount > 0) 1368 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1369 wd_data, (u_int16_t *)data, bcount >> 1); 1370 } 1371 __wdccommand_done(chp, xfer); 1372 return 1; 1373 } 1374 1375 void 1376 __wdccommand_done(chp, xfer) 1377 struct channel_softc *chp; 1378 struct wdc_xfer *xfer; 1379 { 1380 struct wdc_command *wdc_c = xfer->cmd; 1381 1382 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1383 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1384 1385 callout_stop(&chp->ch_callout); 1386 1387 if (chp->ch_status & WDCS_DWF) 1388 wdc_c->flags |= AT_DF; 1389 if (chp->ch_status & WDCS_ERR) { 1390 wdc_c->flags |= AT_ERROR; 1391 wdc_c->r_error = chp->ch_error; 1392 } 1393 wdc_c->flags |= AT_DONE; 1394 if ((wdc_c->flags & AT_READREG) != 0 && 1395 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1396 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1397 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1398 wd_sdh); 1399 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1400 wd_cyl_hi) << 8; 1401 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1402 wd_cyl_lo); 1403 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1404 wd_sector); 1405 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1406 wd_seccnt); 1407 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1408 wd_error); 1409 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1410 wd_precomp); 1411 } 1412 wdc_free_xfer(chp, xfer); 1413 if (wdc_c->flags & AT_WAIT) 1414 wakeup(wdc_c); 1415 else if (wdc_c->callback) 1416 wdc_c->callback(wdc_c->callback_arg); 1417 wdcstart(chp); 1418 return; 1419 } 1420 1421 /* 1422 * Send a command. The drive should be ready. 1423 * Assumes interrupts are blocked. 1424 */ 1425 void 1426 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1427 struct channel_softc *chp; 1428 u_int8_t drive; 1429 u_int8_t command; 1430 u_int16_t cylin; 1431 u_int8_t head, sector, count, precomp; 1432 { 1433 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1434 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1435 chp->channel, drive, command, cylin, head, sector, count, precomp), 1436 DEBUG_FUNCS); 1437 1438 /* Select drive, head, and addressing mode. */ 1439 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1440 WDSD_IBM | (drive << 4) | head); 1441 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1442 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1443 precomp); 1444 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1445 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1447 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1448 1449 /* Send command. */ 1450 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1451 return; 1452 } 1453 1454 /* 1455 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1456 * tested by the caller. 1457 */ 1458 void 1459 wdccommandshort(chp, drive, command) 1460 struct channel_softc *chp; 1461 int drive; 1462 int command; 1463 { 1464 1465 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1466 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1467 DEBUG_FUNCS); 1468 1469 /* Select drive. */ 1470 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1471 WDSD_IBM | (drive << 4)); 1472 1473 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1474 } 1475 1476 /* Add a command to the queue and start controller. Must be called at splbio */ 1477 1478 void 1479 wdc_exec_xfer(chp, xfer) 1480 struct channel_softc *chp; 1481 struct wdc_xfer *xfer; 1482 { 1483 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1484 chp->channel, xfer->drive), DEBUG_XFERS); 1485 1486 /* complete xfer setup */ 1487 xfer->chp = chp; 1488 1489 /* 1490 * If we are a polled command, and the list is not empty, 1491 * we are doing a dump. Drop the list to allow the polled command 1492 * to complete, we're going to reboot soon anyway. 1493 */ 1494 if ((xfer->c_flags & C_POLL) != 0 && 1495 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1496 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1497 } 1498 /* insert at the end of command list */ 1499 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1500 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1501 chp->ch_flags), DEBUG_XFERS); 1502 wdcstart(chp); 1503 } 1504 1505 struct wdc_xfer * 1506 wdc_get_xfer(flags) 1507 int flags; 1508 { 1509 struct wdc_xfer *xfer; 1510 int s; 1511 1512 s = splbio(); 1513 xfer = pool_get(&wdc_xfer_pool, 1514 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1515 splx(s); 1516 memset(xfer, 0, sizeof(struct wdc_xfer)); 1517 return xfer; 1518 } 1519 1520 void 1521 wdc_free_xfer(chp, xfer) 1522 struct channel_softc *chp; 1523 struct wdc_xfer *xfer; 1524 { 1525 struct wdc_softc *wdc = chp->wdc; 1526 int s; 1527 1528 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1529 (*wdc->free_hw)(chp); 1530 s = splbio(); 1531 chp->ch_flags &= ~WDCF_ACTIVE; 1532 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1533 pool_put(&wdc_xfer_pool, xfer); 1534 splx(s); 1535 } 1536 1537 /* 1538 * Kill off all pending xfers for a channel_softc. 1539 * 1540 * Must be called at splbio(). 1541 */ 1542 void 1543 wdc_kill_pending(chp) 1544 struct channel_softc *chp; 1545 { 1546 struct wdc_xfer *xfer; 1547 1548 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1549 chp = xfer->chp; 1550 (*xfer->c_kill_xfer)(chp, xfer); 1551 } 1552 } 1553 1554 static void 1555 __wdcerror(chp, msg) 1556 struct channel_softc *chp; 1557 char *msg; 1558 { 1559 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1560 1561 if (xfer == NULL) 1562 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1563 msg); 1564 else 1565 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1566 chp->channel, xfer->drive, msg); 1567 } 1568 1569 /* 1570 * the bit bucket 1571 */ 1572 void 1573 wdcbit_bucket(chp, size) 1574 struct channel_softc *chp; 1575 int size; 1576 { 1577 1578 for (; size >= 2; size -= 2) 1579 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1580 if (size) 1581 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1582 } 1583 1584 int 1585 wdc_addref(chp) 1586 struct channel_softc *chp; 1587 { 1588 struct wdc_softc *wdc = chp->wdc; 1589 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1590 int s, error = 0; 1591 1592 s = splbio(); 1593 if (adapter->_generic.scsipi_refcnt++ == 0 && 1594 adapter->_generic.scsipi_enable != NULL) { 1595 error = (*adapter->_generic.scsipi_enable)(wdc, 1); 1596 if (error) 1597 adapter->_generic.scsipi_refcnt--; 1598 } 1599 splx(s); 1600 return (error); 1601 } 1602 1603 void 1604 wdc_delref(chp) 1605 struct channel_softc *chp; 1606 { 1607 struct wdc_softc *wdc = chp->wdc; 1608 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1609 int s; 1610 1611 s = splbio(); 1612 if (adapter->_generic.scsipi_refcnt-- == 1 && 1613 adapter->_generic.scsipi_enable != NULL) 1614 (void) (*adapter->_generic.scsipi_enable)(wdc, 0); 1615 splx(s); 1616 } 1617 1618 void 1619 wdc_print_modes(struct channel_softc *chp) 1620 { 1621 int drive; 1622 struct ata_drive_datas *drvp; 1623 1624 for (drive = 0; drive < 2; drive++) { 1625 drvp = &chp->ch_drive[drive]; 1626 if ((drvp->drive_flags & DRIVE) == 0) 1627 continue; 1628 printf("%s(%s:%d:%d): using PIO mode %d", 1629 drvp->drv_softc->dv_xname, 1630 chp->wdc->sc_dev.dv_xname, 1631 chp->channel, drive, drvp->PIO_mode); 1632 if (drvp->drive_flags & DRIVE_DMA) 1633 printf(", DMA mode %d", drvp->DMA_mode); 1634 if (drvp->drive_flags & DRIVE_UDMA) { 1635 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1636 if (drvp->UDMA_mode == 2) 1637 printf(" (Ultra/33)"); 1638 else if (drvp->UDMA_mode == 4) 1639 printf(" (Ultra/66)"); 1640 else if (drvp->UDMA_mode == 5) 1641 printf(" (Ultra/100)"); 1642 } 1643 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1644 printf(" (using DMA data transfers)"); 1645 printf("\n"); 1646 } 1647 } 1648
Indexes created Wed Sep 24 05:09:52 GMT 2025